3 files changed, 81 insertions, 20 deletions

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index d3d1cfd51e09..e384e2534594 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -293,6 +293,58 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
         return PCIBIOS_SUCCESSFUL;
 }
 
+/*
+ * Remove windows, starting from the largest ones to the smallest
+ * ones.
+ */
+static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
+                                   phys_addr_t base, size_t size)
+{
+        while (size) {
+                size_t sz = 1 << (fls(size) - 1);
+
+                mvebu_mbus_del_window(base, sz);
+                base += sz;
+                size -= sz;
+        }
+}
+
+/*
+ * MBus windows can only have a power of two size, but PCI BARs do not
+ * have this constraint. Therefore, we have to split the PCI BAR into
+ * areas each having a power of two size. We start from the largest
+ * one (i.e highest order bit set in the size).
+ */
+static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
+                                   unsigned int target, unsigned int attribute,
+                                   phys_addr_t base, size_t size,
+                                   phys_addr_t remap)
+{
+        size_t size_mapped = 0;
+
+        while (size) {
+                size_t sz = 1 << (fls(size) - 1);
+                int ret;
+
+                ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
+                                                        sz, remap);
+                if (ret) {
+                        dev_err(&port->pcie->pdev->dev,
+                                "Could not create MBus window at 0x%x, size 0x%x: %d\n",
+                                base, sz, ret);
+                        mvebu_pcie_del_windows(port, base - size_mapped,
+                                               size_mapped);
+                        return;
+                }
+
+                size -= sz;
+                size_mapped += sz;
+                base += sz;
+                if (remap != MVEBU_MBUS_NO_REMAP)
+                        remap += sz;
+        }
+}
+
 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
 {
         phys_addr_t iobase;
@@ -304,8 +356,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
 
                 /* If a window was configured, remove it */
                 if (port->iowin_base) {
-                        mvebu_mbus_del_window(port->iowin_base,
-                                              port->iowin_size);
+                        mvebu_pcie_del_windows(port, port->iowin_base,
+                                               port->iowin_size);
                         port->iowin_base = 0;
                         port->iowin_size = 0;
                 }
@@ -331,11 +383,11 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
         port->iowin_base = port->pcie->io.start + iobase;
         port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
                             (port->bridge.iolimitupper << 16)) -
-                            iobase);
+                            iobase) + 1;
 
-        mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
-                                          port->iowin_base, port->iowin_size,
-                                          iobase);
+        mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
+                               port->iowin_base, port->iowin_size,
+                               iobase);
 }
 
 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
@@ -346,8 +398,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
 
                 /* If a window was configured, remove it */
                 if (port->memwin_base) {
-                        mvebu_mbus_del_window(port->memwin_base,
-                                              port->memwin_size);
+                        mvebu_pcie_del_windows(port, port->memwin_base,
+                                               port->memwin_size);
                         port->memwin_base = 0;
                         port->memwin_size = 0;
                 }
@@ -364,10 +416,11 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
         port->memwin_base  = ((port->bridge.membase & 0xFFF0) << 16);
         port->memwin_size  =
                 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
-                port->memwin_base;
+                port->memwin_base + 1;
 
-        mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
-                                    port->memwin_base, port->memwin_size);
+        mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
+                               port->memwin_base, port->memwin_size,
+                               MVEBU_MBUS_NO_REMAP);
 }
 
 /*
@@ -743,14 +796,21 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
 
         /*
          * On the PCI-to-PCI bridge side, the I/O windows must have at
-         * least a 64 KB size and be aligned on their size, and the
-         * memory windows must have at least a 1 MB size and be
-         * aligned on their size
+         * least a 64 KB size and the memory windows must have at
+         * least a 1 MB size. Moreover, MBus windows need to have a
+         * base address aligned on their size, and their size must be
+         * a power of two. This means that if the BAR doesn't have a
+         * power of two size, several MBus windows will actually be
+         * created. We need to ensure that the biggest MBus window
+         * (which will be the first one) is aligned on its size, which
+         * explains the rounddown_pow_of_two() being done here.
          */
         if (res->flags & IORESOURCE_IO)
-                return round_up(start, max_t(resource_size_t, SZ_64K, size));
+                return round_up(start, max_t(resource_size_t, SZ_64K,
+                                             rounddown_pow_of_two(size)));
         else if (res->flags & IORESOURCE_MEM)
-                return round_up(start, max_t(resource_size_t, SZ_1M, size));
+                return round_up(start, max_t(resource_size_t, SZ_1M,
+                                             rounddown_pow_of_two(size)));
         else
                 return start;
 }
diff --git a/drivers/pci/hotplug/shpchp_ctrl.c b/drivers/pci/hotplug/shpchp_ctrl.c
index 58499277903a..6efc2ec5e4db 100644
--- a/drivers/pci/hotplug/shpchp_ctrl.c
+++ b/drivers/pci/hotplug/shpchp_ctrl.c
@@ -282,8 +282,8 @@ static int board_added(struct slot *p_slot)
                 return WRONG_BUS_FREQUENCY;
         }
 
-        bsp = ctrl->pci_dev->bus->cur_bus_speed;
-        msp = ctrl->pci_dev->bus->max_bus_speed;
+        bsp = ctrl->pci_dev->subordinate->cur_bus_speed;
+        msp = ctrl->pci_dev->subordinate->max_bus_speed;
 
         /* Check if there are other slots or devices on the same bus */
         if (!list_empty(&ctrl->pci_dev->subordinate->devices))
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7325d43bf030..759475ef6ff3 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3067,7 +3067,8 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)
         if (!pci_is_pcie(dev))
                 return 1;
 
-        return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND);
+        return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
+                                    PCI_EXP_DEVSTA_TRPND);
 }
 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
 
@@ -3109,7 +3110,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
                 return 0;
 
         /* Wait for Transaction Pending bit clean */
-        if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP))
+        if (pci_wait_for_pending(dev, pos + PCI_AF_STATUS, PCI_AF_STATUS_TP))
                 goto clear;
 
         dev_err(&dev->dev, "transaction is not cleared; "