diff options
Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r-- | drivers/pci/probe.c | 406 |
1 files changed, 182 insertions, 224 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index b1724cf31b66..003a9b3c293f 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c | |||
@@ -14,8 +14,6 @@ | |||
14 | 14 | ||
15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | 15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ |
16 | #define CARDBUS_RESERVE_BUSNR 3 | 16 | #define CARDBUS_RESERVE_BUSNR 3 |
17 | #define PCI_CFG_SPACE_SIZE 256 | ||
18 | #define PCI_CFG_SPACE_EXP_SIZE 4096 | ||
19 | 17 | ||
20 | /* Ugh. Need to stop exporting this to modules. */ | 18 | /* Ugh. Need to stop exporting this to modules. */ |
21 | LIST_HEAD(pci_root_buses); | 19 | LIST_HEAD(pci_root_buses); |
@@ -44,50 +42,6 @@ int no_pci_devices(void) | |||
44 | } | 42 | } |
45 | EXPORT_SYMBOL(no_pci_devices); | 43 | EXPORT_SYMBOL(no_pci_devices); |
46 | 44 | ||
47 | #ifdef HAVE_PCI_LEGACY | ||
48 | /** | ||
49 | * pci_create_legacy_files - create legacy I/O port and memory files | ||
50 | * @b: bus to create files under | ||
51 | * | ||
52 | * Some platforms allow access to legacy I/O port and ISA memory space on | ||
53 | * a per-bus basis. This routine creates the files and ties them into | ||
54 | * their associated read, write and mmap files from pci-sysfs.c | ||
55 | */ | ||
56 | static void pci_create_legacy_files(struct pci_bus *b) | ||
57 | { | ||
58 | b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2, | ||
59 | GFP_ATOMIC); | ||
60 | if (b->legacy_io) { | ||
61 | b->legacy_io->attr.name = "legacy_io"; | ||
62 | b->legacy_io->size = 0xffff; | ||
63 | b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; | ||
64 | b->legacy_io->read = pci_read_legacy_io; | ||
65 | b->legacy_io->write = pci_write_legacy_io; | ||
66 | device_create_bin_file(&b->dev, b->legacy_io); | ||
67 | |||
68 | /* Allocated above after the legacy_io struct */ | ||
69 | b->legacy_mem = b->legacy_io + 1; | ||
70 | b->legacy_mem->attr.name = "legacy_mem"; | ||
71 | b->legacy_mem->size = 1024*1024; | ||
72 | b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR; | ||
73 | b->legacy_mem->mmap = pci_mmap_legacy_mem; | ||
74 | device_create_bin_file(&b->dev, b->legacy_mem); | ||
75 | } | ||
76 | } | ||
77 | |||
78 | void pci_remove_legacy_files(struct pci_bus *b) | ||
79 | { | ||
80 | if (b->legacy_io) { | ||
81 | device_remove_bin_file(&b->dev, b->legacy_io); | ||
82 | device_remove_bin_file(&b->dev, b->legacy_mem); | ||
83 | kfree(b->legacy_io); /* both are allocated here */ | ||
84 | } | ||
85 | } | ||
86 | #else /* !HAVE_PCI_LEGACY */ | ||
87 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | ||
88 | void pci_remove_legacy_files(struct pci_bus *bus) { return; } | ||
89 | #endif /* HAVE_PCI_LEGACY */ | ||
90 | |||
91 | /* | 45 | /* |
92 | * PCI Bus Class Devices | 46 | * PCI Bus Class Devices |
93 | */ | 47 | */ |
@@ -163,12 +117,9 @@ static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |||
163 | return IORESOURCE_MEM; | 117 | return IORESOURCE_MEM; |
164 | } | 118 | } |
165 | 119 | ||
166 | /* | 120 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
167 | * Find the extent of a PCI decode.. | ||
168 | */ | ||
169 | static u32 pci_size(u32 base, u32 maxbase, u32 mask) | ||
170 | { | 121 | { |
171 | u32 size = mask & maxbase; /* Find the significant bits */ | 122 | u64 size = mask & maxbase; /* Find the significant bits */ |
172 | if (!size) | 123 | if (!size) |
173 | return 0; | 124 | return 0; |
174 | 125 | ||
@@ -184,135 +135,148 @@ static u32 pci_size(u32 base, u32 maxbase, u32 mask) | |||
184 | return size; | 135 | return size; |
185 | } | 136 | } |
186 | 137 | ||
187 | static u64 pci_size64(u64 base, u64 maxbase, u64 mask) | 138 | enum pci_bar_type { |
188 | { | 139 | pci_bar_unknown, /* Standard PCI BAR probe */ |
189 | u64 size = mask & maxbase; /* Find the significant bits */ | 140 | pci_bar_io, /* An io port BAR */ |
190 | if (!size) | 141 | pci_bar_mem32, /* A 32-bit memory BAR */ |
191 | return 0; | 142 | pci_bar_mem64, /* A 64-bit memory BAR */ |
143 | }; | ||
192 | 144 | ||
193 | /* Get the lowest of them to find the decode size, and | 145 | static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) |
194 | from that the extent. */ | 146 | { |
195 | size = (size & ~(size-1)) - 1; | 147 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
148 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; | ||
149 | return pci_bar_io; | ||
150 | } | ||
196 | 151 | ||
197 | /* base == maxbase can be valid only if the BAR has | 152 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
198 | already been programmed with all 1s. */ | ||
199 | if (base == maxbase && ((base | size) & mask) != mask) | ||
200 | return 0; | ||
201 | 153 | ||
202 | return size; | 154 | if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) |
155 | return pci_bar_mem64; | ||
156 | return pci_bar_mem32; | ||
203 | } | 157 | } |
204 | 158 | ||
205 | static inline int is_64bit_memory(u32 mask) | 159 | /* |
160 | * If the type is not unknown, we assume that the lowest bit is 'enable'. | ||
161 | * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. | ||
162 | */ | ||
163 | static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | ||
164 | struct resource *res, unsigned int pos) | ||
206 | { | 165 | { |
207 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == | 166 | u32 l, sz, mask; |
208 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) | ||
209 | return 1; | ||
210 | return 0; | ||
211 | } | ||
212 | 167 | ||
213 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) | 168 | mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0; |
214 | { | ||
215 | unsigned int pos, reg, next; | ||
216 | u32 l, sz; | ||
217 | struct resource *res; | ||
218 | 169 | ||
219 | for(pos=0; pos<howmany; pos = next) { | 170 | res->name = pci_name(dev); |
220 | u64 l64; | ||
221 | u64 sz64; | ||
222 | u32 raw_sz; | ||
223 | 171 | ||
224 | next = pos+1; | 172 | pci_read_config_dword(dev, pos, &l); |
225 | res = &dev->resource[pos]; | 173 | pci_write_config_dword(dev, pos, mask); |
226 | res->name = pci_name(dev); | 174 | pci_read_config_dword(dev, pos, &sz); |
227 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); | 175 | pci_write_config_dword(dev, pos, l); |
228 | pci_read_config_dword(dev, reg, &l); | 176 | |
229 | pci_write_config_dword(dev, reg, ~0); | 177 | /* |
230 | pci_read_config_dword(dev, reg, &sz); | 178 | * All bits set in sz means the device isn't working properly. |
231 | pci_write_config_dword(dev, reg, l); | 179 | * If the BAR isn't implemented, all bits must be 0. If it's a |
232 | if (!sz || sz == 0xffffffff) | 180 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit |
233 | continue; | 181 | * 1 must be clear. |
234 | if (l == 0xffffffff) | 182 | */ |
235 | l = 0; | 183 | if (!sz || sz == 0xffffffff) |
236 | raw_sz = sz; | 184 | goto fail; |
237 | if ((l & PCI_BASE_ADDRESS_SPACE) == | 185 | |
238 | PCI_BASE_ADDRESS_SPACE_MEMORY) { | 186 | /* |
239 | sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK); | 187 | * I don't know how l can have all bits set. Copied from old code. |
240 | /* | 188 | * Maybe it fixes a bug on some ancient platform. |
241 | * For 64bit prefetchable memory sz could be 0, if the | 189 | */ |
242 | * real size is bigger than 4G, so we need to check | 190 | if (l == 0xffffffff) |
243 | * szhi for that. | 191 | l = 0; |
244 | */ | 192 | |
245 | if (!is_64bit_memory(l) && !sz) | 193 | if (type == pci_bar_unknown) { |
246 | continue; | 194 | type = decode_bar(res, l); |
247 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; | 195 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; |
248 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; | 196 | if (type == pci_bar_io) { |
197 | l &= PCI_BASE_ADDRESS_IO_MASK; | ||
198 | mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff; | ||
249 | } else { | 199 | } else { |
250 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); | 200 | l &= PCI_BASE_ADDRESS_MEM_MASK; |
251 | if (!sz) | 201 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
252 | continue; | ||
253 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; | ||
254 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; | ||
255 | } | 202 | } |
256 | res->end = res->start + (unsigned long) sz; | 203 | } else { |
257 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; | 204 | res->flags |= (l & IORESOURCE_ROM_ENABLE); |
258 | if (is_64bit_memory(l)) { | 205 | l &= PCI_ROM_ADDRESS_MASK; |
259 | u32 szhi, lhi; | 206 | mask = (u32)PCI_ROM_ADDRESS_MASK; |
260 | 207 | } | |
261 | pci_read_config_dword(dev, reg+4, &lhi); | 208 | |
262 | pci_write_config_dword(dev, reg+4, ~0); | 209 | if (type == pci_bar_mem64) { |
263 | pci_read_config_dword(dev, reg+4, &szhi); | 210 | u64 l64 = l; |
264 | pci_write_config_dword(dev, reg+4, lhi); | 211 | u64 sz64 = sz; |
265 | sz64 = ((u64)szhi << 32) | raw_sz; | 212 | u64 mask64 = mask | (u64)~0 << 32; |
266 | l64 = ((u64)lhi << 32) | l; | 213 | |
267 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); | 214 | pci_read_config_dword(dev, pos + 4, &l); |
268 | next++; | 215 | pci_write_config_dword(dev, pos + 4, ~0); |
269 | #if BITS_PER_LONG == 64 | 216 | pci_read_config_dword(dev, pos + 4, &sz); |
270 | if (!sz64) { | 217 | pci_write_config_dword(dev, pos + 4, l); |
271 | res->start = 0; | 218 | |
272 | res->end = 0; | 219 | l64 |= ((u64)l << 32); |
273 | res->flags = 0; | 220 | sz64 |= ((u64)sz << 32); |
274 | continue; | 221 | |
275 | } | 222 | sz64 = pci_size(l64, sz64, mask64); |
276 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; | 223 | |
277 | res->end = res->start + sz64; | 224 | if (!sz64) |
278 | #else | 225 | goto fail; |
279 | if (sz64 > 0x100000000ULL) { | 226 | |
280 | dev_err(&dev->dev, "BAR %d: can't handle 64-bit" | 227 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
281 | " BAR\n", pos); | 228 | dev_err(&dev->dev, "can't handle 64-bit BAR\n"); |
282 | res->start = 0; | 229 | goto fail; |
283 | res->flags = 0; | 230 | } else if ((sizeof(resource_size_t) < 8) && l) { |
284 | } else if (lhi) { | 231 | /* Address above 32-bit boundary; disable the BAR */ |
285 | /* 64-bit wide address, treat as disabled */ | 232 | pci_write_config_dword(dev, pos, 0); |
286 | pci_write_config_dword(dev, reg, | 233 | pci_write_config_dword(dev, pos + 4, 0); |
287 | l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK); | 234 | res->start = 0; |
288 | pci_write_config_dword(dev, reg+4, 0); | 235 | res->end = sz64; |
289 | res->start = 0; | 236 | } else { |
290 | res->end = sz; | 237 | res->start = l64; |
291 | } | 238 | res->end = l64 + sz64; |
292 | #endif | 239 | dev_printk(KERN_DEBUG, &dev->dev, |
240 | "reg %x 64bit mmio: %pR\n", pos, res); | ||
293 | } | 241 | } |
242 | } else { | ||
243 | sz = pci_size(l, sz, mask); | ||
244 | |||
245 | if (!sz) | ||
246 | goto fail; | ||
247 | |||
248 | res->start = l; | ||
249 | res->end = l + sz; | ||
250 | |||
251 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos, | ||
252 | (res->flags & IORESOURCE_IO) ? "io port" : "32bit mmio", | ||
253 | res); | ||
294 | } | 254 | } |
255 | |||
256 | out: | ||
257 | return (type == pci_bar_mem64) ? 1 : 0; | ||
258 | fail: | ||
259 | res->flags = 0; | ||
260 | goto out; | ||
261 | } | ||
262 | |||
263 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) | ||
264 | { | ||
265 | unsigned int pos, reg; | ||
266 | |||
267 | for (pos = 0; pos < howmany; pos++) { | ||
268 | struct resource *res = &dev->resource[pos]; | ||
269 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); | ||
270 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); | ||
271 | } | ||
272 | |||
295 | if (rom) { | 273 | if (rom) { |
274 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; | ||
296 | dev->rom_base_reg = rom; | 275 | dev->rom_base_reg = rom; |
297 | res = &dev->resource[PCI_ROM_RESOURCE]; | 276 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
298 | res->name = pci_name(dev); | 277 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | |
299 | pci_read_config_dword(dev, rom, &l); | 278 | IORESOURCE_SIZEALIGN; |
300 | pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE); | 279 | __pci_read_base(dev, pci_bar_mem32, res, rom); |
301 | pci_read_config_dword(dev, rom, &sz); | ||
302 | pci_write_config_dword(dev, rom, l); | ||
303 | if (l == 0xffffffff) | ||
304 | l = 0; | ||
305 | if (sz && sz != 0xffffffff) { | ||
306 | sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK); | ||
307 | if (sz) { | ||
308 | res->flags = (l & IORESOURCE_ROM_ENABLE) | | ||
309 | IORESOURCE_MEM | IORESOURCE_PREFETCH | | ||
310 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | ||
311 | IORESOURCE_SIZEALIGN; | ||
312 | res->start = l & PCI_ROM_ADDRESS_MASK; | ||
313 | res->end = res->start + (unsigned long) sz; | ||
314 | } | ||
315 | } | ||
316 | } | 280 | } |
317 | } | 281 | } |
318 | 282 | ||
@@ -334,9 +298,6 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child) | |||
334 | child->resource[i] = child->parent->resource[i - 3]; | 298 | child->resource[i] = child->parent->resource[i - 3]; |
335 | } | 299 | } |
336 | 300 | ||
337 | for(i=0; i<3; i++) | ||
338 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | ||
339 | |||
340 | res = child->resource[0]; | 301 | res = child->resource[0]; |
341 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | 302 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); |
342 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | 303 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); |
@@ -357,6 +318,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child) | |||
357 | res->start = base; | 318 | res->start = base; |
358 | if (!res->end) | 319 | if (!res->end) |
359 | res->end = limit + 0xfff; | 320 | res->end = limit + 0xfff; |
321 | dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res); | ||
360 | } | 322 | } |
361 | 323 | ||
362 | res = child->resource[1]; | 324 | res = child->resource[1]; |
@@ -368,6 +330,8 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child) | |||
368 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; | 330 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
369 | res->start = base; | 331 | res->start = base; |
370 | res->end = limit + 0xfffff; | 332 | res->end = limit + 0xfffff; |
333 | dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n", | ||
334 | res); | ||
371 | } | 335 | } |
372 | 336 | ||
373 | res = child->resource[2]; | 337 | res = child->resource[2]; |
@@ -403,6 +367,9 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child) | |||
403 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; | 367 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; |
404 | res->start = base; | 368 | res->start = base; |
405 | res->end = limit + 0xfffff; | 369 | res->end = limit + 0xfffff; |
370 | dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n", | ||
371 | (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32", | ||
372 | res); | ||
406 | } | 373 | } |
407 | } | 374 | } |
408 | 375 | ||
@@ -510,19 +477,27 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |||
510 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | 477 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
511 | u32 buses, i, j = 0; | 478 | u32 buses, i, j = 0; |
512 | u16 bctl; | 479 | u16 bctl; |
480 | int broken = 0; | ||
513 | 481 | ||
514 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | 482 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
515 | 483 | ||
516 | dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", | 484 | dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", |
517 | buses & 0xffffff, pass); | 485 | buses & 0xffffff, pass); |
518 | 486 | ||
487 | /* Check if setup is sensible at all */ | ||
488 | if (!pass && | ||
489 | ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) { | ||
490 | dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); | ||
491 | broken = 1; | ||
492 | } | ||
493 | |||
519 | /* Disable MasterAbortMode during probing to avoid reporting | 494 | /* Disable MasterAbortMode during probing to avoid reporting |
520 | of bus errors (in some architectures) */ | 495 | of bus errors (in some architectures) */ |
521 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | 496 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
522 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | 497 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, |
523 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | 498 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); |
524 | 499 | ||
525 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { | 500 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) { |
526 | unsigned int cmax, busnr; | 501 | unsigned int cmax, busnr; |
527 | /* | 502 | /* |
528 | * Bus already configured by firmware, process it in the first | 503 | * Bus already configured by firmware, process it in the first |
@@ -560,7 +535,7 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |||
560 | * do in the second pass. | 535 | * do in the second pass. |
561 | */ | 536 | */ |
562 | if (!pass) { | 537 | if (!pass) { |
563 | if (pcibios_assign_all_busses()) | 538 | if (pcibios_assign_all_busses() || broken) |
564 | /* Temporarily disable forwarding of the | 539 | /* Temporarily disable forwarding of the |
565 | configuration cycles on all bridges in | 540 | configuration cycles on all bridges in |
566 | this bus segment to avoid possible | 541 | this bus segment to avoid possible |
@@ -723,7 +698,7 @@ static int pci_setup_device(struct pci_dev * dev) | |||
723 | dev->class = class; | 698 | dev->class = class; |
724 | class >>= 8; | 699 | class >>= 8; |
725 | 700 | ||
726 | dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n", | 701 | dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n", |
727 | dev->vendor, dev->device, class, dev->hdr_type); | 702 | dev->vendor, dev->device, class, dev->hdr_type); |
728 | 703 | ||
729 | /* "Unknown power state" */ | 704 | /* "Unknown power state" */ |
@@ -805,6 +780,11 @@ static int pci_setup_device(struct pci_dev * dev) | |||
805 | return 0; | 780 | return 0; |
806 | } | 781 | } |
807 | 782 | ||
783 | static void pci_release_capabilities(struct pci_dev *dev) | ||
784 | { | ||
785 | pci_vpd_release(dev); | ||
786 | } | ||
787 | |||
808 | /** | 788 | /** |
809 | * pci_release_dev - free a pci device structure when all users of it are finished. | 789 | * pci_release_dev - free a pci device structure when all users of it are finished. |
810 | * @dev: device that's been disconnected | 790 | * @dev: device that's been disconnected |
@@ -817,7 +797,7 @@ static void pci_release_dev(struct device *dev) | |||
817 | struct pci_dev *pci_dev; | 797 | struct pci_dev *pci_dev; |
818 | 798 | ||
819 | pci_dev = to_pci_dev(dev); | 799 | pci_dev = to_pci_dev(dev); |
820 | pci_vpd_release(pci_dev); | 800 | pci_release_capabilities(pci_dev); |
821 | kfree(pci_dev); | 801 | kfree(pci_dev); |
822 | } | 802 | } |
823 | 803 | ||
@@ -848,8 +828,9 @@ static void set_pcie_port_type(struct pci_dev *pdev) | |||
848 | int pci_cfg_space_size_ext(struct pci_dev *dev) | 828 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
849 | { | 829 | { |
850 | u32 status; | 830 | u32 status; |
831 | int pos = PCI_CFG_SPACE_SIZE; | ||
851 | 832 | ||
852 | if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL) | 833 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
853 | goto fail; | 834 | goto fail; |
854 | if (status == 0xffffffff) | 835 | if (status == 0xffffffff) |
855 | goto fail; | 836 | goto fail; |
@@ -897,8 +878,6 @@ struct pci_dev *alloc_pci_dev(void) | |||
897 | 878 | ||
898 | INIT_LIST_HEAD(&dev->bus_list); | 879 | INIT_LIST_HEAD(&dev->bus_list); |
899 | 880 | ||
900 | pci_msi_init_pci_dev(dev); | ||
901 | |||
902 | return dev; | 881 | return dev; |
903 | } | 882 | } |
904 | EXPORT_SYMBOL(alloc_pci_dev); | 883 | EXPORT_SYMBOL(alloc_pci_dev); |
@@ -910,6 +889,7 @@ EXPORT_SYMBOL(alloc_pci_dev); | |||
910 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | 889 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
911 | { | 890 | { |
912 | struct pci_dev *dev; | 891 | struct pci_dev *dev; |
892 | struct pci_slot *slot; | ||
913 | u32 l; | 893 | u32 l; |
914 | u8 hdr_type; | 894 | u8 hdr_type; |
915 | int delay = 1; | 895 | int delay = 1; |
@@ -958,6 +938,10 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |||
958 | dev->error_state = pci_channel_io_normal; | 938 | dev->error_state = pci_channel_io_normal; |
959 | set_pcie_port_type(dev); | 939 | set_pcie_port_type(dev); |
960 | 940 | ||
941 | list_for_each_entry(slot, &bus->slots, list) | ||
942 | if (PCI_SLOT(devfn) == slot->number) | ||
943 | dev->slot = slot; | ||
944 | |||
961 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | 945 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) |
962 | set this higher, assuming the system even supports it. */ | 946 | set this higher, assuming the system even supports it. */ |
963 | dev->dma_mask = 0xffffffff; | 947 | dev->dma_mask = 0xffffffff; |
@@ -966,9 +950,22 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |||
966 | return NULL; | 950 | return NULL; |
967 | } | 951 | } |
968 | 952 | ||
953 | return dev; | ||
954 | } | ||
955 | |||
956 | static void pci_init_capabilities(struct pci_dev *dev) | ||
957 | { | ||
958 | /* MSI/MSI-X list */ | ||
959 | pci_msi_init_pci_dev(dev); | ||
960 | |||
961 | /* Power Management */ | ||
962 | pci_pm_init(dev); | ||
963 | |||
964 | /* Vital Product Data */ | ||
969 | pci_vpd_pci22_init(dev); | 965 | pci_vpd_pci22_init(dev); |
970 | 966 | ||
971 | return dev; | 967 | /* Alternative Routing-ID Forwarding */ |
968 | pci_enable_ari(dev); | ||
972 | } | 969 | } |
973 | 970 | ||
974 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) | 971 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
@@ -987,8 +984,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) | |||
987 | /* Fix up broken headers */ | 984 | /* Fix up broken headers */ |
988 | pci_fixup_device(pci_fixup_header, dev); | 985 | pci_fixup_device(pci_fixup_header, dev); |
989 | 986 | ||
990 | /* Initialize power management of the device */ | 987 | /* Initialize various capabilities */ |
991 | pci_pm_init(dev); | 988 | pci_init_capabilities(dev); |
992 | 989 | ||
993 | /* | 990 | /* |
994 | * Add the device to our list of discovered devices | 991 | * Add the device to our list of discovered devices |
@@ -1053,7 +1050,8 @@ int pci_scan_slot(struct pci_bus *bus, int devfn) | |||
1053 | } | 1050 | } |
1054 | } | 1051 | } |
1055 | 1052 | ||
1056 | if (bus->self) | 1053 | /* only one slot has pcie device */ |
1054 | if (bus->self && nr) | ||
1057 | pcie_aspm_init_link_state(bus->self); | 1055 | pcie_aspm_init_link_state(bus->self); |
1058 | 1056 | ||
1059 | return nr; | 1057 | return nr; |
@@ -1195,8 +1193,11 @@ EXPORT_SYMBOL(pci_scan_bridge); | |||
1195 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); | 1193 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1196 | #endif | 1194 | #endif |
1197 | 1195 | ||
1198 | static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b) | 1196 | static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
1199 | { | 1197 | { |
1198 | const struct pci_dev *a = to_pci_dev(d_a); | ||
1199 | const struct pci_dev *b = to_pci_dev(d_b); | ||
1200 | |||
1200 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; | 1201 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
1201 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | 1202 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; |
1202 | 1203 | ||
@@ -1209,50 +1210,7 @@ static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev | |||
1209 | return 0; | 1210 | return 0; |
1210 | } | 1211 | } |
1211 | 1212 | ||
1212 | /* | ||
1213 | * Yes, this forcably breaks the klist abstraction temporarily. It | ||
1214 | * just wants to sort the klist, not change reference counts and | ||
1215 | * take/drop locks rapidly in the process. It does all this while | ||
1216 | * holding the lock for the list, so objects can't otherwise be | ||
1217 | * added/removed while we're swizzling. | ||
1218 | */ | ||
1219 | static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list) | ||
1220 | { | ||
1221 | struct list_head *pos; | ||
1222 | struct klist_node *n; | ||
1223 | struct device *dev; | ||
1224 | struct pci_dev *b; | ||
1225 | |||
1226 | list_for_each(pos, list) { | ||
1227 | n = container_of(pos, struct klist_node, n_node); | ||
1228 | dev = container_of(n, struct device, knode_bus); | ||
1229 | b = to_pci_dev(dev); | ||
1230 | if (pci_sort_bf_cmp(a, b) <= 0) { | ||
1231 | list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node); | ||
1232 | return; | ||
1233 | } | ||
1234 | } | ||
1235 | list_move_tail(&a->dev.knode_bus.n_node, list); | ||
1236 | } | ||
1237 | |||
1238 | void __init pci_sort_breadthfirst(void) | 1213 | void __init pci_sort_breadthfirst(void) |
1239 | { | 1214 | { |
1240 | LIST_HEAD(sorted_devices); | 1215 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
1241 | struct list_head *pos, *tmp; | ||
1242 | struct klist_node *n; | ||
1243 | struct device *dev; | ||
1244 | struct pci_dev *pdev; | ||
1245 | struct klist *device_klist; | ||
1246 | |||
1247 | device_klist = bus_get_device_klist(&pci_bus_type); | ||
1248 | |||
1249 | spin_lock(&device_klist->k_lock); | ||
1250 | list_for_each_safe(pos, tmp, &device_klist->k_list) { | ||
1251 | n = container_of(pos, struct klist_node, n_node); | ||
1252 | dev = container_of(n, struct device, knode_bus); | ||
1253 | pdev = to_pci_dev(dev); | ||
1254 | pci_insertion_sort_klist(pdev, &sorted_devices); | ||
1255 | } | ||
1256 | list_splice(&sorted_devices, &device_klist->k_list); | ||
1257 | spin_unlock(&device_klist->k_lock); | ||
1258 | } | 1216 | } |