1 files changed, 182 insertions, 224 deletions

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index b1724cf31b66..003a9b3c293f 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -14,8 +14,6 @@
 
 #define CARDBUS_LATENCY_TIMER   176     /* secondary latency timer */
 #define CARDBUS_RESERVE_BUSNR   3
-#define PCI_CFG_SPACE_SIZE      256
-#define PCI_CFG_SPACE_EXP_SIZE  4096
 
 /* Ugh.  Need to stop exporting this to modules. */
 LIST_HEAD(pci_root_buses);
@@ -44,50 +42,6 @@ int no_pci_devices(void)
 }
 EXPORT_SYMBOL(no_pci_devices);
 
-#ifdef HAVE_PCI_LEGACY
-/**
- * pci_create_legacy_files - create legacy I/O port and memory files
- * @b: bus to create files under
- *
- * Some platforms allow access to legacy I/O port and ISA memory space on
- * a per-bus basis.  This routine creates the files and ties them into
- * their associated read, write and mmap files from pci-sysfs.c
- */
-static void pci_create_legacy_files(struct pci_bus *b)
-{
-        b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
-                               GFP_ATOMIC);
-        if (b->legacy_io) {
-                b->legacy_io->attr.name = "legacy_io";
-                b->legacy_io->size = 0xffff;
-                b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
-                b->legacy_io->read = pci_read_legacy_io;
-                b->legacy_io->write = pci_write_legacy_io;
-                device_create_bin_file(&b->dev, b->legacy_io);
-
-                /* Allocated above after the legacy_io struct */
-                b->legacy_mem = b->legacy_io + 1;
-                b->legacy_mem->attr.name = "legacy_mem";
-                b->legacy_mem->size = 1024*1024;
-                b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
-                b->legacy_mem->mmap = pci_mmap_legacy_mem;
-                device_create_bin_file(&b->dev, b->legacy_mem);
-        }
-}
-
-void pci_remove_legacy_files(struct pci_bus *b)
-{
-        if (b->legacy_io) {
-                device_remove_bin_file(&b->dev, b->legacy_io);
-                device_remove_bin_file(&b->dev, b->legacy_mem);
-                kfree(b->legacy_io); /* both are allocated here */
-        }
-}
-#else /* !HAVE_PCI_LEGACY */
-static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
-void pci_remove_legacy_files(struct pci_bus *bus) { return; }
-#endif /* HAVE_PCI_LEGACY */
-
 /*
  * PCI Bus Class Devices
  */
@@ -163,12 +117,9 @@ static inline unsigned int pci_calc_resource_flags(unsigned int flags)
         return IORESOURCE_MEM;
 }
 
-/*
- * Find the extent of a PCI decode..
- */
-static u32 pci_size(u32 base, u32 maxbase, u32 mask)
+static u64 pci_size(u64 base, u64 maxbase, u64 mask)
 {
-        u32 size = mask & maxbase;      /* Find the significant bits */
+        u64 size = mask & maxbase;      /* Find the significant bits */
         if (!size)
                 return 0;
 
@@ -184,135 +135,148 @@ static u32 pci_size(u32 base, u32 maxbase, u32 mask)
         return size;
 }
 
-static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
-{
-        u64 size = mask & maxbase;      /* Find the significant bits */
-        if (!size)
-                return 0;
+enum pci_bar_type {
+        pci_bar_unknown,        /* Standard PCI BAR probe */
+        pci_bar_io,             /* An io port BAR */
+        pci_bar_mem32,          /* A 32-bit memory BAR */
+        pci_bar_mem64,          /* A 64-bit memory BAR */
+};
 
-        /* Get the lowest of them to find the decode size, and
-           from that the extent.  */
-        size = (size & ~(size-1)) - 1;
+static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
+{
+        if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+                res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
+                return pci_bar_io;
+        }
 
-        /* base == maxbase can be valid only if the BAR has
-           already been programmed with all 1s.  */
-        if (base == maxbase && ((base | size) & mask) != mask)
-                return 0;
+        res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
 
-        return size;
+        if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
+                return pci_bar_mem64;
+        return pci_bar_mem32;
 }
 
-static inline int is_64bit_memory(u32 mask)
+/*
+ * If the type is not unknown, we assume that the lowest bit is 'enable'.
+ * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
+ */
+static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
+                        struct resource *res, unsigned int pos)
 {
-        if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
-            (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
-                return 1;
-        return 0;
-}
+        u32 l, sz, mask;
 
-static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
-{
-        unsigned int pos, reg, next;
-        u32 l, sz;
-        struct resource *res;
+        mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
 
-        for(pos=0; pos<howmany; pos = next) {
-                u64 l64;
-                u64 sz64;
-                u32 raw_sz;
+        res->name = pci_name(dev);
 
-                next = pos+1;
-                res = &dev->resource[pos];
-                res->name = pci_name(dev);
-                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
-                pci_read_config_dword(dev, reg, &l);
-                pci_write_config_dword(dev, reg, ~0);
-                pci_read_config_dword(dev, reg, &sz);
-                pci_write_config_dword(dev, reg, l);
-                if (!sz || sz == 0xffffffff)
-                        continue;
-                if (l == 0xffffffff)
-                        l = 0;
-                raw_sz = sz;
-                if ((l & PCI_BASE_ADDRESS_SPACE) ==
-                                PCI_BASE_ADDRESS_SPACE_MEMORY) {
-                        sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
-                        /*
-                         * For 64bit prefetchable memory sz could be 0, if the
-                         * real size is bigger than 4G, so we need to check
-                         * szhi for that.
-                         */
-                        if (!is_64bit_memory(l) && !sz)
-                                continue;
-                        res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
-                        res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
+        pci_read_config_dword(dev, pos, &l);
+        pci_write_config_dword(dev, pos, mask);
+        pci_read_config_dword(dev, pos, &sz);
+        pci_write_config_dword(dev, pos, l);
+
+        /*
+         * All bits set in sz means the device isn't working properly.
+         * If the BAR isn't implemented, all bits must be 0.  If it's a
+         * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
+         * 1 must be clear.
+         */
+        if (!sz || sz == 0xffffffff)
+                goto fail;
+
+        /*
+         * I don't know how l can have all bits set.  Copied from old code.
+         * Maybe it fixes a bug on some ancient platform.
+         */
+        if (l == 0xffffffff)
+                l = 0;
+
+        if (type == pci_bar_unknown) {
+                type = decode_bar(res, l);
+                res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
+                if (type == pci_bar_io) {
+                        l &= PCI_BASE_ADDRESS_IO_MASK;
+                        mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
                 } else {
-                        sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
-                        if (!sz)
-                                continue;
-                        res->start = l & PCI_BASE_ADDRESS_IO_MASK;
-                        res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
+                        l &= PCI_BASE_ADDRESS_MEM_MASK;
+                        mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
                 }
-                res->end = res->start + (unsigned long) sz;
-                res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
-                if (is_64bit_memory(l)) {
-                        u32 szhi, lhi;
-
-                        pci_read_config_dword(dev, reg+4, &lhi);
-                        pci_write_config_dword(dev, reg+4, ~0);
-                        pci_read_config_dword(dev, reg+4, &szhi);
-                        pci_write_config_dword(dev, reg+4, lhi);
-                        sz64 = ((u64)szhi << 32) | raw_sz;
-                        l64 = ((u64)lhi << 32) | l;
-                        sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
-                        next++;
-#if BITS_PER_LONG == 64
-                        if (!sz64) {
-                                res->start = 0;
-                                res->end = 0;
-                                res->flags = 0;
-                                continue;
-                        }
-                        res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
-                        res->end = res->start + sz64;
-#else
-                        if (sz64 > 0x100000000ULL) {
-                                dev_err(&dev->dev, "BAR %d: can't handle 64-bit"
-                                        " BAR\n", pos);
-                                res->start = 0;
-                                res->flags = 0;
-                        } else if (lhi) {
-                                /* 64-bit wide address, treat as disabled */
-                                pci_write_config_dword(dev, reg,
-                                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
-                                pci_write_config_dword(dev, reg+4, 0);
-                                res->start = 0;
-                                res->end = sz;
-                        }
-#endif
+        } else {
+                res->flags |= (l & IORESOURCE_ROM_ENABLE);
+                l &= PCI_ROM_ADDRESS_MASK;
+                mask = (u32)PCI_ROM_ADDRESS_MASK;
+        }
+
+        if (type == pci_bar_mem64) {
+                u64 l64 = l;
+                u64 sz64 = sz;
+                u64 mask64 = mask | (u64)~0 << 32;
+
+                pci_read_config_dword(dev, pos + 4, &l);
+                pci_write_config_dword(dev, pos + 4, ~0);
+                pci_read_config_dword(dev, pos + 4, &sz);
+                pci_write_config_dword(dev, pos + 4, l);
+
+                l64 |= ((u64)l << 32);
+                sz64 |= ((u64)sz << 32);
+
+                sz64 = pci_size(l64, sz64, mask64);
+
+                if (!sz64)
+                        goto fail;
+
+                if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
+                        dev_err(&dev->dev, "can't handle 64-bit BAR\n");
+                        goto fail;
+                } else if ((sizeof(resource_size_t) < 8) && l) {
+                        /* Address above 32-bit boundary; disable the BAR */
+                        pci_write_config_dword(dev, pos, 0);
+                        pci_write_config_dword(dev, pos + 4, 0);
+                        res->start = 0;
+                        res->end = sz64;
+                } else {
+                        res->start = l64;
+                        res->end = l64 + sz64;
+                        dev_printk(KERN_DEBUG, &dev->dev,
+                                "reg %x 64bit mmio: %pR\n", pos, res);
                 }
+        } else {
+                sz = pci_size(l, sz, mask);
+
+                if (!sz)
+                        goto fail;
+
+                res->start = l;
+                res->end = l + sz;
+
+                dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos,
+                        (res->flags & IORESOURCE_IO) ? "io port" : "32bit mmio",
+                        res);
         }
+
+ out:
+        return (type == pci_bar_mem64) ? 1 : 0;
+ fail:
+        res->flags = 0;
+        goto out;
+}
+
+static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
+{
+        unsigned int pos, reg;
+
+        for (pos = 0; pos < howmany; pos++) {
+                struct resource *res = &dev->resource[pos];
+                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
+                pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+        }
+
         if (rom) {
+                struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
                 dev->rom_base_reg = rom;
-                res = &dev->resource[PCI_ROM_RESOURCE];
-                res->name = pci_name(dev);
-                pci_read_config_dword(dev, rom, &l);
-                pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
-                pci_read_config_dword(dev, rom, &sz);
-                pci_write_config_dword(dev, rom, l);
-                if (l == 0xffffffff)
-                        l = 0;
-                if (sz && sz != 0xffffffff) {
-                        sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
-                        if (sz) {
-                                res->flags = (l & IORESOURCE_ROM_ENABLE) |
-                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
-                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
-                                  IORESOURCE_SIZEALIGN;
-                                res->start = l & PCI_ROM_ADDRESS_MASK;
-                                res->end = res->start + (unsigned long) sz;
-                        }
-                }
+                res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
+                                IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
+                                IORESOURCE_SIZEALIGN;
+                __pci_read_base(dev, pci_bar_mem32, res, rom);
         }
 }
 
@@ -334,9 +298,6 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
                         child->resource[i] = child->parent->resource[i - 3];
         }
 
-        for(i=0; i<3; i++)
-                child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
-
         res = child->resource[0];
         pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
         pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
@@ -357,6 +318,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
                         res->start = base;
                 if (!res->end)
                         res->end = limit + 0xfff;
+                dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res);
         }
 
         res = child->resource[1];
@@ -368,6 +330,8 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
                 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
                 res->start = base;
                 res->end = limit + 0xfffff;
+                dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n",
+                        res);
         }
 
         res = child->resource[2];
@@ -403,6 +367,9 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
                 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
                 res->start = base;
                 res->end = limit + 0xfffff;
+                dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n",
+                        (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
+                        res);
         }
 }
 
@@ -510,19 +477,27 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
         int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
         u32 buses, i, j = 0;
         u16 bctl;
+        int broken = 0;
 
         pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
 
         dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
                 buses & 0xffffff, pass);
 
+        /* Check if setup is sensible at all */
+        if (!pass &&
+            ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
+                dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
+                broken = 1;
+        }
+
         /* Disable MasterAbortMode during probing to avoid reporting
            of bus errors (in some architectures) */ 
         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
         pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
                               bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 
-        if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
+        if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
                 unsigned int cmax, busnr;
                 /*
                  * Bus already configured by firmware, process it in the first
@@ -560,7 +535,7 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
                  * do in the second pass.
                  */
                 if (!pass) {
-                        if (pcibios_assign_all_busses())
+                        if (pcibios_assign_all_busses() || broken)
                                 /* Temporarily disable forwarding of the
                                    configuration cycles on all bridges in
                                    this bus segment to avoid possible
@@ -723,7 +698,7 @@ static int pci_setup_device(struct pci_dev * dev)
         dev->class = class;
         class >>= 8;
 
-        dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n",
+        dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
                  dev->vendor, dev->device, class, dev->hdr_type);
 
         /* "Unknown power state" */
@@ -805,6 +780,11 @@ static int pci_setup_device(struct pci_dev * dev)
         return 0;
 }
 
+static void pci_release_capabilities(struct pci_dev *dev)
+{
+        pci_vpd_release(dev);
+}
+
 /**
  * pci_release_dev - free a pci device structure when all users of it are finished.
  * @dev: device that's been disconnected
@@ -817,7 +797,7 @@ static void pci_release_dev(struct device *dev)
         struct pci_dev *pci_dev;
 
         pci_dev = to_pci_dev(dev);
-        pci_vpd_release(pci_dev);
+        pci_release_capabilities(pci_dev);
         kfree(pci_dev);
 }
 
@@ -848,8 +828,9 @@ static void set_pcie_port_type(struct pci_dev *pdev)
 int pci_cfg_space_size_ext(struct pci_dev *dev)
 {
         u32 status;
+        int pos = PCI_CFG_SPACE_SIZE;
 
-        if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
+        if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
                 goto fail;
         if (status == 0xffffffff)
                 goto fail;
@@ -897,8 +878,6 @@ struct pci_dev *alloc_pci_dev(void)
 
         INIT_LIST_HEAD(&dev->bus_list);
 
-        pci_msi_init_pci_dev(dev);
-
         return dev;
 }
 EXPORT_SYMBOL(alloc_pci_dev);
@@ -910,6 +889,7 @@ EXPORT_SYMBOL(alloc_pci_dev);
 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
 {
         struct pci_dev *dev;
+        struct pci_slot *slot;
         u32 l;
         u8 hdr_type;
         int delay = 1;
@@ -958,6 +938,10 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
         dev->error_state = pci_channel_io_normal;
         set_pcie_port_type(dev);
 
+        list_for_each_entry(slot, &bus->slots, list)
+                if (PCI_SLOT(devfn) == slot->number)
+                        dev->slot = slot;
+
         /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
            set this higher, assuming the system even supports it.  */
         dev->dma_mask = 0xffffffff;
@@ -966,9 +950,22 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
                 return NULL;
         }
 
+        return dev;
+}
+
+static void pci_init_capabilities(struct pci_dev *dev)
+{
+        /* MSI/MSI-X list */
+        pci_msi_init_pci_dev(dev);
+
+        /* Power Management */
+        pci_pm_init(dev);
+
+        /* Vital Product Data */
         pci_vpd_pci22_init(dev);
 
-        return dev;
+        /* Alternative Routing-ID Forwarding */
+        pci_enable_ari(dev);
 }
 
 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
@@ -987,8 +984,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
         /* Fix up broken headers */
         pci_fixup_device(pci_fixup_header, dev);
 
-        /* Initialize power management of the device */
-        pci_pm_init(dev);
+        /* Initialize various capabilities */
+        pci_init_capabilities(dev);
 
         /*
          * Add the device to our list of discovered devices
@@ -1053,7 +1050,8 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
                 }
         }
 
-        if (bus->self)
+        /* only one slot has pcie device */
+        if (bus->self && nr)
                 pcie_aspm_init_link_state(bus->self);
 
         return nr;
@@ -1195,8 +1193,11 @@ EXPORT_SYMBOL(pci_scan_bridge);
 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
 #endif
 
-static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
+static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
 {
+        const struct pci_dev *a = to_pci_dev(d_a);
+        const struct pci_dev *b = to_pci_dev(d_b);
+
         if      (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
         else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return  1;
 
@@ -1209,50 +1210,7 @@ static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev
         return 0;
 }
 
-/*
- * Yes, this forcably breaks the klist abstraction temporarily.  It
- * just wants to sort the klist, not change reference counts and
- * take/drop locks rapidly in the process.  It does all this while
- * holding the lock for the list, so objects can't otherwise be
- * added/removed while we're swizzling.
- */
-static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
-{
-        struct list_head *pos;
-        struct klist_node *n;
-        struct device *dev;
-        struct pci_dev *b;
-
-        list_for_each(pos, list) {
-                n = container_of(pos, struct klist_node, n_node);
-                dev = container_of(n, struct device, knode_bus);
-                b = to_pci_dev(dev);
-                if (pci_sort_bf_cmp(a, b) <= 0) {
-                        list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
-                        return;
-                }
-        }
-        list_move_tail(&a->dev.knode_bus.n_node, list);
-}
-
 void __init pci_sort_breadthfirst(void)
 {
-        LIST_HEAD(sorted_devices);
-        struct list_head *pos, *tmp;
-        struct klist_node *n;
-        struct device *dev;
-        struct pci_dev *pdev;
-        struct klist *device_klist;
-
-        device_klist = bus_get_device_klist(&pci_bus_type);
-
-        spin_lock(&device_klist->k_lock);
-        list_for_each_safe(pos, tmp, &device_klist->k_list) {
-                n = container_of(pos, struct klist_node, n_node);
-                dev = container_of(n, struct device, knode_bus);
-                pdev = to_pci_dev(dev);
-                pci_insertion_sort_klist(pdev, &sorted_devices);
-        }
-        list_splice(&sorted_devices, &device_klist->k_list);
-        spin_unlock(&device_klist->k_lock);
+        bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
 }