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path: root/drivers/pci/pci.c
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Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r--drivers/pci/pci.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 17bd9325a245..48807556b47a 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1393,35 +1393,35 @@ int pci_restore_standard_config(struct pci_dev *dev)
1393 pci_power_t prev_state; 1393 pci_power_t prev_state;
1394 int error; 1394 int error;
1395 1395
1396 pci_restore_state(dev);
1397 pci_update_current_state(dev, PCI_D0); 1396 pci_update_current_state(dev, PCI_D0);
1398 1397
1399 prev_state = dev->current_state; 1398 prev_state = dev->current_state;
1400 if (prev_state == PCI_D0) 1399 if (prev_state == PCI_D0)
1401 return 0; 1400 goto Restore;
1402 1401
1403 error = pci_raw_set_power_state(dev, PCI_D0, false); 1402 error = pci_raw_set_power_state(dev, PCI_D0, false);
1404 if (error) 1403 if (error)
1405 return error; 1404 return error;
1406 1405
1407 if (pci_is_bridge(dev)) { 1406 /*
1408 if (prev_state > PCI_D1) 1407 * This assumes that we won't get a bus in B2 or B3 from the BIOS, but
1409 mdelay(PCI_PM_BUS_WAIT); 1408 * we've made this assumption forever and it appears to be universally
1410 } else { 1409 * satisfied.
1411 switch(prev_state) { 1410 */
1412 case PCI_D3cold: 1411 switch(prev_state) {
1413 case PCI_D3hot: 1412 case PCI_D3cold:
1414 mdelay(pci_pm_d3_delay); 1413 case PCI_D3hot:
1415 break; 1414 mdelay(pci_pm_d3_delay);
1416 case PCI_D2: 1415 break;
1417 udelay(PCI_PM_D2_DELAY); 1416 case PCI_D2:
1418 break; 1417 udelay(PCI_PM_D2_DELAY);
1419 } 1418 break;
1420 } 1419 }
1421 1420
1422 dev->current_state = PCI_D0; 1421 dev->current_state = PCI_D0;
1423 1422
1424 return 0; 1423 Restore:
1424 return pci_restore_state(dev);
1425} 1425}
1426 1426
1427/** 1427/**