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path: root/drivers/pci/msi.c
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Diffstat (limited to 'drivers/pci/msi.c')
-rw-r--r--drivers/pci/msi.c64
1 files changed, 45 insertions, 19 deletions
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index d9f06fbfa0bf..d986afb7032b 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -127,17 +127,23 @@ static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
127 * reliably as devices without an INTx disable bit will then generate a 127 * reliably as devices without an INTx disable bit will then generate a
128 * level IRQ which will never be cleared. 128 * level IRQ which will never be cleared.
129 */ 129 */
130static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) 130static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
131{ 131{
132 u32 mask_bits = desc->masked; 132 u32 mask_bits = desc->masked;
133 133
134 if (!desc->msi_attrib.maskbit) 134 if (!desc->msi_attrib.maskbit)
135 return; 135 return 0;
136 136
137 mask_bits &= ~mask; 137 mask_bits &= ~mask;
138 mask_bits |= flag; 138 mask_bits |= flag;
139 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); 139 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
140 desc->masked = mask_bits; 140
141 return mask_bits;
142}
143
144static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
145{
146 desc->masked = __msi_mask_irq(desc, mask, flag);
141} 147}
142 148
143/* 149/*
@@ -147,15 +153,21 @@ static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
147 * file. This saves a few milliseconds when initialising devices with lots 153 * file. This saves a few milliseconds when initialising devices with lots
148 * of MSI-X interrupts. 154 * of MSI-X interrupts.
149 */ 155 */
150static void msix_mask_irq(struct msi_desc *desc, u32 flag) 156static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
151{ 157{
152 u32 mask_bits = desc->masked; 158 u32 mask_bits = desc->masked;
153 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 159 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
154 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 160 PCI_MSIX_ENTRY_VECTOR_CTRL;
155 mask_bits &= ~1; 161 mask_bits &= ~1;
156 mask_bits |= flag; 162 mask_bits |= flag;
157 writel(mask_bits, desc->mask_base + offset); 163 writel(mask_bits, desc->mask_base + offset);
158 desc->masked = mask_bits; 164
165 return mask_bits;
166}
167
168static void msix_mask_irq(struct msi_desc *desc, u32 flag)
169{
170 desc->masked = __msix_mask_irq(desc, flag);
159} 171}
160 172
161static void msi_set_mask_bit(unsigned irq, u32 flag) 173static void msi_set_mask_bit(unsigned irq, u32 flag)
@@ -188,9 +200,9 @@ void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
188 void __iomem *base = entry->mask_base + 200 void __iomem *base = entry->mask_base +
189 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 201 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
190 202
191 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 203 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
192 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 204 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
193 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 205 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
194 } else { 206 } else {
195 struct pci_dev *dev = entry->dev; 207 struct pci_dev *dev = entry->dev;
196 int pos = entry->msi_attrib.pos; 208 int pos = entry->msi_attrib.pos;
@@ -225,11 +237,9 @@ void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
225 base = entry->mask_base + 237 base = entry->mask_base +
226 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 238 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
227 239
228 writel(msg->address_lo, 240 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
229 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 241 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
230 writel(msg->address_hi, 242 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
231 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
232 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
233 } else { 243 } else {
234 struct pci_dev *dev = entry->dev; 244 struct pci_dev *dev = entry->dev;
235 int pos = entry->msi_attrib.pos; 245 int pos = entry->msi_attrib.pos;
@@ -385,6 +395,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
385 /* Configure MSI capability structure */ 395 /* Configure MSI capability structure */
386 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); 396 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
387 if (ret) { 397 if (ret) {
398 msi_mask_irq(entry, mask, ~mask);
388 msi_free_irqs(dev); 399 msi_free_irqs(dev);
389 return ret; 400 return ret;
390 } 401 }
@@ -439,8 +450,14 @@ static int msix_capability_init(struct pci_dev *dev,
439 450
440 for (i = 0; i < nvec; i++) { 451 for (i = 0; i < nvec; i++) {
441 entry = alloc_msi_entry(dev); 452 entry = alloc_msi_entry(dev);
442 if (!entry) 453 if (!entry) {
443 break; 454 if (!i)
455 iounmap(base);
456 else
457 msi_free_irqs(dev);
458 /* No enough memory. Don't try again */
459 return -ENOMEM;
460 }
444 461
445 j = entries[i].entry; 462 j = entries[i].entry;
446 entry->msi_attrib.is_msix = 1; 463 entry->msi_attrib.is_msix = 1;
@@ -487,7 +504,7 @@ static int msix_capability_init(struct pci_dev *dev,
487 set_irq_msi(entry->irq, entry); 504 set_irq_msi(entry->irq, entry);
488 j = entries[i].entry; 505 j = entries[i].entry;
489 entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE + 506 entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE +
490 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 507 PCI_MSIX_ENTRY_VECTOR_CTRL);
491 msix_mask_irq(entry, 1); 508 msix_mask_irq(entry, 1);
492 i++; 509 i++;
493 } 510 }
@@ -611,9 +628,11 @@ void pci_msi_shutdown(struct pci_dev *dev)
611 pci_intx_for_msi(dev, 1); 628 pci_intx_for_msi(dev, 1);
612 dev->msi_enabled = 0; 629 dev->msi_enabled = 0;
613 630
631 /* Return the device with MSI unmasked as initial states */
614 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); 632 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
615 mask = msi_capable_mask(ctrl); 633 mask = msi_capable_mask(ctrl);
616 msi_mask_irq(desc, mask, ~mask); 634 /* Keep cached state to be restored */
635 __msi_mask_irq(desc, mask, ~mask);
617 636
618 /* Restore dev->irq to its default pin-assertion irq */ 637 /* Restore dev->irq to its default pin-assertion irq */
619 dev->irq = desc->msi_attrib.default_irq; 638 dev->irq = desc->msi_attrib.default_irq;
@@ -653,7 +672,6 @@ static int msi_free_irqs(struct pci_dev* dev)
653 672
654 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { 673 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
655 if (entry->msi_attrib.is_msix) { 674 if (entry->msi_attrib.is_msix) {
656 msix_mask_irq(entry, 1);
657 if (list_is_last(&entry->list, &dev->msi_list)) 675 if (list_is_last(&entry->list, &dev->msi_list))
658 iounmap(entry->mask_base); 676 iounmap(entry->mask_base);
659 } 677 }
@@ -741,9 +759,17 @@ static void msix_free_all_irqs(struct pci_dev *dev)
741 759
742void pci_msix_shutdown(struct pci_dev* dev) 760void pci_msix_shutdown(struct pci_dev* dev)
743{ 761{
762 struct msi_desc *entry;
763
744 if (!pci_msi_enable || !dev || !dev->msix_enabled) 764 if (!pci_msi_enable || !dev || !dev->msix_enabled)
745 return; 765 return;
746 766
767 /* Return the device with MSI-X masked as initial states */
768 list_for_each_entry(entry, &dev->msi_list, list) {
769 /* Keep cached states to be restored */
770 __msix_mask_irq(entry, 1);
771 }
772
747 msix_set_enable(dev, 0); 773 msix_set_enable(dev, 0);
748 pci_intx_for_msi(dev, 1); 774 pci_intx_for_msi(dev, 1);
749 dev->msix_enabled = 0; 775 dev->msix_enabled = 0;