diff options
Diffstat (limited to 'drivers/pci/hotplug/shpchp_hpc.c')
-rw-r--r-- | drivers/pci/hotplug/shpchp_hpc.c | 175 |
1 files changed, 37 insertions, 138 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c index 8d98410bf1c0..40905a6c8094 100644 --- a/drivers/pci/hotplug/shpchp_hpc.c +++ b/drivers/pci/hotplug/shpchp_hpc.c | |||
@@ -27,17 +27,10 @@ | |||
27 | * | 27 | * |
28 | */ | 28 | */ |
29 | 29 | ||
30 | #include <linux/config.h> | ||
31 | #include <linux/kernel.h> | 30 | #include <linux/kernel.h> |
32 | #include <linux/module.h> | 31 | #include <linux/module.h> |
33 | #include <linux/types.h> | 32 | #include <linux/types.h> |
34 | #include <linux/slab.h> | ||
35 | #include <linux/vmalloc.h> | ||
36 | #include <linux/interrupt.h> | ||
37 | #include <linux/spinlock.h> | ||
38 | #include <linux/delay.h> | ||
39 | #include <linux/pci.h> | 33 | #include <linux/pci.h> |
40 | #include <asm/system.h> | ||
41 | #include "shpchp.h" | 34 | #include "shpchp.h" |
42 | 35 | ||
43 | #ifdef DEBUG | 36 | #ifdef DEBUG |
@@ -282,7 +275,7 @@ static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds) | |||
282 | 275 | ||
283 | static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) | 276 | static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) |
284 | { | 277 | { |
285 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 278 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
286 | u16 cmd_status; | 279 | u16 cmd_status; |
287 | int retval = 0; | 280 | int retval = 0; |
288 | u16 temp_word; | 281 | u16 temp_word; |
@@ -320,7 +313,6 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) | |||
320 | * command. | 313 | * command. |
321 | */ | 314 | */ |
322 | writew(temp_word, php_ctlr->creg + CMD); | 315 | writew(temp_word, php_ctlr->creg + CMD); |
323 | dbg("%s: temp_word written %x\n", __FUNCTION__, temp_word); | ||
324 | 316 | ||
325 | DBG_LEAVE_ROUTINE | 317 | DBG_LEAVE_ROUTINE |
326 | return retval; | 318 | return retval; |
@@ -328,7 +320,7 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) | |||
328 | 320 | ||
329 | static int hpc_check_cmd_status(struct controller *ctrl) | 321 | static int hpc_check_cmd_status(struct controller *ctrl) |
330 | { | 322 | { |
331 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle; | 323 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; |
332 | u16 cmd_status; | 324 | u16 cmd_status; |
333 | int retval = 0; | 325 | int retval = 0; |
334 | 326 | ||
@@ -368,7 +360,7 @@ static int hpc_check_cmd_status(struct controller *ctrl) | |||
368 | 360 | ||
369 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | 361 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
370 | { | 362 | { |
371 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 363 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
372 | u32 slot_reg; | 364 | u32 slot_reg; |
373 | u16 slot_status; | 365 | u16 slot_status; |
374 | u8 atten_led_state; | 366 | u8 atten_led_state; |
@@ -408,7 +400,7 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status) | |||
408 | 400 | ||
409 | static int hpc_get_power_status(struct slot * slot, u8 *status) | 401 | static int hpc_get_power_status(struct slot * slot, u8 *status) |
410 | { | 402 | { |
411 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 403 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
412 | u32 slot_reg; | 404 | u32 slot_reg; |
413 | u16 slot_status; | 405 | u16 slot_status; |
414 | u8 slot_state; | 406 | u8 slot_state; |
@@ -450,7 +442,7 @@ static int hpc_get_power_status(struct slot * slot, u8 *status) | |||
450 | 442 | ||
451 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | 443 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
452 | { | 444 | { |
453 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 445 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
454 | u32 slot_reg; | 446 | u32 slot_reg; |
455 | u16 slot_status; | 447 | u16 slot_status; |
456 | 448 | ||
@@ -473,7 +465,7 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status) | |||
473 | 465 | ||
474 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | 466 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) |
475 | { | 467 | { |
476 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 468 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
477 | u32 slot_reg; | 469 | u32 slot_reg; |
478 | u16 slot_status; | 470 | u16 slot_status; |
479 | u8 card_state; | 471 | u8 card_state; |
@@ -496,7 +488,7 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |||
496 | 488 | ||
497 | static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) | 489 | static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) |
498 | { | 490 | { |
499 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 491 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
500 | 492 | ||
501 | DBG_ENTER_ROUTINE | 493 | DBG_ENTER_ROUTINE |
502 | 494 | ||
@@ -513,7 +505,7 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) | |||
513 | 505 | ||
514 | static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | 506 | static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) |
515 | { | 507 | { |
516 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 508 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
517 | u32 slot_reg; | 509 | u32 slot_reg; |
518 | u16 slot_status, sec_bus_status; | 510 | u16 slot_status, sec_bus_status; |
519 | u8 m66_cap, pcix_cap, pi; | 511 | u8 m66_cap, pcix_cap, pi; |
@@ -594,7 +586,7 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |||
594 | 586 | ||
595 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | 587 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) |
596 | { | 588 | { |
597 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 589 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
598 | u16 sec_bus_status; | 590 | u16 sec_bus_status; |
599 | u8 pi; | 591 | u8 pi; |
600 | int retval = 0; | 592 | int retval = 0; |
@@ -623,7 +615,7 @@ static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | |||
623 | 615 | ||
624 | static int hpc_query_power_fault(struct slot * slot) | 616 | static int hpc_query_power_fault(struct slot * slot) |
625 | { | 617 | { |
626 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 618 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
627 | u32 slot_reg; | 619 | u32 slot_reg; |
628 | u16 slot_status; | 620 | u16 slot_status; |
629 | u8 pwr_fault_state, status; | 621 | u8 pwr_fault_state, status; |
@@ -647,7 +639,7 @@ static int hpc_query_power_fault(struct slot * slot) | |||
647 | 639 | ||
648 | static int hpc_set_attention_status(struct slot *slot, u8 value) | 640 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
649 | { | 641 | { |
650 | struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 642 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
651 | u8 slot_cmd = 0; | 643 | u8 slot_cmd = 0; |
652 | int rc = 0; | 644 | int rc = 0; |
653 | 645 | ||
@@ -683,7 +675,7 @@ static int hpc_set_attention_status(struct slot *slot, u8 value) | |||
683 | 675 | ||
684 | static void hpc_set_green_led_on(struct slot *slot) | 676 | static void hpc_set_green_led_on(struct slot *slot) |
685 | { | 677 | { |
686 | struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 678 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
687 | u8 slot_cmd; | 679 | u8 slot_cmd; |
688 | 680 | ||
689 | if (!slot->ctrl->hpc_ctlr_handle) { | 681 | if (!slot->ctrl->hpc_ctlr_handle) { |
@@ -705,7 +697,7 @@ static void hpc_set_green_led_on(struct slot *slot) | |||
705 | 697 | ||
706 | static void hpc_set_green_led_off(struct slot *slot) | 698 | static void hpc_set_green_led_off(struct slot *slot) |
707 | { | 699 | { |
708 | struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 700 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
709 | u8 slot_cmd; | 701 | u8 slot_cmd; |
710 | 702 | ||
711 | if (!slot->ctrl->hpc_ctlr_handle) { | 703 | if (!slot->ctrl->hpc_ctlr_handle) { |
@@ -727,7 +719,7 @@ static void hpc_set_green_led_off(struct slot *slot) | |||
727 | 719 | ||
728 | static void hpc_set_green_led_blink(struct slot *slot) | 720 | static void hpc_set_green_led_blink(struct slot *slot) |
729 | { | 721 | { |
730 | struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 722 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
731 | u8 slot_cmd; | 723 | u8 slot_cmd; |
732 | 724 | ||
733 | if (!slot->ctrl->hpc_ctlr_handle) { | 725 | if (!slot->ctrl->hpc_ctlr_handle) { |
@@ -754,7 +746,7 @@ int shpc_get_ctlr_slot_config(struct controller *ctrl, | |||
754 | int *updown, /* physical_slot_num increament: 1 or -1 */ | 746 | int *updown, /* physical_slot_num increament: 1 or -1 */ |
755 | int *flags) | 747 | int *flags) |
756 | { | 748 | { |
757 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle; | 749 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; |
758 | 750 | ||
759 | DBG_ENTER_ROUTINE | 751 | DBG_ENTER_ROUTINE |
760 | 752 | ||
@@ -776,7 +768,7 @@ int shpc_get_ctlr_slot_config(struct controller *ctrl, | |||
776 | 768 | ||
777 | static void hpc_release_ctlr(struct controller *ctrl) | 769 | static void hpc_release_ctlr(struct controller *ctrl) |
778 | { | 770 | { |
779 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle; | 771 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; |
780 | struct php_ctlr_state_s *p, *p_prev; | 772 | struct php_ctlr_state_s *p, *p_prev; |
781 | 773 | ||
782 | DBG_ENTER_ROUTINE | 774 | DBG_ENTER_ROUTINE |
@@ -796,10 +788,8 @@ static void hpc_release_ctlr(struct controller *ctrl) | |||
796 | } | 788 | } |
797 | } | 789 | } |
798 | if (php_ctlr->pci_dev) { | 790 | if (php_ctlr->pci_dev) { |
799 | dbg("%s: before calling iounmap & release_mem_region\n", __FUNCTION__); | ||
800 | iounmap(php_ctlr->creg); | 791 | iounmap(php_ctlr->creg); |
801 | release_mem_region(pci_resource_start(php_ctlr->pci_dev, 0), pci_resource_len(php_ctlr->pci_dev, 0)); | 792 | release_mem_region(pci_resource_start(php_ctlr->pci_dev, 0), pci_resource_len(php_ctlr->pci_dev, 0)); |
802 | dbg("%s: before calling iounmap & release_mem_region\n", __FUNCTION__); | ||
803 | php_ctlr->pci_dev = NULL; | 793 | php_ctlr->pci_dev = NULL; |
804 | } | 794 | } |
805 | 795 | ||
@@ -828,7 +818,7 @@ DBG_LEAVE_ROUTINE | |||
828 | 818 | ||
829 | static int hpc_power_on_slot(struct slot * slot) | 819 | static int hpc_power_on_slot(struct slot * slot) |
830 | { | 820 | { |
831 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 821 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
832 | u8 slot_cmd; | 822 | u8 slot_cmd; |
833 | int retval = 0; | 823 | int retval = 0; |
834 | 824 | ||
@@ -859,7 +849,7 @@ static int hpc_power_on_slot(struct slot * slot) | |||
859 | 849 | ||
860 | static int hpc_slot_enable(struct slot * slot) | 850 | static int hpc_slot_enable(struct slot * slot) |
861 | { | 851 | { |
862 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 852 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
863 | u8 slot_cmd; | 853 | u8 slot_cmd; |
864 | int retval = 0; | 854 | int retval = 0; |
865 | 855 | ||
@@ -890,7 +880,7 @@ static int hpc_slot_enable(struct slot * slot) | |||
890 | 880 | ||
891 | static int hpc_slot_disable(struct slot * slot) | 881 | static int hpc_slot_disable(struct slot * slot) |
892 | { | 882 | { |
893 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 883 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
894 | u8 slot_cmd; | 884 | u8 slot_cmd; |
895 | int retval = 0; | 885 | int retval = 0; |
896 | 886 | ||
@@ -920,51 +910,12 @@ static int hpc_slot_disable(struct slot * slot) | |||
920 | return retval; | 910 | return retval; |
921 | } | 911 | } |
922 | 912 | ||
923 | static int hpc_enable_all_slots( struct slot *slot ) | ||
924 | { | ||
925 | int retval = 0; | ||
926 | |||
927 | DBG_ENTER_ROUTINE | ||
928 | |||
929 | if (!slot->ctrl->hpc_ctlr_handle) { | ||
930 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | ||
931 | return -1; | ||
932 | } | ||
933 | |||
934 | retval = shpc_write_cmd(slot, 0, SET_ENABLE_ALL); | ||
935 | if (retval) { | ||
936 | err("%s: Write command failed!\n", __FUNCTION__); | ||
937 | return -1; | ||
938 | } | ||
939 | |||
940 | DBG_LEAVE_ROUTINE | ||
941 | |||
942 | return retval; | ||
943 | } | ||
944 | |||
945 | static int hpc_pwr_on_all_slots(struct slot *slot) | ||
946 | { | ||
947 | int retval = 0; | ||
948 | |||
949 | DBG_ENTER_ROUTINE | ||
950 | |||
951 | retval = shpc_write_cmd(slot, 0, SET_PWR_ON_ALL); | ||
952 | |||
953 | if (retval) { | ||
954 | err("%s: Write command failed!\n", __FUNCTION__); | ||
955 | return -1; | ||
956 | } | ||
957 | |||
958 | DBG_LEAVE_ROUTINE | ||
959 | return retval; | ||
960 | } | ||
961 | |||
962 | static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) | 913 | static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) |
963 | { | 914 | { |
964 | u8 slot_cmd; | 915 | u8 slot_cmd; |
965 | u8 pi; | 916 | u8 pi; |
966 | int retval = 0; | 917 | int retval = 0; |
967 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 918 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
968 | 919 | ||
969 | DBG_ENTER_ROUTINE | 920 | DBG_ENTER_ROUTINE |
970 | 921 | ||
@@ -1089,18 +1040,13 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1089 | 1040 | ||
1090 | if (!intr_loc) | 1041 | if (!intr_loc) |
1091 | return IRQ_NONE; | 1042 | return IRQ_NONE; |
1092 | dbg("%s: shpc_isr proceeds\n", __FUNCTION__); | ||
1093 | dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); | 1043 | dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); |
1094 | 1044 | ||
1095 | if(!shpchp_poll_mode) { | 1045 | if(!shpchp_poll_mode) { |
1096 | /* Mask Global Interrupt Mask - see implementation note on p. 139 */ | 1046 | /* Mask Global Interrupt Mask - see implementation note on p. 139 */ |
1097 | /* of SHPC spec rev 1.0*/ | 1047 | /* of SHPC spec rev 1.0*/ |
1098 | temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); | 1048 | temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); |
1099 | dbg("%s: Before masking global interrupt, temp_dword = %x\n", | ||
1100 | __FUNCTION__, temp_dword); | ||
1101 | temp_dword |= 0x00000001; | 1049 | temp_dword |= 0x00000001; |
1102 | dbg("%s: After masking global interrupt, temp_dword = %x\n", | ||
1103 | __FUNCTION__, temp_dword); | ||
1104 | writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); | 1050 | writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); |
1105 | 1051 | ||
1106 | intr_loc2 = readl(php_ctlr->creg + INTR_LOC); | 1052 | intr_loc2 = readl(php_ctlr->creg + INTR_LOC); |
@@ -1114,11 +1060,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1114 | * Detect bit in Controller SERR-INT register | 1060 | * Detect bit in Controller SERR-INT register |
1115 | */ | 1061 | */ |
1116 | temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); | 1062 | temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); |
1117 | dbg("%s: Before clearing CCIP, temp_dword = %x\n", | ||
1118 | __FUNCTION__, temp_dword); | ||
1119 | temp_dword &= 0xfffeffff; | 1063 | temp_dword &= 0xfffeffff; |
1120 | dbg("%s: After clearing CCIP, temp_dword = %x\n", | ||
1121 | __FUNCTION__, temp_dword); | ||
1122 | writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); | 1064 | writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); |
1123 | wake_up_interruptible(&ctrl->queue); | 1065 | wake_up_interruptible(&ctrl->queue); |
1124 | } | 1066 | } |
@@ -1126,11 +1068,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1126 | if ((intr_loc = (intr_loc >> 1)) == 0) { | 1068 | if ((intr_loc = (intr_loc >> 1)) == 0) { |
1127 | /* Unmask Global Interrupt Mask */ | 1069 | /* Unmask Global Interrupt Mask */ |
1128 | temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); | 1070 | temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); |
1129 | dbg("%s: 1-Before unmasking global interrupt, temp_dword = %x\n", | ||
1130 | __FUNCTION__, temp_dword); | ||
1131 | temp_dword &= 0xfffffffe; | 1071 | temp_dword &= 0xfffffffe; |
1132 | dbg("%s: 1-After unmasking global interrupt, temp_dword = %x\n", | ||
1133 | __FUNCTION__, temp_dword); | ||
1134 | writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); | 1072 | writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); |
1135 | 1073 | ||
1136 | return IRQ_NONE; | 1074 | return IRQ_NONE; |
@@ -1140,11 +1078,9 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1140 | /* To find out which slot has interrupt pending */ | 1078 | /* To find out which slot has interrupt pending */ |
1141 | if ((intr_loc >> hp_slot) & 0x01) { | 1079 | if ((intr_loc >> hp_slot) & 0x01) { |
1142 | temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot)); | 1080 | temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot)); |
1143 | dbg("%s: Slot %x with intr, temp_dword = %x\n", | 1081 | dbg("%s: Slot %x with intr, slot register = %x\n", |
1144 | __FUNCTION__, hp_slot, temp_dword); | 1082 | __FUNCTION__, hp_slot, temp_dword); |
1145 | temp_byte = (temp_dword >> 16) & 0xFF; | 1083 | temp_byte = (temp_dword >> 16) & 0xFF; |
1146 | dbg("%s: Slot with intr, temp_byte = %x\n", | ||
1147 | __FUNCTION__, temp_byte); | ||
1148 | if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08)) | 1084 | if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08)) |
1149 | schedule_flag += php_ctlr->switch_change_callback( | 1085 | schedule_flag += php_ctlr->switch_change_callback( |
1150 | hp_slot, php_ctlr->callback_instance_id); | 1086 | hp_slot, php_ctlr->callback_instance_id); |
@@ -1160,8 +1096,6 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1160 | 1096 | ||
1161 | /* Clear all slot events */ | 1097 | /* Clear all slot events */ |
1162 | temp_dword = 0xe01f3fff; | 1098 | temp_dword = 0xe01f3fff; |
1163 | dbg("%s: Clearing slot events, temp_dword = %x\n", | ||
1164 | __FUNCTION__, temp_dword); | ||
1165 | writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot)); | 1099 | writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot)); |
1166 | 1100 | ||
1167 | intr_loc2 = readl(php_ctlr->creg + INTR_LOC); | 1101 | intr_loc2 = readl(php_ctlr->creg + INTR_LOC); |
@@ -1171,11 +1105,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1171 | if (!shpchp_poll_mode) { | 1105 | if (!shpchp_poll_mode) { |
1172 | /* Unmask Global Interrupt Mask */ | 1106 | /* Unmask Global Interrupt Mask */ |
1173 | temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); | 1107 | temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); |
1174 | dbg("%s: 2-Before unmasking global interrupt, temp_dword = %x\n", | ||
1175 | __FUNCTION__, temp_dword); | ||
1176 | temp_dword &= 0xfffffffe; | 1108 | temp_dword &= 0xfffffffe; |
1177 | dbg("%s: 2-After unmasking global interrupt, temp_dword = %x\n", | ||
1178 | __FUNCTION__, temp_dword); | ||
1179 | writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); | 1109 | writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); |
1180 | } | 1110 | } |
1181 | 1111 | ||
@@ -1184,7 +1114,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1184 | 1114 | ||
1185 | static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) | 1115 | static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) |
1186 | { | 1116 | { |
1187 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 1117 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1188 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; | 1118 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
1189 | int retval = 0; | 1119 | int retval = 0; |
1190 | u8 pi; | 1120 | u8 pi; |
@@ -1253,7 +1183,7 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |||
1253 | 1183 | ||
1254 | static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) | 1184 | static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) |
1255 | { | 1185 | { |
1256 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle; | 1186 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1257 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; | 1187 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
1258 | u16 sec_bus_status; | 1188 | u16 sec_bus_status; |
1259 | int retval = 0; | 1189 | int retval = 0; |
@@ -1367,8 +1297,6 @@ static struct hpc_ops shpchp_hpc_ops = { | |||
1367 | .power_on_slot = hpc_power_on_slot, | 1297 | .power_on_slot = hpc_power_on_slot, |
1368 | .slot_enable = hpc_slot_enable, | 1298 | .slot_enable = hpc_slot_enable, |
1369 | .slot_disable = hpc_slot_disable, | 1299 | .slot_disable = hpc_slot_disable, |
1370 | .enable_all_slots = hpc_enable_all_slots, | ||
1371 | .pwr_on_all_slots = hpc_pwr_on_all_slots, | ||
1372 | .set_bus_speed_mode = hpc_set_bus_speed_mode, | 1300 | .set_bus_speed_mode = hpc_set_bus_speed_mode, |
1373 | .set_attention_status = hpc_set_attention_status, | 1301 | .set_attention_status = hpc_set_attention_status, |
1374 | .get_power_status = hpc_get_power_status, | 1302 | .get_power_status = hpc_get_power_status, |
@@ -1391,12 +1319,7 @@ static struct hpc_ops shpchp_hpc_ops = { | |||
1391 | .check_cmd_status = hpc_check_cmd_status, | 1319 | .check_cmd_status = hpc_check_cmd_status, |
1392 | }; | 1320 | }; |
1393 | 1321 | ||
1394 | int shpc_init(struct controller * ctrl, | 1322 | int shpc_init(struct controller * ctrl, struct pci_dev * pdev) |
1395 | struct pci_dev * pdev, | ||
1396 | php_intr_callback_t attention_button_callback, | ||
1397 | php_intr_callback_t switch_change_callback, | ||
1398 | php_intr_callback_t presence_change_callback, | ||
1399 | php_intr_callback_t power_fault_callback) | ||
1400 | { | 1323 | { |
1401 | struct php_ctlr_state_s *php_ctlr, *p; | 1324 | struct php_ctlr_state_s *php_ctlr, *p; |
1402 | void *instance_id = ctrl; | 1325 | void *instance_id = ctrl; |
@@ -1405,7 +1328,6 @@ int shpc_init(struct controller * ctrl, | |||
1405 | static int first = 1; | 1328 | static int first = 1; |
1406 | u32 shpc_cap_offset, shpc_base_offset; | 1329 | u32 shpc_cap_offset, shpc_base_offset; |
1407 | u32 tempdword, slot_reg; | 1330 | u32 tempdword, slot_reg; |
1408 | u16 vendor_id, device_id; | ||
1409 | u8 i; | 1331 | u8 i; |
1410 | 1332 | ||
1411 | DBG_ENTER_ROUTINE | 1333 | DBG_ENTER_ROUTINE |
@@ -1422,21 +1344,8 @@ int shpc_init(struct controller * ctrl, | |||
1422 | 1344 | ||
1423 | php_ctlr->pci_dev = pdev; /* save pci_dev in context */ | 1345 | php_ctlr->pci_dev = pdev; /* save pci_dev in context */ |
1424 | 1346 | ||
1425 | rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id); | 1347 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == |
1426 | dbg("%s: Vendor ID: %x\n",__FUNCTION__, vendor_id); | 1348 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { |
1427 | if (rc) { | ||
1428 | err("%s: unable to read PCI configuration data\n", __FUNCTION__); | ||
1429 | goto abort_free_ctlr; | ||
1430 | } | ||
1431 | |||
1432 | rc = pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); | ||
1433 | dbg("%s: Device ID: %x\n",__FUNCTION__, device_id); | ||
1434 | if (rc) { | ||
1435 | err("%s: unable to read PCI configuration data\n", __FUNCTION__); | ||
1436 | goto abort_free_ctlr; | ||
1437 | } | ||
1438 | |||
1439 | if ((vendor_id == PCI_VENDOR_ID_AMD) || (device_id == PCI_DEVICE_ID_AMD_GOLAM_7450)) { | ||
1440 | shpc_base_offset = 0; /* amd shpc driver doesn't use this; assume 0 */ | 1349 | shpc_base_offset = 0; /* amd shpc driver doesn't use this; assume 0 */ |
1441 | } else { | 1350 | } else { |
1442 | if ((shpc_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC)) == 0) { | 1351 | if ((shpc_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC)) == 0) { |
@@ -1469,7 +1378,8 @@ int shpc_init(struct controller * ctrl, | |||
1469 | err("%s : pci_read_config_dword failed\n", __FUNCTION__); | 1378 | err("%s : pci_read_config_dword failed\n", __FUNCTION__); |
1470 | goto abort_free_ctlr; | 1379 | goto abort_free_ctlr; |
1471 | } | 1380 | } |
1472 | dbg("%s: offset %d: tempdword %x\n", __FUNCTION__,i, tempdword); | 1381 | dbg("%s: offset %d: value %x\n", __FUNCTION__,i, |
1382 | tempdword); | ||
1473 | } | 1383 | } |
1474 | } | 1384 | } |
1475 | 1385 | ||
@@ -1478,13 +1388,6 @@ int shpc_init(struct controller * ctrl, | |||
1478 | first = 0; | 1388 | first = 0; |
1479 | } | 1389 | } |
1480 | 1390 | ||
1481 | dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number, PCI_SLOT(pdev->devfn), | ||
1482 | PCI_FUNC(pdev->devfn), pdev->irq); | ||
1483 | for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) | ||
1484 | if (pci_resource_len(pdev, rc) > 0) | ||
1485 | dbg("pci resource[%d] start=0x%lx(len=0x%lx), shpc_base_offset %x\n", rc, | ||
1486 | pci_resource_start(pdev, rc), pci_resource_len(pdev, rc), shpc_base_offset); | ||
1487 | |||
1488 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, | 1391 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, |
1489 | pdev->subsystem_device); | 1392 | pdev->subsystem_device); |
1490 | 1393 | ||
@@ -1504,7 +1407,6 @@ int shpc_init(struct controller * ctrl, | |||
1504 | goto abort_free_ctlr; | 1407 | goto abort_free_ctlr; |
1505 | } | 1408 | } |
1506 | dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); | 1409 | dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); |
1507 | dbg("%s: physical addr %p\n", __FUNCTION__, (void*)pci_resource_start(pdev, 0)); | ||
1508 | 1410 | ||
1509 | init_MUTEX(&ctrl->crit_sect); | 1411 | init_MUTEX(&ctrl->crit_sect); |
1510 | /* Setup wait queue */ | 1412 | /* Setup wait queue */ |
@@ -1512,13 +1414,10 @@ int shpc_init(struct controller * ctrl, | |||
1512 | 1414 | ||
1513 | /* Find the IRQ */ | 1415 | /* Find the IRQ */ |
1514 | php_ctlr->irq = pdev->irq; | 1416 | php_ctlr->irq = pdev->irq; |
1515 | dbg("HPC interrupt = %d\n", php_ctlr->irq); | 1417 | php_ctlr->attention_button_callback = shpchp_handle_attention_button, |
1516 | 1418 | php_ctlr->switch_change_callback = shpchp_handle_switch_change; | |
1517 | /* Save interrupt callback info */ | 1419 | php_ctlr->presence_change_callback = shpchp_handle_presence_change; |
1518 | php_ctlr->attention_button_callback = attention_button_callback; | 1420 | php_ctlr->power_fault_callback = shpchp_handle_power_fault; |
1519 | php_ctlr->switch_change_callback = switch_change_callback; | ||
1520 | php_ctlr->presence_change_callback = presence_change_callback; | ||
1521 | php_ctlr->power_fault_callback = power_fault_callback; | ||
1522 | php_ctlr->callback_instance_id = instance_id; | 1421 | php_ctlr->callback_instance_id = instance_id; |
1523 | 1422 | ||
1524 | /* Return PCI Controller Info */ | 1423 | /* Return PCI Controller Info */ |
@@ -1556,7 +1455,6 @@ int shpc_init(struct controller * ctrl, | |||
1556 | if (rc) { | 1455 | if (rc) { |
1557 | info("Can't get msi for the hotplug controller\n"); | 1456 | info("Can't get msi for the hotplug controller\n"); |
1558 | info("Use INTx for the hotplug controller\n"); | 1457 | info("Use INTx for the hotplug controller\n"); |
1559 | dbg("%s: rc = %x\n", __FUNCTION__, rc); | ||
1560 | } else | 1458 | } else |
1561 | php_ctlr->irq = pdev->irq; | 1459 | php_ctlr->irq = pdev->irq; |
1562 | 1460 | ||
@@ -1566,9 +1464,11 @@ int shpc_init(struct controller * ctrl, | |||
1566 | err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); | 1464 | err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); |
1567 | goto abort_free_ctlr; | 1465 | goto abort_free_ctlr; |
1568 | } | 1466 | } |
1569 | /* Execute OSHP method here */ | ||
1570 | } | 1467 | } |
1571 | dbg("%s: Before adding HPC to HPC list\n", __FUNCTION__); | 1468 | dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, |
1469 | pdev->bus->number, PCI_SLOT(pdev->devfn), | ||
1470 | PCI_FUNC(pdev->devfn), pdev->irq); | ||
1471 | get_hp_hw_control_from_firmware(pdev); | ||
1572 | 1472 | ||
1573 | /* Add this HPC instance into the HPC list */ | 1473 | /* Add this HPC instance into the HPC list */ |
1574 | spin_lock(&list_lock); | 1474 | spin_lock(&list_lock); |
@@ -1607,7 +1507,6 @@ int shpc_init(struct controller * ctrl, | |||
1607 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); | 1507 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1608 | } | 1508 | } |
1609 | 1509 | ||
1610 | dbg("%s: Leaving shpc_init\n", __FUNCTION__); | ||
1611 | DBG_LEAVE_ROUTINE | 1510 | DBG_LEAVE_ROUTINE |
1612 | return 0; | 1511 | return 0; |
1613 | 1512 | ||