diff options
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 34 |
1 files changed, 2 insertions, 32 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c index 29ca2931c22a..1a751c9d09c4 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | |||
@@ -633,8 +633,7 @@ int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, | |||
633 | struct hwtstamp_config config; | 633 | struct hwtstamp_config config; |
634 | u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED; | 634 | u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED; |
635 | u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED; | 635 | u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED; |
636 | u32 tsync_rx_mtrl = 0; | 636 | u32 tsync_rx_mtrl = PTP_EV_PORT << 16; |
637 | bool is_l4 = false; | ||
638 | bool is_l2 = false; | 637 | bool is_l2 = false; |
639 | u32 regval; | 638 | u32 regval; |
640 | 639 | ||
@@ -657,16 +656,15 @@ int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, | |||
657 | switch (config.rx_filter) { | 656 | switch (config.rx_filter) { |
658 | case HWTSTAMP_FILTER_NONE: | 657 | case HWTSTAMP_FILTER_NONE: |
659 | tsync_rx_ctl = 0; | 658 | tsync_rx_ctl = 0; |
659 | tsync_rx_mtrl = 0; | ||
660 | break; | 660 | break; |
661 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | 661 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
662 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; | 662 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; |
663 | tsync_rx_mtrl = IXGBE_RXMTRL_V1_SYNC_MSG; | 663 | tsync_rx_mtrl = IXGBE_RXMTRL_V1_SYNC_MSG; |
664 | is_l4 = true; | ||
665 | break; | 664 | break; |
666 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | 665 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
667 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; | 666 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; |
668 | tsync_rx_mtrl = IXGBE_RXMTRL_V1_DELAY_REQ_MSG; | 667 | tsync_rx_mtrl = IXGBE_RXMTRL_V1_DELAY_REQ_MSG; |
669 | is_l4 = true; | ||
670 | break; | 668 | break; |
671 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | 669 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
672 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | 670 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: |
@@ -679,7 +677,6 @@ int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, | |||
679 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | 677 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
680 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2; | 678 | tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2; |
681 | is_l2 = true; | 679 | is_l2 = true; |
682 | is_l4 = true; | ||
683 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | 680 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
684 | break; | 681 | break; |
685 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | 682 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
@@ -713,33 +710,6 @@ int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, | |||
713 | else | 710 | else |
714 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); | 711 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); |
715 | 712 | ||
716 | #define PTP_PORT 319 | ||
717 | /* L4 Queue Filter[3]: filter by destination port and protocol */ | ||
718 | if (is_l4) { | ||
719 | u32 ftqf = (IXGBE_FTQF_PROTOCOL_UDP /* UDP */ | ||
720 | | IXGBE_FTQF_POOL_MASK_EN /* Pool not compared */ | ||
721 | | IXGBE_FTQF_QUEUE_ENABLE); | ||
722 | |||
723 | ftqf |= ((IXGBE_FTQF_PROTOCOL_COMP_MASK /* protocol check */ | ||
724 | & IXGBE_FTQF_DEST_PORT_MASK /* dest check */ | ||
725 | & IXGBE_FTQF_SOURCE_PORT_MASK) /* source check */ | ||
726 | << IXGBE_FTQF_5TUPLE_MASK_SHIFT); | ||
727 | |||
728 | IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(3), | ||
729 | (3 << IXGBE_IMIR_RX_QUEUE_SHIFT_82599 | | ||
730 | IXGBE_IMIR_SIZE_BP_82599)); | ||
731 | |||
732 | /* enable port check */ | ||
733 | IXGBE_WRITE_REG(hw, IXGBE_SDPQF(3), | ||
734 | (htons(PTP_PORT) | | ||
735 | htons(PTP_PORT) << 16)); | ||
736 | |||
737 | IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), ftqf); | ||
738 | |||
739 | tsync_rx_mtrl |= PTP_PORT << 16; | ||
740 | } else { | ||
741 | IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), 0); | ||
742 | } | ||
743 | 713 | ||
744 | /* enable/disable TX */ | 714 | /* enable/disable TX */ |
745 | regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); | 715 | regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); |