diff options
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/wireless/ath/carl9170/eeprom.h | 216 | ||||
-rw-r--r-- | drivers/net/wireless/ath/carl9170/fwcmd.h | 268 | ||||
-rw-r--r-- | drivers/net/wireless/ath/carl9170/fwdesc.h | 237 | ||||
-rw-r--r-- | drivers/net/wireless/ath/carl9170/hw.h | 736 | ||||
-rw-r--r-- | drivers/net/wireless/ath/carl9170/phy.h | 567 | ||||
-rw-r--r-- | drivers/net/wireless/ath/carl9170/wlan.h | 412 |
6 files changed, 2436 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/carl9170/eeprom.h b/drivers/net/wireless/ath/carl9170/eeprom.h new file mode 100644 index 000000000000..7cff40ac7759 --- /dev/null +++ b/drivers/net/wireless/ath/carl9170/eeprom.h | |||
@@ -0,0 +1,216 @@ | |||
1 | /* | ||
2 | * Shared Atheros AR9170 Header | ||
3 | * | ||
4 | * EEPROM layout | ||
5 | * | ||
6 | * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, see | ||
20 | * http://www.gnu.org/licenses/. | ||
21 | * | ||
22 | * This file incorporates work covered by the following copyright and | ||
23 | * permission notice: | ||
24 | * Copyright (c) 2007-2008 Atheros Communications, Inc. | ||
25 | * | ||
26 | * Permission to use, copy, modify, and/or distribute this software for any | ||
27 | * purpose with or without fee is hereby granted, provided that the above | ||
28 | * copyright notice and this permission notice appear in all copies. | ||
29 | * | ||
30 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
31 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
32 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
33 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
34 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
35 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
36 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
37 | */ | ||
38 | #ifndef __CARL9170_SHARED_EEPROM_H | ||
39 | #define __CARL9170_SHARED_EEPROM_H | ||
40 | |||
41 | #define AR9170_EEPROM_START 0x1600 | ||
42 | |||
43 | #define AR5416_MAX_CHAINS 2 | ||
44 | #define AR5416_MODAL_SPURS 5 | ||
45 | |||
46 | struct ar9170_eeprom_modal { | ||
47 | __le32 antCtrlChain[AR5416_MAX_CHAINS]; | ||
48 | __le32 antCtrlCommon; | ||
49 | s8 antennaGainCh[AR5416_MAX_CHAINS]; | ||
50 | u8 switchSettling; | ||
51 | u8 txRxAttenCh[AR5416_MAX_CHAINS]; | ||
52 | u8 rxTxMarginCh[AR5416_MAX_CHAINS]; | ||
53 | s8 adcDesiredSize; | ||
54 | s8 pgaDesiredSize; | ||
55 | u8 xlnaGainCh[AR5416_MAX_CHAINS]; | ||
56 | u8 txEndToXpaOff; | ||
57 | u8 txEndToRxOn; | ||
58 | u8 txFrameToXpaOn; | ||
59 | u8 thresh62; | ||
60 | s8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; | ||
61 | u8 xpdGain; | ||
62 | u8 xpd; | ||
63 | s8 iqCalICh[AR5416_MAX_CHAINS]; | ||
64 | s8 iqCalQCh[AR5416_MAX_CHAINS]; | ||
65 | u8 pdGainOverlap; | ||
66 | u8 ob; | ||
67 | u8 db; | ||
68 | u8 xpaBiasLvl; | ||
69 | u8 pwrDecreaseFor2Chain; | ||
70 | u8 pwrDecreaseFor3Chain; | ||
71 | u8 txFrameToDataStart; | ||
72 | u8 txFrameToPaOn; | ||
73 | u8 ht40PowerIncForPdadc; | ||
74 | u8 bswAtten[AR5416_MAX_CHAINS]; | ||
75 | u8 bswMargin[AR5416_MAX_CHAINS]; | ||
76 | u8 swSettleHt40; | ||
77 | u8 reserved[22]; | ||
78 | struct spur_channel { | ||
79 | __le16 spurChan; | ||
80 | u8 spurRangeLow; | ||
81 | u8 spurRangeHigh; | ||
82 | } __packed spur_channels[AR5416_MODAL_SPURS]; | ||
83 | } __packed; | ||
84 | |||
85 | #define AR5416_NUM_PD_GAINS 4 | ||
86 | #define AR5416_PD_GAIN_ICEPTS 5 | ||
87 | |||
88 | struct ar9170_calibration_data_per_freq { | ||
89 | u8 pwr_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | ||
90 | u8 vpd_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | ||
91 | } __packed; | ||
92 | |||
93 | #define AR5416_NUM_5G_CAL_PIERS 8 | ||
94 | #define AR5416_NUM_2G_CAL_PIERS 4 | ||
95 | |||
96 | #define AR5416_NUM_5G_TARGET_PWRS 8 | ||
97 | #define AR5416_NUM_2G_CCK_TARGET_PWRS 3 | ||
98 | #define AR5416_NUM_2G_OFDM_TARGET_PWRS 4 | ||
99 | #define AR5416_MAX_NUM_TGT_PWRS 8 | ||
100 | |||
101 | struct ar9170_calibration_target_power_legacy { | ||
102 | u8 freq; | ||
103 | u8 power[4]; | ||
104 | } __packed; | ||
105 | |||
106 | struct ar9170_calibration_target_power_ht { | ||
107 | u8 freq; | ||
108 | u8 power[8]; | ||
109 | } __packed; | ||
110 | |||
111 | #define AR5416_NUM_CTLS 24 | ||
112 | |||
113 | struct ar9170_calctl_edges { | ||
114 | u8 channel; | ||
115 | #define AR9170_CALCTL_EDGE_FLAGS 0xC0 | ||
116 | u8 power_flags; | ||
117 | } __packed; | ||
118 | |||
119 | #define AR5416_NUM_BAND_EDGES 8 | ||
120 | |||
121 | struct ar9170_calctl_data { | ||
122 | struct ar9170_calctl_edges | ||
123 | control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; | ||
124 | } __packed; | ||
125 | |||
126 | struct ar9170_eeprom { | ||
127 | __le16 length; | ||
128 | __le16 checksum; | ||
129 | __le16 version; | ||
130 | u8 operating_flags; | ||
131 | #define AR9170_OPFLAG_5GHZ 1 | ||
132 | #define AR9170_OPFLAG_2GHZ 2 | ||
133 | u8 misc; | ||
134 | __le16 reg_domain[2]; | ||
135 | u8 mac_address[6]; | ||
136 | u8 rx_mask; | ||
137 | u8 tx_mask; | ||
138 | __le16 rf_silent; | ||
139 | __le16 bluetooth_options; | ||
140 | __le16 device_capabilities; | ||
141 | __le32 build_number; | ||
142 | u8 deviceType; | ||
143 | u8 reserved[33]; | ||
144 | |||
145 | u8 customer_data[64]; | ||
146 | |||
147 | struct ar9170_eeprom_modal | ||
148 | modal_header[2]; | ||
149 | |||
150 | u8 cal_freq_pier_5G[AR5416_NUM_5G_CAL_PIERS]; | ||
151 | u8 cal_freq_pier_2G[AR5416_NUM_2G_CAL_PIERS]; | ||
152 | |||
153 | struct ar9170_calibration_data_per_freq | ||
154 | cal_pier_data_5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS], | ||
155 | cal_pier_data_2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; | ||
156 | |||
157 | /* power calibration data */ | ||
158 | struct ar9170_calibration_target_power_legacy | ||
159 | cal_tgt_pwr_5G[AR5416_NUM_5G_TARGET_PWRS]; | ||
160 | struct ar9170_calibration_target_power_ht | ||
161 | cal_tgt_pwr_5G_ht20[AR5416_NUM_5G_TARGET_PWRS], | ||
162 | cal_tgt_pwr_5G_ht40[AR5416_NUM_5G_TARGET_PWRS]; | ||
163 | |||
164 | struct ar9170_calibration_target_power_legacy | ||
165 | cal_tgt_pwr_2G_cck[AR5416_NUM_2G_CCK_TARGET_PWRS], | ||
166 | cal_tgt_pwr_2G_ofdm[AR5416_NUM_2G_OFDM_TARGET_PWRS]; | ||
167 | struct ar9170_calibration_target_power_ht | ||
168 | cal_tgt_pwr_2G_ht20[AR5416_NUM_2G_OFDM_TARGET_PWRS], | ||
169 | cal_tgt_pwr_2G_ht40[AR5416_NUM_2G_OFDM_TARGET_PWRS]; | ||
170 | |||
171 | /* conformance testing limits */ | ||
172 | u8 ctl_index[AR5416_NUM_CTLS]; | ||
173 | struct ar9170_calctl_data | ||
174 | ctl_data[AR5416_NUM_CTLS]; | ||
175 | |||
176 | u8 pad; | ||
177 | __le16 subsystem_id; | ||
178 | } __packed; | ||
179 | |||
180 | #define AR9170_LED_MODE_POWER_ON 0x0001 | ||
181 | #define AR9170_LED_MODE_RESERVED 0x0002 | ||
182 | #define AR9170_LED_MODE_DISABLE_STATE 0x0004 | ||
183 | #define AR9170_LED_MODE_OFF_IN_PSM 0x0008 | ||
184 | |||
185 | /* AR9170_LED_MODE BIT is set */ | ||
186 | #define AR9170_LED_MODE_FREQUENCY_S 4 | ||
187 | #define AR9170_LED_MODE_FREQUENCY 0x0030 | ||
188 | #define AR9170_LED_MODE_FREQUENCY_1HZ 0x0000 | ||
189 | #define AR9170_LED_MODE_FREQUENCY_0_5HZ 0x0010 | ||
190 | #define AR9170_LED_MODE_FREQUENCY_0_25HZ 0x0020 | ||
191 | #define AR9170_LED_MODE_FREQUENCY_0_125HZ 0x0030 | ||
192 | |||
193 | /* AR9170_LED_MODE BIT is not set */ | ||
194 | #define AR9170_LED_MODE_CONN_STATE_S 4 | ||
195 | #define AR9170_LED_MODE_CONN_STATE 0x0030 | ||
196 | #define AR9170_LED_MODE_CONN_STATE_FORCE_OFF 0x0000 | ||
197 | #define AR9170_LED_MODE_CONN_STATE_FORCE_ON 0x0010 | ||
198 | /* Idle off / Active on */ | ||
199 | #define AR9170_LED_MODE_CONN_STATE_IOFF_AON 0x0020 | ||
200 | /* Idle on / Active off */ | ||
201 | #define AR9170_LED_MODE_CONN_STATE_ION_AOFF 0x0010 | ||
202 | |||
203 | #define AR9170_LED_MODE_MODE 0x0040 | ||
204 | #define AR9170_LED_MODE_RESERVED2 0x0080 | ||
205 | |||
206 | #define AR9170_LED_MODE_TON_SCAN_S 8 | ||
207 | #define AR9170_LED_MODE_TON_SCAN 0x0f00 | ||
208 | |||
209 | #define AR9170_LED_MODE_TOFF_SCAN_S 12 | ||
210 | #define AR9170_LED_MODE_TOFF_SCAN 0xf000 | ||
211 | |||
212 | struct ar9170_led_mode { | ||
213 | __le16 led; | ||
214 | }; | ||
215 | |||
216 | #endif /* __CARL9170_SHARED_EEPROM_H */ | ||
diff --git a/drivers/net/wireless/ath/carl9170/fwcmd.h b/drivers/net/wireless/ath/carl9170/fwcmd.h new file mode 100644 index 000000000000..d4a4e1dbef06 --- /dev/null +++ b/drivers/net/wireless/ath/carl9170/fwcmd.h | |||
@@ -0,0 +1,268 @@ | |||
1 | /* | ||
2 | * Shared Atheros AR9170 Header | ||
3 | * | ||
4 | * Firmware command interface definitions | ||
5 | * | ||
6 | * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> | ||
7 | * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, see | ||
20 | * http://www.gnu.org/licenses/. | ||
21 | * | ||
22 | * This file incorporates work covered by the following copyright and | ||
23 | * permission notice: | ||
24 | * Copyright (c) 2007-2008 Atheros Communications, Inc. | ||
25 | * | ||
26 | * Permission to use, copy, modify, and/or distribute this software for any | ||
27 | * purpose with or without fee is hereby granted, provided that the above | ||
28 | * copyright notice and this permission notice appear in all copies. | ||
29 | * | ||
30 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
31 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
32 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
33 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
34 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
35 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
36 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
37 | */ | ||
38 | |||
39 | #ifndef __CARL9170_SHARED_FWCMD_H | ||
40 | #define __CARL9170_SHARED_FWCMD_H | ||
41 | |||
42 | #define CARL9170_MAX_CMD_LEN 64 | ||
43 | #define CARL9170_MAX_CMD_PAYLOAD_LEN 60 | ||
44 | |||
45 | #define CARL9170FW_API_MIN_VER 1 | ||
46 | #define CARL9170FW_API_MAX_VER 1 | ||
47 | |||
48 | enum carl9170_cmd_oids { | ||
49 | CARL9170_CMD_RREG = 0x00, | ||
50 | CARL9170_CMD_WREG = 0x01, | ||
51 | CARL9170_CMD_ECHO = 0x02, | ||
52 | CARL9170_CMD_SWRST = 0x03, | ||
53 | CARL9170_CMD_REBOOT = 0x04, | ||
54 | CARL9170_CMD_BCN_CTRL = 0x05, | ||
55 | CARL9170_CMD_READ_TSF = 0x06, | ||
56 | |||
57 | /* CAM */ | ||
58 | CARL9170_CMD_EKEY = 0x10, | ||
59 | CARL9170_CMD_DKEY = 0x11, | ||
60 | |||
61 | /* RF / PHY */ | ||
62 | CARL9170_CMD_FREQUENCY = 0x20, | ||
63 | CARL9170_CMD_RF_INIT = 0x21, | ||
64 | CARL9170_CMD_SYNTH = 0x22, | ||
65 | CARL9170_CMD_FREQ_START = 0x23, | ||
66 | CARL9170_CMD_PSM = 0x24, | ||
67 | |||
68 | /* Asychronous command flag */ | ||
69 | CARL9170_CMD_ASYNC_FLAG = 0x40, | ||
70 | CARL9170_CMD_WREG_ASYNC = (CARL9170_CMD_WREG | | ||
71 | CARL9170_CMD_ASYNC_FLAG), | ||
72 | CARL9170_CMD_REBOOT_ASYNC = (CARL9170_CMD_REBOOT | | ||
73 | CARL9170_CMD_ASYNC_FLAG), | ||
74 | CARL9170_CMD_BCN_CTRL_ASYNC = (CARL9170_CMD_BCN_CTRL | | ||
75 | CARL9170_CMD_ASYNC_FLAG), | ||
76 | CARL9170_CMD_PSM_ASYNC = (CARL9170_CMD_PSM | | ||
77 | CARL9170_CMD_ASYNC_FLAG), | ||
78 | |||
79 | /* responses and traps */ | ||
80 | CARL9170_RSP_FLAG = 0xc0, | ||
81 | CARL9170_RSP_PRETBTT = 0xc0, | ||
82 | CARL9170_RSP_TXCOMP = 0xc1, | ||
83 | CARL9170_RSP_BEACON_CONFIG = 0xc2, | ||
84 | CARL9170_RSP_ATIM = 0xc3, | ||
85 | CARL9170_RSP_WATCHDOG = 0xc6, | ||
86 | CARL9170_RSP_TEXT = 0xca, | ||
87 | CARL9170_RSP_HEXDUMP = 0xcc, | ||
88 | CARL9170_RSP_RADAR = 0xcd, | ||
89 | CARL9170_RSP_GPIO = 0xce, | ||
90 | CARL9170_RSP_BOOT = 0xcf, | ||
91 | }; | ||
92 | |||
93 | struct carl9170_set_key_cmd { | ||
94 | __le16 user; | ||
95 | __le16 keyId; | ||
96 | __le16 type; | ||
97 | u8 macAddr[6]; | ||
98 | u32 key[4]; | ||
99 | } __packed; | ||
100 | #define CARL9170_SET_KEY_CMD_SIZE 28 | ||
101 | |||
102 | struct carl9170_disable_key_cmd { | ||
103 | __le16 user; | ||
104 | __le16 padding; | ||
105 | } __packed; | ||
106 | #define CARL9170_DISABLE_KEY_CMD_SIZE 4 | ||
107 | |||
108 | struct carl9170_u32_list { | ||
109 | u32 vals[0]; | ||
110 | } __packed; | ||
111 | |||
112 | struct carl9170_reg_list { | ||
113 | __le32 regs[0]; | ||
114 | } __packed; | ||
115 | |||
116 | struct carl9170_write_reg { | ||
117 | struct { | ||
118 | __le32 addr; | ||
119 | __le32 val; | ||
120 | } regs[0] __packed; | ||
121 | } __packed; | ||
122 | |||
123 | #define CARL9170FW_PHY_HT_ENABLE 0x4 | ||
124 | #define CARL9170FW_PHY_HT_DYN2040 0x8 | ||
125 | #define CARL9170FW_PHY_HT_EXT_CHAN_OFF 0x3 | ||
126 | #define CARL9170FW_PHY_HT_EXT_CHAN_OFF_S 2 | ||
127 | |||
128 | struct carl9170_rf_init { | ||
129 | __le32 freq; | ||
130 | u8 ht_settings; | ||
131 | u8 padding2[3]; | ||
132 | __le32 delta_slope_coeff_exp; | ||
133 | __le32 delta_slope_coeff_man; | ||
134 | __le32 delta_slope_coeff_exp_shgi; | ||
135 | __le32 delta_slope_coeff_man_shgi; | ||
136 | __le32 finiteLoopCount; | ||
137 | } __packed; | ||
138 | #define CARL9170_RF_INIT_SIZE 28 | ||
139 | |||
140 | struct carl9170_rf_init_result { | ||
141 | __le32 ret; /* AR9170_PHY_REG_AGC_CONTROL */ | ||
142 | } __packed; | ||
143 | #define CARL9170_RF_INIT_RESULT_SIZE 4 | ||
144 | |||
145 | #define CARL9170_PSM_SLEEP 0x1000 | ||
146 | #define CARL9170_PSM_SOFTWARE 0 | ||
147 | #define CARL9170_PSM_WAKE 0 /* internally used. */ | ||
148 | #define CARL9170_PSM_COUNTER 0xfff | ||
149 | #define CARL9170_PSM_COUNTER_S 0 | ||
150 | |||
151 | struct carl9170_psm { | ||
152 | __le32 state; | ||
153 | } __packed; | ||
154 | #define CARL9170_PSM_SIZE 4 | ||
155 | |||
156 | struct carl9170_bcn_ctrl_cmd { | ||
157 | __le32 vif_id; | ||
158 | __le32 mode; | ||
159 | __le32 bcn_addr; | ||
160 | __le32 bcn_len; | ||
161 | } __packed; | ||
162 | #define CARL9170_BCN_CTRL_CMD_SIZE 16 | ||
163 | |||
164 | #define CARL9170_BCN_CTRL_DRAIN 0 | ||
165 | #define CARL9170_BCN_CTRL_CAB_TRIGGER 1 | ||
166 | |||
167 | struct carl9170_cmd_head { | ||
168 | union { | ||
169 | struct { | ||
170 | u8 len; | ||
171 | u8 cmd; | ||
172 | u8 seq; | ||
173 | u8 ext; | ||
174 | } __packed; | ||
175 | |||
176 | u32 hdr_data; | ||
177 | } __packed; | ||
178 | } __packed; | ||
179 | |||
180 | struct carl9170_cmd { | ||
181 | struct carl9170_cmd_head hdr; | ||
182 | union { | ||
183 | struct carl9170_set_key_cmd setkey; | ||
184 | struct carl9170_disable_key_cmd disablekey; | ||
185 | struct carl9170_u32_list echo; | ||
186 | struct carl9170_reg_list rreg; | ||
187 | struct carl9170_write_reg wreg; | ||
188 | struct carl9170_rf_init rf_init; | ||
189 | struct carl9170_psm psm; | ||
190 | struct carl9170_bcn_ctrl_cmd bcn_ctrl; | ||
191 | u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN]; | ||
192 | } __packed; | ||
193 | } __packed; | ||
194 | |||
195 | #define CARL9170_TX_STATUS_QUEUE 3 | ||
196 | #define CARL9170_TX_STATUS_QUEUE_S 0 | ||
197 | #define CARL9170_TX_STATUS_RIX_S 2 | ||
198 | #define CARL9170_TX_STATUS_RIX (3 << CARL9170_TX_STATUS_RIX_S) | ||
199 | #define CARL9170_TX_STATUS_TRIES_S 4 | ||
200 | #define CARL9170_TX_STATUS_TRIES (7 << CARL9170_TX_STATUS_TRIES_S) | ||
201 | #define CARL9170_TX_STATUS_SUCCESS 0x80 | ||
202 | |||
203 | /* | ||
204 | * NOTE: | ||
205 | * Both structs [carl9170_tx_status and _carl9170_tx_status] | ||
206 | * need to be "bit for bit" in sync. | ||
207 | */ | ||
208 | struct carl9170_tx_status { | ||
209 | /* | ||
210 | * Beware of compiler bugs in all gcc pre 4.4! | ||
211 | */ | ||
212 | |||
213 | u8 cookie; | ||
214 | u8 queue:2; | ||
215 | u8 rix:2; | ||
216 | u8 tries:3; | ||
217 | u8 success:1; | ||
218 | } __packed; | ||
219 | struct _carl9170_tx_status { | ||
220 | /* | ||
221 | * This version should be immune to all alignment bugs. | ||
222 | */ | ||
223 | |||
224 | u8 cookie; | ||
225 | u8 info; | ||
226 | } __packed; | ||
227 | #define CARL9170_TX_STATUS_SIZE 2 | ||
228 | |||
229 | #define CARL9170_RSP_TX_STATUS_NUM (CARL9170_MAX_CMD_PAYLOAD_LEN / \ | ||
230 | sizeof(struct _carl9170_tx_status)) | ||
231 | |||
232 | #define CARL9170_TX_MAX_RATE_TRIES 7 | ||
233 | |||
234 | #define CARL9170_TX_MAX_RATES 4 | ||
235 | #define CARL9170_TX_MAX_RETRY_RATES (CARL9170_TX_MAX_RATES - 1) | ||
236 | #define CARL9170_ERR_MAGIC "ERR:" | ||
237 | #define CARL9170_BUG_MAGIC "BUG:" | ||
238 | |||
239 | struct carl9170_gpio { | ||
240 | __le32 gpio; | ||
241 | } __packed; | ||
242 | #define CARL9170_GPIO_SIZE 4 | ||
243 | |||
244 | struct carl9170_tsf_rsp { | ||
245 | union { | ||
246 | __le32 tsf[2]; | ||
247 | __le64 tsf_64; | ||
248 | } __packed; | ||
249 | } __packed; | ||
250 | #define CARL9170_TSF_RSP_SIZE 8 | ||
251 | |||
252 | struct carl9170_rsp { | ||
253 | struct carl9170_cmd_head hdr; | ||
254 | |||
255 | union { | ||
256 | struct carl9170_rf_init_result rf_init_res; | ||
257 | struct carl9170_u32_list rreg_res; | ||
258 | struct carl9170_u32_list echo; | ||
259 | struct carl9170_tx_status tx_status[0]; | ||
260 | struct _carl9170_tx_status _tx_status[0]; | ||
261 | struct carl9170_gpio gpio; | ||
262 | struct carl9170_tsf_rsp tsf; | ||
263 | struct carl9170_psm psm; | ||
264 | u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN]; | ||
265 | } __packed; | ||
266 | } __packed; | ||
267 | |||
268 | #endif /* __CARL9170_SHARED_FWCMD_H */ | ||
diff --git a/drivers/net/wireless/ath/carl9170/fwdesc.h b/drivers/net/wireless/ath/carl9170/fwdesc.h new file mode 100644 index 000000000000..7cd811708fe5 --- /dev/null +++ b/drivers/net/wireless/ath/carl9170/fwdesc.h | |||
@@ -0,0 +1,237 @@ | |||
1 | /* | ||
2 | * Shared CARL9170 Header | ||
3 | * | ||
4 | * Firmware descriptor format | ||
5 | * | ||
6 | * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; see the file COPYING. If not, see | ||
19 | * http://www.gnu.org/licenses/. | ||
20 | */ | ||
21 | |||
22 | #ifndef __CARL9170_SHARED_FWDESC_H | ||
23 | #define __CARL9170_SHARED_FWDESC_H | ||
24 | |||
25 | /* NOTE: Don't mess with the order of the flags! */ | ||
26 | enum carl9170fw_feature_list { | ||
27 | /* Always set */ | ||
28 | CARL9170FW_DUMMY_FEATURE, | ||
29 | |||
30 | /* | ||
31 | * Indicates that this image has special boot block which prevents | ||
32 | * legacy drivers to drive the firmware. | ||
33 | */ | ||
34 | CARL9170FW_MINIBOOT, | ||
35 | |||
36 | /* usb registers are initialized by the firmware */ | ||
37 | CARL9170FW_USB_INIT_FIRMWARE, | ||
38 | |||
39 | /* command traps & notifications are send through EP2 */ | ||
40 | CARL9170FW_USB_RESP_EP2, | ||
41 | |||
42 | /* usb download (app -> fw) stream */ | ||
43 | CARL9170FW_USB_DOWN_STREAM, | ||
44 | |||
45 | /* usb upload (fw -> app) stream */ | ||
46 | CARL9170FW_USB_UP_STREAM, | ||
47 | |||
48 | /* unusable - reserved to flag non-functional debug firmwares */ | ||
49 | CARL9170FW_UNUSABLE, | ||
50 | |||
51 | /* AR9170_CMD_RF_INIT, AR9170_CMD_FREQ_START, AR9170_CMD_FREQUENCY */ | ||
52 | CARL9170FW_COMMAND_PHY, | ||
53 | |||
54 | /* AR9170_CMD_EKEY, AR9170_CMD_DKEY */ | ||
55 | CARL9170FW_COMMAND_CAM, | ||
56 | |||
57 | /* Firmware has a software Content After Beacon Queueing mechanism */ | ||
58 | CARL9170FW_WLANTX_CAB, | ||
59 | |||
60 | /* The firmware is capable of responding to incoming BAR frames */ | ||
61 | CARL9170FW_HANDLE_BACK_REQ, | ||
62 | |||
63 | /* GPIO Interrupt | CARL9170_RSP_GPIO */ | ||
64 | CARL9170FW_GPIO_INTERRUPT, | ||
65 | |||
66 | /* Firmware PSM support | CARL9170_CMD_PSM */ | ||
67 | CARL9170FW_PSM, | ||
68 | |||
69 | /* KEEP LAST */ | ||
70 | __CARL9170FW_FEATURE_NUM | ||
71 | }; | ||
72 | |||
73 | #define OTUS_MAGIC "OTAR" | ||
74 | #define MOTD_MAGIC "MOTD" | ||
75 | #define FIX_MAGIC "FIX\0" | ||
76 | #define DBG_MAGIC "DBG\0" | ||
77 | #define CHK_MAGIC "CHK\0" | ||
78 | #define LAST_MAGIC "LAST" | ||
79 | |||
80 | #define CARL9170FW_SET_DAY(d) (((d) - 1) % 31) | ||
81 | #define CARL9170FW_SET_MONTH(m) ((((m) - 1) % 12) * 31) | ||
82 | #define CARL9170FW_SET_YEAR(y) (((y) - 10) * 372) | ||
83 | |||
84 | #define CARL9170FW_GET_DAY(d) (((d) % 31) + 1) | ||
85 | #define CARL9170FW_GET_MONTH(m) ((((m) / 31) % 12) + 1) | ||
86 | #define CARL9170FW_GET_YEAR(y) ((y) / 372 + 10) | ||
87 | |||
88 | struct carl9170fw_desc_head { | ||
89 | u8 magic[4]; | ||
90 | __le16 length; | ||
91 | u8 min_ver; | ||
92 | u8 cur_ver; | ||
93 | } __packed; | ||
94 | #define CARL9170FW_DESC_HEAD_SIZE \ | ||
95 | (sizeof(struct carl9170fw_desc_head)) | ||
96 | |||
97 | #define CARL9170FW_OTUS_DESC_MIN_VER 6 | ||
98 | #define CARL9170FW_OTUS_DESC_CUR_VER 6 | ||
99 | struct carl9170fw_otus_desc { | ||
100 | struct carl9170fw_desc_head head; | ||
101 | __le32 feature_set; | ||
102 | __le32 fw_address; | ||
103 | __le32 bcn_addr; | ||
104 | __le16 bcn_len; | ||
105 | __le16 miniboot_size; | ||
106 | __le16 tx_frag_len; | ||
107 | __le16 rx_max_frame_len; | ||
108 | u8 tx_descs; | ||
109 | u8 cmd_bufs; | ||
110 | u8 api_ver; | ||
111 | u8 vif_num; | ||
112 | } __packed; | ||
113 | #define CARL9170FW_OTUS_DESC_SIZE \ | ||
114 | (sizeof(struct carl9170fw_otus_desc)) | ||
115 | |||
116 | #define CARL9170FW_MOTD_STRING_LEN 24 | ||
117 | #define CARL9170FW_MOTD_RELEASE_LEN 20 | ||
118 | #define CARL9170FW_MOTD_DESC_MIN_VER 1 | ||
119 | #define CARL9170FW_MOTD_DESC_CUR_VER 2 | ||
120 | struct carl9170fw_motd_desc { | ||
121 | struct carl9170fw_desc_head head; | ||
122 | __le32 fw_year_month_day; | ||
123 | char desc[CARL9170FW_MOTD_STRING_LEN]; | ||
124 | char release[CARL9170FW_MOTD_RELEASE_LEN]; | ||
125 | } __packed; | ||
126 | #define CARL9170FW_MOTD_DESC_SIZE \ | ||
127 | (sizeof(struct carl9170fw_motd_desc)) | ||
128 | |||
129 | #define CARL9170FW_FIX_DESC_MIN_VER 1 | ||
130 | #define CARL9170FW_FIX_DESC_CUR_VER 2 | ||
131 | struct carl9170fw_fix_entry { | ||
132 | __le32 address; | ||
133 | __le32 mask; | ||
134 | __le32 value; | ||
135 | } __packed; | ||
136 | |||
137 | struct carl9170fw_fix_desc { | ||
138 | struct carl9170fw_desc_head head; | ||
139 | struct carl9170fw_fix_entry data[0]; | ||
140 | } __packed; | ||
141 | #define CARL9170FW_FIX_DESC_SIZE \ | ||
142 | (sizeof(struct carl9170fw_fix_desc)) | ||
143 | |||
144 | #define CARL9170FW_DBG_DESC_MIN_VER 1 | ||
145 | #define CARL9170FW_DBG_DESC_CUR_VER 2 | ||
146 | struct carl9170fw_dbg_desc { | ||
147 | struct carl9170fw_desc_head head; | ||
148 | |||
149 | __le32 bogoclock_addr; | ||
150 | __le32 counter_addr; | ||
151 | __le32 rx_total_addr; | ||
152 | __le32 rx_overrun_addr; | ||
153 | |||
154 | /* Put your debugging definitions here */ | ||
155 | } __packed; | ||
156 | #define CARL9170FW_DBG_DESC_SIZE \ | ||
157 | (sizeof(struct carl9170fw_dbg_desc)) | ||
158 | |||
159 | #define CARL9170FW_CHK_DESC_MIN_VER 1 | ||
160 | #define CARL9170FW_CHK_DESC_CUR_VER 2 | ||
161 | struct carl9170fw_chk_desc { | ||
162 | struct carl9170fw_desc_head head; | ||
163 | __le32 fw_crc32; | ||
164 | __le32 hdr_crc32; | ||
165 | } __packed; | ||
166 | #define CARL9170FW_CHK_DESC_SIZE \ | ||
167 | (sizeof(struct carl9170fw_chk_desc)) | ||
168 | |||
169 | #define CARL9170FW_LAST_DESC_MIN_VER 1 | ||
170 | #define CARL9170FW_LAST_DESC_CUR_VER 2 | ||
171 | struct carl9170fw_last_desc { | ||
172 | struct carl9170fw_desc_head head; | ||
173 | } __packed; | ||
174 | #define CARL9170FW_LAST_DESC_SIZE \ | ||
175 | (sizeof(struct carl9170fw_fix_desc)) | ||
176 | |||
177 | #define CARL9170FW_DESC_MAX_LENGTH 8192 | ||
178 | |||
179 | #define CARL9170FW_FILL_DESC(_magic, _length, _min_ver, _cur_ver) \ | ||
180 | .head = { \ | ||
181 | .magic = _magic, \ | ||
182 | .length = cpu_to_le16(_length), \ | ||
183 | .min_ver = _min_ver, \ | ||
184 | .cur_ver = _cur_ver, \ | ||
185 | } | ||
186 | |||
187 | static inline void carl9170fw_fill_desc(struct carl9170fw_desc_head *head, | ||
188 | u8 magic[4], __le16 length, | ||
189 | u8 min_ver, u8 cur_ver) | ||
190 | { | ||
191 | head->magic[0] = magic[0]; | ||
192 | head->magic[1] = magic[1]; | ||
193 | head->magic[2] = magic[2]; | ||
194 | head->magic[3] = magic[3]; | ||
195 | |||
196 | head->length = length; | ||
197 | head->min_ver = min_ver; | ||
198 | head->cur_ver = cur_ver; | ||
199 | } | ||
200 | |||
201 | #define carl9170fw_for_each_hdr(desc, fw_desc) \ | ||
202 | for (desc = fw_desc; \ | ||
203 | memcmp(desc->magic, LAST_MAGIC, 4) && \ | ||
204 | le16_to_cpu(desc->length) >= CARL9170FW_DESC_HEAD_SIZE && \ | ||
205 | le16_to_cpu(desc->length) < CARL9170FW_DESC_MAX_LENGTH; \ | ||
206 | desc = (void *)((unsigned long)desc + le16_to_cpu(desc->length))) | ||
207 | |||
208 | #define CHECK_HDR_VERSION(head, _min_ver) \ | ||
209 | (((head)->cur_ver < _min_ver) || ((head)->min_ver > _min_ver)) \ | ||
210 | |||
211 | static inline bool carl9170fw_supports(__le32 list, u8 feature) | ||
212 | { | ||
213 | return le32_to_cpu(list) & BIT(feature); | ||
214 | } | ||
215 | |||
216 | static inline bool carl9170fw_desc_cmp(const struct carl9170fw_desc_head *head, | ||
217 | const u8 descid[4], u16 min_len, | ||
218 | u8 compatible_revision) | ||
219 | { | ||
220 | if (descid[0] == head->magic[0] && descid[1] == head->magic[1] && | ||
221 | descid[2] == head->magic[2] && descid[3] == head->magic[3] && | ||
222 | !CHECK_HDR_VERSION(head, compatible_revision) && | ||
223 | (le16_to_cpu(head->length) >= min_len)) | ||
224 | return true; | ||
225 | |||
226 | return false; | ||
227 | } | ||
228 | |||
229 | #define CARL9170FW_MIN_SIZE 32 | ||
230 | #define CARL9170FW_MAX_SIZE 16384 | ||
231 | |||
232 | static inline bool carl9170fw_size_check(unsigned int len) | ||
233 | { | ||
234 | return (len <= CARL9170FW_MAX_SIZE && len >= CARL9170FW_MIN_SIZE); | ||
235 | } | ||
236 | |||
237 | #endif /* __CARL9170_SHARED_FWDESC_H */ | ||
diff --git a/drivers/net/wireless/ath/carl9170/hw.h b/drivers/net/wireless/ath/carl9170/hw.h new file mode 100644 index 000000000000..b1292ac5b703 --- /dev/null +++ b/drivers/net/wireless/ath/carl9170/hw.h | |||
@@ -0,0 +1,736 @@ | |||
1 | /* | ||
2 | * Shared Atheros AR9170 Header | ||
3 | * | ||
4 | * Register map, hardware-specific definitions | ||
5 | * | ||
6 | * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> | ||
7 | * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, see | ||
20 | * http://www.gnu.org/licenses/. | ||
21 | * | ||
22 | * This file incorporates work covered by the following copyright and | ||
23 | * permission notice: | ||
24 | * Copyright (c) 2007-2008 Atheros Communications, Inc. | ||
25 | * | ||
26 | * Permission to use, copy, modify, and/or distribute this software for any | ||
27 | * purpose with or without fee is hereby granted, provided that the above | ||
28 | * copyright notice and this permission notice appear in all copies. | ||
29 | * | ||
30 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
31 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
32 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
33 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
34 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
35 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
36 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
37 | */ | ||
38 | |||
39 | #ifndef __CARL9170_SHARED_HW_H | ||
40 | #define __CARL9170_SHARED_HW_H | ||
41 | |||
42 | /* High Speed UART */ | ||
43 | #define AR9170_UART_REG_BASE 0x1c0000 | ||
44 | |||
45 | /* Definitions of interrupt registers */ | ||
46 | #define AR9170_UART_REG_RX_BUFFER (AR9170_UART_REG_BASE + 0x000) | ||
47 | #define AR9170_UART_REG_TX_HOLDING (AR9170_UART_REG_BASE + 0x004) | ||
48 | #define AR9170_UART_REG_FIFO_CONTROL (AR9170_UART_REG_BASE + 0x010) | ||
49 | #define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO 0x02 | ||
50 | #define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO 0x04 | ||
51 | |||
52 | #define AR9170_UART_REG_LINE_CONTROL (AR9170_UART_REG_BASE + 0x014) | ||
53 | #define AR9170_UART_REG_MODEM_CONTROL (AR9170_UART_REG_BASE + 0x018) | ||
54 | #define AR9170_UART_MODEM_CTRL_DTR_BIT 0x01 | ||
55 | #define AR9170_UART_MODEM_CTRL_RTS_BIT 0x02 | ||
56 | #define AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK 0x10 | ||
57 | #define AR9170_UART_MODEM_CTRL_AUTO_RTS 0x20 | ||
58 | #define AR9170_UART_MODEM_CTRL_AUTO_CTR 0x40 | ||
59 | |||
60 | #define AR9170_UART_REG_LINE_STATUS (AR9170_UART_REG_BASE + 0x01c) | ||
61 | #define AR9170_UART_LINE_STS_RX_DATA_READY 0x01 | ||
62 | #define AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN 0x02 | ||
63 | #define AR9170_UART_LINE_STS_RX_BREAK_IND 0x10 | ||
64 | #define AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY 0x20 | ||
65 | #define AR9170_UART_LINE_STS_TRANSMITTER_EMPTY 0x40 | ||
66 | |||
67 | #define AR9170_UART_REG_MODEM_STATUS (AR9170_UART_REG_BASE + 0x020) | ||
68 | #define AR9170_UART_MODEM_STS_CTS_CHANGE 0x01 | ||
69 | #define AR9170_UART_MODEM_STS_DSR_CHANGE 0x02 | ||
70 | #define AR9170_UART_MODEM_STS_DCD_CHANGE 0x08 | ||
71 | #define AR9170_UART_MODEM_STS_CTS_COMPL 0x10 | ||
72 | #define AR9170_UART_MODEM_STS_DSR_COMPL 0x20 | ||
73 | #define AR9170_UART_MODEM_STS_DCD_COMPL 0x80 | ||
74 | |||
75 | #define AR9170_UART_REG_SCRATCH (AR9170_UART_REG_BASE + 0x024) | ||
76 | #define AR9170_UART_REG_DIVISOR_LSB (AR9170_UART_REG_BASE + 0x028) | ||
77 | #define AR9170_UART_REG_DIVISOR_MSB (AR9170_UART_REG_BASE + 0x02c) | ||
78 | #define AR9170_UART_REG_WORD_RX_BUFFER (AR9170_UART_REG_BASE + 0x034) | ||
79 | #define AR9170_UART_REG_WORD_TX_HOLDING (AR9170_UART_REG_BASE + 0x038) | ||
80 | #define AR9170_UART_REG_FIFO_COUNT (AR9170_UART_REG_BASE + 0x03c) | ||
81 | #define AR9170_UART_REG_REMAINDER (AR9170_UART_REG_BASE + 0x04c) | ||
82 | |||
83 | /* Timer */ | ||
84 | #define AR9170_TIMER_REG_BASE 0x1c1000 | ||
85 | |||
86 | #define AR9170_TIMER_REG_WATCH_DOG (AR9170_TIMER_REG_BASE + 0x000) | ||
87 | #define AR9170_TIMER_REG_TIMER0 (AR9170_TIMER_REG_BASE + 0x010) | ||
88 | #define AR9170_TIMER_REG_TIMER1 (AR9170_TIMER_REG_BASE + 0x014) | ||
89 | #define AR9170_TIMER_REG_TIMER2 (AR9170_TIMER_REG_BASE + 0x018) | ||
90 | #define AR9170_TIMER_REG_TIMER3 (AR9170_TIMER_REG_BASE + 0x01c) | ||
91 | #define AR9170_TIMER_REG_TIMER4 (AR9170_TIMER_REG_BASE + 0x020) | ||
92 | #define AR9170_TIMER_REG_CONTROL (AR9170_TIMER_REG_BASE + 0x024) | ||
93 | #define AR9170_TIMER_CTRL_DISABLE_CLOCK 0x100 | ||
94 | |||
95 | #define AR9170_TIMER_REG_INTERRUPT (AR9170_TIMER_REG_BASE + 0x028) | ||
96 | #define AR9170_TIMER_INT_TIMER0 0x001 | ||
97 | #define AR9170_TIMER_INT_TIMER1 0x002 | ||
98 | #define AR9170_TIMER_INT_TIMER2 0x004 | ||
99 | #define AR9170_TIMER_INT_TIMER3 0x008 | ||
100 | #define AR9170_TIMER_INT_TIMER4 0x010 | ||
101 | #define AR9170_TIMER_INT_TICK_TIMER 0x100 | ||
102 | |||
103 | #define AR9170_TIMER_REG_TICK_TIMER (AR9170_TIMER_REG_BASE + 0x030) | ||
104 | #define AR9170_TIMER_REG_CLOCK_LOW (AR9170_TIMER_REG_BASE + 0x040) | ||
105 | #define AR9170_TIMER_REG_CLOCK_HIGH (AR9170_TIMER_REG_BASE + 0x044) | ||
106 | |||
107 | #define AR9170_MAC_REG_BASE 0x1c3000 | ||
108 | |||
109 | #define AR9170_MAC_REG_POWER_STATE_CTRL (AR9170_MAC_REG_BASE + 0x500) | ||
110 | #define AR9170_MAC_POWER_STATE_CTRL_RESET 0x20 | ||
111 | |||
112 | #define AR9170_MAC_REG_MAC_POWER_STATE_CTRL (AR9170_MAC_REG_BASE + 0x50c) | ||
113 | |||
114 | #define AR9170_MAC_REG_INT_CTRL (AR9170_MAC_REG_BASE + 0x510) | ||
115 | #define AR9170_MAC_INT_TXC BIT(0) | ||
116 | #define AR9170_MAC_INT_RXC BIT(1) | ||
117 | #define AR9170_MAC_INT_RETRY_FAIL BIT(2) | ||
118 | #define AR9170_MAC_INT_WAKEUP BIT(3) | ||
119 | #define AR9170_MAC_INT_ATIM BIT(4) | ||
120 | #define AR9170_MAC_INT_DTIM BIT(5) | ||
121 | #define AR9170_MAC_INT_CFG_BCN BIT(6) | ||
122 | #define AR9170_MAC_INT_ABORT BIT(7) | ||
123 | #define AR9170_MAC_INT_QOS BIT(8) | ||
124 | #define AR9170_MAC_INT_MIMO_PS BIT(9) | ||
125 | #define AR9170_MAC_INT_KEY_GEN BIT(10) | ||
126 | #define AR9170_MAC_INT_DECRY_NOUSER BIT(11) | ||
127 | #define AR9170_MAC_INT_RADAR BIT(12) | ||
128 | #define AR9170_MAC_INT_QUIET_FRAME BIT(13) | ||
129 | #define AR9170_MAC_INT_PRETBTT BIT(14) | ||
130 | |||
131 | #define AR9170_MAC_REG_TSF_L (AR9170_MAC_REG_BASE + 0x514) | ||
132 | #define AR9170_MAC_REG_TSF_H (AR9170_MAC_REG_BASE + 0x518) | ||
133 | |||
134 | #define AR9170_MAC_REG_ATIM_WINDOW (AR9170_MAC_REG_BASE + 0x51c) | ||
135 | #define AR9170_MAC_ATIM_PERIOD_S 0 | ||
136 | #define AR9170_MAC_ATIM_PERIOD 0x0000ffff | ||
137 | |||
138 | #define AR9170_MAC_REG_BCN_PERIOD (AR9170_MAC_REG_BASE + 0x520) | ||
139 | #define AR9170_MAC_BCN_PERIOD_S 0 | ||
140 | #define AR9170_MAC_BCN_PERIOD 0x0000ffff | ||
141 | #define AR9170_MAC_BCN_DTIM_S 16 | ||
142 | #define AR9170_MAC_BCN_DTIM 0x00ff0000 | ||
143 | #define AR9170_MAC_BCN_AP_MODE BIT(24) | ||
144 | #define AR9170_MAC_BCN_IBSS_MODE BIT(25) | ||
145 | #define AR9170_MAC_BCN_PWR_MGT BIT(26) | ||
146 | #define AR9170_MAC_BCN_STA_PS BIT(27) | ||
147 | |||
148 | #define AR9170_MAC_REG_PRETBTT (AR9170_MAC_REG_BASE + 0x524) | ||
149 | #define AR9170_MAC_PRETBTT_S 0 | ||
150 | #define AR9170_MAC_PRETBTT 0x0000ffff | ||
151 | #define AR9170_MAC_PRETBTT2_S 16 | ||
152 | #define AR9170_MAC_PRETBTT2 0xffff0000 | ||
153 | |||
154 | #define AR9170_MAC_REG_MAC_ADDR_L (AR9170_MAC_REG_BASE + 0x610) | ||
155 | #define AR9170_MAC_REG_MAC_ADDR_H (AR9170_MAC_REG_BASE + 0x614) | ||
156 | #define AR9170_MAC_REG_BSSID_L (AR9170_MAC_REG_BASE + 0x618) | ||
157 | #define AR9170_MAC_REG_BSSID_H (AR9170_MAC_REG_BASE + 0x61c) | ||
158 | |||
159 | #define AR9170_MAC_REG_GROUP_HASH_TBL_L (AR9170_MAC_REG_BASE + 0x624) | ||
160 | #define AR9170_MAC_REG_GROUP_HASH_TBL_H (AR9170_MAC_REG_BASE + 0x628) | ||
161 | |||
162 | #define AR9170_MAC_REG_RX_TIMEOUT (AR9170_MAC_REG_BASE + 0x62c) | ||
163 | |||
164 | #define AR9170_MAC_REG_BASIC_RATE (AR9170_MAC_REG_BASE + 0x630) | ||
165 | #define AR9170_MAC_REG_MANDATORY_RATE (AR9170_MAC_REG_BASE + 0x634) | ||
166 | #define AR9170_MAC_REG_RTS_CTS_RATE (AR9170_MAC_REG_BASE + 0x638) | ||
167 | #define AR9170_MAC_REG_BACKOFF_PROTECT (AR9170_MAC_REG_BASE + 0x63c) | ||
168 | #define AR9170_MAC_REG_RX_THRESHOLD (AR9170_MAC_REG_BASE + 0x640) | ||
169 | #define AR9170_MAC_REG_AFTER_PNP (AR9170_MAC_REG_BASE + 0x648) | ||
170 | #define AR9170_MAC_REG_RX_PE_DELAY (AR9170_MAC_REG_BASE + 0x64c) | ||
171 | |||
172 | #define AR9170_MAC_REG_DYNAMIC_SIFS_ACK (AR9170_MAC_REG_BASE + 0x658) | ||
173 | #define AR9170_MAC_REG_SNIFFER (AR9170_MAC_REG_BASE + 0x674) | ||
174 | #define AR9170_MAC_SNIFFER_ENABLE_PROMISC BIT(0) | ||
175 | #define AR9170_MAC_SNIFFER_DEFAULTS 0x02000000 | ||
176 | #define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678) | ||
177 | #define AR9170_MAC_ENCRYPTION_RX_SOFTWARE BIT(3) | ||
178 | #define AR9170_MAC_ENCRYPTION_DEFAULTS 0x70 | ||
179 | |||
180 | #define AR9170_MAC_REG_MISC_680 (AR9170_MAC_REG_BASE + 0x680) | ||
181 | #define AR9170_MAC_REG_MISC_684 (AR9170_MAC_REG_BASE + 0x684) | ||
182 | #define AR9170_MAC_REG_TX_UNDERRUN (AR9170_MAC_REG_BASE + 0x688) | ||
183 | |||
184 | #define AR9170_MAC_REG_FRAMETYPE_FILTER (AR9170_MAC_REG_BASE + 0x68c) | ||
185 | #define AR9170_MAC_FTF_ASSOC_REQ BIT(0) | ||
186 | #define AR9170_MAC_FTF_ASSOC_RESP BIT(1) | ||
187 | #define AR9170_MAC_FTF_REASSOC_REQ BIT(2) | ||
188 | #define AR9170_MAC_FTF_REASSOC_RESP BIT(3) | ||
189 | #define AR9170_MAC_FTF_PRB_REQ BIT(4) | ||
190 | #define AR9170_MAC_FTF_PRB_RESP BIT(5) | ||
191 | #define AR9170_MAC_FTF_BIT6 BIT(6) | ||
192 | #define AR9170_MAC_FTF_BIT7 BIT(7) | ||
193 | #define AR9170_MAC_FTF_BEACON BIT(8) | ||
194 | #define AR9170_MAC_FTF_ATIM BIT(9) | ||
195 | #define AR9170_MAC_FTF_DEASSOC BIT(10) | ||
196 | #define AR9170_MAC_FTF_AUTH BIT(11) | ||
197 | #define AR9170_MAC_FTF_DEAUTH BIT(12) | ||
198 | #define AR9170_MAC_FTF_BIT13 BIT(13) | ||
199 | #define AR9170_MAC_FTF_BIT14 BIT(14) | ||
200 | #define AR9170_MAC_FTF_BIT15 BIT(15) | ||
201 | #define AR9170_MAC_FTF_BAR BIT(24) | ||
202 | #define AR9170_MAC_FTF_BA BIT(25) | ||
203 | #define AR9170_MAC_FTF_PSPOLL BIT(26) | ||
204 | #define AR9170_MAC_FTF_RTS BIT(27) | ||
205 | #define AR9170_MAC_FTF_CTS BIT(28) | ||
206 | #define AR9170_MAC_FTF_ACK BIT(29) | ||
207 | #define AR9170_MAC_FTF_CFE BIT(30) | ||
208 | #define AR9170_MAC_FTF_CFE_ACK BIT(31) | ||
209 | #define AR9170_MAC_FTF_DEFAULTS 0x0500ffff | ||
210 | #define AR9170_MAC_FTF_MONITOR 0xff00ffff | ||
211 | |||
212 | #define AR9170_MAC_REG_ACK_EXTENSION (AR9170_MAC_REG_BASE + 0x690) | ||
213 | #define AR9170_MAC_REG_ACK_TPC (AR9170_MAC_REG_BASE + 0x694) | ||
214 | #define AR9170_MAC_REG_EIFS_AND_SIFS (AR9170_MAC_REG_BASE + 0x698) | ||
215 | #define AR9170_MAC_REG_RX_TIMEOUT_COUNT (AR9170_MAC_REG_BASE + 0x69c) | ||
216 | #define AR9170_MAC_REG_RX_TOTAL (AR9170_MAC_REG_BASE + 0x6a0) | ||
217 | #define AR9170_MAC_REG_RX_CRC32 (AR9170_MAC_REG_BASE + 0x6a4) | ||
218 | #define AR9170_MAC_REG_RX_CRC16 (AR9170_MAC_REG_BASE + 0x6a8) | ||
219 | #define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI (AR9170_MAC_REG_BASE + 0x6ac) | ||
220 | #define AR9170_MAC_REG_RX_OVERRUN (AR9170_MAC_REG_BASE + 0x6b0) | ||
221 | #define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL (AR9170_MAC_REG_BASE + 0x6bc) | ||
222 | #define AR9170_MAC_REG_TX_BLOCKACKS (AR9170_MAC_REG_BASE + 0x6c0) | ||
223 | #define AR9170_MAC_REG_NAV_COUNT (AR9170_MAC_REG_BASE + 0x6c4) | ||
224 | #define AR9170_MAC_REG_BACKOFF_STATUS (AR9170_MAC_REG_BASE + 0x6c8) | ||
225 | #define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6cc) | ||
226 | |||
227 | #define AR9170_MAC_REG_TX_COMPLETE (AR9170_MAC_REG_BASE + 0x6d4) | ||
228 | |||
229 | #define AR9170_MAC_REG_CHANNEL_BUSY (AR9170_MAC_REG_BASE + 0x6e8) | ||
230 | #define AR9170_MAC_REG_EXT_BUSY (AR9170_MAC_REG_BASE + 0x6ec) | ||
231 | |||
232 | #define AR9170_MAC_REG_SLOT_TIME (AR9170_MAC_REG_BASE + 0x6f0) | ||
233 | #define AR9170_MAC_REG_TX_TOTAL (AR9170_MAC_REG_BASE + 0x6f4) | ||
234 | #define AR9170_MAC_REG_ACK_FC (AR9170_MAC_REG_BASE + 0x6f8) | ||
235 | |||
236 | #define AR9170_MAC_REG_CAM_MODE (AR9170_MAC_REG_BASE + 0x700) | ||
237 | #define AR9170_MAC_CAM_IBSS 0xe0 | ||
238 | #define AR9170_MAC_CAM_AP 0xa1 | ||
239 | #define AR9170_MAC_CAM_STA 0x2 | ||
240 | #define AR9170_MAC_CAM_AP_WDS 0x3 | ||
241 | #define AR9170_MAC_CAM_DEFAULTS (0xf << 24) | ||
242 | #define AR9170_MAC_CAM_HOST_PENDING 0x80000000 | ||
243 | |||
244 | #define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L (AR9170_MAC_REG_BASE + 0x704) | ||
245 | #define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H (AR9170_MAC_REG_BASE + 0x708) | ||
246 | |||
247 | #define AR9170_MAC_REG_CAM_ADDR (AR9170_MAC_REG_BASE + 0x70c) | ||
248 | #define AR9170_MAC_CAM_ADDR_WRITE 0x80000000 | ||
249 | #define AR9170_MAC_REG_CAM_DATA0 (AR9170_MAC_REG_BASE + 0x720) | ||
250 | #define AR9170_MAC_REG_CAM_DATA1 (AR9170_MAC_REG_BASE + 0x724) | ||
251 | #define AR9170_MAC_REG_CAM_DATA2 (AR9170_MAC_REG_BASE + 0x728) | ||
252 | #define AR9170_MAC_REG_CAM_DATA3 (AR9170_MAC_REG_BASE + 0x72c) | ||
253 | |||
254 | #define AR9170_MAC_REG_CAM_DBG0 (AR9170_MAC_REG_BASE + 0x730) | ||
255 | #define AR9170_MAC_REG_CAM_DBG1 (AR9170_MAC_REG_BASE + 0x734) | ||
256 | #define AR9170_MAC_REG_CAM_DBG2 (AR9170_MAC_REG_BASE + 0x738) | ||
257 | #define AR9170_MAC_REG_CAM_STATE (AR9170_MAC_REG_BASE + 0x73c) | ||
258 | #define AR9170_MAC_CAM_STATE_READ_PENDING 0x40000000 | ||
259 | #define AR9170_MAC_CAM_STATE_WRITE_PENDING 0x80000000 | ||
260 | |||
261 | #define AR9170_MAC_REG_CAM_TXKEY (AR9170_MAC_REG_BASE + 0x740) | ||
262 | #define AR9170_MAC_REG_CAM_RXKEY (AR9170_MAC_REG_BASE + 0x750) | ||
263 | |||
264 | #define AR9170_MAC_REG_CAM_TX_ENC_TYPE (AR9170_MAC_REG_BASE + 0x760) | ||
265 | #define AR9170_MAC_REG_CAM_RX_ENC_TYPE (AR9170_MAC_REG_BASE + 0x770) | ||
266 | #define AR9170_MAC_REG_CAM_TX_SERACH_HIT (AR9170_MAC_REG_BASE + 0x780) | ||
267 | #define AR9170_MAC_REG_CAM_RX_SERACH_HIT (AR9170_MAC_REG_BASE + 0x790) | ||
268 | |||
269 | #define AR9170_MAC_REG_AC0_CW (AR9170_MAC_REG_BASE + 0xb00) | ||
270 | #define AR9170_MAC_REG_AC1_CW (AR9170_MAC_REG_BASE + 0xb04) | ||
271 | #define AR9170_MAC_REG_AC2_CW (AR9170_MAC_REG_BASE + 0xb08) | ||
272 | #define AR9170_MAC_REG_AC3_CW (AR9170_MAC_REG_BASE + 0xb0c) | ||
273 | #define AR9170_MAC_REG_AC4_CW (AR9170_MAC_REG_BASE + 0xb10) | ||
274 | #define AR9170_MAC_REG_AC2_AC1_AC0_AIFS (AR9170_MAC_REG_BASE + 0xb14) | ||
275 | #define AR9170_MAC_REG_AC4_AC3_AC2_AIFS (AR9170_MAC_REG_BASE + 0xb18) | ||
276 | #define AR9170_MAC_REG_TXOP_ACK_EXTENSION (AR9170_MAC_REG_BASE + 0xb1c) | ||
277 | #define AR9170_MAC_REG_TXOP_ACK_INTERVAL (AR9170_MAC_REG_BASE + 0xb20) | ||
278 | #define AR9170_MAC_REG_CONTENTION_POINT (AR9170_MAC_REG_BASE + 0xb24) | ||
279 | #define AR9170_MAC_REG_RETRY_MAX (AR9170_MAC_REG_BASE + 0xb28) | ||
280 | #define AR9170_MAC_REG_TID_CFACK_CFEND_RATE (AR9170_MAC_REG_BASE + 0xb2c) | ||
281 | #define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND (AR9170_MAC_REG_BASE + 0xb30) | ||
282 | #define AR9170_MAC_REG_TKIP_TSC (AR9170_MAC_REG_BASE + 0xb34) | ||
283 | #define AR9170_MAC_REG_TXOP_DURATION (AR9170_MAC_REG_BASE + 0xb38) | ||
284 | #define AR9170_MAC_REG_TX_QOS_THRESHOLD (AR9170_MAC_REG_BASE + 0xb3c) | ||
285 | #define AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA (AR9170_MAC_REG_BASE + 0xb40) | ||
286 | #define AR9170_MAC_VIRTUAL_CCA_Q0 BIT(15) | ||
287 | #define AR9170_MAC_VIRTUAL_CCA_Q1 BIT(16) | ||
288 | #define AR9170_MAC_VIRTUAL_CCA_Q2 BIT(17) | ||
289 | #define AR9170_MAC_VIRTUAL_CCA_Q3 BIT(18) | ||
290 | #define AR9170_MAC_VIRTUAL_CCA_Q4 BIT(19) | ||
291 | #define AR9170_MAC_VIRTUAL_CCA_ALL (0xf8000) | ||
292 | |||
293 | #define AR9170_MAC_REG_AC1_AC0_TXOP (AR9170_MAC_REG_BASE + 0xb44) | ||
294 | #define AR9170_MAC_REG_AC3_AC2_TXOP (AR9170_MAC_REG_BASE + 0xb48) | ||
295 | |||
296 | #define AR9170_MAC_REG_AMPDU_COUNT (AR9170_MAC_REG_BASE + 0xb88) | ||
297 | #define AR9170_MAC_REG_MPDU_COUNT (AR9170_MAC_REG_BASE + 0xb8c) | ||
298 | |||
299 | #define AR9170_MAC_REG_AMPDU_FACTOR (AR9170_MAC_REG_BASE + 0xb9c) | ||
300 | #define AR9170_MAC_AMPDU_FACTOR 0x7f0000 | ||
301 | #define AR9170_MAC_AMPDU_FACTOR_S 16 | ||
302 | #define AR9170_MAC_REG_AMPDU_DENSITY (AR9170_MAC_REG_BASE + 0xba0) | ||
303 | #define AR9170_MAC_AMPDU_DENSITY 0x7 | ||
304 | #define AR9170_MAC_AMPDU_DENSITY_S 0 | ||
305 | |||
306 | #define AR9170_MAC_REG_FCS_SELECT (AR9170_MAC_REG_BASE + 0xbb0) | ||
307 | #define AR9170_MAC_FCS_SWFCS 0x1 | ||
308 | #define AR9170_MAC_FCS_FIFO_PROT 0x4 | ||
309 | |||
310 | #define AR9170_MAC_REG_RTS_CTS_TPC (AR9170_MAC_REG_BASE + 0xbb4) | ||
311 | #define AR9170_MAC_REG_CFEND_QOSNULL_TPC (AR9170_MAC_REG_BASE + 0xbb8) | ||
312 | |||
313 | #define AR9170_MAC_REG_ACK_TABLE (AR9170_MAC_REG_BASE + 0xc00) | ||
314 | #define AR9170_MAC_REG_RX_CONTROL (AR9170_MAC_REG_BASE + 0xc40) | ||
315 | #define AR9170_MAC_RX_CTRL_DEAGG 0x1 | ||
316 | #define AR9170_MAC_RX_CTRL_SHORT_FILTER 0x2 | ||
317 | #define AR9170_MAC_RX_CTRL_SA_DA_SEARCH 0x20 | ||
318 | #define AR9170_MAC_RX_CTRL_PASS_TO_HOST BIT(28) | ||
319 | #define AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER BIT(30) | ||
320 | |||
321 | #define AR9170_MAC_REG_RX_CONTROL_1 (AR9170_MAC_REG_BASE + 0xc44) | ||
322 | |||
323 | #define AR9170_MAC_REG_AMPDU_RX_THRESH (AR9170_MAC_REG_BASE + 0xc50) | ||
324 | |||
325 | #define AR9170_MAC_REG_RX_MPDU (AR9170_MAC_REG_BASE + 0xca0) | ||
326 | #define AR9170_MAC_REG_RX_DROPPED_MPDU (AR9170_MAC_REG_BASE + 0xca4) | ||
327 | #define AR9170_MAC_REG_RX_DEL_MPDU (AR9170_MAC_REG_BASE + 0xca8) | ||
328 | #define AR9170_MAC_REG_RX_PHY_MISC_ERROR (AR9170_MAC_REG_BASE + 0xcac) | ||
329 | #define AR9170_MAC_REG_RX_PHY_XR_ERROR (AR9170_MAC_REG_BASE + 0xcb0) | ||
330 | #define AR9170_MAC_REG_RX_PHY_OFDM_ERROR (AR9170_MAC_REG_BASE + 0xcb4) | ||
331 | #define AR9170_MAC_REG_RX_PHY_CCK_ERROR (AR9170_MAC_REG_BASE + 0xcb8) | ||
332 | #define AR9170_MAC_REG_RX_PHY_HT_ERROR (AR9170_MAC_REG_BASE + 0xcbc) | ||
333 | #define AR9170_MAC_REG_RX_PHY_TOTAL (AR9170_MAC_REG_BASE + 0xcc0) | ||
334 | |||
335 | #define AR9170_MAC_REG_DMA_TXQ_ADDR (AR9170_MAC_REG_BASE + 0xd00) | ||
336 | #define AR9170_MAC_REG_DMA_TXQ_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd04) | ||
337 | #define AR9170_MAC_REG_DMA_TXQ0_ADDR (AR9170_MAC_REG_BASE + 0xd00) | ||
338 | #define AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd04) | ||
339 | #define AR9170_MAC_REG_DMA_TXQ1_ADDR (AR9170_MAC_REG_BASE + 0xd08) | ||
340 | #define AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd0c) | ||
341 | #define AR9170_MAC_REG_DMA_TXQ2_ADDR (AR9170_MAC_REG_BASE + 0xd10) | ||
342 | #define AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd14) | ||
343 | #define AR9170_MAC_REG_DMA_TXQ3_ADDR (AR9170_MAC_REG_BASE + 0xd18) | ||
344 | #define AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd1c) | ||
345 | #define AR9170_MAC_REG_DMA_TXQ4_ADDR (AR9170_MAC_REG_BASE + 0xd20) | ||
346 | #define AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd24) | ||
347 | #define AR9170_MAC_REG_DMA_RXQ_ADDR (AR9170_MAC_REG_BASE + 0xd28) | ||
348 | #define AR9170_MAC_REG_DMA_RXQ_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd2c) | ||
349 | |||
350 | #define AR9170_MAC_REG_DMA_TRIGGER (AR9170_MAC_REG_BASE + 0xd30) | ||
351 | #define AR9170_DMA_TRIGGER_TXQ0 BIT(0) | ||
352 | #define AR9170_DMA_TRIGGER_TXQ1 BIT(1) | ||
353 | #define AR9170_DMA_TRIGGER_TXQ2 BIT(2) | ||
354 | #define AR9170_DMA_TRIGGER_TXQ3 BIT(3) | ||
355 | #define AR9170_DMA_TRIGGER_TXQ4 BIT(4) | ||
356 | #define AR9170_DMA_TRIGGER_RXQ BIT(8) | ||
357 | |||
358 | #define AR9170_MAC_REG_DMA_WLAN_STATUS (AR9170_MAC_REG_BASE + 0xd38) | ||
359 | #define AR9170_MAC_REG_DMA_STATUS (AR9170_MAC_REG_BASE + 0xd3c) | ||
360 | |||
361 | #define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xd7c) | ||
362 | #define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f | ||
363 | #define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0 | ||
364 | #define AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000 | ||
365 | #define AR9170_MAC_TXRX_MPI_RX_TO_MASK 0xfff00000 | ||
366 | |||
367 | #define AR9170_MAC_REG_BCN_ADDR (AR9170_MAC_REG_BASE + 0xd84) | ||
368 | #define AR9170_MAC_REG_BCN_LENGTH (AR9170_MAC_REG_BASE + 0xd88) | ||
369 | #define AR9170_MAC_BCN_LENGTH_MAX 256 | ||
370 | |||
371 | #define AR9170_MAC_REG_BCN_STATUS (AR9170_MAC_REG_BASE + 0xd8c) | ||
372 | |||
373 | #define AR9170_MAC_REG_BCN_PLCP (AR9170_MAC_REG_BASE + 0xd90) | ||
374 | #define AR9170_MAC_REG_BCN_CTRL (AR9170_MAC_REG_BASE + 0xd94) | ||
375 | #define AR9170_BCN_CTRL_READY 0x01 | ||
376 | #define AR9170_BCN_CTRL_LOCK 0x02 | ||
377 | |||
378 | #define AR9170_MAC_REG_BCN_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd98) | ||
379 | #define AR9170_MAC_REG_BCN_COUNT (AR9170_MAC_REG_BASE + 0xd9c) | ||
380 | |||
381 | |||
382 | #define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xda0) | ||
383 | #define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xda4) | ||
384 | |||
385 | #define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR (AR9170_MAC_REG_BASE + 0xdc0) | ||
386 | |||
387 | /* Random number generator */ | ||
388 | #define AR9170_RAND_REG_BASE 0x1d0000 | ||
389 | |||
390 | #define AR9170_RAND_REG_NUM (AR9170_RAND_REG_BASE + 0x000) | ||
391 | #define AR9170_RAND_REG_MODE (AR9170_RAND_REG_BASE + 0x004) | ||
392 | #define AR9170_RAND_MODE_MANUAL 0x000 | ||
393 | #define AR9170_RAND_MODE_FREE 0x001 | ||
394 | |||
395 | /* GPIO */ | ||
396 | #define AR9170_GPIO_REG_BASE 0x1d0100 | ||
397 | #define AR9170_GPIO_REG_PORT_TYPE (AR9170_GPIO_REG_BASE + 0x000) | ||
398 | #define AR9170_GPIO_REG_PORT_DATA (AR9170_GPIO_REG_BASE + 0x004) | ||
399 | #define AR9170_GPIO_PORT_LED_0 1 | ||
400 | #define AR9170_GPIO_PORT_LED_1 2 | ||
401 | /* WPS Button GPIO for TP-Link TL-WN821N */ | ||
402 | #define AR9170_GPIO_PORT_WPS_BUTTON_PRESSED 4 | ||
403 | |||
404 | /* Memory Controller */ | ||
405 | #define AR9170_MC_REG_BASE 0x1d1000 | ||
406 | |||
407 | #define AR9170_MC_REG_FLASH_WAIT_STATE (AR9170_MC_REG_BASE + 0x000) | ||
408 | #define AR9170_MC_REG_SEEPROM_WP0 (AR9170_MC_REG_BASE + 0x400) | ||
409 | #define AR9170_MC_REG_SEEPROM_WP1 (AR9170_MC_REG_BASE + 0x404) | ||
410 | #define AR9170_MC_REG_SEEPROM_WP2 (AR9170_MC_REG_BASE + 0x408) | ||
411 | |||
412 | /* Interrupt Controller */ | ||
413 | #define AR9170_MAX_INT_SRC 9 | ||
414 | #define AR9170_INT_REG_BASE 0x1d2000 | ||
415 | |||
416 | #define AR9170_INT_REG_FLAG (AR9170_INT_REG_BASE + 0x000) | ||
417 | #define AR9170_INT_REG_FIQ_MASK (AR9170_INT_REG_BASE + 0x004) | ||
418 | #define AR9170_INT_REG_IRQ_MASK (AR9170_INT_REG_BASE + 0x008) | ||
419 | /* INT_REG_FLAG, INT_REG_FIQ_MASK and INT_REG_IRQ_MASK */ | ||
420 | #define AR9170_INT_FLAG_WLAN 0x001 | ||
421 | #define AR9170_INT_FLAG_PTAB_BIT 0x002 | ||
422 | #define AR9170_INT_FLAG_SE_BIT 0x004 | ||
423 | #define AR9170_INT_FLAG_UART_BIT 0x008 | ||
424 | #define AR9170_INT_FLAG_TIMER_BIT 0x010 | ||
425 | #define AR9170_INT_FLAG_EXT_BIT 0x020 | ||
426 | #define AR9170_INT_FLAG_SW_BIT 0x040 | ||
427 | #define AR9170_INT_FLAG_USB_BIT 0x080 | ||
428 | #define AR9170_INT_FLAG_ETHERNET_BIT 0x100 | ||
429 | |||
430 | #define AR9170_INT_REG_PRIORITY1 (AR9170_INT_REG_BASE + 0x00c) | ||
431 | #define AR9170_INT_REG_PRIORITY2 (AR9170_INT_REG_BASE + 0x010) | ||
432 | #define AR9170_INT_REG_PRIORITY3 (AR9170_INT_REG_BASE + 0x014) | ||
433 | #define AR9170_INT_REG_EXT_INT_CONTROL (AR9170_INT_REG_BASE + 0x018) | ||
434 | #define AR9170_INT_REG_SW_INT_CONTROL (AR9170_INT_REG_BASE + 0x01c) | ||
435 | #define AR9170_INT_SW_INT_ENABLE 0x1 | ||
436 | |||
437 | #define AR9170_INT_REG_FIQ_ENCODE (AR9170_INT_REG_BASE + 0x020) | ||
438 | #define AR9170_INT_INT_IRQ_ENCODE (AR9170_INT_REG_BASE + 0x024) | ||
439 | |||
440 | /* Power Management */ | ||
441 | #define AR9170_PWR_REG_BASE 0x1d4000 | ||
442 | |||
443 | #define AR9170_PWR_REG_POWER_STATE (AR9170_PWR_REG_BASE + 0x000) | ||
444 | |||
445 | #define AR9170_PWR_REG_RESET (AR9170_PWR_REG_BASE + 0x004) | ||
446 | #define AR9170_PWR_RESET_COMMIT_RESET_MASK BIT(0) | ||
447 | #define AR9170_PWR_RESET_WLAN_MASK BIT(1) | ||
448 | #define AR9170_PWR_RESET_DMA_MASK BIT(2) | ||
449 | #define AR9170_PWR_RESET_BRIDGE_MASK BIT(3) | ||
450 | #define AR9170_PWR_RESET_AHB_MASK BIT(9) | ||
451 | #define AR9170_PWR_RESET_BB_WARM_RESET BIT(10) | ||
452 | #define AR9170_PWR_RESET_BB_COLD_RESET BIT(11) | ||
453 | #define AR9170_PWR_RESET_ADDA_CLK_COLD_RESET BIT(12) | ||
454 | #define AR9170_PWR_RESET_PLL BIT(13) | ||
455 | #define AR9170_PWR_RESET_USB_PLL BIT(14) | ||
456 | |||
457 | #define AR9170_PWR_REG_CLOCK_SEL (AR9170_PWR_REG_BASE + 0x008) | ||
458 | #define AR9170_PWR_CLK_AHB_40MHZ 0 | ||
459 | #define AR9170_PWR_CLK_AHB_20_22MHZ 1 | ||
460 | #define AR9170_PWR_CLK_AHB_40_44MHZ 2 | ||
461 | #define AR9170_PWR_CLK_AHB_80_88MHZ 3 | ||
462 | #define AR9170_PWR_CLK_DAC_160_INV_DLY 0x70 | ||
463 | |||
464 | #define AR9170_PWR_REG_CHIP_REVISION (AR9170_PWR_REG_BASE + 0x010) | ||
465 | #define AR9170_PWR_REG_PLL_ADDAC (AR9170_PWR_REG_BASE + 0x014) | ||
466 | #define AR9170_PWR_REG_WATCH_DOG_MAGIC (AR9170_PWR_REG_BASE + 0x020) | ||
467 | |||
468 | /* Faraday USB Controller */ | ||
469 | #define AR9170_USB_REG_BASE 0x1e1000 | ||
470 | |||
471 | #define AR9170_USB_REG_MAIN_CTRL (AR9170_USB_REG_BASE + 0x000) | ||
472 | #define AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP BIT(0) | ||
473 | #define AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT BIT(2) | ||
474 | #define AR9170_USB_MAIN_CTRL_HIGHSPEED BIT(6) | ||
475 | |||
476 | #define AR9170_USB_REG_DEVICE_ADDRESS (AR9170_USB_REG_BASE + 0x001) | ||
477 | #define AR9170_USB_DEVICE_ADDRESS_CONFIGURE BIT(7) | ||
478 | |||
479 | #define AR9170_USB_REG_TEST (AR9170_USB_REG_BASE + 0x002) | ||
480 | #define AR9170_USB_REG_PHY_TEST_SELECT (AR9170_USB_REG_BASE + 0x008) | ||
481 | #define AR9170_USB_REG_CX_CONFIG_STATUS (AR9170_USB_REG_BASE + 0x00b) | ||
482 | #define AR9170_USB_REG_EP0_DATA (AR9170_USB_REG_BASE + 0x00c) | ||
483 | #define AR9170_USB_REG_EP0_DATA1 (AR9170_USB_REG_BASE + 0x00c) | ||
484 | #define AR9170_USB_REG_EP0_DATA2 (AR9170_USB_REG_BASE + 0x00d) | ||
485 | |||
486 | #define AR9170_USB_REG_INTR_MASK_BYTE_0 (AR9170_USB_REG_BASE + 0x011) | ||
487 | #define AR9170_USB_REG_INTR_MASK_BYTE_1 (AR9170_USB_REG_BASE + 0x012) | ||
488 | #define AR9170_USB_REG_INTR_MASK_BYTE_2 (AR9170_USB_REG_BASE + 0x013) | ||
489 | #define AR9170_USB_REG_INTR_MASK_BYTE_3 (AR9170_USB_REG_BASE + 0x014) | ||
490 | #define AR9170_USB_REG_INTR_MASK_BYTE_4 (AR9170_USB_REG_BASE + 0x015) | ||
491 | #define AR9170_USB_INTR_DISABLE_OUT_INT (BIT(7) | BIT(6)) | ||
492 | |||
493 | #define AR9170_USB_REG_INTR_MASK_BYTE_5 (AR9170_USB_REG_BASE + 0x016) | ||
494 | #define AR9170_USB_REG_INTR_MASK_BYTE_6 (AR9170_USB_REG_BASE + 0x017) | ||
495 | #define AR9170_USB_INTR_DISABLE_IN_INT BIT(6) | ||
496 | |||
497 | #define AR9170_USB_REG_INTR_MASK_BYTE_7 (AR9170_USB_REG_BASE + 0x018) | ||
498 | |||
499 | #define AR9170_USB_REG_INTR_GROUP (AR9170_USB_REG_BASE + 0x020) | ||
500 | |||
501 | #define AR9170_USB_REG_INTR_SOURCE_0 (AR9170_USB_REG_BASE + 0x021) | ||
502 | #define AR9170_USB_REG_INTR_SOURCE_1 (AR9170_USB_REG_BASE + 0x022) | ||
503 | #define AR9170_USB_REG_INTR_SOURCE_2 (AR9170_USB_REG_BASE + 0x023) | ||
504 | #define AR9170_USB_REG_INTR_SOURCE_3 (AR9170_USB_REG_BASE + 0x024) | ||
505 | #define AR9170_USB_REG_INTR_SOURCE_4 (AR9170_USB_REG_BASE + 0x025) | ||
506 | #define AR9170_USB_REG_INTR_SOURCE_5 (AR9170_USB_REG_BASE + 0x026) | ||
507 | #define AR9170_USB_REG_INTR_SOURCE_6 (AR9170_USB_REG_BASE + 0x027) | ||
508 | #define AR9170_USB_REG_INTR_SOURCE_7 (AR9170_USB_REG_BASE + 0x028) | ||
509 | |||
510 | #define AR9170_USB_REG_EP_MAP (AR9170_USB_REG_BASE + 0x030) | ||
511 | #define AR9170_USB_REG_EP1_MAP (AR9170_USB_REG_BASE + 0x030) | ||
512 | #define AR9170_USB_REG_EP2_MAP (AR9170_USB_REG_BASE + 0x031) | ||
513 | #define AR9170_USB_REG_EP3_MAP (AR9170_USB_REG_BASE + 0x032) | ||
514 | #define AR9170_USB_REG_EP4_MAP (AR9170_USB_REG_BASE + 0x033) | ||
515 | #define AR9170_USB_REG_EP5_MAP (AR9170_USB_REG_BASE + 0x034) | ||
516 | #define AR9170_USB_REG_EP6_MAP (AR9170_USB_REG_BASE + 0x035) | ||
517 | #define AR9170_USB_REG_EP7_MAP (AR9170_USB_REG_BASE + 0x036) | ||
518 | #define AR9170_USB_REG_EP8_MAP (AR9170_USB_REG_BASE + 0x037) | ||
519 | #define AR9170_USB_REG_EP9_MAP (AR9170_USB_REG_BASE + 0x038) | ||
520 | #define AR9170_USB_REG_EP10_MAP (AR9170_USB_REG_BASE + 0x039) | ||
521 | |||
522 | #define AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH (AR9170_USB_REG_BASE + 0x03f) | ||
523 | #define AR9170_USB_EP_IN_TOGGLE 0x10 | ||
524 | |||
525 | #define AR9170_USB_REG_EP_IN_MAX_SIZE_LOW (AR9170_USB_REG_BASE + 0x03e) | ||
526 | |||
527 | #define AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH (AR9170_USB_REG_BASE + 0x05f) | ||
528 | #define AR9170_USB_EP_OUT_TOGGLE 0x10 | ||
529 | |||
530 | #define AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW (AR9170_USB_REG_BASE + 0x05e) | ||
531 | |||
532 | #define AR9170_USB_REG_EP3_BYTE_COUNT_HIGH (AR9170_USB_REG_BASE + 0x0ae) | ||
533 | #define AR9170_USB_REG_EP3_BYTE_COUNT_LOW (AR9170_USB_REG_BASE + 0x0be) | ||
534 | #define AR9170_USB_REG_EP4_BYTE_COUNT_HIGH (AR9170_USB_REG_BASE + 0x0af) | ||
535 | #define AR9170_USB_REG_EP4_BYTE_COUNT_LOW (AR9170_USB_REG_BASE + 0x0bf) | ||
536 | |||
537 | #define AR9170_USB_REG_FIFO_MAP (AR9170_USB_REG_BASE + 0x080) | ||
538 | #define AR9170_USB_REG_FIFO0_MAP (AR9170_USB_REG_BASE + 0x080) | ||
539 | #define AR9170_USB_REG_FIFO1_MAP (AR9170_USB_REG_BASE + 0x081) | ||
540 | #define AR9170_USB_REG_FIFO2_MAP (AR9170_USB_REG_BASE + 0x082) | ||
541 | #define AR9170_USB_REG_FIFO3_MAP (AR9170_USB_REG_BASE + 0x083) | ||
542 | #define AR9170_USB_REG_FIFO4_MAP (AR9170_USB_REG_BASE + 0x084) | ||
543 | #define AR9170_USB_REG_FIFO5_MAP (AR9170_USB_REG_BASE + 0x085) | ||
544 | #define AR9170_USB_REG_FIFO6_MAP (AR9170_USB_REG_BASE + 0x086) | ||
545 | #define AR9170_USB_REG_FIFO7_MAP (AR9170_USB_REG_BASE + 0x087) | ||
546 | #define AR9170_USB_REG_FIFO8_MAP (AR9170_USB_REG_BASE + 0x088) | ||
547 | #define AR9170_USB_REG_FIFO9_MAP (AR9170_USB_REG_BASE + 0x089) | ||
548 | |||
549 | #define AR9170_USB_REG_FIFO_CONFIG (AR9170_USB_REG_BASE + 0x090) | ||
550 | #define AR9170_USB_REG_FIFO0_CONFIG (AR9170_USB_REG_BASE + 0x090) | ||
551 | #define AR9170_USB_REG_FIFO1_CONFIG (AR9170_USB_REG_BASE + 0x091) | ||
552 | #define AR9170_USB_REG_FIFO2_CONFIG (AR9170_USB_REG_BASE + 0x092) | ||
553 | #define AR9170_USB_REG_FIFO3_CONFIG (AR9170_USB_REG_BASE + 0x093) | ||
554 | #define AR9170_USB_REG_FIFO4_CONFIG (AR9170_USB_REG_BASE + 0x094) | ||
555 | #define AR9170_USB_REG_FIFO5_CONFIG (AR9170_USB_REG_BASE + 0x095) | ||
556 | #define AR9170_USB_REG_FIFO6_CONFIG (AR9170_USB_REG_BASE + 0x096) | ||
557 | #define AR9170_USB_REG_FIFO7_CONFIG (AR9170_USB_REG_BASE + 0x097) | ||
558 | #define AR9170_USB_REG_FIFO8_CONFIG (AR9170_USB_REG_BASE + 0x098) | ||
559 | #define AR9170_USB_REG_FIFO9_CONFIG (AR9170_USB_REG_BASE + 0x099) | ||
560 | |||
561 | #define AR9170_USB_REG_EP3_DATA (AR9170_USB_REG_BASE + 0x0f8) | ||
562 | #define AR9170_USB_REG_EP4_DATA (AR9170_USB_REG_BASE + 0x0fc) | ||
563 | |||
564 | #define AR9170_USB_REG_FIFO_SIZE (AR9170_USB_REG_BASE + 0x100) | ||
565 | #define AR9170_USB_REG_DMA_CTL (AR9170_USB_REG_BASE + 0x108) | ||
566 | #define AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE BIT(0) | ||
567 | #define AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE BIT(1) | ||
568 | #define AR9170_USB_DMA_CTL_HIGH_SPEED BIT(2) | ||
569 | #define AR9170_USB_DMA_CTL_UP_PACKET_MODE BIT(3) | ||
570 | #define AR9170_USB_DMA_CTL_UP_STREAM_S 4 | ||
571 | #define AR9170_USB_DMA_CTL_UP_STREAM (BIT(4) | BIT(5)) | ||
572 | #define AR9170_USB_DMA_CTL_UP_STREAM_4K (0) | ||
573 | #define AR9170_USB_DMA_CTL_UP_STREAM_8K BIT(4) | ||
574 | #define AR9170_USB_DMA_CTL_UP_STREAM_16K BIT(5) | ||
575 | #define AR9170_USB_DMA_CTL_UP_STREAM_32K (BIT(4) | BIT(5)) | ||
576 | #define AR9170_USB_DMA_CTL_DOWN_STREAM BIT(6) | ||
577 | |||
578 | #define AR9170_USB_REG_DMA_STATUS (AR9170_USB_REG_BASE + 0x10c) | ||
579 | #define AR9170_USB_DMA_STATUS_UP_IDLE BIT(8) | ||
580 | #define AR9170_USB_DMA_STATUS_DN_IDLE BIT(16) | ||
581 | |||
582 | #define AR9170_USB_REG_MAX_AGG_UPLOAD (AR9170_USB_REG_BASE + 0x110) | ||
583 | #define AR9170_USB_REG_UPLOAD_TIME_CTL (AR9170_USB_REG_BASE + 0x114) | ||
584 | #define AR9170_USB_REG_CBUS_CTRL (AR9170_USB_REG_BASE + 0x1f0) | ||
585 | #define AR9170_USB_CBUS_CTRL_BUFFER_END (BIT(1)) | ||
586 | |||
587 | /* PCI/USB to AHB Bridge */ | ||
588 | #define AR9170_PTA_REG_BASE 0x1e2000 | ||
589 | |||
590 | #define AR9170_PTA_REG_CMD (AR9170_PTA_REG_BASE + 0x000) | ||
591 | #define AR9170_PTA_REG_PARAM1 (AR9170_PTA_REG_BASE + 0x004) | ||
592 | #define AR9170_PTA_REG_PARAM2 (AR9170_PTA_REG_BASE + 0x008) | ||
593 | #define AR9170_PTA_REG_PARAM3 (AR9170_PTA_REG_BASE + 0x00c) | ||
594 | #define AR9170_PTA_REG_RSP (AR9170_PTA_REG_BASE + 0x010) | ||
595 | #define AR9170_PTA_REG_STATUS1 (AR9170_PTA_REG_BASE + 0x014) | ||
596 | #define AR9170_PTA_REG_STATUS2 (AR9170_PTA_REG_BASE + 0x018) | ||
597 | #define AR9170_PTA_REG_STATUS3 (AR9170_PTA_REG_BASE + 0x01c) | ||
598 | #define AR9170_PTA_REG_AHB_INT_FLAG (AR9170_PTA_REG_BASE + 0x020) | ||
599 | #define AR9170_PTA_REG_AHB_INT_MASK (AR9170_PTA_REG_BASE + 0x024) | ||
600 | #define AR9170_PTA_REG_AHB_INT_ACK (AR9170_PTA_REG_BASE + 0x028) | ||
601 | #define AR9170_PTA_REG_AHB_SCRATCH1 (AR9170_PTA_REG_BASE + 0x030) | ||
602 | #define AR9170_PTA_REG_AHB_SCRATCH2 (AR9170_PTA_REG_BASE + 0x034) | ||
603 | #define AR9170_PTA_REG_AHB_SCRATCH3 (AR9170_PTA_REG_BASE + 0x038) | ||
604 | #define AR9170_PTA_REG_AHB_SCRATCH4 (AR9170_PTA_REG_BASE + 0x03c) | ||
605 | |||
606 | #define AR9170_PTA_REG_SHARE_MEM_CTRL (AR9170_PTA_REG_BASE + 0x124) | ||
607 | |||
608 | /* | ||
609 | * PCI to AHB Bridge | ||
610 | */ | ||
611 | |||
612 | #define AR9170_PTA_REG_INT_FLAG (AR9170_PTA_REG_BASE + 0x100) | ||
613 | #define AR9170_PTA_INT_FLAG_DN 0x01 | ||
614 | #define AR9170_PTA_INT_FLAG_UP 0x02 | ||
615 | #define AR9170_PTA_INT_FLAG_CMD 0x04 | ||
616 | |||
617 | #define AR9170_PTA_REG_INT_MASK (AR9170_PTA_REG_BASE + 0x104) | ||
618 | #define AR9170_PTA_REG_DN_DMA_ADDRL (AR9170_PTA_REG_BASE + 0x108) | ||
619 | #define AR9170_PTA_REG_DN_DMA_ADDRH (AR9170_PTA_REG_BASE + 0x10c) | ||
620 | #define AR9170_PTA_REG_UP_DMA_ADDRL (AR9170_PTA_REG_BASE + 0x110) | ||
621 | #define AR9170_PTA_REG_UP_DMA_ADDRH (AR9170_PTA_REG_BASE + 0x114) | ||
622 | #define AR9170_PTA_REG_DN_PEND_TIME (AR9170_PTA_REG_BASE + 0x118) | ||
623 | #define AR9170_PTA_REG_UP_PEND_TIME (AR9170_PTA_REG_BASE + 0x11c) | ||
624 | #define AR9170_PTA_REG_CONTROL (AR9170_PTA_REG_BASE + 0x120) | ||
625 | #define AR9170_PTA_CTRL_4_BEAT_BURST 0x00 | ||
626 | #define AR9170_PTA_CTRL_8_BEAT_BURST 0x01 | ||
627 | #define AR9170_PTA_CTRL_16_BEAT_BURST 0x02 | ||
628 | #define AR9170_PTA_CTRL_LOOPBACK_MODE 0x10 | ||
629 | |||
630 | #define AR9170_PTA_REG_MEM_CTRL (AR9170_PTA_REG_BASE + 0x124) | ||
631 | #define AR9170_PTA_REG_MEM_ADDR (AR9170_PTA_REG_BASE + 0x128) | ||
632 | #define AR9170_PTA_REG_DN_DMA_TRIGGER (AR9170_PTA_REG_BASE + 0x12c) | ||
633 | #define AR9170_PTA_REG_UP_DMA_TRIGGER (AR9170_PTA_REG_BASE + 0x130) | ||
634 | #define AR9170_PTA_REG_DMA_STATUS (AR9170_PTA_REG_BASE + 0x134) | ||
635 | #define AR9170_PTA_REG_DN_CURR_ADDRL (AR9170_PTA_REG_BASE + 0x138) | ||
636 | #define AR9170_PTA_REG_DN_CURR_ADDRH (AR9170_PTA_REG_BASE + 0x13c) | ||
637 | #define AR9170_PTA_REG_UP_CURR_ADDRL (AR9170_PTA_REG_BASE + 0x140) | ||
638 | #define AR9170_PTA_REG_UP_CURR_ADDRH (AR9170_PTA_REG_BASE + 0x144) | ||
639 | #define AR9170_PTA_REG_DMA_MODE_CTRL (AR9170_PTA_REG_BASE + 0x148) | ||
640 | #define AR9170_PTA_DMA_MODE_CTRL_RESET BIT(0) | ||
641 | #define AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB BIT(1) | ||
642 | |||
643 | /* Protocol Controller Module */ | ||
644 | #define AR9170_MAC_REG_PC_REG_BASE (AR9170_MAC_REG_BASE + 0xe00) | ||
645 | |||
646 | |||
647 | #define AR9170_NUM_LEDS 2 | ||
648 | |||
649 | /* CAM */ | ||
650 | #define AR9170_CAM_MAX_USER 64 | ||
651 | #define AR9170_CAM_MAX_KEY_LENGTH 16 | ||
652 | |||
653 | #define AR9170_SRAM_OFFSET 0x100000 | ||
654 | #define AR9170_SRAM_SIZE 0x18000 | ||
655 | |||
656 | #define AR9170_PRAM_OFFSET 0x200000 | ||
657 | #define AR9170_PRAM_SIZE 0x8000 | ||
658 | |||
659 | enum cpu_clock { | ||
660 | AHB_STATIC_40MHZ = 0, | ||
661 | AHB_GMODE_22MHZ = 1, | ||
662 | AHB_AMODE_20MHZ = 1, | ||
663 | AHB_GMODE_44MHZ = 2, | ||
664 | AHB_AMODE_40MHZ = 2, | ||
665 | AHB_GMODE_88MHZ = 3, | ||
666 | AHB_AMODE_80MHZ = 3 | ||
667 | }; | ||
668 | |||
669 | /* USB endpoints */ | ||
670 | enum ar9170_usb_ep { | ||
671 | /* | ||
672 | * Control EP is always EP 0 (USB SPEC) | ||
673 | * | ||
674 | * The weird thing is: the original firmware has a few | ||
675 | * comments that suggest that the actual EP numbers | ||
676 | * are in the 1 to 10 range?! | ||
677 | */ | ||
678 | AR9170_USB_EP_CTRL = 0, | ||
679 | |||
680 | AR9170_USB_EP_TX, | ||
681 | AR9170_USB_EP_RX, | ||
682 | AR9170_USB_EP_IRQ, | ||
683 | AR9170_USB_EP_CMD, | ||
684 | AR9170_USB_NUM_EXTRA_EP = 4, | ||
685 | |||
686 | __AR9170_USB_NUM_EP, | ||
687 | |||
688 | __AR9170_USB_NUM_MAX_EP = 10 | ||
689 | }; | ||
690 | |||
691 | enum ar9170_usb_fifo { | ||
692 | __AR9170_USB_NUM_MAX_FIFO = 10 | ||
693 | }; | ||
694 | |||
695 | enum ar9170_tx_queues { | ||
696 | AR9170_TXQ0 = 0, | ||
697 | AR9170_TXQ1, | ||
698 | AR9170_TXQ2, | ||
699 | AR9170_TXQ3, | ||
700 | AR9170_TXQ_SPECIAL, | ||
701 | |||
702 | /* keep last */ | ||
703 | __AR9170_NUM_TX_QUEUES = 5 | ||
704 | }; | ||
705 | |||
706 | #define AR9170_TX_STREAM_TAG 0x697e | ||
707 | #define AR9170_RX_STREAM_TAG 0x4e00 | ||
708 | #define AR9170_RX_STREAM_MAX_SIZE 0xffff | ||
709 | |||
710 | struct ar9170_stream { | ||
711 | __le16 length; | ||
712 | __le16 tag; | ||
713 | |||
714 | u8 payload[0]; | ||
715 | }; | ||
716 | |||
717 | #define AR9170_MAX_ACKTABLE_ENTRIES 8 | ||
718 | #define AR9170_MAX_VIRTUAL_MAC 7 | ||
719 | |||
720 | #define AR9170_USB_EP_CTRL_MAX 64 | ||
721 | #define AR9170_USB_EP_TX_MAX 512 | ||
722 | #define AR9170_USB_EP_RX_MAX 512 | ||
723 | #define AR9170_USB_EP_IRQ_MAX 64 | ||
724 | #define AR9170_USB_EP_CMD_MAX 64 | ||
725 | |||
726 | /* Trigger PRETBTT interrupt 6 Kus earlier */ | ||
727 | #define CARL9170_PRETBTT_KUS 6 | ||
728 | |||
729 | #define AR5416_MAX_RATE_POWER 63 | ||
730 | |||
731 | #define SET_VAL(reg, value, newvalue) \ | ||
732 | (value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg)) | ||
733 | |||
734 | #define MOD_VAL(reg, value, newvalue) \ | ||
735 | (((value) & ~reg) | (((newvalue) << reg##_S) & reg)) | ||
736 | #endif /* __CARL9170_SHARED_HW_H */ | ||
diff --git a/drivers/net/wireless/ath/carl9170/phy.h b/drivers/net/wireless/ath/carl9170/phy.h new file mode 100644 index 000000000000..53c18d34ffcc --- /dev/null +++ b/drivers/net/wireless/ath/carl9170/phy.h | |||
@@ -0,0 +1,567 @@ | |||
1 | /* | ||
2 | * Shared Atheros AR9170 Header | ||
3 | * | ||
4 | * PHY register map | ||
5 | * | ||
6 | * Copyright (c) 2008-2009 Atheros Communications Inc. | ||
7 | * | ||
8 | * Permission to use, copy, modify, and/or distribute this software for any | ||
9 | * purpose with or without fee is hereby granted, provided that the above | ||
10 | * copyright notice and this permission notice appear in all copies. | ||
11 | * | ||
12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
19 | */ | ||
20 | |||
21 | #ifndef __CARL9170_SHARED_PHY_H | ||
22 | #define __CARL9170_SHARED_PHY_H | ||
23 | |||
24 | #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800) | ||
25 | #define AR9170_PHY_REG(_n) (AR9170_PHY_REG_BASE + \ | ||
26 | ((_n) << 2)) | ||
27 | |||
28 | #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000) | ||
29 | #define AR9170_PHY_TEST_AGC_CLR 0x10000000 | ||
30 | #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000 | ||
31 | |||
32 | #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004) | ||
33 | #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001 | ||
34 | #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002 | ||
35 | #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004 | ||
36 | #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008 | ||
37 | #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010 | ||
38 | /* For 25 MHz channel spacing -- not used but supported by hw */ | ||
39 | #define AR9170_PHY_TURBO_FC_DYN2040_EXT_CH 0x00000020 | ||
40 | #define AR9170_PHY_TURBO_FC_HT_EN 0x00000040 | ||
41 | #define AR9170_PHY_TURBO_FC_SHORT_GI_40 0x00000080 | ||
42 | #define AR9170_PHY_TURBO_FC_WALSH 0x00000100 | ||
43 | #define AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 0x00000200 | ||
44 | #define AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO 0x00000800 | ||
45 | |||
46 | #define AR9170_PHY_REG_TEST2 (AR9170_PHY_REG_BASE + 0x0008) | ||
47 | |||
48 | #define AR9170_PHY_REG_TIMING2 (AR9170_PHY_REG_BASE + 0x0010) | ||
49 | #define AR9170_PHY_TIMING2_USE_FORCE 0x00001000 | ||
50 | #define AR9170_PHY_TIMING2_FORCE 0x00000fff | ||
51 | #define AR9170_PHY_TIMING2_FORCE_S 0 | ||
52 | |||
53 | #define AR9170_PHY_REG_TIMING3 (AR9170_PHY_REG_BASE + 0x0014) | ||
54 | #define AR9170_PHY_TIMING3_DSC_EXP 0x0001e000 | ||
55 | #define AR9170_PHY_TIMING3_DSC_EXP_S 13 | ||
56 | #define AR9170_PHY_TIMING3_DSC_MAN 0xfffe0000 | ||
57 | #define AR9170_PHY_TIMING3_DSC_MAN_S 17 | ||
58 | |||
59 | #define AR9170_PHY_REG_CHIP_ID (AR9170_PHY_REG_BASE + 0x0018) | ||
60 | #define AR9170_PHY_CHIP_ID_REV_0 0x80 | ||
61 | #define AR9170_PHY_CHIP_ID_REV_1 0x81 | ||
62 | #define AR9170_PHY_CHIP_ID_9160_REV_0 0xb0 | ||
63 | |||
64 | #define AR9170_PHY_REG_ACTIVE (AR9170_PHY_REG_BASE + 0x001c) | ||
65 | #define AR9170_PHY_ACTIVE_EN 0x00000001 | ||
66 | #define AR9170_PHY_ACTIVE_DIS 0x00000000 | ||
67 | |||
68 | #define AR9170_PHY_REG_RF_CTL2 (AR9170_PHY_REG_BASE + 0x0024) | ||
69 | #define AR9170_PHY_RF_CTL2_TX_END_DATA_START 0x000000ff | ||
70 | #define AR9170_PHY_RF_CTL2_TX_END_DATA_START_S 0 | ||
71 | #define AR9170_PHY_RF_CTL2_TX_END_PA_ON 0x0000ff00 | ||
72 | #define AR9170_PHY_RF_CTL2_TX_END_PA_ON_S 8 | ||
73 | |||
74 | #define AR9170_PHY_REG_RF_CTL3 (AR9170_PHY_REG_BASE + 0x0028) | ||
75 | #define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON 0x00ff0000 | ||
76 | #define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S 16 | ||
77 | |||
78 | #define AR9170_PHY_REG_ADC_CTL (AR9170_PHY_REG_BASE + 0x002c) | ||
79 | #define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 | ||
80 | #define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 | ||
81 | #define AR9170_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 | ||
82 | #define AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 | ||
83 | #define AR9170_PHY_ADC_CTL_OFF_PWDADC 0x00008000 | ||
84 | #define AR9170_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 | ||
85 | #define AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S 16 | ||
86 | |||
87 | #define AR9170_PHY_REG_ADC_SERIAL_CTL (AR9170_PHY_REG_BASE + 0x0030) | ||
88 | #define AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC 0x00000000 | ||
89 | #define AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO 0x00000001 | ||
90 | |||
91 | #define AR9170_PHY_REG_RF_CTL4 (AR9170_PHY_REG_BASE + 0x0034) | ||
92 | #define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF 0xff000000 | ||
93 | #define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 | ||
94 | #define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00ff0000 | ||
95 | #define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 | ||
96 | #define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000ff00 | ||
97 | #define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 | ||
98 | #define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000ff | ||
99 | #define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 | ||
100 | |||
101 | #define AR9170_PHY_REG_TSTDAC_CONST (AR9170_PHY_REG_BASE + 0x003c) | ||
102 | |||
103 | #define AR9170_PHY_REG_SETTLING (AR9170_PHY_REG_BASE + 0x0044) | ||
104 | #define AR9170_PHY_SETTLING_SWITCH 0x00003f80 | ||
105 | #define AR9170_PHY_SETTLING_SWITCH_S 7 | ||
106 | |||
107 | #define AR9170_PHY_REG_RXGAIN (AR9170_PHY_REG_BASE + 0x0048) | ||
108 | #define AR9170_PHY_REG_RXGAIN_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2048) | ||
109 | #define AR9170_PHY_RXGAIN_TXRX_ATTEN 0x0003f000 | ||
110 | #define AR9170_PHY_RXGAIN_TXRX_ATTEN_S 12 | ||
111 | #define AR9170_PHY_RXGAIN_TXRX_RF_MAX 0x007c0000 | ||
112 | #define AR9170_PHY_RXGAIN_TXRX_RF_MAX_S 18 | ||
113 | |||
114 | #define AR9170_PHY_REG_DESIRED_SZ (AR9170_PHY_REG_BASE + 0x0050) | ||
115 | #define AR9170_PHY_DESIRED_SZ_ADC 0x000000ff | ||
116 | #define AR9170_PHY_DESIRED_SZ_ADC_S 0 | ||
117 | #define AR9170_PHY_DESIRED_SZ_PGA 0x0000ff00 | ||
118 | #define AR9170_PHY_DESIRED_SZ_PGA_S 8 | ||
119 | #define AR9170_PHY_DESIRED_SZ_TOT_DES 0x0ff00000 | ||
120 | #define AR9170_PHY_DESIRED_SZ_TOT_DES_S 20 | ||
121 | |||
122 | #define AR9170_PHY_REG_FIND_SIG (AR9170_PHY_REG_BASE + 0x0058) | ||
123 | #define AR9170_PHY_FIND_SIG_FIRSTEP 0x0003f000 | ||
124 | #define AR9170_PHY_FIND_SIG_FIRSTEP_S 12 | ||
125 | #define AR9170_PHY_FIND_SIG_FIRPWR 0x03fc0000 | ||
126 | #define AR9170_PHY_FIND_SIG_FIRPWR_S 18 | ||
127 | |||
128 | #define AR9170_PHY_REG_AGC_CTL1 (AR9170_PHY_REG_BASE + 0x005c) | ||
129 | #define AR9170_PHY_AGC_CTL1_COARSE_LOW 0x00007f80 | ||
130 | #define AR9170_PHY_AGC_CTL1_COARSE_LOW_S 7 | ||
131 | #define AR9170_PHY_AGC_CTL1_COARSE_HIGH 0x003f8000 | ||
132 | #define AR9170_PHY_AGC_CTL1_COARSE_HIGH_S 15 | ||
133 | |||
134 | #define AR9170_PHY_REG_AGC_CONTROL (AR9170_PHY_REG_BASE + 0x0060) | ||
135 | #define AR9170_PHY_AGC_CONTROL_CAL 0x00000001 | ||
136 | #define AR9170_PHY_AGC_CONTROL_NF 0x00000002 | ||
137 | #define AR9170_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 | ||
138 | #define AR9170_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 | ||
139 | #define AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 | ||
140 | |||
141 | #define AR9170_PHY_REG_CCA (AR9170_PHY_REG_BASE + 0x0064) | ||
142 | #define AR9170_PHY_CCA_MINCCA_PWR 0x0ff80000 | ||
143 | #define AR9170_PHY_CCA_MINCCA_PWR_S 19 | ||
144 | #define AR9170_PHY_CCA_THRESH62 0x0007f000 | ||
145 | #define AR9170_PHY_CCA_THRESH62_S 12 | ||
146 | |||
147 | #define AR9170_PHY_REG_SFCORR (AR9170_PHY_REG_BASE + 0x0068) | ||
148 | #define AR9170_PHY_SFCORR_M2COUNT_THR 0x0000001f | ||
149 | #define AR9170_PHY_SFCORR_M2COUNT_THR_S 0 | ||
150 | #define AR9170_PHY_SFCORR_M1_THRESH 0x00fe0000 | ||
151 | #define AR9170_PHY_SFCORR_M1_THRESH_S 17 | ||
152 | #define AR9170_PHY_SFCORR_M2_THRESH 0x7f000000 | ||
153 | #define AR9170_PHY_SFCORR_M2_THRESH_S 24 | ||
154 | |||
155 | #define AR9170_PHY_REG_SFCORR_LOW (AR9170_PHY_REG_BASE + 0x006c) | ||
156 | #define AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 | ||
157 | #define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003f00 | ||
158 | #define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 | ||
159 | #define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001fc000 | ||
160 | #define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 | ||
161 | #define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0fe00000 | ||
162 | #define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 | ||
163 | |||
164 | #define AR9170_PHY_REG_SLEEP_CTR_CONTROL (AR9170_PHY_REG_BASE + 0x0070) | ||
165 | #define AR9170_PHY_REG_SLEEP_CTR_LIMIT (AR9170_PHY_REG_BASE + 0x0074) | ||
166 | #define AR9170_PHY_REG_SLEEP_SCAL (AR9170_PHY_REG_BASE + 0x0078) | ||
167 | |||
168 | #define AR9170_PHY_REG_PLL_CTL (AR9170_PHY_REG_BASE + 0x007c) | ||
169 | #define AR9170_PHY_PLL_CTL_40 0xaa | ||
170 | #define AR9170_PHY_PLL_CTL_40_5413 0x04 | ||
171 | #define AR9170_PHY_PLL_CTL_44 0xab | ||
172 | #define AR9170_PHY_PLL_CTL_44_2133 0xeb | ||
173 | #define AR9170_PHY_PLL_CTL_40_2133 0xea | ||
174 | |||
175 | #define AR9170_PHY_REG_BIN_MASK_1 (AR9170_PHY_REG_BASE + 0x0100) | ||
176 | #define AR9170_PHY_REG_BIN_MASK_2 (AR9170_PHY_REG_BASE + 0x0104) | ||
177 | #define AR9170_PHY_REG_BIN_MASK_3 (AR9170_PHY_REG_BASE + 0x0108) | ||
178 | #define AR9170_PHY_REG_MASK_CTL (AR9170_PHY_REG_BASE + 0x010c) | ||
179 | |||
180 | /* analogue power on time (100ns) */ | ||
181 | #define AR9170_PHY_REG_RX_DELAY (AR9170_PHY_REG_BASE + 0x0114) | ||
182 | #define AR9170_PHY_REG_SEARCH_START_DELAY (AR9170_PHY_REG_BASE + 0x0118) | ||
183 | #define AR9170_PHY_RX_DELAY_DELAY 0x00003fff | ||
184 | |||
185 | #define AR9170_PHY_REG_TIMING_CTRL4(_i) (AR9170_PHY_REG_BASE + \ | ||
186 | (0x0120 + ((_i) << 12))) | ||
187 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01f | ||
188 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 | ||
189 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7e0 | ||
190 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 | ||
191 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 | ||
192 | #define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xf000 | ||
193 | #define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 | ||
194 | #define AR9170_PHY_TIMING_CTRL4_DO_IQCAL 0x10000 | ||
195 | #define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 | ||
196 | #define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 | ||
197 | #define AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 | ||
198 | #define AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 | ||
199 | |||
200 | #define AR9170_PHY_REG_TIMING5 (AR9170_PHY_REG_BASE + 0x0124) | ||
201 | #define AR9170_PHY_TIMING5_CYCPWR_THR1 0x000000fe | ||
202 | #define AR9170_PHY_TIMING5_CYCPWR_THR1_S 1 | ||
203 | |||
204 | #define AR9170_PHY_REG_POWER_TX_RATE1 (AR9170_PHY_REG_BASE + 0x0134) | ||
205 | #define AR9170_PHY_REG_POWER_TX_RATE2 (AR9170_PHY_REG_BASE + 0x0138) | ||
206 | #define AR9170_PHY_REG_POWER_TX_RATE_MAX (AR9170_PHY_REG_BASE + 0x013c) | ||
207 | #define AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 | ||
208 | |||
209 | #define AR9170_PHY_REG_FRAME_CTL (AR9170_PHY_REG_BASE + 0x0144) | ||
210 | #define AR9170_PHY_FRAME_CTL_TX_CLIP 0x00000038 | ||
211 | #define AR9170_PHY_FRAME_CTL_TX_CLIP_S 3 | ||
212 | |||
213 | #define AR9170_PHY_REG_SPUR_REG (AR9170_PHY_REG_BASE + 0x014c) | ||
214 | #define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL (0xff << 18) | ||
215 | #define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 | ||
216 | #define AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 | ||
217 | #define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT (0xff << 9) | ||
218 | #define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 | ||
219 | #define AR9170_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 | ||
220 | #define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7f | ||
221 | #define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 | ||
222 | |||
223 | #define AR9170_PHY_REG_RADAR_EXT (AR9170_PHY_REG_BASE + 0x0140) | ||
224 | #define AR9170_PHY_RADAR_EXT_ENA 0x00004000 | ||
225 | |||
226 | #define AR9170_PHY_REG_RADAR_0 (AR9170_PHY_REG_BASE + 0x0154) | ||
227 | #define AR9170_PHY_RADAR_0_ENA 0x00000001 | ||
228 | #define AR9170_PHY_RADAR_0_FFT_ENA 0x80000000 | ||
229 | /* inband pulse threshold */ | ||
230 | #define AR9170_PHY_RADAR_0_INBAND 0x0000003e | ||
231 | #define AR9170_PHY_RADAR_0_INBAND_S 1 | ||
232 | /* pulse RSSI threshold */ | ||
233 | #define AR9170_PHY_RADAR_0_PRSSI 0x00000fc0 | ||
234 | #define AR9170_PHY_RADAR_0_PRSSI_S 6 | ||
235 | /* pulse height threshold */ | ||
236 | #define AR9170_PHY_RADAR_0_HEIGHT 0x0003f000 | ||
237 | #define AR9170_PHY_RADAR_0_HEIGHT_S 12 | ||
238 | /* radar RSSI threshold */ | ||
239 | #define AR9170_PHY_RADAR_0_RRSSI 0x00fc0000 | ||
240 | #define AR9170_PHY_RADAR_0_RRSSI_S 18 | ||
241 | /* radar firepower threshold */ | ||
242 | #define AR9170_PHY_RADAR_0_FIRPWR 0x7f000000 | ||
243 | #define AR9170_PHY_RADAR_0_FIRPWR_S 24 | ||
244 | |||
245 | #define AR9170_PHY_REG_RADAR_1 (AR9170_PHY_REG_BASE + 0x0158) | ||
246 | #define AR9170_PHY_RADAR_1_RELPWR_ENA 0x00800000 | ||
247 | #define AR9170_PHY_RADAR_1_USE_FIR128 0x00400000 | ||
248 | #define AR9170_PHY_RADAR_1_RELPWR_THRESH 0x003f0000 | ||
249 | #define AR9170_PHY_RADAR_1_RELPWR_THRESH_S 16 | ||
250 | #define AR9170_PHY_RADAR_1_BLOCK_CHECK 0x00008000 | ||
251 | #define AR9170_PHY_RADAR_1_MAX_RRSSI 0x00004000 | ||
252 | #define AR9170_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 | ||
253 | #define AR9170_PHY_RADAR_1_RELSTEP_THRESH 0x00001f00 | ||
254 | #define AR9170_PHY_RADAR_1_RELSTEP_THRESH_S 8 | ||
255 | #define AR9170_PHY_RADAR_1_MAXLEN 0x000000ff | ||
256 | #define AR9170_PHY_RADAR_1_MAXLEN_S 0 | ||
257 | |||
258 | #define AR9170_PHY_REG_SWITCH_CHAIN_0 (AR9170_PHY_REG_BASE + 0x0160) | ||
259 | #define AR9170_PHY_REG_SWITCH_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2160) | ||
260 | |||
261 | #define AR9170_PHY_REG_SWITCH_COM (AR9170_PHY_REG_BASE + 0x0164) | ||
262 | |||
263 | #define AR9170_PHY_REG_CCA_THRESHOLD (AR9170_PHY_REG_BASE + 0x0168) | ||
264 | |||
265 | #define AR9170_PHY_REG_SIGMA_DELTA (AR9170_PHY_REG_BASE + 0x016c) | ||
266 | #define AR9170_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 | ||
267 | #define AR9170_PHY_SIGMA_DELTA_ADC_SEL_S 0 | ||
268 | #define AR9170_PHY_SIGMA_DELTA_FILT2 0x000000f8 | ||
269 | #define AR9170_PHY_SIGMA_DELTA_FILT2_S 3 | ||
270 | #define AR9170_PHY_SIGMA_DELTA_FILT1 0x00001f00 | ||
271 | #define AR9170_PHY_SIGMA_DELTA_FILT1_S 8 | ||
272 | #define AR9170_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 | ||
273 | #define AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S 13 | ||
274 | |||
275 | #define AR9170_PHY_REG_RESTART (AR9170_PHY_REG_BASE + 0x0170) | ||
276 | #define AR9170_PHY_RESTART_DIV_GC 0x001c0000 | ||
277 | #define AR9170_PHY_RESTART_DIV_GC_S 18 | ||
278 | |||
279 | #define AR9170_PHY_REG_RFBUS_REQ (AR9170_PHY_REG_BASE + 0x017c) | ||
280 | #define AR9170_PHY_RFBUS_REQ_EN 0x00000001 | ||
281 | |||
282 | #define AR9170_PHY_REG_TIMING7 (AR9170_PHY_REG_BASE + 0x0180) | ||
283 | #define AR9170_PHY_REG_TIMING8 (AR9170_PHY_REG_BASE + 0x0184) | ||
284 | #define AR9170_PHY_TIMING8_PILOT_MASK_2 0x000fffff | ||
285 | #define AR9170_PHY_TIMING8_PILOT_MASK_2_S 0 | ||
286 | |||
287 | #define AR9170_PHY_REG_BIN_MASK2_1 (AR9170_PHY_REG_BASE + 0x0188) | ||
288 | #define AR9170_PHY_REG_BIN_MASK2_2 (AR9170_PHY_REG_BASE + 0x018c) | ||
289 | #define AR9170_PHY_REG_BIN_MASK2_3 (AR9170_PHY_REG_BASE + 0x0190) | ||
290 | #define AR9170_PHY_REG_BIN_MASK2_4 (AR9170_PHY_REG_BASE + 0x0194) | ||
291 | #define AR9170_PHY_BIN_MASK2_4_MASK_4 0x00003fff | ||
292 | #define AR9170_PHY_BIN_MASK2_4_MASK_4_S 0 | ||
293 | |||
294 | #define AR9170_PHY_REG_TIMING9 (AR9170_PHY_REG_BASE + 0x0198) | ||
295 | #define AR9170_PHY_REG_TIMING10 (AR9170_PHY_REG_BASE + 0x019c) | ||
296 | #define AR9170_PHY_TIMING10_PILOT_MASK_2 0x000fffff | ||
297 | #define AR9170_PHY_TIMING10_PILOT_MASK_2_S 0 | ||
298 | |||
299 | #define AR9170_PHY_REG_TIMING11 (AR9170_PHY_REG_BASE + 0x01a0) | ||
300 | #define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE 0x000fffff | ||
301 | #define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 | ||
302 | #define AR9170_PHY_TIMING11_SPUR_FREQ_SD 0x3ff00000 | ||
303 | #define AR9170_PHY_TIMING11_SPUR_FREQ_SD_S 20 | ||
304 | #define AR9170_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 | ||
305 | #define AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 | ||
306 | |||
307 | #define AR9170_PHY_REG_RX_CHAINMASK (AR9170_PHY_REG_BASE + 0x01a4) | ||
308 | #define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \ | ||
309 | 0x01b4 + ((_i) << 12)) | ||
310 | #define AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 | ||
311 | #define AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 | ||
312 | |||
313 | #define AR9170_PHY_REG_MULTICHAIN_GAIN_CTL (AR9170_PHY_REG_BASE + 0x01ac) | ||
314 | #define AR9170_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000 | ||
315 | #define AR9170_PHY_9285_ANT_DIV_CTL 0x01000000 | ||
316 | #define AR9170_PHY_9285_ANT_DIV_CTL_S 24 | ||
317 | #define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000 | ||
318 | #define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S 25 | ||
319 | #define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000 | ||
320 | #define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27 | ||
321 | #define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000 | ||
322 | #define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 | ||
323 | #define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 | ||
324 | #define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 | ||
325 | #define AR9170_PHY_9285_ANT_DIV_LNA1 2 | ||
326 | #define AR9170_PHY_9285_ANT_DIV_LNA2 1 | ||
327 | #define AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3 | ||
328 | #define AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0 | ||
329 | #define AR9170_PHY_9285_ANT_DIV_GAINTB_0 0 | ||
330 | #define AR9170_PHY_9285_ANT_DIV_GAINTB_1 1 | ||
331 | |||
332 | #define AR9170_PHY_REG_EXT_CCA0 (AR9170_PHY_REG_BASE + 0x01b8) | ||
333 | #define AR9170_PHY_REG_EXT_CCA0_THRESH62 0x000000ff | ||
334 | #define AR9170_PHY_REG_EXT_CCA0_THRESH62_S 0 | ||
335 | |||
336 | #define AR9170_PHY_REG_EXT_CCA (AR9170_PHY_REG_BASE + 0x01bc) | ||
337 | #define AR9170_PHY_EXT_CCA_CYCPWR_THR1 0x0000fe00 | ||
338 | #define AR9170_PHY_EXT_CCA_CYCPWR_THR1_S 9 | ||
339 | #define AR9170_PHY_EXT_CCA_THRESH62 0x007f0000 | ||
340 | #define AR9170_PHY_EXT_CCA_THRESH62_S 16 | ||
341 | #define AR9170_PHY_EXT_MINCCA_PWR 0xff800000 | ||
342 | #define AR9170_PHY_EXT_MINCCA_PWR_S 23 | ||
343 | |||
344 | #define AR9170_PHY_REG_SFCORR_EXT (AR9170_PHY_REG_BASE + 0x01c0) | ||
345 | #define AR9170_PHY_SFCORR_EXT_M1_THRESH 0x0000007f | ||
346 | #define AR9170_PHY_SFCORR_EXT_M1_THRESH_S 0 | ||
347 | #define AR9170_PHY_SFCORR_EXT_M2_THRESH 0x00003f80 | ||
348 | #define AR9170_PHY_SFCORR_EXT_M2_THRESH_S 7 | ||
349 | #define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001fc000 | ||
350 | #define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 | ||
351 | #define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0fe00000 | ||
352 | #define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 | ||
353 | #define AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 | ||
354 | |||
355 | #define AR9170_PHY_REG_HALFGI (AR9170_PHY_REG_BASE + 0x01d0) | ||
356 | #define AR9170_PHY_HALFGI_DSC_MAN 0x0007fff0 | ||
357 | #define AR9170_PHY_HALFGI_DSC_MAN_S 4 | ||
358 | #define AR9170_PHY_HALFGI_DSC_EXP 0x0000000f | ||
359 | #define AR9170_PHY_HALFGI_DSC_EXP_S 0 | ||
360 | |||
361 | #define AR9170_PHY_REG_CHANNEL_MASK_01_30 (AR9170_PHY_REG_BASE + 0x01d4) | ||
362 | #define AR9170_PHY_REG_CHANNEL_MASK_31_60 (AR9170_PHY_REG_BASE + 0x01d8) | ||
363 | |||
364 | #define AR9170_PHY_REG_CHAN_INFO_MEMORY (AR9170_PHY_REG_BASE + 0x01dc) | ||
365 | #define AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 | ||
366 | |||
367 | #define AR9170_PHY_REG_HEAVY_CLIP_ENABLE (AR9170_PHY_REG_BASE + 0x01e0) | ||
368 | #define AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS (AR9170_PHY_REG_BASE + 0x01ec) | ||
369 | #define AR9170_PHY_RIFS_INIT_DELAY 0x03ff0000 | ||
370 | |||
371 | #define AR9170_PHY_REG_CALMODE (AR9170_PHY_REG_BASE + 0x01f0) | ||
372 | #define AR9170_PHY_CALMODE_IQ 0x00000000 | ||
373 | #define AR9170_PHY_CALMODE_ADC_GAIN 0x00000001 | ||
374 | #define AR9170_PHY_CALMODE_ADC_DC_PER 0x00000002 | ||
375 | #define AR9170_PHY_CALMODE_ADC_DC_INIT 0x00000003 | ||
376 | |||
377 | #define AR9170_PHY_REG_REFCLKDLY (AR9170_PHY_REG_BASE + 0x01f4) | ||
378 | #define AR9170_PHY_REG_REFCLKPD (AR9170_PHY_REG_BASE + 0x01f8) | ||
379 | |||
380 | |||
381 | #define AR9170_PHY_REG_CAL_MEAS_0(_i) (AR9170_PHY_REG_BASE + \ | ||
382 | 0x0410 + ((_i) << 12)) | ||
383 | #define AR9170_PHY_REG_CAL_MEAS_1(_i) (AR9170_PHY_REG_BASE + \ | ||
384 | 0x0414 \ + ((_i) << 12)) | ||
385 | #define AR9170_PHY_REG_CAL_MEAS_2(_i) (AR9170_PHY_REG_BASE + \ | ||
386 | 0x0418 + ((_i) << 12)) | ||
387 | #define AR9170_PHY_REG_CAL_MEAS_3(_i) (AR9170_PHY_REG_BASE + \ | ||
388 | 0x041c + ((_i) << 12)) | ||
389 | |||
390 | #define AR9170_PHY_REG_CURRENT_RSSI (AR9170_PHY_REG_BASE + 0x041c) | ||
391 | |||
392 | #define AR9170_PHY_REG_RFBUS_GRANT (AR9170_PHY_REG_BASE + 0x0420) | ||
393 | #define AR9170_PHY_RFBUS_GRANT_EN 0x00000001 | ||
394 | |||
395 | #define AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF (AR9170_PHY_REG_BASE + 0x04f4) | ||
396 | #define AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 | ||
397 | |||
398 | #define AR9170_PHY_REG_CHAN_INFO_GAIN (AR9170_PHY_REG_BASE + 0x04fc) | ||
399 | |||
400 | #define AR9170_PHY_REG_MODE (AR9170_PHY_REG_BASE + 0x0a00) | ||
401 | #define AR9170_PHY_MODE_ASYNCFIFO 0x80 | ||
402 | #define AR9170_PHY_MODE_AR2133 0x08 | ||
403 | #define AR9170_PHY_MODE_AR5111 0x00 | ||
404 | #define AR9170_PHY_MODE_AR5112 0x08 | ||
405 | #define AR9170_PHY_MODE_DYNAMIC 0x04 | ||
406 | #define AR9170_PHY_MODE_RF2GHZ 0x02 | ||
407 | #define AR9170_PHY_MODE_RF5GHZ 0x00 | ||
408 | #define AR9170_PHY_MODE_CCK 0x01 | ||
409 | #define AR9170_PHY_MODE_OFDM 0x00 | ||
410 | #define AR9170_PHY_MODE_DYN_CCK_DISABLE 0x100 | ||
411 | |||
412 | #define AR9170_PHY_REG_CCK_TX_CTRL (AR9170_PHY_REG_BASE + 0x0a04) | ||
413 | #define AR9170_PHY_CCK_TX_CTRL_JAPAN 0x00000010 | ||
414 | #define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000c | ||
415 | #define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 | ||
416 | |||
417 | #define AR9170_PHY_REG_CCK_DETECT (AR9170_PHY_REG_BASE + 0x0a08) | ||
418 | #define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003f | ||
419 | #define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 | ||
420 | /* [12:6] settling time for antenna switch */ | ||
421 | #define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001fc0 | ||
422 | #define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 | ||
423 | #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 | ||
424 | #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 | ||
425 | |||
426 | #define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c) | ||
427 | #define AR9170_PHY_REG_GAIN_2GHZ (AR9170_PHY_REG_BASE + 0x0a0c) | ||
428 | #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00fc0000 | ||
429 | #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 | ||
430 | #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003c00 | ||
431 | #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 | ||
432 | #define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001f | ||
433 | #define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 | ||
434 | #define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003e0000 | ||
435 | #define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 | ||
436 | #define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001f000 | ||
437 | #define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 | ||
438 | #define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000fc0 | ||
439 | #define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 | ||
440 | #define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003f | ||
441 | #define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 | ||
442 | |||
443 | #define AR9170_PHY_REG_CCK_RXCTRL4 (AR9170_PHY_REG_BASE + 0x0a1c) | ||
444 | #define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01f80000 | ||
445 | #define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 | ||
446 | |||
447 | #define AR9170_PHY_REG_DAG_CTRLCCK (AR9170_PHY_REG_BASE + 0x0a28) | ||
448 | #define AR9170_REG_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 | ||
449 | #define AR9170_REG_DAG_CTRLCCK_RSSI_THR 0x0001fc00 | ||
450 | #define AR9170_REG_DAG_CTRLCCK_RSSI_THR_S 10 | ||
451 | |||
452 | #define AR9170_PHY_REG_FORCE_CLKEN_CCK (AR9170_PHY_REG_BASE + 0x0a2c) | ||
453 | #define AR9170_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 | ||
454 | |||
455 | #define AR9170_PHY_REG_POWER_TX_RATE3 (AR9170_PHY_REG_BASE + 0x0a34) | ||
456 | #define AR9170_PHY_REG_POWER_TX_RATE4 (AR9170_PHY_REG_BASE + 0x0a38) | ||
457 | |||
458 | #define AR9170_PHY_REG_SCRM_SEQ_XR (AR9170_PHY_REG_BASE + 0x0a3c) | ||
459 | #define AR9170_PHY_REG_HEADER_DETECT_XR (AR9170_PHY_REG_BASE + 0x0a40) | ||
460 | #define AR9170_PHY_REG_CHIRP_DETECTED_XR (AR9170_PHY_REG_BASE + 0x0a44) | ||
461 | #define AR9170_PHY_REG_BLUETOOTH (AR9170_PHY_REG_BASE + 0x0a54) | ||
462 | |||
463 | #define AR9170_PHY_REG_TPCRG1 (AR9170_PHY_REG_BASE + 0x0a58) | ||
464 | #define AR9170_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 | ||
465 | #define AR9170_PHY_TPCRG1_NUM_PD_GAIN_S 14 | ||
466 | #define AR9170_PHY_TPCRG1_PD_GAIN_1 0x00030000 | ||
467 | #define AR9170_PHY_TPCRG1_PD_GAIN_1_S 16 | ||
468 | #define AR9170_PHY_TPCRG1_PD_GAIN_2 0x000c0000 | ||
469 | #define AR9170_PHY_TPCRG1_PD_GAIN_2_S 18 | ||
470 | #define AR9170_PHY_TPCRG1_PD_GAIN_3 0x00300000 | ||
471 | #define AR9170_PHY_TPCRG1_PD_GAIN_3_S 20 | ||
472 | #define AR9170_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 | ||
473 | #define AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S 22 | ||
474 | |||
475 | #define AR9170_PHY_REG_TX_PWRCTRL4 (AR9170_PHY_REG_BASE + 0x0a64) | ||
476 | #define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 | ||
477 | #define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 | ||
478 | #define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001fe | ||
479 | #define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 | ||
480 | |||
481 | #define AR9170_PHY_REG_ANALOG_SWAP (AR9170_PHY_REG_BASE + 0x0a68) | ||
482 | #define AR9170_PHY_ANALOG_SWAP_AB 0x0001 | ||
483 | #define AR9170_PHY_ANALOG_SWAP_ALT_CHAIN 0x00000040 | ||
484 | |||
485 | #define AR9170_PHY_REG_TPCRG5 (AR9170_PHY_REG_BASE + 0x0a6c) | ||
486 | #define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000f | ||
487 | #define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 | ||
488 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003f0 | ||
489 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 | ||
490 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000fc00 | ||
491 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 | ||
492 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003f0000 | ||
493 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 | ||
494 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0fc00000 | ||
495 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 | ||
496 | |||
497 | #define AR9170_PHY_REG_TX_PWRCTRL6_0 (AR9170_PHY_REG_BASE + 0x0a70) | ||
498 | #define AR9170_PHY_REG_TX_PWRCTRL6_1 (AR9170_PHY_REG_BASE + 0x1a70) | ||
499 | #define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000 | ||
500 | #define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 | ||
501 | |||
502 | #define AR9170_PHY_REG_TX_PWRCTRL7 (AR9170_PHY_REG_BASE + 0x0a74) | ||
503 | #define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01f80000 | ||
504 | #define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 | ||
505 | |||
506 | #define AR9170_PHY_REG_TX_PWRCTRL9 (AR9170_PHY_REG_BASE + 0x0a7c) | ||
507 | #define AR9170_PHY_TX_DESIRED_SCALE_CCK 0x00007c00 | ||
508 | #define AR9170_PHY_TX_DESIRED_SCALE_CCK_S 10 | ||
509 | #define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 | ||
510 | #define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 | ||
511 | |||
512 | #define AR9170_PHY_REG_TX_GAIN_TBL1 (AR9170_PHY_REG_BASE + 0x0b00) | ||
513 | #define AR9170_PHY_TX_GAIN 0x0007f000 | ||
514 | #define AR9170_PHY_TX_GAIN_S 12 | ||
515 | |||
516 | /* Carrier leak calibration control, do it after AGC calibration */ | ||
517 | #define AR9170_PHY_REG_CL_CAL_CTL (AR9170_PHY_REG_BASE + 0x0b58) | ||
518 | #define AR9170_PHY_CL_CAL_ENABLE 0x00000002 | ||
519 | #define AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE 0x00000001 | ||
520 | |||
521 | #define AR9170_PHY_REG_POWER_TX_RATE5 (AR9170_PHY_REG_BASE + 0x0b8c) | ||
522 | #define AR9170_PHY_REG_POWER_TX_RATE6 (AR9170_PHY_REG_BASE + 0x0b90) | ||
523 | |||
524 | #define AR9170_PHY_REG_CH0_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x0b98) | ||
525 | #define AR9170_PHY_REG_CH1_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x1b98) | ||
526 | #define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP 0x0000fc00 | ||
527 | #define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S 10 | ||
528 | |||
529 | #define AR9170_PHY_REG_CAL_CHAINMASK (AR9170_PHY_REG_BASE + 0x0b9c) | ||
530 | #define AR9170_PHY_REG_VIT_MASK2_M_46_61 (AR9170_PHY_REG_BASE + 0x0ba0) | ||
531 | #define AR9170_PHY_REG_MASK2_M_31_45 (AR9170_PHY_REG_BASE + 0x0ba4) | ||
532 | #define AR9170_PHY_REG_MASK2_M_16_30 (AR9170_PHY_REG_BASE + 0x0ba8) | ||
533 | #define AR9170_PHY_REG_MASK2_M_00_15 (AR9170_PHY_REG_BASE + 0x0bac) | ||
534 | #define AR9170_PHY_REG_PILOT_MASK_01_30 (AR9170_PHY_REG_BASE + 0x0bb0) | ||
535 | #define AR9170_PHY_REG_PILOT_MASK_31_60 (AR9170_PHY_REG_BASE + 0x0bb4) | ||
536 | #define AR9170_PHY_REG_MASK2_P_15_01 (AR9170_PHY_REG_BASE + 0x0bb8) | ||
537 | #define AR9170_PHY_REG_MASK2_P_30_16 (AR9170_PHY_REG_BASE + 0x0bbc) | ||
538 | #define AR9170_PHY_REG_MASK2_P_45_31 (AR9170_PHY_REG_BASE + 0x0bc0) | ||
539 | #define AR9170_PHY_REG_MASK2_P_61_45 (AR9170_PHY_REG_BASE + 0x0bc4) | ||
540 | #define AR9170_PHY_REG_POWER_TX_SUB (AR9170_PHY_REG_BASE + 0x0bc8) | ||
541 | #define AR9170_PHY_REG_POWER_TX_RATE7 (AR9170_PHY_REG_BASE + 0x0bcc) | ||
542 | #define AR9170_PHY_REG_POWER_TX_RATE8 (AR9170_PHY_REG_BASE + 0x0bd0) | ||
543 | #define AR9170_PHY_REG_POWER_TX_RATE9 (AR9170_PHY_REG_BASE + 0x0bd4) | ||
544 | #define AR9170_PHY_REG_XPA_CFG (AR9170_PHY_REG_BASE + 0x0bd8) | ||
545 | #define AR9170_PHY_FORCE_XPA_CFG 0x000000001 | ||
546 | #define AR9170_PHY_FORCE_XPA_CFG_S 0 | ||
547 | |||
548 | #define AR9170_PHY_REG_CH1_CCA (AR9170_PHY_REG_BASE + 0x1064) | ||
549 | #define AR9170_PHY_CH1_MINCCA_PWR 0x0ff80000 | ||
550 | #define AR9170_PHY_CH1_MINCCA_PWR_S 19 | ||
551 | |||
552 | #define AR9170_PHY_REG_CH2_CCA (AR9170_PHY_REG_BASE + 0x2064) | ||
553 | #define AR9170_PHY_CH2_MINCCA_PWR 0x0ff80000 | ||
554 | #define AR9170_PHY_CH2_MINCCA_PWR_S 19 | ||
555 | |||
556 | #define AR9170_PHY_REG_CH1_EXT_CCA (AR9170_PHY_REG_BASE + 0x11bc) | ||
557 | #define AR9170_PHY_CH1_EXT_MINCCA_PWR 0xff800000 | ||
558 | #define AR9170_PHY_CH1_EXT_MINCCA_PWR_S 23 | ||
559 | |||
560 | #define AR9170_PHY_REG_CH2_EXT_CCA (AR9170_PHY_REG_BASE + 0x21bc) | ||
561 | #define AR9170_PHY_CH2_EXT_MINCCA_PWR 0xff800000 | ||
562 | #define AR9170_PHY_CH2_EXT_MINCCA_PWR_S 23 | ||
563 | |||
564 | #define REDUCE_CHAIN_0 0x00000050 | ||
565 | #define REDUCE_CHAIN_1 0x00000051 | ||
566 | |||
567 | #endif /* __CARL9170_SHARED_PHY_H */ | ||
diff --git a/drivers/net/wireless/ath/carl9170/wlan.h b/drivers/net/wireless/ath/carl9170/wlan.h new file mode 100644 index 000000000000..48ead2268f50 --- /dev/null +++ b/drivers/net/wireless/ath/carl9170/wlan.h | |||
@@ -0,0 +1,412 @@ | |||
1 | /* | ||
2 | * Shared Atheros AR9170 Header | ||
3 | * | ||
4 | * RX/TX meta descriptor format | ||
5 | * | ||
6 | * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> | ||
7 | * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, see | ||
20 | * http://www.gnu.org/licenses/. | ||
21 | * | ||
22 | * This file incorporates work covered by the following copyright and | ||
23 | * permission notice: | ||
24 | * Copyright (c) 2007-2008 Atheros Communications, Inc. | ||
25 | * | ||
26 | * Permission to use, copy, modify, and/or distribute this software for any | ||
27 | * purpose with or without fee is hereby granted, provided that the above | ||
28 | * copyright notice and this permission notice appear in all copies. | ||
29 | * | ||
30 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
31 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
32 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
33 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
34 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
35 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
36 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
37 | */ | ||
38 | |||
39 | #ifndef __CARL9170_SHARED_WLAN_H | ||
40 | #define __CARL9170_SHARED_WLAN_H | ||
41 | |||
42 | #include "fwcmd.h" | ||
43 | |||
44 | #define AR9170_RX_PHY_RATE_CCK_1M 0x0a | ||
45 | #define AR9170_RX_PHY_RATE_CCK_2M 0x14 | ||
46 | #define AR9170_RX_PHY_RATE_CCK_5M 0x37 | ||
47 | #define AR9170_RX_PHY_RATE_CCK_11M 0x6e | ||
48 | |||
49 | #define AR9170_ENC_ALG_NONE 0x0 | ||
50 | #define AR9170_ENC_ALG_WEP64 0x1 | ||
51 | #define AR9170_ENC_ALG_TKIP 0x2 | ||
52 | #define AR9170_ENC_ALG_AESCCMP 0x4 | ||
53 | #define AR9170_ENC_ALG_WEP128 0x5 | ||
54 | #define AR9170_ENC_ALG_WEP256 0x6 | ||
55 | #define AR9170_ENC_ALG_CENC 0x7 | ||
56 | |||
57 | #define AR9170_RX_ENC_SOFTWARE 0x8 | ||
58 | |||
59 | #define AR9170_RX_STATUS_MODULATION 0x03 | ||
60 | #define AR9170_RX_STATUS_MODULATION_S 0 | ||
61 | #define AR9170_RX_STATUS_MODULATION_CCK 0x00 | ||
62 | #define AR9170_RX_STATUS_MODULATION_OFDM 0x01 | ||
63 | #define AR9170_RX_STATUS_MODULATION_HT 0x02 | ||
64 | #define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03 | ||
65 | |||
66 | /* depends on modulation */ | ||
67 | #define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08 | ||
68 | #define AR9170_RX_STATUS_GREENFIELD 0x08 | ||
69 | |||
70 | #define AR9170_RX_STATUS_MPDU 0x30 | ||
71 | #define AR9170_RX_STATUS_MPDU_S 4 | ||
72 | #define AR9170_RX_STATUS_MPDU_SINGLE 0x00 | ||
73 | #define AR9170_RX_STATUS_MPDU_FIRST 0x20 | ||
74 | #define AR9170_RX_STATUS_MPDU_MIDDLE 0x30 | ||
75 | #define AR9170_RX_STATUS_MPDU_LAST 0x10 | ||
76 | |||
77 | #define AR9170_RX_ERROR_RXTO 0x01 | ||
78 | #define AR9170_RX_ERROR_OVERRUN 0x02 | ||
79 | #define AR9170_RX_ERROR_DECRYPT 0x04 | ||
80 | #define AR9170_RX_ERROR_FCS 0x08 | ||
81 | #define AR9170_RX_ERROR_WRONG_RA 0x10 | ||
82 | #define AR9170_RX_ERROR_PLCP 0x20 | ||
83 | #define AR9170_RX_ERROR_MMIC 0x40 | ||
84 | #define AR9170_RX_ERROR_FATAL 0x80 | ||
85 | |||
86 | /* these are either-or */ | ||
87 | #define AR9170_TX_MAC_PROT_RTS 0x0001 | ||
88 | #define AR9170_TX_MAC_PROT_CTS 0x0002 | ||
89 | #define AR9170_TX_MAC_PROT 0x0003 | ||
90 | |||
91 | #define AR9170_TX_MAC_NO_ACK 0x0004 | ||
92 | /* if unset, MAC will only do SIFS space before frame */ | ||
93 | #define AR9170_TX_MAC_BACKOFF 0x0008 | ||
94 | #define AR9170_TX_MAC_BURST 0x0010 | ||
95 | #define AR9170_TX_MAC_AGGR 0x0020 | ||
96 | |||
97 | /* encryption is a two-bit field */ | ||
98 | #define AR9170_TX_MAC_ENCR_NONE 0x0000 | ||
99 | #define AR9170_TX_MAC_ENCR_RC4 0x0040 | ||
100 | #define AR9170_TX_MAC_ENCR_CENC 0x0080 | ||
101 | #define AR9170_TX_MAC_ENCR_AES 0x00c0 | ||
102 | |||
103 | #define AR9170_TX_MAC_MMIC 0x0100 | ||
104 | #define AR9170_TX_MAC_HW_DURATION 0x0200 | ||
105 | #define AR9170_TX_MAC_QOS_S 10 | ||
106 | #define AR9170_TX_MAC_QOS 0x0c00 | ||
107 | #define AR9170_TX_MAC_DISABLE_TXOP 0x1000 | ||
108 | #define AR9170_TX_MAC_TXOP_RIFS 0x2000 | ||
109 | #define AR9170_TX_MAC_IMM_BA 0x4000 | ||
110 | |||
111 | /* either-or */ | ||
112 | #define AR9170_TX_PHY_MOD_CCK 0x00000000 | ||
113 | #define AR9170_TX_PHY_MOD_OFDM 0x00000001 | ||
114 | #define AR9170_TX_PHY_MOD_HT 0x00000002 | ||
115 | |||
116 | /* depends on modulation */ | ||
117 | #define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004 | ||
118 | #define AR9170_TX_PHY_GREENFIELD 0x00000004 | ||
119 | |||
120 | #define AR9170_TX_PHY_BW_S 3 | ||
121 | #define AR9170_TX_PHY_BW (3 << AR9170_TX_PHY_BW_SHIFT) | ||
122 | #define AR9170_TX_PHY_BW_20MHZ 0 | ||
123 | #define AR9170_TX_PHY_BW_40MHZ 2 | ||
124 | #define AR9170_TX_PHY_BW_40MHZ_DUP 3 | ||
125 | |||
126 | #define AR9170_TX_PHY_TX_HEAVY_CLIP_S 6 | ||
127 | #define AR9170_TX_PHY_TX_HEAVY_CLIP (7 << \ | ||
128 | AR9170_TX_PHY_TX_HEAVY_CLIP_S) | ||
129 | |||
130 | #define AR9170_TX_PHY_TX_PWR_S 9 | ||
131 | #define AR9170_TX_PHY_TX_PWR (0x3f << \ | ||
132 | AR9170_TX_PHY_TX_PWR_S) | ||
133 | |||
134 | #define AR9170_TX_PHY_TXCHAIN_S 15 | ||
135 | #define AR9170_TX_PHY_TXCHAIN (7 << \ | ||
136 | AR9170_TX_PHY_TXCHAIN_S) | ||
137 | #define AR9170_TX_PHY_TXCHAIN_1 1 | ||
138 | /* use for cck, ofdm 6/9/12/18/24 and HT if capable */ | ||
139 | #define AR9170_TX_PHY_TXCHAIN_2 5 | ||
140 | |||
141 | #define AR9170_TX_PHY_MCS_S 18 | ||
142 | #define AR9170_TX_PHY_MCS (0x7f << \ | ||
143 | AR9170_TX_PHY_MCS_S) | ||
144 | |||
145 | #define AR9170_TX_PHY_RATE_CCK_1M 0x0 | ||
146 | #define AR9170_TX_PHY_RATE_CCK_2M 0x1 | ||
147 | #define AR9170_TX_PHY_RATE_CCK_5M 0x2 | ||
148 | #define AR9170_TX_PHY_RATE_CCK_11M 0x3 | ||
149 | |||
150 | /* same as AR9170_RX_PHY_RATE */ | ||
151 | #define AR9170_TXRX_PHY_RATE_OFDM_6M 0xb | ||
152 | #define AR9170_TXRX_PHY_RATE_OFDM_9M 0xf | ||
153 | #define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa | ||
154 | #define AR9170_TXRX_PHY_RATE_OFDM_18M 0xe | ||
155 | #define AR9170_TXRX_PHY_RATE_OFDM_24M 0x9 | ||
156 | #define AR9170_TXRX_PHY_RATE_OFDM_36M 0xd | ||
157 | #define AR9170_TXRX_PHY_RATE_OFDM_48M 0x8 | ||
158 | #define AR9170_TXRX_PHY_RATE_OFDM_54M 0xc | ||
159 | |||
160 | #define AR9170_TXRX_PHY_RATE_HT_MCS0 0x0 | ||
161 | #define AR9170_TXRX_PHY_RATE_HT_MCS1 0x1 | ||
162 | #define AR9170_TXRX_PHY_RATE_HT_MCS2 0x2 | ||
163 | #define AR9170_TXRX_PHY_RATE_HT_MCS3 0x3 | ||
164 | #define AR9170_TXRX_PHY_RATE_HT_MCS4 0x4 | ||
165 | #define AR9170_TXRX_PHY_RATE_HT_MCS5 0x5 | ||
166 | #define AR9170_TXRX_PHY_RATE_HT_MCS6 0x6 | ||
167 | #define AR9170_TXRX_PHY_RATE_HT_MCS7 0x7 | ||
168 | #define AR9170_TXRX_PHY_RATE_HT_MCS8 0x8 | ||
169 | #define AR9170_TXRX_PHY_RATE_HT_MCS9 0x9 | ||
170 | #define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa | ||
171 | #define AR9170_TXRX_PHY_RATE_HT_MCS11 0xb | ||
172 | #define AR9170_TXRX_PHY_RATE_HT_MCS12 0xc | ||
173 | #define AR9170_TXRX_PHY_RATE_HT_MCS13 0xd | ||
174 | #define AR9170_TXRX_PHY_RATE_HT_MCS14 0xe | ||
175 | #define AR9170_TXRX_PHY_RATE_HT_MCS15 0xf | ||
176 | |||
177 | #define AR9170_TX_PHY_SHORT_GI 0x80000000 | ||
178 | |||
179 | #ifdef __CARL9170FW__ | ||
180 | struct ar9170_tx_hw_mac_control { | ||
181 | union { | ||
182 | struct { | ||
183 | /* | ||
184 | * Beware of compiler bugs in all gcc pre 4.4! | ||
185 | */ | ||
186 | |||
187 | u8 erp_prot:2; | ||
188 | u8 no_ack:1; | ||
189 | u8 backoff:1; | ||
190 | u8 burst:1; | ||
191 | u8 ampdu:1; | ||
192 | |||
193 | u8 enc_mode:2; | ||
194 | |||
195 | u8 hw_mmic:1; | ||
196 | u8 hw_duration:1; | ||
197 | |||
198 | u8 qos_queue:2; | ||
199 | |||
200 | u8 disable_txop:1; | ||
201 | u8 txop_rifs:1; | ||
202 | |||
203 | u8 ba_end:1; | ||
204 | u8 probe:1; | ||
205 | } __packed; | ||
206 | |||
207 | __le16 set; | ||
208 | } __packed; | ||
209 | } __packed; | ||
210 | |||
211 | struct ar9170_tx_hw_phy_control { | ||
212 | union { | ||
213 | struct { | ||
214 | /* | ||
215 | * Beware of compiler bugs in all gcc pre 4.4! | ||
216 | */ | ||
217 | |||
218 | u8 modulation:2; | ||
219 | u8 preamble:1; | ||
220 | u8 bandwidth:2; | ||
221 | u8:1; | ||
222 | u8 heavy_clip:3; | ||
223 | u8 tx_power:6; | ||
224 | u8 chains:3; | ||
225 | u8 mcs:7; | ||
226 | u8:6; | ||
227 | u8 short_gi:1; | ||
228 | } __packed; | ||
229 | |||
230 | __le32 set; | ||
231 | } __packed; | ||
232 | } __packed; | ||
233 | |||
234 | struct ar9170_tx_rate_info { | ||
235 | u8 tries:3; | ||
236 | u8 erp_prot:2; | ||
237 | u8 ampdu:1; | ||
238 | u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */ | ||
239 | } __packed; | ||
240 | |||
241 | struct carl9170_tx_superdesc { | ||
242 | __le16 len; | ||
243 | u8 rix; | ||
244 | u8 cnt; | ||
245 | u8 cookie; | ||
246 | u8 ampdu_density:3; | ||
247 | u8 ampdu_factor:2; | ||
248 | u8 ampdu_commit_density:1; | ||
249 | u8 ampdu_commit_factor:1; | ||
250 | u8 ampdu_unused_bit:1; | ||
251 | u8 queue:2; | ||
252 | u8 reserved:1; | ||
253 | u8 vif_id:3; | ||
254 | u8 fill_in_tsf:1; | ||
255 | u8 cab:1; | ||
256 | u8 padding2; | ||
257 | struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES]; | ||
258 | struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES]; | ||
259 | } __packed; | ||
260 | |||
261 | struct ar9170_tx_hwdesc { | ||
262 | __le16 length; | ||
263 | struct ar9170_tx_hw_mac_control mac; | ||
264 | struct ar9170_tx_hw_phy_control phy; | ||
265 | } __packed; | ||
266 | |||
267 | struct ar9170_tx_frame { | ||
268 | struct ar9170_tx_hwdesc hdr; | ||
269 | |||
270 | union { | ||
271 | struct ieee80211_hdr i3e; | ||
272 | u8 payload[0]; | ||
273 | } data; | ||
274 | } __packed; | ||
275 | |||
276 | struct carl9170_tx_superframe { | ||
277 | struct carl9170_tx_superdesc s; | ||
278 | struct ar9170_tx_frame f; | ||
279 | } __packed; | ||
280 | |||
281 | #endif /* __CARL9170FW__ */ | ||
282 | |||
283 | struct _ar9170_tx_hwdesc { | ||
284 | __le16 length; | ||
285 | __le16 mac_control; | ||
286 | __le32 phy_control; | ||
287 | } __packed; | ||
288 | |||
289 | #define CARL9170_TX_SUPER_AMPDU_DENSITY_S 0 | ||
290 | #define CARL9170_TX_SUPER_AMPDU_DENSITY 0x7 | ||
291 | #define CARL9170_TX_SUPER_AMPDU_FACTOR 0x18 | ||
292 | #define CARL9170_TX_SUPER_AMPDU_FACTOR_S 3 | ||
293 | #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY 0x20 | ||
294 | #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S 5 | ||
295 | #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40 | ||
296 | #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S 6 | ||
297 | |||
298 | #define CARL9170_TX_SUPER_MISC_QUEUE 0x3 | ||
299 | #define CARL9170_TX_SUPER_MISC_QUEUE_S 0 | ||
300 | #define CARL9170_TX_SUPER_MISC_VIF_ID 0x38 | ||
301 | #define CARL9170_TX_SUPER_MISC_VIF_ID_S 3 | ||
302 | #define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40 | ||
303 | #define CARL9170_TX_SUPER_MISC_CAB 0x80 | ||
304 | |||
305 | #define CARL9170_TX_SUPER_RI_TRIES 0x7 | ||
306 | #define CARL9170_TX_SUPER_RI_TRIES_S 0 | ||
307 | #define CARL9170_TX_SUPER_RI_ERP_PROT 0x18 | ||
308 | #define CARL9170_TX_SUPER_RI_ERP_PROT_S 3 | ||
309 | #define CARL9170_TX_SUPER_RI_AMPDU 0x20 | ||
310 | #define CARL9170_TX_SUPER_RI_AMPDU_S 5 | ||
311 | |||
312 | struct _carl9170_tx_superdesc { | ||
313 | __le16 len; | ||
314 | u8 rix; | ||
315 | u8 cnt; | ||
316 | u8 cookie; | ||
317 | u8 ampdu_settings; | ||
318 | u8 misc; | ||
319 | u8 padding; | ||
320 | u8 ri[CARL9170_TX_MAX_RATES]; | ||
321 | __le32 rr[CARL9170_TX_MAX_RETRY_RATES]; | ||
322 | } __packed; | ||
323 | |||
324 | struct _carl9170_tx_superframe { | ||
325 | struct _carl9170_tx_superdesc s; | ||
326 | struct _ar9170_tx_hwdesc f; | ||
327 | u8 frame_data[0]; | ||
328 | } __packed; | ||
329 | |||
330 | #define CARL9170_TX_SUPERDESC_LEN 24 | ||
331 | #define AR9170_TX_HWDESC_LEN 8 | ||
332 | #define AR9170_TX_SUPERFRAME_LEN (CARL9170_TX_HWDESC_LEN + \ | ||
333 | AR9170_TX_SUPERDESC_LEN) | ||
334 | |||
335 | struct ar9170_rx_head { | ||
336 | u8 plcp[12]; | ||
337 | } __packed; | ||
338 | |||
339 | struct ar9170_rx_phystatus { | ||
340 | union { | ||
341 | struct { | ||
342 | u8 rssi_ant0, rssi_ant1, rssi_ant2, | ||
343 | rssi_ant0x, rssi_ant1x, rssi_ant2x, | ||
344 | rssi_combined; | ||
345 | } __packed; | ||
346 | u8 rssi[7]; | ||
347 | } __packed; | ||
348 | |||
349 | u8 evm_stream0[6], evm_stream1[6]; | ||
350 | u8 phy_err; | ||
351 | } __packed; | ||
352 | |||
353 | struct ar9170_rx_macstatus { | ||
354 | u8 SAidx, DAidx; | ||
355 | u8 error; | ||
356 | u8 status; | ||
357 | } __packed; | ||
358 | |||
359 | struct ar9170_rx_frame_single { | ||
360 | struct ar9170_rx_head phy_head; | ||
361 | struct ieee80211_hdr i3e; | ||
362 | struct ar9170_rx_phystatus phy_tail; | ||
363 | struct ar9170_rx_macstatus macstatus; | ||
364 | } __packed; | ||
365 | |||
366 | struct ar9170_rx_frame_head { | ||
367 | struct ar9170_rx_head phy_head; | ||
368 | struct ieee80211_hdr i3e; | ||
369 | struct ar9170_rx_macstatus macstatus; | ||
370 | } __packed; | ||
371 | |||
372 | struct ar9170_rx_frame_middle { | ||
373 | struct ieee80211_hdr i3e; | ||
374 | struct ar9170_rx_macstatus macstatus; | ||
375 | } __packed; | ||
376 | |||
377 | struct ar9170_rx_frame_tail { | ||
378 | struct ieee80211_hdr i3e; | ||
379 | struct ar9170_rx_phystatus phy_tail; | ||
380 | struct ar9170_rx_macstatus macstatus; | ||
381 | } __packed; | ||
382 | |||
383 | struct ar9170_rx_frame { | ||
384 | union { | ||
385 | struct ar9170_rx_frame_single single; | ||
386 | struct ar9170_rx_frame_head head; | ||
387 | struct ar9170_rx_frame_middle middle; | ||
388 | struct ar9170_rx_frame_tail tail; | ||
389 | } __packed; | ||
390 | } __packed; | ||
391 | |||
392 | static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t) | ||
393 | { | ||
394 | return (t->SAidx & 0xc0) >> 4 | | ||
395 | (t->DAidx & 0xc0) >> 6; | ||
396 | } | ||
397 | |||
398 | enum ar9170_txq { | ||
399 | AR9170_TXQ_BE, | ||
400 | |||
401 | AR9170_TXQ_VI, | ||
402 | AR9170_TXQ_VO, | ||
403 | AR9170_TXQ_BK, | ||
404 | |||
405 | __AR9170_NUM_TXQ, | ||
406 | }; | ||
407 | |||
408 | static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 }; | ||
409 | |||
410 | #define AR9170_TXQ_DEPTH 32 | ||
411 | |||
412 | #endif /* __CARL9170_SHARED_WLAN_H */ | ||