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-rw-r--r--drivers/net/ethernet/intel/e1000e/defines.h1
-rw-r--r--drivers/net/ethernet/intel/e1000e/e1000.h2
-rw-r--r--drivers/net/ethernet/intel/e1000e/ethtool.c6
-rw-r--r--drivers/net/ethernet/intel/e1000e/hw.h6
-rw-r--r--drivers/net/ethernet/intel/e1000e/ich8lan.c770
-rw-r--r--drivers/net/ethernet/intel/e1000e/ich8lan.h9
-rw-r--r--drivers/net/ethernet/intel/e1000e/netdev.c50
-rw-r--r--drivers/net/ethernet/intel/e1000e/ptp.c4
-rw-r--r--drivers/net/ethernet/intel/e1000e/regs.h3
9 files changed, 768 insertions, 83 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h
index bb7ab3c321d6..0570c668ec3d 100644
--- a/drivers/net/ethernet/intel/e1000e/defines.h
+++ b/drivers/net/ethernet/intel/e1000e/defines.h
@@ -141,6 +141,7 @@
141#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 141#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
142#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 142#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
143#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 143#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
144#define E1000_RCTL_RDMTS_HEX 0x00010000
144#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 145#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
145#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 146#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
146#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 147#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index 9416e5a7e0c8..a69f09e37b58 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -132,6 +132,7 @@ enum e1000_boards {
132 board_pchlan, 132 board_pchlan,
133 board_pch2lan, 133 board_pch2lan,
134 board_pch_lpt, 134 board_pch_lpt,
135 board_pch_spt
135}; 136};
136 137
137struct e1000_ps_page { 138struct e1000_ps_page {
@@ -501,6 +502,7 @@ extern const struct e1000_info e1000_ich10_info;
501extern const struct e1000_info e1000_pch_info; 502extern const struct e1000_info e1000_pch_info;
502extern const struct e1000_info e1000_pch2_info; 503extern const struct e1000_info e1000_pch2_info;
503extern const struct e1000_info e1000_pch_lpt_info; 504extern const struct e1000_info e1000_pch_lpt_info;
505extern const struct e1000_info e1000_pch_spt_info;
504extern const struct e1000_info e1000_es2_info; 506extern const struct e1000_info e1000_es2_info;
505 507
506void e1000e_ptp_init(struct e1000_adapter *adapter); 508void e1000e_ptp_init(struct e1000_adapter *adapter);
diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c
index 865ce45f9ec3..11f486e4ff7b 100644
--- a/drivers/net/ethernet/intel/e1000e/ethtool.c
+++ b/drivers/net/ethernet/intel/e1000e/ethtool.c
@@ -896,18 +896,20 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
896 case e1000_pchlan: 896 case e1000_pchlan:
897 case e1000_pch2lan: 897 case e1000_pch2lan:
898 case e1000_pch_lpt: 898 case e1000_pch_lpt:
899 case e1000_pch_spt:
899 mask |= (1 << 18); 900 mask |= (1 << 18);
900 break; 901 break;
901 default: 902 default:
902 break; 903 break;
903 } 904 }
904 905
905 if (mac->type == e1000_pch_lpt) 906 if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt))
906 wlock_mac = (er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK) >> 907 wlock_mac = (er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK) >>
907 E1000_FWSM_WLOCK_MAC_SHIFT; 908 E1000_FWSM_WLOCK_MAC_SHIFT;
908 909
909 for (i = 0; i < mac->rar_entry_count; i++) { 910 for (i = 0; i < mac->rar_entry_count; i++) {
910 if (mac->type == e1000_pch_lpt) { 911 if ((mac->type == e1000_pch_lpt) ||
912 (mac->type == e1000_pch_spt)) {
911 /* Cannot test write-protected SHRAL[n] registers */ 913 /* Cannot test write-protected SHRAL[n] registers */
912 if ((wlock_mac == 1) || (wlock_mac && (i > wlock_mac))) 914 if ((wlock_mac == 1) || (wlock_mac && (i > wlock_mac)))
913 continue; 915 continue;
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index 72f5475c4b90..19e8c487db06 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -87,6 +87,10 @@ struct e1000_hw;
87#define E1000_DEV_ID_PCH_I218_V2 0x15A1 87#define E1000_DEV_ID_PCH_I218_V2 0x15A1
88#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 88#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
89#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 89#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
90#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
91#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
92#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
93#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
90 94
91#define E1000_REVISION_4 4 95#define E1000_REVISION_4 4
92 96
@@ -108,6 +112,7 @@ enum e1000_mac_type {
108 e1000_pchlan, 112 e1000_pchlan,
109 e1000_pch2lan, 113 e1000_pch2lan,
110 e1000_pch_lpt, 114 e1000_pch_lpt,
115 e1000_pch_spt,
111}; 116};
112 117
113enum e1000_media_type { 118enum e1000_media_type {
@@ -153,6 +158,7 @@ enum e1000_bus_width {
153 e1000_bus_width_pcie_x1, 158 e1000_bus_width_pcie_x1,
154 e1000_bus_width_pcie_x2, 159 e1000_bus_width_pcie_x2,
155 e1000_bus_width_pcie_x4 = 4, 160 e1000_bus_width_pcie_x4 = 4,
161 e1000_bus_width_pcie_x8 = 8,
156 e1000_bus_width_32, 162 e1000_bus_width_32,
157 e1000_bus_width_64, 163 e1000_bus_width_64,
158 e1000_bus_width_reserved 164 e1000_bus_width_reserved
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index 48b74a549155..7523f510c7e4 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -123,6 +123,14 @@ static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
123 u16 *data); 123 u16 *data);
124static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 124static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data); 125 u8 size, u16 *data);
126static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
127 u32 *data);
128static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
129 u32 offset, u32 *data);
130static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
131 u32 offset, u32 data);
132static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
133 u32 offset, u32 dword);
126static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 134static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
127static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 135static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
128static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 136static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
@@ -229,7 +237,8 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
229 if (ret_val) 237 if (ret_val)
230 return false; 238 return false;
231out: 239out:
232 if (hw->mac.type == e1000_pch_lpt) { 240 if ((hw->mac.type == e1000_pch_lpt) ||
241 (hw->mac.type == e1000_pch_spt)) {
233 /* Unforce SMBus mode in PHY */ 242 /* Unforce SMBus mode in PHY */
234 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 243 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
235 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 244 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
@@ -321,6 +330,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
321 */ 330 */
322 switch (hw->mac.type) { 331 switch (hw->mac.type) {
323 case e1000_pch_lpt: 332 case e1000_pch_lpt:
333 case e1000_pch_spt:
324 if (e1000_phy_is_accessible_pchlan(hw)) 334 if (e1000_phy_is_accessible_pchlan(hw))
325 break; 335 break;
326 336
@@ -461,6 +471,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
461 /* fall-through */ 471 /* fall-through */
462 case e1000_pch2lan: 472 case e1000_pch2lan:
463 case e1000_pch_lpt: 473 case e1000_pch_lpt:
474 case e1000_pch_spt:
464 /* In case the PHY needs to be in mdio slow mode, 475 /* In case the PHY needs to be in mdio slow mode,
465 * set slow mode and try to get the PHY id again. 476 * set slow mode and try to get the PHY id again.
466 */ 477 */
@@ -590,35 +601,50 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
590 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 601 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
591 u32 gfpreg, sector_base_addr, sector_end_addr; 602 u32 gfpreg, sector_base_addr, sector_end_addr;
592 u16 i; 603 u16 i;
604 u32 nvm_size;
593 605
594 /* Can't read flash registers if the register set isn't mapped. */ 606 /* Can't read flash registers if the register set isn't mapped. */
595 if (!hw->flash_address) {
596 e_dbg("ERROR: Flash registers not mapped\n");
597 return -E1000_ERR_CONFIG;
598 }
599
600 nvm->type = e1000_nvm_flash_sw; 607 nvm->type = e1000_nvm_flash_sw;
608 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
609 * STRAP register
610 */
611 if (hw->mac.type == e1000_pch_spt) {
612 nvm->flash_base_addr = 0;
613 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
614 * NVM_SIZE_MULTIPLIER;
615 nvm->flash_bank_size = nvm_size / 2;
616 /* Adjust to word count */
617 nvm->flash_bank_size /= sizeof(u16);
618 /* Set the base address for flash register access */
619 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
620 } else {
621 if (!hw->flash_address) {
622 e_dbg("ERROR: Flash registers not mapped\n");
623 return -E1000_ERR_CONFIG;
624 }
601 625
602 gfpreg = er32flash(ICH_FLASH_GFPREG); 626 gfpreg = er32flash(ICH_FLASH_GFPREG);
603 627
604 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 628 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
605 * Add 1 to sector_end_addr since this sector is included in 629 * Add 1 to sector_end_addr since this sector is included in
606 * the overall size. 630 * the overall size.
607 */ 631 */
608 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 632 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
609 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 633 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
610 634
611 /* flash_base_addr is byte-aligned */ 635 /* flash_base_addr is byte-aligned */
612 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 636 nvm->flash_base_addr = sector_base_addr
637 << FLASH_SECTOR_ADDR_SHIFT;
613 638
614 /* find total size of the NVM, then cut in half since the total 639 /* find total size of the NVM, then cut in half since the total
615 * size represents two separate NVM banks. 640 * size represents two separate NVM banks.
616 */ 641 */
617 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 642 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
618 << FLASH_SECTOR_ADDR_SHIFT); 643 << FLASH_SECTOR_ADDR_SHIFT);
619 nvm->flash_bank_size /= 2; 644 nvm->flash_bank_size /= 2;
620 /* Adjust to word count */ 645 /* Adjust to word count */
621 nvm->flash_bank_size /= sizeof(u16); 646 nvm->flash_bank_size /= sizeof(u16);
647 }
622 648
623 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 649 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
624 650
@@ -682,6 +708,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
682 mac->ops.rar_set = e1000_rar_set_pch2lan; 708 mac->ops.rar_set = e1000_rar_set_pch2lan;
683 /* fall-through */ 709 /* fall-through */
684 case e1000_pch_lpt: 710 case e1000_pch_lpt:
711 case e1000_pch_spt:
685 case e1000_pchlan: 712 case e1000_pchlan:
686 /* check management mode */ 713 /* check management mode */
687 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 714 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
@@ -699,7 +726,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
699 break; 726 break;
700 } 727 }
701 728
702 if (mac->type == e1000_pch_lpt) { 729 if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt)) {
703 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 730 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
704 mac->ops.rar_set = e1000_rar_set_pch_lpt; 731 mac->ops.rar_set = e1000_rar_set_pch_lpt;
705 mac->ops.setup_physical_interface = 732 mac->ops.setup_physical_interface =
@@ -919,8 +946,9 @@ release:
919 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 946 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
920 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 947 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
921 948
922 if (!link || ((status & E1000_STATUS_SPEED_100) && 949 if ((hw->phy.revision > 5) || !link ||
923 (status & E1000_STATUS_FD))) 950 ((status & E1000_STATUS_SPEED_100) &&
951 (status & E1000_STATUS_FD)))
924 goto update_fextnvm6; 952 goto update_fextnvm6;
925 953
926 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg); 954 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
@@ -1100,6 +1128,21 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1100 if (ret_val) 1128 if (ret_val)
1101 goto out; 1129 goto out;
1102 1130
1131 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1132 * LPLU and disable Gig speed when entering ULP
1133 */
1134 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1135 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1136 &phy_reg);
1137 if (ret_val)
1138 goto release;
1139 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1140 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1141 phy_reg);
1142 if (ret_val)
1143 goto release;
1144 }
1145
1103 /* Force SMBus mode in PHY */ 1146 /* Force SMBus mode in PHY */
1104 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1147 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1105 if (ret_val) 1148 if (ret_val)
@@ -1302,7 +1345,8 @@ out:
1302static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1345static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1303{ 1346{
1304 struct e1000_mac_info *mac = &hw->mac; 1347 struct e1000_mac_info *mac = &hw->mac;
1305 s32 ret_val; 1348 s32 ret_val, tipg_reg = 0;
1349 u16 emi_addr, emi_val = 0;
1306 bool link; 1350 bool link;
1307 u16 phy_reg; 1351 u16 phy_reg;
1308 1352
@@ -1333,48 +1377,55 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1333 * the IPG and reduce Rx latency in the PHY. 1377 * the IPG and reduce Rx latency in the PHY.
1334 */ 1378 */
1335 if (((hw->mac.type == e1000_pch2lan) || 1379 if (((hw->mac.type == e1000_pch2lan) ||
1336 (hw->mac.type == e1000_pch_lpt)) && link) { 1380 (hw->mac.type == e1000_pch_lpt) ||
1381 (hw->mac.type == e1000_pch_spt)) && link) {
1337 u32 reg; 1382 u32 reg;
1338 1383
1339 reg = er32(STATUS); 1384 reg = er32(STATUS);
1385 tipg_reg = er32(TIPG);
1386 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1387
1340 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) { 1388 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1341 u16 emi_addr; 1389 tipg_reg |= 0xFF;
1390 /* Reduce Rx latency in analog PHY */
1391 emi_val = 0;
1392 } else {
1342 1393
1343 reg = er32(TIPG); 1394 /* Roll back the default values */
1344 reg &= ~E1000_TIPG_IPGT_MASK; 1395 tipg_reg |= 0x08;
1345 reg |= 0xFF; 1396 emi_val = 1;
1346 ew32(TIPG, reg); 1397 }
1347 1398
1348 /* Reduce Rx latency in analog PHY */ 1399 ew32(TIPG, tipg_reg);
1349 ret_val = hw->phy.ops.acquire(hw);
1350 if (ret_val)
1351 return ret_val;
1352 1400
1353 if (hw->mac.type == e1000_pch2lan) 1401 ret_val = hw->phy.ops.acquire(hw);
1354 emi_addr = I82579_RX_CONFIG; 1402 if (ret_val)
1355 else 1403 return ret_val;
1356 emi_addr = I217_RX_CONFIG;
1357 1404
1358 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0); 1405 if (hw->mac.type == e1000_pch2lan)
1406 emi_addr = I82579_RX_CONFIG;
1407 else
1408 emi_addr = I217_RX_CONFIG;
1409 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1359 1410
1360 hw->phy.ops.release(hw); 1411 hw->phy.ops.release(hw);
1361 1412
1362 if (ret_val) 1413 if (ret_val)
1363 return ret_val; 1414 return ret_val;
1364 }
1365 } 1415 }
1366 1416
1367 /* Work-around I218 hang issue */ 1417 /* Work-around I218 hang issue */
1368 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1418 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1369 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1419 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1370 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1420 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1371 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1421 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3) ||
1422 (hw->mac.type == e1000_pch_spt)) {
1372 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1423 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1373 if (ret_val) 1424 if (ret_val)
1374 return ret_val; 1425 return ret_val;
1375 } 1426 }
1376 1427 if ((hw->mac.type == e1000_pch_lpt) ||
1377 if (hw->mac.type == e1000_pch_lpt) { 1428 (hw->mac.type == e1000_pch_spt)) {
1378 /* Set platform power management values for 1429 /* Set platform power management values for
1379 * Latency Tolerance Reporting (LTR) 1430 * Latency Tolerance Reporting (LTR)
1380 */ 1431 */
@@ -1386,6 +1437,19 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1386 /* Clear link partner's EEE ability */ 1437 /* Clear link partner's EEE ability */
1387 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1438 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1388 1439
1440 /* FEXTNVM6 K1-off workaround */
1441 if (hw->mac.type == e1000_pch_spt) {
1442 u32 pcieanacfg = er32(PCIEANACFG);
1443 u32 fextnvm6 = er32(FEXTNVM6);
1444
1445 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1446 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1447 else
1448 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1449
1450 ew32(FEXTNVM6, fextnvm6);
1451 }
1452
1389 if (!link) 1453 if (!link)
1390 return 0; /* No link detected */ 1454 return 0; /* No link detected */
1391 1455
@@ -1479,6 +1543,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1479 case e1000_pchlan: 1543 case e1000_pchlan:
1480 case e1000_pch2lan: 1544 case e1000_pch2lan:
1481 case e1000_pch_lpt: 1545 case e1000_pch_lpt:
1546 case e1000_pch_spt:
1482 rc = e1000_init_phy_params_pchlan(hw); 1547 rc = e1000_init_phy_params_pchlan(hw);
1483 break; 1548 break;
1484 default: 1549 default:
@@ -1929,6 +1994,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1929 case e1000_pchlan: 1994 case e1000_pchlan:
1930 case e1000_pch2lan: 1995 case e1000_pch2lan:
1931 case e1000_pch_lpt: 1996 case e1000_pch_lpt:
1997 case e1000_pch_spt:
1932 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 1998 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1933 break; 1999 break;
1934 default: 2000 default:
@@ -2961,6 +3027,20 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2961 s32 ret_val; 3027 s32 ret_val;
2962 3028
2963 switch (hw->mac.type) { 3029 switch (hw->mac.type) {
3030 /* In SPT, read from the CTRL_EXT reg instead of
3031 * accessing the sector valid bits from the nvm
3032 */
3033 case e1000_pch_spt:
3034 *bank = er32(CTRL_EXT)
3035 & E1000_CTRL_EXT_NVMVS;
3036 if ((*bank == 0) || (*bank == 1)) {
3037 e_dbg("ERROR: No valid NVM bank present\n");
3038 return -E1000_ERR_NVM;
3039 } else {
3040 *bank = *bank - 2;
3041 return 0;
3042 }
3043 break;
2964 case e1000_ich8lan: 3044 case e1000_ich8lan:
2965 case e1000_ich9lan: 3045 case e1000_ich9lan:
2966 eecd = er32(EECD); 3046 eecd = er32(EECD);
@@ -3008,6 +3088,99 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3008} 3088}
3009 3089
3010/** 3090/**
3091 * e1000_read_nvm_spt - NVM access for SPT
3092 * @hw: pointer to the HW structure
3093 * @offset: The offset (in bytes) of the word(s) to read.
3094 * @words: Size of data to read in words.
3095 * @data: pointer to the word(s) to read at offset.
3096 *
3097 * Reads a word(s) from the NVM
3098 **/
3099static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3100 u16 *data)
3101{
3102 struct e1000_nvm_info *nvm = &hw->nvm;
3103 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3104 u32 act_offset;
3105 s32 ret_val = 0;
3106 u32 bank = 0;
3107 u32 dword = 0;
3108 u16 offset_to_read;
3109 u16 i;
3110
3111 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3112 (words == 0)) {
3113 e_dbg("nvm parameter(s) out of bounds\n");
3114 ret_val = -E1000_ERR_NVM;
3115 goto out;
3116 }
3117
3118 nvm->ops.acquire(hw);
3119
3120 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3121 if (ret_val) {
3122 e_dbg("Could not detect valid bank, assuming bank 0\n");
3123 bank = 0;
3124 }
3125
3126 act_offset = (bank) ? nvm->flash_bank_size : 0;
3127 act_offset += offset;
3128
3129 ret_val = 0;
3130
3131 for (i = 0; i < words; i += 2) {
3132 if (words - i == 1) {
3133 if (dev_spec->shadow_ram[offset + i].modified) {
3134 data[i] =
3135 dev_spec->shadow_ram[offset + i].value;
3136 } else {
3137 offset_to_read = act_offset + i -
3138 ((act_offset + i) % 2);
3139 ret_val =
3140 e1000_read_flash_dword_ich8lan(hw,
3141 offset_to_read,
3142 &dword);
3143 if (ret_val)
3144 break;
3145 if ((act_offset + i) % 2 == 0)
3146 data[i] = (u16)(dword & 0xFFFF);
3147 else
3148 data[i] = (u16)((dword >> 16) & 0xFFFF);
3149 }
3150 } else {
3151 offset_to_read = act_offset + i;
3152 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3153 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3154 ret_val =
3155 e1000_read_flash_dword_ich8lan(hw,
3156 offset_to_read,
3157 &dword);
3158 if (ret_val)
3159 break;
3160 }
3161 if (dev_spec->shadow_ram[offset + i].modified)
3162 data[i] =
3163 dev_spec->shadow_ram[offset + i].value;
3164 else
3165 data[i] = (u16)(dword & 0xFFFF);
3166 if (dev_spec->shadow_ram[offset + i].modified)
3167 data[i + 1] =
3168 dev_spec->shadow_ram[offset + i + 1].value;
3169 else
3170 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3171 }
3172 }
3173
3174 nvm->ops.release(hw);
3175
3176out:
3177 if (ret_val)
3178 e_dbg("NVM read error: %d\n", ret_val);
3179
3180 return ret_val;
3181}
3182
3183/**
3011 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3184 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3012 * @hw: pointer to the HW structure 3185 * @hw: pointer to the HW structure
3013 * @offset: The offset (in bytes) of the word(s) to read. 3186 * @offset: The offset (in bytes) of the word(s) to read.
@@ -3090,8 +3263,10 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3090 /* Clear FCERR and DAEL in hw status by writing 1 */ 3263 /* Clear FCERR and DAEL in hw status by writing 1 */
3091 hsfsts.hsf_status.flcerr = 1; 3264 hsfsts.hsf_status.flcerr = 1;
3092 hsfsts.hsf_status.dael = 1; 3265 hsfsts.hsf_status.dael = 1;
3093 3266 if (hw->mac.type == e1000_pch_spt)
3094 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3267 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3268 else
3269 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3095 3270
3096 /* Either we should have a hardware SPI cycle in progress 3271 /* Either we should have a hardware SPI cycle in progress
3097 * bit to check against, in order to start a new cycle or 3272 * bit to check against, in order to start a new cycle or
@@ -3107,7 +3282,10 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3107 * Begin by setting Flash Cycle Done. 3282 * Begin by setting Flash Cycle Done.
3108 */ 3283 */
3109 hsfsts.hsf_status.flcdone = 1; 3284 hsfsts.hsf_status.flcdone = 1;
3110 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3285 if (hw->mac.type == e1000_pch_spt)
3286 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3287 else
3288 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3111 ret_val = 0; 3289 ret_val = 0;
3112 } else { 3290 } else {
3113 s32 i; 3291 s32 i;
@@ -3128,7 +3306,11 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3128 * now set the Flash Cycle Done. 3306 * now set the Flash Cycle Done.
3129 */ 3307 */
3130 hsfsts.hsf_status.flcdone = 1; 3308 hsfsts.hsf_status.flcdone = 1;
3131 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3309 if (hw->mac.type == e1000_pch_spt)
3310 ew32flash(ICH_FLASH_HSFSTS,
3311 hsfsts.regval & 0xFFFF);
3312 else
3313 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3132 } else { 3314 } else {
3133 e_dbg("Flash controller busy, cannot get access\n"); 3315 e_dbg("Flash controller busy, cannot get access\n");
3134 } 3316 }
@@ -3151,9 +3333,16 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3151 u32 i = 0; 3333 u32 i = 0;
3152 3334
3153 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3335 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3154 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3336 if (hw->mac.type == e1000_pch_spt)
3337 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3338 else
3339 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3155 hsflctl.hsf_ctrl.flcgo = 1; 3340 hsflctl.hsf_ctrl.flcgo = 1;
3156 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3341
3342 if (hw->mac.type == e1000_pch_spt)
3343 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3344 else
3345 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3157 3346
3158 /* wait till FDONE bit is set to 1 */ 3347 /* wait till FDONE bit is set to 1 */
3159 do { 3348 do {
@@ -3170,6 +3359,23 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3170} 3359}
3171 3360
3172/** 3361/**
3362 * e1000_read_flash_dword_ich8lan - Read dword from flash
3363 * @hw: pointer to the HW structure
3364 * @offset: offset to data location
3365 * @data: pointer to the location for storing the data
3366 *
3367 * Reads the flash dword at offset into data. Offset is converted
3368 * to bytes before read.
3369 **/
3370static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3371 u32 *data)
3372{
3373 /* Must convert word offset into bytes. */
3374 offset <<= 1;
3375 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3376}
3377
3378/**
3173 * e1000_read_flash_word_ich8lan - Read word from flash 3379 * e1000_read_flash_word_ich8lan - Read word from flash
3174 * @hw: pointer to the HW structure 3380 * @hw: pointer to the HW structure
3175 * @offset: offset to data location 3381 * @offset: offset to data location
@@ -3201,7 +3407,14 @@ static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3201 s32 ret_val; 3407 s32 ret_val;
3202 u16 word = 0; 3408 u16 word = 0;
3203 3409
3204 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3410 /* In SPT, only 32 bits access is supported,
3411 * so this function should not be called.
3412 */
3413 if (hw->mac.type == e1000_pch_spt)
3414 return -E1000_ERR_NVM;
3415 else
3416 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3417
3205 if (ret_val) 3418 if (ret_val)
3206 return ret_val; 3419 return ret_val;
3207 3420
@@ -3287,6 +3500,82 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3287} 3500}
3288 3501
3289/** 3502/**
3503 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3504 * @hw: pointer to the HW structure
3505 * @offset: The offset (in bytes) of the dword to read.
3506 * @data: Pointer to the dword to store the value read.
3507 *
3508 * Reads a byte or word from the NVM using the flash access registers.
3509 **/
3510
3511static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3512 u32 *data)
3513{
3514 union ich8_hws_flash_status hsfsts;
3515 union ich8_hws_flash_ctrl hsflctl;
3516 u32 flash_linear_addr;
3517 s32 ret_val = -E1000_ERR_NVM;
3518 u8 count = 0;
3519
3520 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3521 hw->mac.type != e1000_pch_spt)
3522 return -E1000_ERR_NVM;
3523 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3524 hw->nvm.flash_base_addr);
3525
3526 do {
3527 udelay(1);
3528 /* Steps */
3529 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3530 if (ret_val)
3531 break;
3532 /* In SPT, This register is in Lan memory space, not flash.
3533 * Therefore, only 32 bit access is supported
3534 */
3535 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3536
3537 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3538 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3539 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3540 /* In SPT, This register is in Lan memory space, not flash.
3541 * Therefore, only 32 bit access is supported
3542 */
3543 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3544 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3545
3546 ret_val =
3547 e1000_flash_cycle_ich8lan(hw,
3548 ICH_FLASH_READ_COMMAND_TIMEOUT);
3549
3550 /* Check if FCERR is set to 1, if set to 1, clear it
3551 * and try the whole sequence a few more times, else
3552 * read in (shift in) the Flash Data0, the order is
3553 * least significant byte first msb to lsb
3554 */
3555 if (!ret_val) {
3556 *data = er32flash(ICH_FLASH_FDATA0);
3557 break;
3558 } else {
3559 /* If we've gotten here, then things are probably
3560 * completely hosed, but if the error condition is
3561 * detected, it won't hurt to give it another try...
3562 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3563 */
3564 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3565 if (hsfsts.hsf_status.flcerr) {
3566 /* Repeat for some time before giving up. */
3567 continue;
3568 } else if (!hsfsts.hsf_status.flcdone) {
3569 e_dbg("Timeout error - flash cycle did not complete.\n");
3570 break;
3571 }
3572 }
3573 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3574
3575 return ret_val;
3576}
3577
3578/**
3290 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3579 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3291 * @hw: pointer to the HW structure 3580 * @hw: pointer to the HW structure
3292 * @offset: The offset (in bytes) of the word(s) to write. 3581 * @offset: The offset (in bytes) of the word(s) to write.
@@ -3321,7 +3610,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3321} 3610}
3322 3611
3323/** 3612/**
3324 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3613 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3325 * @hw: pointer to the HW structure 3614 * @hw: pointer to the HW structure
3326 * 3615 *
3327 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3616 * The NVM checksum is updated by calling the generic update_nvm_checksum,
@@ -3331,13 +3620,13 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3331 * After a successful commit, the shadow ram is cleared and is ready for 3620 * After a successful commit, the shadow ram is cleared and is ready for
3332 * future writes. 3621 * future writes.
3333 **/ 3622 **/
3334static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3623static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3335{ 3624{
3336 struct e1000_nvm_info *nvm = &hw->nvm; 3625 struct e1000_nvm_info *nvm = &hw->nvm;
3337 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3626 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3338 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3627 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3339 s32 ret_val; 3628 s32 ret_val;
3340 u16 data; 3629 u32 dword = 0;
3341 3630
3342 ret_val = e1000e_update_nvm_checksum_generic(hw); 3631 ret_val = e1000e_update_nvm_checksum_generic(hw);
3343 if (ret_val) 3632 if (ret_val)
@@ -3371,12 +3660,175 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3371 if (ret_val) 3660 if (ret_val)
3372 goto release; 3661 goto release;
3373 } 3662 }
3374 3663 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3375 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3376 /* Determine whether to write the value stored 3664 /* Determine whether to write the value stored
3377 * in the other NVM bank or a modified value stored 3665 * in the other NVM bank or a modified value stored
3378 * in the shadow RAM 3666 * in the shadow RAM
3379 */ 3667 */
3668 ret_val = e1000_read_flash_dword_ich8lan(hw,
3669 i + old_bank_offset,
3670 &dword);
3671
3672 if (dev_spec->shadow_ram[i].modified) {
3673 dword &= 0xffff0000;
3674 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3675 }
3676 if (dev_spec->shadow_ram[i + 1].modified) {
3677 dword &= 0x0000ffff;
3678 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3679 << 16);
3680 }
3681 if (ret_val)
3682 break;
3683
3684 /* If the word is 0x13, then make sure the signature bits
3685 * (15:14) are 11b until the commit has completed.
3686 * This will allow us to write 10b which indicates the
3687 * signature is valid. We want to do this after the write
3688 * has completed so that we don't mark the segment valid
3689 * while the write is still in progress
3690 */
3691 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3692 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3693
3694 /* Convert offset to bytes. */
3695 act_offset = (i + new_bank_offset) << 1;
3696
3697 usleep_range(100, 200);
3698
3699 /* Write the data to the new bank. Offset in words */
3700 act_offset = i + new_bank_offset;
3701 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3702 dword);
3703 if (ret_val)
3704 break;
3705 }
3706
3707 /* Don't bother writing the segment valid bits if sector
3708 * programming failed.
3709 */
3710 if (ret_val) {
3711 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3712 e_dbg("Flash commit failed.\n");
3713 goto release;
3714 }
3715
3716 /* Finally validate the new segment by setting bit 15:14
3717 * to 10b in word 0x13 , this can be done without an
3718 * erase as well since these bits are 11 to start with
3719 * and we need to change bit 14 to 0b
3720 */
3721 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3722
3723 /*offset in words but we read dword */
3724 --act_offset;
3725 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3726
3727 if (ret_val)
3728 goto release;
3729
3730 dword &= 0xBFFFFFFF;
3731 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3732
3733 if (ret_val)
3734 goto release;
3735
3736 /* And invalidate the previously valid segment by setting
3737 * its signature word (0x13) high_byte to 0b. This can be
3738 * done without an erase because flash erase sets all bits
3739 * to 1's. We can write 1's to 0's without an erase
3740 */
3741 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3742
3743 /* offset in words but we read dword */
3744 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3745 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3746
3747 if (ret_val)
3748 goto release;
3749
3750 dword &= 0x00FFFFFF;
3751 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3752
3753 if (ret_val)
3754 goto release;
3755
3756 /* Great! Everything worked, we can now clear the cached entries. */
3757 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3758 dev_spec->shadow_ram[i].modified = false;
3759 dev_spec->shadow_ram[i].value = 0xFFFF;
3760 }
3761
3762release:
3763 nvm->ops.release(hw);
3764
3765 /* Reload the EEPROM, or else modifications will not appear
3766 * until after the next adapter reset.
3767 */
3768 if (!ret_val) {
3769 nvm->ops.reload(hw);
3770 usleep_range(10000, 20000);
3771 }
3772
3773out:
3774 if (ret_val)
3775 e_dbg("NVM update error: %d\n", ret_val);
3776
3777 return ret_val;
3778}
3779
3780/**
3781 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3782 * @hw: pointer to the HW structure
3783 *
3784 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3785 * which writes the checksum to the shadow ram. The changes in the shadow
3786 * ram are then committed to the EEPROM by processing each bank at a time
3787 * checking for the modified bit and writing only the pending changes.
3788 * After a successful commit, the shadow ram is cleared and is ready for
3789 * future writes.
3790 **/
3791static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3792{
3793 struct e1000_nvm_info *nvm = &hw->nvm;
3794 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3795 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3796 s32 ret_val;
3797 u16 data = 0;
3798
3799 ret_val = e1000e_update_nvm_checksum_generic(hw);
3800 if (ret_val)
3801 goto out;
3802
3803 if (nvm->type != e1000_nvm_flash_sw)
3804 goto out;
3805
3806 nvm->ops.acquire(hw);
3807
3808 /* We're writing to the opposite bank so if we're on bank 1,
3809 * write to bank 0 etc. We also need to erase the segment that
3810 * is going to be written
3811 */
3812 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3813 if (ret_val) {
3814 e_dbg("Could not detect valid bank, assuming bank 0\n");
3815 bank = 0;
3816 }
3817
3818 if (bank == 0) {
3819 new_bank_offset = nvm->flash_bank_size;
3820 old_bank_offset = 0;
3821 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3822 if (ret_val)
3823 goto release;
3824 } else {
3825 old_bank_offset = nvm->flash_bank_size;
3826 new_bank_offset = 0;
3827 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3828 if (ret_val)
3829 goto release;
3830 }
3831 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3380 if (dev_spec->shadow_ram[i].modified) { 3832 if (dev_spec->shadow_ram[i].modified) {
3381 data = dev_spec->shadow_ram[i].value; 3833 data = dev_spec->shadow_ram[i].value;
3382 } else { 3834 } else {
@@ -3498,6 +3950,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3498 */ 3950 */
3499 switch (hw->mac.type) { 3951 switch (hw->mac.type) {
3500 case e1000_pch_lpt: 3952 case e1000_pch_lpt:
3953 case e1000_pch_spt:
3501 word = NVM_COMPAT; 3954 word = NVM_COMPAT;
3502 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 3955 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3503 break; 3956 break;
@@ -3583,9 +4036,13 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3583 s32 ret_val; 4036 s32 ret_val;
3584 u8 count = 0; 4037 u8 count = 0;
3585 4038
3586 if (size < 1 || size > 2 || data > size * 0xff || 4039 if (hw->mac.type == e1000_pch_spt) {
3587 offset > ICH_FLASH_LINEAR_ADDR_MASK) 4040 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3588 return -E1000_ERR_NVM; 4041 return -E1000_ERR_NVM;
4042 } else {
4043 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4044 return -E1000_ERR_NVM;
4045 }
3589 4046
3590 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4047 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3591 hw->nvm.flash_base_addr); 4048 hw->nvm.flash_base_addr);
@@ -3596,12 +4053,25 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3596 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4053 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3597 if (ret_val) 4054 if (ret_val)
3598 break; 4055 break;
4056 /* In SPT, This register is in Lan memory space, not
4057 * flash. Therefore, only 32 bit access is supported
4058 */
4059 if (hw->mac.type == e1000_pch_spt)
4060 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4061 else
4062 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3599 4063
3600 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3601 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4064 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3602 hsflctl.hsf_ctrl.fldbcount = size - 1; 4065 hsflctl.hsf_ctrl.fldbcount = size - 1;
3603 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4066 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3604 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4067 /* In SPT, This register is in Lan memory space,
4068 * not flash. Therefore, only 32 bit access is
4069 * supported
4070 */
4071 if (hw->mac.type == e1000_pch_spt)
4072 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4073 else
4074 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3605 4075
3606 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4076 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3607 4077
@@ -3640,6 +4110,90 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3640} 4110}
3641 4111
3642/** 4112/**
4113* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4114* @hw: pointer to the HW structure
4115* @offset: The offset (in bytes) of the dwords to read.
4116* @data: The 4 bytes to write to the NVM.
4117*
4118* Writes one/two/four bytes to the NVM using the flash access registers.
4119**/
4120static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4121 u32 data)
4122{
4123 union ich8_hws_flash_status hsfsts;
4124 union ich8_hws_flash_ctrl hsflctl;
4125 u32 flash_linear_addr;
4126 s32 ret_val;
4127 u8 count = 0;
4128
4129 if (hw->mac.type == e1000_pch_spt) {
4130 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4131 return -E1000_ERR_NVM;
4132 }
4133 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4134 hw->nvm.flash_base_addr);
4135 do {
4136 udelay(1);
4137 /* Steps */
4138 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4139 if (ret_val)
4140 break;
4141
4142 /* In SPT, This register is in Lan memory space, not
4143 * flash. Therefore, only 32 bit access is supported
4144 */
4145 if (hw->mac.type == e1000_pch_spt)
4146 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4147 >> 16;
4148 else
4149 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4150
4151 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4152 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4153
4154 /* In SPT, This register is in Lan memory space,
4155 * not flash. Therefore, only 32 bit access is
4156 * supported
4157 */
4158 if (hw->mac.type == e1000_pch_spt)
4159 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4160 else
4161 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4162
4163 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4164
4165 ew32flash(ICH_FLASH_FDATA0, data);
4166
4167 /* check if FCERR is set to 1 , if set to 1, clear it
4168 * and try the whole sequence a few more times else done
4169 */
4170 ret_val =
4171 e1000_flash_cycle_ich8lan(hw,
4172 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4173
4174 if (!ret_val)
4175 break;
4176
4177 /* If we're here, then things are most likely
4178 * completely hosed, but if the error condition
4179 * is detected, it won't hurt to give it another
4180 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4181 */
4182 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4183
4184 if (hsfsts.hsf_status.flcerr)
4185 /* Repeat for some time before giving up. */
4186 continue;
4187 if (!hsfsts.hsf_status.flcdone) {
4188 e_dbg("Timeout error - flash cycle did not complete.\n");
4189 break;
4190 }
4191 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4192
4193 return ret_val;
4194}
4195
4196/**
3643 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4197 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3644 * @hw: pointer to the HW structure 4198 * @hw: pointer to the HW structure
3645 * @offset: The index of the byte to read. 4199 * @offset: The index of the byte to read.
@@ -3656,6 +4210,40 @@ static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3656} 4210}
3657 4211
3658/** 4212/**
4213* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4214* @hw: pointer to the HW structure
4215* @offset: The offset of the word to write.
4216* @dword: The dword to write to the NVM.
4217*
4218* Writes a single dword to the NVM using the flash access registers.
4219* Goes through a retry algorithm before giving up.
4220**/
4221static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4222 u32 offset, u32 dword)
4223{
4224 s32 ret_val;
4225 u16 program_retries;
4226
4227 /* Must convert word offset into bytes. */
4228 offset <<= 1;
4229 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4230
4231 if (!ret_val)
4232 return ret_val;
4233 for (program_retries = 0; program_retries < 100; program_retries++) {
4234 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4235 usleep_range(100, 200);
4236 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4237 if (!ret_val)
4238 break;
4239 }
4240 if (program_retries == 100)
4241 return -E1000_ERR_NVM;
4242
4243 return 0;
4244}
4245
4246/**
3659 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4247 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3660 * @hw: pointer to the HW structure 4248 * @hw: pointer to the HW structure
3661 * @offset: The offset of the byte to write. 4249 * @offset: The offset of the byte to write.
@@ -3759,9 +4347,18 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3759 /* Write a value 11 (block Erase) in Flash 4347 /* Write a value 11 (block Erase) in Flash
3760 * Cycle field in hw flash control 4348 * Cycle field in hw flash control
3761 */ 4349 */
3762 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4350 if (hw->mac.type == e1000_pch_spt)
4351 hsflctl.regval =
4352 er32flash(ICH_FLASH_HSFSTS) >> 16;
4353 else
4354 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4355
3763 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4356 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3764 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4357 if (hw->mac.type == e1000_pch_spt)
4358 ew32flash(ICH_FLASH_HSFSTS,
4359 hsflctl.regval << 16);
4360 else
4361 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3765 4362
3766 /* Write the last 24 bits of an index within the 4363 /* Write the last 24 bits of an index within the
3767 * block into Flash Linear address field in Flash 4364 * block into Flash Linear address field in Flash
@@ -4180,7 +4777,8 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4180 ew32(RFCTL, reg); 4777 ew32(RFCTL, reg);
4181 4778
4182 /* Enable ECC on Lynxpoint */ 4779 /* Enable ECC on Lynxpoint */
4183 if (hw->mac.type == e1000_pch_lpt) { 4780 if ((hw->mac.type == e1000_pch_lpt) ||
4781 (hw->mac.type == e1000_pch_spt)) {
4184 reg = er32(PBECCSTS); 4782 reg = er32(PBECCSTS);
4185 reg |= E1000_PBECCSTS_ECC_ENABLE; 4783 reg |= E1000_PBECCSTS_ECC_ENABLE;
4186 ew32(PBECCSTS, reg); 4784 ew32(PBECCSTS, reg);
@@ -4583,7 +5181,8 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4583 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5181 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4584 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5182 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4585 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5183 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4586 (device_id == E1000_DEV_ID_PCH_I218_V3)) { 5184 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5185 (hw->mac.type == e1000_pch_spt)) {
4587 u32 fextnvm6 = er32(FEXTNVM6); 5186 u32 fextnvm6 = er32(FEXTNVM6);
4588 5187
4589 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5188 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
@@ -5058,6 +5657,17 @@ static const struct e1000_nvm_operations ich8_nvm_ops = {
5058 .write = e1000_write_nvm_ich8lan, 5657 .write = e1000_write_nvm_ich8lan,
5059}; 5658};
5060 5659
5660static const struct e1000_nvm_operations spt_nvm_ops = {
5661 .acquire = e1000_acquire_nvm_ich8lan,
5662 .release = e1000_release_nvm_ich8lan,
5663 .read = e1000_read_nvm_spt,
5664 .update = e1000_update_nvm_checksum_spt,
5665 .reload = e1000e_reload_nvm_generic,
5666 .valid_led_default = e1000_valid_led_default_ich8lan,
5667 .validate = e1000_validate_nvm_checksum_ich8lan,
5668 .write = e1000_write_nvm_ich8lan,
5669};
5670
5061const struct e1000_info e1000_ich8_info = { 5671const struct e1000_info e1000_ich8_info = {
5062 .mac = e1000_ich8lan, 5672 .mac = e1000_ich8lan,
5063 .flags = FLAG_HAS_WOL 5673 .flags = FLAG_HAS_WOL
@@ -5166,3 +5776,23 @@ const struct e1000_info e1000_pch_lpt_info = {
5166 .phy_ops = &ich8_phy_ops, 5776 .phy_ops = &ich8_phy_ops,
5167 .nvm_ops = &ich8_nvm_ops, 5777 .nvm_ops = &ich8_nvm_ops,
5168}; 5778};
5779
5780const struct e1000_info e1000_pch_spt_info = {
5781 .mac = e1000_pch_spt,
5782 .flags = FLAG_IS_ICH
5783 | FLAG_HAS_WOL
5784 | FLAG_HAS_HW_TIMESTAMP
5785 | FLAG_HAS_CTRLEXT_ON_LOAD
5786 | FLAG_HAS_AMT
5787 | FLAG_HAS_FLASH
5788 | FLAG_HAS_JUMBO_FRAMES
5789 | FLAG_APME_IN_WUC,
5790 .flags2 = FLAG2_HAS_PHY_STATS
5791 | FLAG2_HAS_EEE,
5792 .pba = 26,
5793 .max_hw_frame_size = 9018,
5794 .get_variants = e1000_get_variants_ich8lan,
5795 .mac_ops = &ich8_mac_ops,
5796 .phy_ops = &ich8_phy_ops,
5797 .nvm_ops = &spt_nvm_ops,
5798};
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
index 8066a498eaac..770a573b9eea 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.h
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
@@ -95,9 +95,18 @@
95 95
96#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 96#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
97#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 97#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
98#define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000
99/* bit for disabling packet buffer read */
100#define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
98 101
99#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 102#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
100 103
104#define K1_ENTRY_LATENCY 0
105#define K1_MIN_TIME 1
106#define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field */
107#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */
108#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
109
101#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 110#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
102 111
103#define E1000_ICH_RAR_ENTRIES 7 112#define E1000_ICH_RAR_ENTRIES 7
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 1e8c40fd5c3d..6fa4fc05709e 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -70,6 +70,7 @@ static const struct e1000_info *e1000_info_tbl[] = {
70 [board_pchlan] = &e1000_pch_info, 70 [board_pchlan] = &e1000_pch_info,
71 [board_pch2lan] = &e1000_pch2_info, 71 [board_pch2lan] = &e1000_pch2_info,
72 [board_pch_lpt] = &e1000_pch_lpt_info, 72 [board_pch_lpt] = &e1000_pch_lpt_info,
73 [board_pch_spt] = &e1000_pch_spt_info,
73}; 74};
74 75
75struct e1000_reg_info { 76struct e1000_reg_info {
@@ -1796,7 +1797,8 @@ static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1796 } 1797 }
1797 1798
1798 /* Reset on uncorrectable ECC error */ 1799 /* Reset on uncorrectable ECC error */
1799 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) { 1800 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1801 (hw->mac.type == e1000_pch_spt))) {
1800 u32 pbeccsts = er32(PBECCSTS); 1802 u32 pbeccsts = er32(PBECCSTS);
1801 1803
1802 adapter->corr_errors += 1804 adapter->corr_errors +=
@@ -1876,7 +1878,8 @@ static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1876 } 1878 }
1877 1879
1878 /* Reset on uncorrectable ECC error */ 1880 /* Reset on uncorrectable ECC error */
1879 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) { 1881 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1882 (hw->mac.type == e1000_pch_spt))) {
1880 u32 pbeccsts = er32(PBECCSTS); 1883 u32 pbeccsts = er32(PBECCSTS);
1881 1884
1882 adapter->corr_errors += 1885 adapter->corr_errors +=
@@ -2257,7 +2260,8 @@ static void e1000_irq_enable(struct e1000_adapter *adapter)
2257 if (adapter->msix_entries) { 2260 if (adapter->msix_entries) {
2258 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2261 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2259 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC); 2262 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2260 } else if (hw->mac.type == e1000_pch_lpt) { 2263 } else if ((hw->mac.type == e1000_pch_lpt) ||
2264 (hw->mac.type == e1000_pch_spt)) {
2261 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2265 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2262 } else { 2266 } else {
2263 ew32(IMS, IMS_ENABLE_MASK); 2267 ew32(IMS, IMS_ENABLE_MASK);
@@ -3014,6 +3018,19 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
3014 ew32(TCTL, tctl); 3018 ew32(TCTL, tctl);
3015 3019
3016 hw->mac.ops.config_collision_dist(hw); 3020 hw->mac.ops.config_collision_dist(hw);
3021
3022 /* SPT Si errata workaround to avoid data corruption */
3023 if (hw->mac.type == e1000_pch_spt) {
3024 u32 reg_val;
3025
3026 reg_val = er32(IOSFPC);
3027 reg_val |= E1000_RCTL_RDMTS_HEX;
3028 ew32(IOSFPC, reg_val);
3029
3030 reg_val = er32(TARC(0));
3031 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ;
3032 ew32(TARC(0), reg_val);
3033 }
3017} 3034}
3018 3035
3019/** 3036/**
@@ -3490,8 +3507,11 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3490 struct e1000_hw *hw = &adapter->hw; 3507 struct e1000_hw *hw = &adapter->hw;
3491 u32 incvalue, incperiod, shift; 3508 u32 incvalue, incperiod, shift;
3492 3509
3493 /* Make sure clock is enabled on I217 before checking the frequency */ 3510 /* Make sure clock is enabled on I217/I218/I219 before checking
3494 if ((hw->mac.type == e1000_pch_lpt) && 3511 * the frequency
3512 */
3513 if (((hw->mac.type == e1000_pch_lpt) ||
3514 (hw->mac.type == e1000_pch_spt)) &&
3495 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3515 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3496 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3516 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3497 u32 fextnvm7 = er32(FEXTNVM7); 3517 u32 fextnvm7 = er32(FEXTNVM7);
@@ -3505,10 +3525,13 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3505 switch (hw->mac.type) { 3525 switch (hw->mac.type) {
3506 case e1000_pch2lan: 3526 case e1000_pch2lan:
3507 case e1000_pch_lpt: 3527 case e1000_pch_lpt:
3508 /* On I217, the clock frequency is 25MHz or 96MHz as 3528 case e1000_pch_spt:
3509 * indicated by the System Clock Frequency Indication 3529 /* On I217, I218 and I219, the clock frequency is 25MHz
3530 * or 96MHz as indicated by the System Clock Frequency
3531 * Indication
3510 */ 3532 */
3511 if ((hw->mac.type != e1000_pch_lpt) || 3533 if (((hw->mac.type != e1000_pch_lpt) &&
3534 (hw->mac.type != e1000_pch_spt)) ||
3512 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { 3535 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3513 /* Stable 96MHz frequency */ 3536 /* Stable 96MHz frequency */
3514 incperiod = INCPERIOD_96MHz; 3537 incperiod = INCPERIOD_96MHz;
@@ -3875,6 +3898,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3875 break; 3898 break;
3876 case e1000_pch2lan: 3899 case e1000_pch2lan:
3877 case e1000_pch_lpt: 3900 case e1000_pch_lpt:
3901 case e1000_pch_spt:
3878 fc->refresh_time = 0x0400; 3902 fc->refresh_time = 0x0400;
3879 3903
3880 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 3904 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
@@ -4759,7 +4783,8 @@ static void e1000e_update_stats(struct e1000_adapter *adapter)
4759 adapter->stats.mgpdc += er32(MGTPDC); 4783 adapter->stats.mgpdc += er32(MGTPDC);
4760 4784
4761 /* Correctable ECC Errors */ 4785 /* Correctable ECC Errors */
4762 if (hw->mac.type == e1000_pch_lpt) { 4786 if ((hw->mac.type == e1000_pch_lpt) ||
4787 (hw->mac.type == e1000_pch_spt)) {
4763 u32 pbeccsts = er32(PBECCSTS); 4788 u32 pbeccsts = er32(PBECCSTS);
4764 4789
4765 adapter->corr_errors += 4790 adapter->corr_errors +=
@@ -6144,7 +6169,8 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6144 6169
6145 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6170 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6146 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6171 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6147 } else if (hw->mac.type == e1000_pch_lpt) { 6172 } else if ((hw->mac.type == e1000_pch_lpt) ||
6173 (hw->mac.type == e1000_pch_spt)) {
6148 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6174 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6149 /* ULP does not support wake from unicast, multicast 6175 /* ULP does not support wake from unicast, multicast
6150 * or broadcast. 6176 * or broadcast.
@@ -7213,6 +7239,10 @@ static const struct pci_device_id e1000_pci_tbl[] = {
7213 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7239 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7214 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7240 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7215 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7241 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7242 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7243 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7244 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7245 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7216 7246
7217 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7247 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7218}; 7248};
diff --git a/drivers/net/ethernet/intel/e1000e/ptp.c b/drivers/net/ethernet/intel/e1000e/ptp.c
index 978ef9c4a043..1490f1e8d6aa 100644
--- a/drivers/net/ethernet/intel/e1000e/ptp.c
+++ b/drivers/net/ethernet/intel/e1000e/ptp.c
@@ -221,7 +221,9 @@ void e1000e_ptp_init(struct e1000_adapter *adapter)
221 switch (hw->mac.type) { 221 switch (hw->mac.type) {
222 case e1000_pch2lan: 222 case e1000_pch2lan:
223 case e1000_pch_lpt: 223 case e1000_pch_lpt:
224 if ((hw->mac.type != e1000_pch_lpt) || 224 case e1000_pch_spt:
225 if (((hw->mac.type != e1000_pch_lpt) &&
226 (hw->mac.type != e1000_pch_spt)) ||
225 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { 227 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
226 adapter->ptp_clock_info.max_adj = 24000000 - 1; 228 adapter->ptp_clock_info.max_adj = 24000000 - 1;
227 break; 229 break;
diff --git a/drivers/net/ethernet/intel/e1000e/regs.h b/drivers/net/ethernet/intel/e1000e/regs.h
index ea235bbe50d3..85eefc4832ba 100644
--- a/drivers/net/ethernet/intel/e1000e/regs.h
+++ b/drivers/net/ethernet/intel/e1000e/regs.h
@@ -38,6 +38,7 @@
38#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 38#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
39#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ 39#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
40#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ 40#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
41#define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */
41#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 42#define E1000_FCT 0x00030 /* Flow Control Type - RW */
42#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 43#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
43#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 44#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
@@ -67,6 +68,7 @@
67#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 68#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
68#define E1000_PBS 0x01008 /* Packet Buffer Size */ 69#define E1000_PBS 0x01008 /* Packet Buffer Size */
69#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ 70#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
71#define E1000_IOSFPC 0x00F28 /* TX corrupted data */
70#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 72#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
71#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 73#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
72#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 74#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
@@ -121,6 +123,7 @@
121 (0x054E4 + ((_i - 16) * 8))) 123 (0x054E4 + ((_i - 16) * 8)))
122#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) 124#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
123#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) 125#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
126#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29)
124#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ 127#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
125#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ 128#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
126#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ 129#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 21:24:08 -0500