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-rw-r--r--drivers/net/wireless/b43/phy_a.c19
-rw-r--r--drivers/net/wireless/b43/phy_g.c228
-rw-r--r--drivers/net/wireless/b43/wa.c85
3 files changed, 103 insertions, 229 deletions
diff --git a/drivers/net/wireless/b43/phy_a.c b/drivers/net/wireless/b43/phy_a.c
index 9bc1957cf37e..6845d120bc2e 100644
--- a/drivers/net/wireless/b43/phy_a.c
+++ b/drivers/net/wireless/b43/phy_a.c
@@ -226,8 +226,7 @@ static void b43_phy_ww(struct b43_wldev *dev)
226 226
227 b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN); 227 b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);
228 b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000); 228 b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);
229 b43_phy_write(dev, B43_PHY_OFDM(0x82), 229 b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300);
230 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
231 b43_radio_write16(dev, 0x0009, 230 b43_radio_write16(dev, 0x0009,
232 b43_radio_read16(dev, 0x0009) | 0x0080); 231 b43_radio_read16(dev, 0x0009) | 0x0080);
233 b43_radio_write16(dev, 0x0012, 232 b43_radio_write16(dev, 0x0012,
@@ -259,14 +258,10 @@ static void b43_phy_ww(struct b43_wldev *dev)
259 b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0); 258 b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
260 b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0); 259 b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
261 b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF); 260 b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
262 b43_phy_write(dev, B43_PHY_OFDM(0xBB), 261 b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053);
263 (b43_phy_read(dev, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053); 262 b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120);
264 b43_phy_write(dev, B43_PHY_OFDM61, 263 b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000);
265 (b43_phy_read(dev, B43_PHY_OFDM61) & 0xFE1F) | 0x0120); 264 b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000);
266 b43_phy_write(dev, B43_PHY_OFDM(0x13),
267 (b43_phy_read(dev, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
268 b43_phy_write(dev, B43_PHY_OFDM(0x14),
269 (b43_phy_read(dev, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
270 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017); 265 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
271 for (i = 0; i < 6; i++) 266 for (i = 0; i < 6; i++)
272 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F); 267 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
@@ -331,9 +326,7 @@ void b43_phy_inita(struct b43_wldev *dev)
331 326
332 if ((phy->type == B43_PHYTYPE_G) && 327 if ((phy->type == B43_PHYTYPE_G) &&
333 (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) { 328 (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
334 b43_phy_write(dev, B43_PHY_OFDM(0x6E), 329 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);
335 (b43_phy_read(dev, B43_PHY_OFDM(0x6E))
336 & 0xE000) | 0x3CF);
337 } 330 }
338} 331}
339 332
diff --git a/drivers/net/wireless/b43/phy_g.c b/drivers/net/wireless/b43/phy_g.c
index 6dcbeb9393eb..9068eda11ba3 100644
--- a/drivers/net/wireless/b43/phy_g.c
+++ b/drivers/net/wireless/b43/phy_g.c
@@ -204,13 +204,9 @@ void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
204 & 0xFFF0) | 204 & 0xFFF0) |
205 baseband_attenuation); 205 baseband_attenuation);
206 } else if (phy->analog > 1) { 206 } else if (phy->analog > 1) {
207 b43_phy_write(dev, B43_PHY_DACCTL, 207 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2));
208 (b43_phy_read(dev, B43_PHY_DACCTL)
209 & 0xFFC3) | (baseband_attenuation << 2));
210 } else { 208 } else {
211 b43_phy_write(dev, B43_PHY_DACCTL, 209 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3));
212 (b43_phy_read(dev, B43_PHY_DACCTL)
213 & 0xFF87) | (baseband_attenuation << 3));
214 } 210 }
215} 211}
216 212
@@ -337,12 +333,9 @@ static void b43_set_all_gains(struct b43_wldev *dev,
337 333
338 if (third != -1) { 334 if (third != -1) {
339 tmp = ((u16) third << 14) | ((u16) third << 6); 335 tmp = ((u16) third << 14) | ((u16) third << 6);
340 b43_phy_write(dev, 0x04A0, 336 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp);
341 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp); 337 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp);
342 b43_phy_write(dev, 0x04A1, 338 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp);
343 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
344 b43_phy_write(dev, 0x04A2,
345 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
346 } 339 }
347 b43_dummy_transmission(dev); 340 b43_dummy_transmission(dev);
348} 341}
@@ -373,12 +366,9 @@ static void b43_set_original_gains(struct b43_wldev *dev)
373 for (i = start; i < end; i++) 366 for (i = start; i < end; i++)
374 b43_ofdmtab_write16(dev, table, i, i - start); 367 b43_ofdmtab_write16(dev, table, i, i - start);
375 368
376 b43_phy_write(dev, 0x04A0, 369 b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040);
377 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040); 370 b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040);
378 b43_phy_write(dev, 0x04A1, 371 b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000);
379 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
380 b43_phy_write(dev, 0x04A2,
381 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
382 b43_dummy_transmission(dev); 372 b43_dummy_transmission(dev);
383} 373}
384 374
@@ -455,11 +445,9 @@ static void b43_calc_nrssi_offset(struct b43_wldev *dev)
455 backup[11] = b43_radio_read16(dev, 0x0043); 445 backup[11] = b43_radio_read16(dev, 0x0043);
456 446
457 b43_phy_mask(dev, 0x0429, 0x7FFF); 447 b43_phy_mask(dev, 0x0429, 0x7FFF);
458 b43_phy_write(dev, 0x0001, 448 b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000);
459 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
460 b43_phy_set(dev, 0x0811, 0x000C); 449 b43_phy_set(dev, 0x0811, 0x000C);
461 b43_phy_write(dev, 0x0812, 450 b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004);
462 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
463 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2)); 451 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2));
464 if (phy->rev >= 6) { 452 if (phy->rev >= 6) {
465 backup[12] = b43_phy_read(dev, 0x002E); 453 backup[12] = b43_phy_read(dev, 0x002E);
@@ -523,8 +511,7 @@ static void b43_calc_nrssi_offset(struct b43_wldev *dev)
523 b43_phy_set(dev, 0x0814, 0x0004); 511 b43_phy_set(dev, 0x0814, 0x0004);
524 b43_phy_mask(dev, 0x0815, 0xFFFB); 512 b43_phy_mask(dev, 0x0815, 0xFFFB);
525 } 513 }
526 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F) 514 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
527 | 0x0040);
528 b43_radio_write16(dev, 0x007A, 515 b43_radio_write16(dev, 0x007A,
529 b43_radio_read16(dev, 0x007A) | 0x000F); 516 b43_radio_read16(dev, 0x007A) | 0x000F);
530 b43_set_all_gains(dev, 3, 0, 1); 517 b43_set_all_gains(dev, 3, 0, 1);
@@ -644,12 +631,8 @@ static void b43_calc_nrssi_slope(struct b43_wldev *dev)
644 b43_radio_write16(dev, 0x007A, 631 b43_radio_write16(dev, 0x007A,
645 b43_radio_read16(dev, 0x007A) & 0x00F7); 632 b43_radio_read16(dev, 0x007A) & 0x00F7);
646 if (phy->rev >= 2) { 633 if (phy->rev >= 2) {
647 b43_phy_write(dev, 0x0811, 634 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030);
648 (b43_phy_read(dev, 0x0811) & 0xFFCF) | 635 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010);
649 0x0030);
650 b43_phy_write(dev, 0x0812,
651 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
652 0x0010);
653 } 636 }
654 b43_radio_write16(dev, 0x007A, 637 b43_radio_write16(dev, 0x007A,
655 b43_radio_read16(dev, 0x007A) | 0x0080); 638 b43_radio_read16(dev, 0x007A) | 0x0080);
@@ -662,8 +645,7 @@ static void b43_calc_nrssi_slope(struct b43_wldev *dev)
662 b43_radio_write16(dev, 0x007A, 645 b43_radio_write16(dev, 0x007A,
663 b43_radio_read16(dev, 0x007A) & 0x007F); 646 b43_radio_read16(dev, 0x007A) & 0x007F);
664 if (phy->rev >= 2) { 647 if (phy->rev >= 2) {
665 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) 648 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
666 & 0xFF9F) | 0x0040);
667 } 649 }
668 650
669 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 651 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
@@ -673,12 +655,8 @@ static void b43_calc_nrssi_slope(struct b43_wldev *dev)
673 b43_radio_read16(dev, 0x007A) | 0x000F); 655 b43_radio_read16(dev, 0x007A) | 0x000F);
674 b43_phy_write(dev, 0x0015, 0xF330); 656 b43_phy_write(dev, 0x0015, 0xF330);
675 if (phy->rev >= 2) { 657 if (phy->rev >= 2) {
676 b43_phy_write(dev, 0x0812, 658 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020);
677 (b43_phy_read(dev, 0x0812) & 0xFFCF) | 659 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020);
678 0x0020);
679 b43_phy_write(dev, 0x0811,
680 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
681 0x0020);
682 } 660 }
683 661
684 b43_set_all_gains(dev, 3, 0, 1); 662 b43_set_all_gains(dev, 3, 0, 1);
@@ -756,13 +734,9 @@ static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
756 if (tmp16 >= 0x20) 734 if (tmp16 >= 0x20)
757 tmp16 -= 0x40; 735 tmp16 -= 0x40;
758 if (tmp16 < 3) { 736 if (tmp16 < 3) {
759 b43_phy_write(dev, 0x048A, 737 b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB);
760 (b43_phy_read(dev, 0x048A)
761 & 0xF000) | 0x09EB);
762 } else { 738 } else {
763 b43_phy_write(dev, 0x048A, 739 b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED);
764 (b43_phy_read(dev, 0x048A)
765 & 0xF000) | 0x0AED);
766 } 740 }
767 } else { 741 } else {
768 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) { 742 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) {
@@ -907,20 +881,15 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
907 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000); 881 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000);
908 882
909 phy_stacksave(0x04A0); 883 phy_stacksave(0x04A0);
910 b43_phy_write(dev, 0x04A0, 884 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008);
911 (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
912 phy_stacksave(0x04A1); 885 phy_stacksave(0x04A1);
913 b43_phy_write(dev, 0x04A1, 886 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605);
914 (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
915 phy_stacksave(0x04A2); 887 phy_stacksave(0x04A2);
916 b43_phy_write(dev, 0x04A2, 888 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204);
917 (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
918 phy_stacksave(0x04A8); 889 phy_stacksave(0x04A8);
919 b43_phy_write(dev, 0x04A8, 890 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803);
920 (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
921 phy_stacksave(0x04AB); 891 phy_stacksave(0x04AB);
922 b43_phy_write(dev, 0x04AB, 892 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605);
923 (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
924 893
925 phy_stacksave(0x04A7); 894 phy_stacksave(0x04A7);
926 b43_phy_write(dev, 0x04A7, 0x0002); 895 b43_phy_write(dev, 0x04A7, 0x0002);
@@ -977,9 +946,7 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
977 phy_stacksave(0x048C); 946 phy_stacksave(0x048C);
978 947
979 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000); 948 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000);
980 b43_phy_write(dev, B43_PHY_G_CRS, 949 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002);
981 (b43_phy_read(dev, B43_PHY_G_CRS)
982 & 0xFFFC) | 0x0002);
983 950
984 b43_phy_write(dev, 0x0033, 0x0800); 951 b43_phy_write(dev, 0x0033, 0x0800);
985 b43_phy_write(dev, 0x04A3, 0x2027); 952 b43_phy_write(dev, 0x04A3, 0x2027);
@@ -988,8 +955,7 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
988 b43_phy_write(dev, 0x04AA, 0x1CA8); 955 b43_phy_write(dev, 0x04AA, 0x1CA8);
989 b43_phy_write(dev, 0x04AC, 0x287A); 956 b43_phy_write(dev, 0x04AC, 0x287A);
990 957
991 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0) 958 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A);
992 & 0xFFC0) | 0x001A);
993 b43_phy_write(dev, 0x04A7, 0x000D); 959 b43_phy_write(dev, 0x04A7, 0x000D);
994 960
995 if (phy->rev < 2) { 961 if (phy->rev < 2) {
@@ -1002,57 +968,37 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
1002 b43_phy_write(dev, 0x04C1, 0x0059); 968 b43_phy_write(dev, 0x04C1, 0x0059);
1003 } 969 }
1004 970
1005 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1) 971 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800);
1006 & 0xC0FF) | 0x1800); 972 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015);
1007 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1) 973 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000);
1008 & 0xFFC0) | 0x0015); 974 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00);
1009 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8) 975 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000);
1010 & 0xCFFF) | 0x1000); 976 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800);
1011 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8) 977 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010);
1012 & 0xF0FF) | 0x0A00); 978 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005);
1013 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB) 979 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010);
1014 & 0xCFFF) | 0x1000); 980 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006);
1015 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB) 981 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800);
1016 & 0xF0FF) | 0x0800); 982 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500);
1017 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB) 983 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B);
1018 & 0xFFCF) | 0x0010);
1019 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1020 & 0xFFF0) | 0x0005);
1021 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1022 & 0xFFCF) | 0x0010);
1023 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1024 & 0xFFF0) | 0x0006);
1025 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
1026 & 0xF0FF) | 0x0800);
1027 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
1028 & 0xF0FF) | 0x0500);
1029 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
1030 & 0xFFF0) | 0x000B);
1031 984
1032 if (phy->rev >= 3) { 985 if (phy->rev >= 3) {
1033 b43_phy_mask(dev, 0x048A, ~0x8000); 986 b43_phy_mask(dev, 0x048A, ~0x8000);
1034 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415) 987 b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8);
1035 & 0x8000) | 0x36D8); 988 b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8);
1036 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416) 989 b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D);
1037 & 0x8000) | 0x36D8);
1038 b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
1039 & 0xFE00) | 0x016D);
1040 } else { 990 } else {
1041 b43_phy_set(dev, 0x048A, 0x1000); 991 b43_phy_set(dev, 0x048A, 0x1000);
1042 b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A) 992 b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000);
1043 & 0x9FFF) | 0x2000);
1044 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW); 993 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
1045 } 994 }
1046 if (phy->rev >= 2) { 995 if (phy->rev >= 2) {
1047 b43_phy_set(dev, 0x042B, 0x0800); 996 b43_phy_set(dev, 0x042B, 0x0800);
1048 } 997 }
1049 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C) 998 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200);
1050 & 0xF0FF) | 0x0200);
1051 if (phy->rev == 2) { 999 if (phy->rev == 2) {
1052 b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE) 1000 b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F);
1053 & 0xFF00) | 0x007F); 1001 b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300);
1054 b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
1055 & 0x00FF) | 0x1300);
1056 } else if (phy->rev >= 6) { 1002 } else if (phy->rev >= 6) {
1057 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F); 1003 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
1058 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F); 1004 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
@@ -1386,9 +1332,7 @@ static u16 b43_radio_init2050(struct b43_wldev *dev)
1386 b43_write16(dev, 0x03E6, 0x0122); 1332 b43_write16(dev, 0x03E6, 0x0122);
1387 } else { 1333 } else {
1388 if (phy->analog >= 2) { 1334 if (phy->analog >= 2) {
1389 b43_phy_write(dev, B43_PHY_CCK(0x03), 1335 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40);
1390 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1391 & 0xFFBF) | 0x40);
1392 } 1336 }
1393 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 1337 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1394 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000)); 1338 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
@@ -1578,8 +1522,7 @@ static void b43_phy_initb5(struct b43_wldev *dev)
1578 value += 0x202; 1522 value += 0x202;
1579 } 1523 }
1580 } 1524 }
1581 b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF) 1525 b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700);
1582 | 0x0700);
1583 if (phy->radio_ver == 0x2050) 1526 if (phy->radio_ver == 0x2050)
1584 b43_phy_write(dev, 0x0038, 0x0667); 1527 b43_phy_write(dev, 0x0038, 0x0667);
1585 1528
@@ -1599,12 +1542,9 @@ static void b43_phy_initb5(struct b43_wldev *dev)
1599 1542
1600 b43_phy_write(dev, 0x001C, 0x186A); 1543 b43_phy_write(dev, 0x001C, 0x186A);
1601 1544
1602 b43_phy_write(dev, 0x0013, 1545 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900);
1603 (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900); 1546 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064);
1604 b43_phy_write(dev, 0x0035, 1547 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A);
1605 (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1606 b43_phy_write(dev, 0x005D,
1607 (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1608 } 1548 }
1609 1549
1610 if (dev->bad_frames_preempt) { 1550 if (dev->bad_frames_preempt) {
@@ -1769,8 +1709,7 @@ static void b43_phy_initb6(struct b43_wldev *dev)
1769 b43_phy_write(dev, 0x0038, 0x0668); 1709 b43_phy_write(dev, 0x0038, 0x0668);
1770 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); 1710 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1771 if (phy->radio_rev <= 5) { 1711 if (phy->radio_rev <= 5) {
1772 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D) 1712 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003);
1773 & 0xFF80) | 0x0003);
1774 } 1713 }
1775 if (phy->radio_rev <= 2) 1714 if (phy->radio_rev <= 2)
1776 b43_radio_write16(dev, 0x005D, 0x000D); 1715 b43_radio_write16(dev, 0x005D, 0x000D);
@@ -1779,8 +1718,7 @@ static void b43_phy_initb6(struct b43_wldev *dev)
1779 b43_write16(dev, 0x3E4, 9); 1718 b43_write16(dev, 0x3E4, 9);
1780 b43_phy_mask(dev, 0x61, 0x0FFF); 1719 b43_phy_mask(dev, 0x61, 0x0FFF);
1781 } else { 1720 } else {
1782 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0) 1721 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004);
1783 | 0x0004);
1784 } 1722 }
1785 if (phy->type == B43_PHYTYPE_B) 1723 if (phy->type == B43_PHYTYPE_B)
1786 B43_WARN_ON(1); 1724 B43_WARN_ON(1);
@@ -1837,9 +1775,7 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1837 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C); 1775 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C);
1838 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C); 1776 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C);
1839 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030); 1777 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030);
1840 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1778 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10);
1841 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1842 & 0xFFCF) | 0x10);
1843 1779
1844 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780); 1780 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1845 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); 1781 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
@@ -1850,9 +1786,7 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1850 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004); 1786 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004);
1851 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB); 1787 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB);
1852 } 1788 }
1853 b43_phy_write(dev, B43_PHY_CCK(0x03), 1789 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40);
1854 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1855 & 0xFF9F) | 0x40);
1856 1790
1857 if (phy->radio_rev == 8) { 1791 if (phy->radio_rev == 8) {
1858 b43_radio_write16(dev, 0x43, 0x000F); 1792 b43_radio_write16(dev, 0x43, 0x000F);
@@ -1869,12 +1803,8 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1869 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); 1803 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1870 b43_phy_write(dev, B43_PHY_LO_CTL, 0); 1804 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1871 1805
1872 b43_phy_write(dev, B43_PHY_CCK(0x2B), 1806 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01);
1873 (b43_phy_read(dev, B43_PHY_CCK(0x2B)) 1807 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800);
1874 & 0xFFC0) | 0x01);
1875 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1876 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1877 & 0xC0FF) | 0x800);
1878 1808
1879 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100); 1809 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1880 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF); 1810 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
@@ -1893,12 +1823,8 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1893 for (i = 0; i < loop_i_max; i++) { 1823 for (i = 0; i < loop_i_max; i++) {
1894 for (j = 0; j < 16; j++) { 1824 for (j = 0; j < 16; j++) {
1895 b43_radio_write16(dev, 0x43, i); 1825 b43_radio_write16(dev, 0x43, i);
1896 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1826 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1897 (b43_phy_read(dev, B43_PHY_RFOVERVAL) 1827 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1898 & 0xF0FF) | (j << 8));
1899 b43_phy_write(dev, B43_PHY_PGACTL,
1900 (b43_phy_read(dev, B43_PHY_PGACTL)
1901 & 0x0FFF) | 0xA000);
1902 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); 1828 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1903 udelay(20); 1829 udelay(20);
1904 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) 1830 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
@@ -1912,12 +1838,8 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1912 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30); 1838 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30);
1913 trsw_rx = 0x1B; 1839 trsw_rx = 0x1B;
1914 for (j = j - 8; j < 16; j++) { 1840 for (j = j - 8; j < 16; j++) {
1915 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1841 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1916 (b43_phy_read(dev, B43_PHY_RFOVERVAL) 1842 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1917 & 0xF0FF) | (j << 8));
1918 b43_phy_write(dev, B43_PHY_PGACTL,
1919 (b43_phy_read(dev, B43_PHY_PGACTL)
1920 & 0x0FFF) | 0xA000);
1921 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); 1843 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1922 udelay(20); 1844 udelay(20);
1923 trsw_rx -= 3; 1845 trsw_rx -= 3;
@@ -1974,11 +1896,9 @@ static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
1974 b43_phy_set(dev, 0x047C, 0x0002); 1896 b43_phy_set(dev, 0x047C, 0x0002);
1975 b43_phy_set(dev, 0x047A, 0xF000); 1897 b43_phy_set(dev, 0x047A, 0xF000);
1976 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { 1898 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
1977 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A) 1899 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1978 & 0xFF0F) | 0x0010);
1979 b43_phy_set(dev, 0x005D, 0x8000); 1900 b43_phy_set(dev, 0x005D, 0x8000);
1980 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E) 1901 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1981 & 0xFFC0) | 0x0010);
1982 b43_phy_write(dev, 0x002E, 0xC07F); 1902 b43_phy_write(dev, 0x002E, 0xC07F);
1983 b43_phy_set(dev, 0x0036, 0x0400); 1903 b43_phy_set(dev, 0x0036, 0x0400);
1984 } else { 1904 } else {
@@ -1986,11 +1906,9 @@ static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
1986 b43_phy_set(dev, 0x0036, 0x0400); 1906 b43_phy_set(dev, 0x0036, 0x0400);
1987 b43_phy_mask(dev, 0x005D, 0x7FFF); 1907 b43_phy_mask(dev, 0x005D, 0x7FFF);
1988 b43_phy_mask(dev, 0x004F, 0xFFFE); 1908 b43_phy_mask(dev, 0x004F, 0xFFFE);
1989 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E) 1909 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1990 & 0xFFC0) | 0x0010);
1991 b43_phy_write(dev, 0x002E, 0xC07F); 1910 b43_phy_write(dev, 0x002E, 0xC07F);
1992 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A) 1911 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1993 & 0xFF0F) | 0x0010);
1994 } 1912 }
1995} 1913}
1996 1914
@@ -2006,10 +1924,8 @@ static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
2006 return; 1924 return;
2007 } 1925 }
2008 1926
2009 b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0) 1927 b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2010 | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); 1928 b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2011 b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
2012 | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2013 b43_gphy_tssi_power_lt_init(dev); 1929 b43_gphy_tssi_power_lt_init(dev);
2014 b43_gphy_gain_lt_init(dev); 1930 b43_gphy_gain_lt_init(dev);
2015 b43_phy_mask(dev, 0x0060, 0xFFBF); 1931 b43_phy_mask(dev, 0x0060, 0xFFBF);
@@ -2134,9 +2050,7 @@ static void b43_phy_initg(struct b43_wldev *dev)
2134 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006); 2050 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2135 } 2051 }
2136 if (tmp == 5) { 2052 if (tmp == 5) {
2137 b43_phy_write(dev, B43_PHY_OFDM(0xCC), 2053 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00);
2138 (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
2139 & 0x00FF) | 0x1F00);
2140 } 2054 }
2141 } 2055 }
2142 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2) 2056 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
@@ -2166,10 +2080,7 @@ static void b43_phy_initg(struct b43_wldev *dev)
2166 | gphy->lo_control->tx_bias); 2080 | gphy->lo_control->tx_bias);
2167 } 2081 }
2168 if (phy->rev >= 6) { 2082 if (phy->rev >= 6) {
2169 b43_phy_write(dev, B43_PHY_CCK(0x36), 2083 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12));
2170 (b43_phy_read(dev, B43_PHY_CCK(0x36))
2171 & 0x0FFF) | (gphy->lo_control->
2172 tx_bias << 12));
2173 } 2084 }
2174 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) 2085 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2175 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075); 2086 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
@@ -2423,8 +2334,7 @@ static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2423 ret[i - 1] = b43_gphy_aci_detect(dev, i); 2334 ret[i - 1] = b43_gphy_aci_detect(dev, i);
2424 } 2335 }
2425 b43_switch_channel(dev, channel); 2336 b43_switch_channel(dev, channel);
2426 b43_phy_write(dev, 0x0802, 2337 b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003);
2427 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2428 b43_phy_mask(dev, 0x0403, 0xFFF8); 2338 b43_phy_mask(dev, 0x0403, 0xFFF8);
2429 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); 2339 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
2430 b43_set_original_gains(dev); 2340 b43_set_original_gains(dev);
diff --git a/drivers/net/wireless/b43/wa.c b/drivers/net/wireless/b43/wa.c
index 701dff84e997..fecb86bd72ef 100644
--- a/drivers/net/wireless/b43/wa.c
+++ b/drivers/net/wireless/b43/wa.c
@@ -72,11 +72,9 @@ void b43_wa_initgains(struct b43_wldev *dev)
72 b43_phy_write(dev, 0x001D, 0x0F40); 72 b43_phy_write(dev, 0x001D, 0x0F40);
73 b43_phy_write(dev, 0x001F, 0x1C00); 73 b43_phy_write(dev, 0x001F, 0x1C00);
74 if (phy->rev <= 3) 74 if (phy->rev <= 3)
75 b43_phy_write(dev, 0x002A, 75 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400);
76 (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x0400);
77 else if (phy->rev == 5) { 76 else if (phy->rev == 5) {
78 b43_phy_write(dev, 0x002A, 77 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00);
79 (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x1A00);
80 b43_phy_write(dev, 0x00CC, 0x2121); 78 b43_phy_write(dev, 0x00CC, 0x2121);
81 } 79 }
82 if (phy->rev >= 3) 80 if (phy->rev >= 3)
@@ -271,8 +269,7 @@ static void b43_wa_2060txlna_gain(struct b43_wldev *dev)
271 269
272static void b43_wa_lms(struct b43_wldev *dev) 270static void b43_wa_lms(struct b43_wldev *dev)
273{ 271{
274 b43_phy_write(dev, 0x0055, 272 b43_phy_maskset(dev, 0x0055, 0xFFC0, 0x0004);
275 (b43_phy_read(dev, 0x0055) & 0xFFC0) | 0x0004);
276} 273}
277 274
278static void b43_wa_mixedsignal(struct b43_wldev *dev) 275static void b43_wa_mixedsignal(struct b43_wldev *dev)
@@ -328,8 +325,7 @@ static void b43_wa_crs_ed(struct b43_wldev *dev)
328 325
329static void b43_wa_crs_thr(struct b43_wldev *dev) 326static void b43_wa_crs_thr(struct b43_wldev *dev)
330{ 327{
331 b43_phy_write(dev, B43_PHY_CRS0, 328 b43_phy_maskset(dev, B43_PHY_CRS0, ~0x03C0, 0xD000);
332 (b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
333} 329}
334 330
335static void b43_wa_crs_blank(struct b43_wldev *dev) 331static void b43_wa_crs_blank(struct b43_wldev *dev)
@@ -386,71 +382,46 @@ static void b43_wa_altagc(struct b43_wldev *dev)
386 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25); 382 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25);
387 } 383 }
388 384
389 b43_phy_write(dev, B43_PHY_CCKSHIFTBITS_WA, 385 b43_phy_maskset(dev, B43_PHY_CCKSHIFTBITS_WA, ~0xFF00, 0x5700);
390 (b43_phy_read(dev, B43_PHY_CCKSHIFTBITS_WA) & ~0xFF00) | 0x5700); 386 b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x007F, 0x000F);
391 b43_phy_write(dev, B43_PHY_OFDM(0x1A), 387 b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x3F80, 0x2B80);
392 (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x007F) | 0x000F); 388 b43_phy_maskset(dev, B43_PHY_ANTWRSETT, 0xF0FF, 0x0300);
393 b43_phy_write(dev, B43_PHY_OFDM(0x1A),
394 (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x3F80) | 0x2B80);
395 b43_phy_write(dev, B43_PHY_ANTWRSETT,
396 (b43_phy_read(dev, B43_PHY_ANTWRSETT) & 0xF0FF) | 0x0300);
397 b43_radio_write16(dev, 0x7A, 389 b43_radio_write16(dev, 0x7A,
398 b43_radio_read16(dev, 0x7A) | 0x0008); 390 b43_radio_read16(dev, 0x7A) | 0x0008);
399 b43_phy_write(dev, B43_PHY_N1P1GAIN, 391 b43_phy_maskset(dev, B43_PHY_N1P1GAIN, ~0x000F, 0x0008);
400 (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x000F) | 0x0008); 392 b43_phy_maskset(dev, B43_PHY_P1P2GAIN, ~0x0F00, 0x0600);
401 b43_phy_write(dev, B43_PHY_P1P2GAIN, 393 b43_phy_maskset(dev, B43_PHY_N1N2GAIN, ~0x0F00, 0x0700);
402 (b43_phy_read(dev, B43_PHY_P1P2GAIN) & ~0x0F00) | 0x0600); 394 b43_phy_maskset(dev, B43_PHY_N1P1GAIN, ~0x0F00, 0x0100);
403 b43_phy_write(dev, B43_PHY_N1N2GAIN,
404 (b43_phy_read(dev, B43_PHY_N1N2GAIN) & ~0x0F00) | 0x0700);
405 b43_phy_write(dev, B43_PHY_N1P1GAIN,
406 (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x0F00) | 0x0100);
407 if (phy->rev == 1) { 395 if (phy->rev == 1) {
408 b43_phy_write(dev, B43_PHY_N1N2GAIN, 396 b43_phy_maskset(dev, B43_PHY_N1N2GAIN, ~0x000F, 0x0007);
409 (b43_phy_read(dev, B43_PHY_N1N2GAIN)
410 & ~0x000F) | 0x0007);
411 } 397 }
412 b43_phy_write(dev, B43_PHY_OFDM(0x88), 398 b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x00FF, 0x001C);
413 (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x00FF) | 0x001C); 399 b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x3F00, 0x0200);
414 b43_phy_write(dev, B43_PHY_OFDM(0x88), 400 b43_phy_maskset(dev, B43_PHY_OFDM(0x96), ~0x00FF, 0x001C);
415 (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x3F00) | 0x0200); 401 b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x00FF, 0x0020);
416 b43_phy_write(dev, B43_PHY_OFDM(0x96), 402 b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x3F00, 0x0200);
417 (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0x00FF) | 0x001C); 403 b43_phy_maskset(dev, B43_PHY_OFDM(0x82), ~0x00FF, 0x002E);
418 b43_phy_write(dev, B43_PHY_OFDM(0x89), 404 b43_phy_maskset(dev, B43_PHY_OFDM(0x96), ~0xFF00, 0x1A00);
419 (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x00FF) | 0x0020); 405 b43_phy_maskset(dev, B43_PHY_OFDM(0x81), ~0x00FF, 0x0028);
420 b43_phy_write(dev, B43_PHY_OFDM(0x89), 406 b43_phy_maskset(dev, B43_PHY_OFDM(0x81), ~0xFF00, 0x2C00);
421 (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x3F00) | 0x0200);
422 b43_phy_write(dev, B43_PHY_OFDM(0x82),
423 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & ~0x00FF) | 0x002E);
424 b43_phy_write(dev, B43_PHY_OFDM(0x96),
425 (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0xFF00) | 0x1A00);
426 b43_phy_write(dev, B43_PHY_OFDM(0x81),
427 (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0x00FF) | 0x0028);
428 b43_phy_write(dev, B43_PHY_OFDM(0x81),
429 (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0xFF00) | 0x2C00);
430 if (phy->rev == 1) { 407 if (phy->rev == 1) {
431 b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B); 408 b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);
432 b43_phy_write(dev, B43_PHY_OFDM(0x1B), 409 b43_phy_maskset(dev, B43_PHY_OFDM(0x1B), ~0x001E, 0x0002);
433 (b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E) | 0x0002);
434 } else { 410 } else {
435 b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x001E); 411 b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x001E);
436 b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A); 412 b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);
437 b43_phy_write(dev, B43_PHY_LPFGAINCTL, 413 b43_phy_maskset(dev, B43_PHY_LPFGAINCTL, ~0x000F, 0x0004);
438 (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0x000F) | 0x0004);
439 if (phy->rev >= 6) { 414 if (phy->rev >= 6) {
440 b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A); 415 b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);
441 b43_phy_write(dev, B43_PHY_LPFGAINCTL, 416 b43_phy_maskset(dev, B43_PHY_LPFGAINCTL, ~0xF000, 0x3000);
442 (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0xF000) | 0x3000);
443 } 417 }
444 } 418 }
445 b43_phy_write(dev, B43_PHY_DIVSRCHIDX, 419 b43_phy_maskset(dev, B43_PHY_DIVSRCHIDX, 0x8080, 0x7874);
446 (b43_phy_read(dev, B43_PHY_DIVSRCHIDX) & 0x8080) | 0x7874);
447 b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00); 420 b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);
448 if (phy->rev == 1) { 421 if (phy->rev == 1) {
449 b43_phy_write(dev, B43_PHY_DIVP1P2GAIN, 422 b43_phy_maskset(dev, B43_PHY_DIVP1P2GAIN, ~0x0F00, 0x0600);
450 (b43_phy_read(dev, B43_PHY_DIVP1P2GAIN) & ~0x0F00) | 0x0600);
451 b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E); 423 b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);
452 b43_phy_write(dev, B43_PHY_ANTWRSETT, 424 b43_phy_maskset(dev, B43_PHY_ANTWRSETT, ~0x00FF, 0x001E);
453 (b43_phy_read(dev, B43_PHY_ANTWRSETT) & ~0x00FF) | 0x001E);
454 b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002); 425 b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);
455 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0); 426 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0);
456 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7); 427 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7);