diff options
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/ich8lan.c | 11 | ||||
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/ich8lan.h | 2 |
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c index 059f1b0112f4..e8587b94b138 100644 --- a/drivers/net/ethernet/intel/e1000e/ich8lan.c +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c | |||
@@ -842,6 +842,17 @@ s32 e1000_set_eee_pchlan(struct e1000_hw *hw) | |||
842 | } | 842 | } |
843 | } | 843 | } |
844 | 844 | ||
845 | if (hw->phy.type == e1000_phy_82579) { | ||
846 | ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, | ||
847 | &data); | ||
848 | if (ret_val) | ||
849 | goto release; | ||
850 | |||
851 | data &= ~I82579_LPI_100_PLL_SHUT; | ||
852 | ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, | ||
853 | data); | ||
854 | } | ||
855 | |||
845 | /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ | 856 | /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ |
846 | ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); | 857 | ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); |
847 | if (ret_val) | 858 | if (ret_val) |
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h index 8fc6c15f31c8..5515126c81c1 100644 --- a/drivers/net/ethernet/intel/e1000e/ich8lan.h +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h | |||
@@ -232,12 +232,14 @@ | |||
232 | #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ | 232 | #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ |
233 | #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ | 233 | #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ |
234 | #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ | 234 | #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ |
235 | #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */ | ||
235 | #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ | 236 | #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ |
236 | #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ | 237 | #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ |
237 | #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ | 238 | #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ |
238 | #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ | 239 | #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ |
239 | #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ | 240 | #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ |
240 | #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ | 241 | #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ |
242 | #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */ | ||
241 | #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ | 243 | #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ |
242 | #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ | 244 | #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ |
243 | #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ | 245 | #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ |