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-rw-r--r--drivers/net/bnx2x/bnx2x_hsi.h9
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c18
2 files changed, 20 insertions, 7 deletions
diff --git a/drivers/net/bnx2x/bnx2x_hsi.h b/drivers/net/bnx2x/bnx2x_hsi.h
index 18c8e23a0e82..4cfd4e9b5586 100644
--- a/drivers/net/bnx2x/bnx2x_hsi.h
+++ b/drivers/net/bnx2x/bnx2x_hsi.h
@@ -244,7 +244,14 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
244 244
245 u16 xgxs_config_tx[4]; /* 0x1A0 */ 245 u16 xgxs_config_tx[4]; /* 0x1A0 */
246 246
247 u32 Reserved1[57]; /* 0x1A8 */ 247 u32 Reserved1[56]; /* 0x1A8 */
248 u32 default_cfg; /* 0x288 */
249 /* Enable BAM on KR */
250#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
251#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
252#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
253#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
254
248 u32 speed_capability_mask2; /* 0x28C */ 255 u32 speed_capability_mask2; /* 0x28C */
249#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 256#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
250#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 257#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 488e251a2d3f..d076b911e160 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -3525,13 +3525,19 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
3525 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 3525 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
3526 3526
3527 /* Enable CL37 BAM */ 3527 /* Enable CL37 BAM */
3528 bnx2x_cl45_read(bp, phy, 3528 if (REG_RD(bp, params->shmem_base +
3529 MDIO_AN_DEVAD, 3529 offsetof(struct shmem_region, dev_info.
3530 MDIO_AN_REG_8073_BAM, &val); 3530 port_hw_config[params->port].default_cfg)) &
3531 bnx2x_cl45_write(bp, phy, 3531 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3532 MDIO_AN_DEVAD,
3533 MDIO_AN_REG_8073_BAM, val | 1);
3534 3532
3533 bnx2x_cl45_read(bp, phy,
3534 MDIO_AN_DEVAD,
3535 MDIO_AN_REG_8073_BAM, &val);
3536 bnx2x_cl45_write(bp, phy,
3537 MDIO_AN_DEVAD,
3538 MDIO_AN_REG_8073_BAM, val | 1);
3539 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3540 }
3535 if (params->loopback_mode == LOOPBACK_EXT) { 3541 if (params->loopback_mode == LOOPBACK_EXT) {
3536 bnx2x_807x_force_10G(bp, phy); 3542 bnx2x_807x_force_10G(bp, phy);
3537 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 3543 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");