diff options
Diffstat (limited to 'drivers/net/wireless/zd1211rw/zd_chip.h')
| -rw-r--r-- | drivers/net/wireless/zd1211rw/zd_chip.h | 827 |
1 files changed, 827 insertions, 0 deletions
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.h b/drivers/net/wireless/zd1211rw/zd_chip.h new file mode 100644 index 000000000000..069d2b467339 --- /dev/null +++ b/drivers/net/wireless/zd1211rw/zd_chip.h | |||
| @@ -0,0 +1,827 @@ | |||
| 1 | /* zd_chip.h | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License as published by | ||
| 5 | * the Free Software Foundation; either version 2 of the License, or | ||
| 6 | * (at your option) any later version. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef _ZD_CHIP_H | ||
| 19 | #define _ZD_CHIP_H | ||
| 20 | |||
| 21 | #include "zd_types.h" | ||
| 22 | #include "zd_rf.h" | ||
| 23 | #include "zd_usb.h" | ||
| 24 | |||
| 25 | /* Header for the Media Access Controller (MAC) and the Baseband Processor | ||
| 26 | * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and | ||
| 27 | * adds a processor for handling the USB protocol. | ||
| 28 | */ | ||
| 29 | |||
| 30 | /* 8-bit hardware registers */ | ||
| 31 | #define CR0 CTL_REG(0x0000) | ||
| 32 | #define CR1 CTL_REG(0x0004) | ||
| 33 | #define CR2 CTL_REG(0x0008) | ||
| 34 | #define CR3 CTL_REG(0x000C) | ||
| 35 | |||
| 36 | #define CR5 CTL_REG(0x0010) | ||
| 37 | /* bit 5: if set short preamble used | ||
| 38 | * bit 6: filter band - Japan channel 14 on, else off | ||
| 39 | */ | ||
| 40 | #define CR6 CTL_REG(0x0014) | ||
| 41 | #define CR7 CTL_REG(0x0018) | ||
| 42 | #define CR8 CTL_REG(0x001C) | ||
| 43 | |||
| 44 | #define CR4 CTL_REG(0x0020) | ||
| 45 | |||
| 46 | #define CR9 CTL_REG(0x0024) | ||
| 47 | /* bit 2: antenna switch (together with CR10) */ | ||
| 48 | #define CR10 CTL_REG(0x0028) | ||
| 49 | /* bit 1: antenna switch (together with CR9) | ||
| 50 | * RF2959 controls with CR11 radion on and off | ||
| 51 | */ | ||
| 52 | #define CR11 CTL_REG(0x002C) | ||
| 53 | /* bit 6: TX power control for OFDM | ||
| 54 | * RF2959 controls with CR10 radio on and off | ||
| 55 | */ | ||
| 56 | #define CR12 CTL_REG(0x0030) | ||
| 57 | #define CR13 CTL_REG(0x0034) | ||
| 58 | #define CR14 CTL_REG(0x0038) | ||
| 59 | #define CR15 CTL_REG(0x003C) | ||
| 60 | #define CR16 CTL_REG(0x0040) | ||
| 61 | #define CR17 CTL_REG(0x0044) | ||
| 62 | #define CR18 CTL_REG(0x0048) | ||
| 63 | #define CR19 CTL_REG(0x004C) | ||
| 64 | #define CR20 CTL_REG(0x0050) | ||
| 65 | #define CR21 CTL_REG(0x0054) | ||
| 66 | #define CR22 CTL_REG(0x0058) | ||
| 67 | #define CR23 CTL_REG(0x005C) | ||
| 68 | #define CR24 CTL_REG(0x0060) /* CCA threshold */ | ||
| 69 | #define CR25 CTL_REG(0x0064) | ||
| 70 | #define CR26 CTL_REG(0x0068) | ||
| 71 | #define CR27 CTL_REG(0x006C) | ||
| 72 | #define CR28 CTL_REG(0x0070) | ||
| 73 | #define CR29 CTL_REG(0x0074) | ||
| 74 | #define CR30 CTL_REG(0x0078) | ||
| 75 | #define CR31 CTL_REG(0x007C) /* TX power control for RF in CCK mode */ | ||
| 76 | #define CR32 CTL_REG(0x0080) | ||
| 77 | #define CR33 CTL_REG(0x0084) | ||
| 78 | #define CR34 CTL_REG(0x0088) | ||
| 79 | #define CR35 CTL_REG(0x008C) | ||
| 80 | #define CR36 CTL_REG(0x0090) | ||
| 81 | #define CR37 CTL_REG(0x0094) | ||
| 82 | #define CR38 CTL_REG(0x0098) | ||
| 83 | #define CR39 CTL_REG(0x009C) | ||
| 84 | #define CR40 CTL_REG(0x00A0) | ||
| 85 | #define CR41 CTL_REG(0x00A4) | ||
| 86 | #define CR42 CTL_REG(0x00A8) | ||
| 87 | #define CR43 CTL_REG(0x00AC) | ||
| 88 | #define CR44 CTL_REG(0x00B0) | ||
| 89 | #define CR45 CTL_REG(0x00B4) | ||
| 90 | #define CR46 CTL_REG(0x00B8) | ||
| 91 | #define CR47 CTL_REG(0x00BC) /* CCK baseband gain | ||
| 92 | * (patch value might be in EEPROM) | ||
| 93 | */ | ||
| 94 | #define CR48 CTL_REG(0x00C0) | ||
| 95 | #define CR49 CTL_REG(0x00C4) | ||
| 96 | #define CR50 CTL_REG(0x00C8) | ||
| 97 | #define CR51 CTL_REG(0x00CC) /* TX power control for RF in 6-36M modes */ | ||
| 98 | #define CR52 CTL_REG(0x00D0) /* TX power control for RF in 48M mode */ | ||
| 99 | #define CR53 CTL_REG(0x00D4) /* TX power control for RF in 54M mode */ | ||
| 100 | #define CR54 CTL_REG(0x00D8) | ||
| 101 | #define CR55 CTL_REG(0x00DC) | ||
| 102 | #define CR56 CTL_REG(0x00E0) | ||
| 103 | #define CR57 CTL_REG(0x00E4) | ||
| 104 | #define CR58 CTL_REG(0x00E8) | ||
| 105 | #define CR59 CTL_REG(0x00EC) | ||
| 106 | #define CR60 CTL_REG(0x00F0) | ||
| 107 | #define CR61 CTL_REG(0x00F4) | ||
| 108 | #define CR62 CTL_REG(0x00F8) | ||
| 109 | #define CR63 CTL_REG(0x00FC) | ||
| 110 | #define CR64 CTL_REG(0x0100) | ||
| 111 | #define CR65 CTL_REG(0x0104) /* OFDM 54M calibration */ | ||
| 112 | #define CR66 CTL_REG(0x0108) /* OFDM 48M calibration */ | ||
| 113 | #define CR67 CTL_REG(0x010C) /* OFDM 36M calibration */ | ||
| 114 | #define CR68 CTL_REG(0x0110) /* CCK calibration */ | ||
| 115 | #define CR69 CTL_REG(0x0114) | ||
| 116 | #define CR70 CTL_REG(0x0118) | ||
| 117 | #define CR71 CTL_REG(0x011C) | ||
| 118 | #define CR72 CTL_REG(0x0120) | ||
| 119 | #define CR73 CTL_REG(0x0124) | ||
| 120 | #define CR74 CTL_REG(0x0128) | ||
| 121 | #define CR75 CTL_REG(0x012C) | ||
| 122 | #define CR76 CTL_REG(0x0130) | ||
| 123 | #define CR77 CTL_REG(0x0134) | ||
| 124 | #define CR78 CTL_REG(0x0138) | ||
| 125 | #define CR79 CTL_REG(0x013C) | ||
| 126 | #define CR80 CTL_REG(0x0140) | ||
| 127 | #define CR81 CTL_REG(0x0144) | ||
| 128 | #define CR82 CTL_REG(0x0148) | ||
| 129 | #define CR83 CTL_REG(0x014C) | ||
| 130 | #define CR84 CTL_REG(0x0150) | ||
| 131 | #define CR85 CTL_REG(0x0154) | ||
| 132 | #define CR86 CTL_REG(0x0158) | ||
| 133 | #define CR87 CTL_REG(0x015C) | ||
| 134 | #define CR88 CTL_REG(0x0160) | ||
| 135 | #define CR89 CTL_REG(0x0164) | ||
| 136 | #define CR90 CTL_REG(0x0168) | ||
| 137 | #define CR91 CTL_REG(0x016C) | ||
| 138 | #define CR92 CTL_REG(0x0170) | ||
| 139 | #define CR93 CTL_REG(0x0174) | ||
| 140 | #define CR94 CTL_REG(0x0178) | ||
| 141 | #define CR95 CTL_REG(0x017C) | ||
| 142 | #define CR96 CTL_REG(0x0180) | ||
| 143 | #define CR97 CTL_REG(0x0184) | ||
| 144 | #define CR98 CTL_REG(0x0188) | ||
| 145 | #define CR99 CTL_REG(0x018C) | ||
| 146 | #define CR100 CTL_REG(0x0190) | ||
| 147 | #define CR101 CTL_REG(0x0194) | ||
| 148 | #define CR102 CTL_REG(0x0198) | ||
| 149 | #define CR103 CTL_REG(0x019C) | ||
| 150 | #define CR104 CTL_REG(0x01A0) | ||
| 151 | #define CR105 CTL_REG(0x01A4) | ||
| 152 | #define CR106 CTL_REG(0x01A8) | ||
| 153 | #define CR107 CTL_REG(0x01AC) | ||
| 154 | #define CR108 CTL_REG(0x01B0) | ||
| 155 | #define CR109 CTL_REG(0x01B4) | ||
| 156 | #define CR110 CTL_REG(0x01B8) | ||
| 157 | #define CR111 CTL_REG(0x01BC) | ||
| 158 | #define CR112 CTL_REG(0x01C0) | ||
| 159 | #define CR113 CTL_REG(0x01C4) | ||
| 160 | #define CR114 CTL_REG(0x01C8) | ||
| 161 | #define CR115 CTL_REG(0x01CC) | ||
| 162 | #define CR116 CTL_REG(0x01D0) | ||
| 163 | #define CR117 CTL_REG(0x01D4) | ||
| 164 | #define CR118 CTL_REG(0x01D8) | ||
| 165 | #define CR119 CTL_REG(0x01DC) | ||
| 166 | #define CR120 CTL_REG(0x01E0) | ||
| 167 | #define CR121 CTL_REG(0x01E4) | ||
| 168 | #define CR122 CTL_REG(0x01E8) | ||
| 169 | #define CR123 CTL_REG(0x01EC) | ||
| 170 | #define CR124 CTL_REG(0x01F0) | ||
| 171 | #define CR125 CTL_REG(0x01F4) | ||
| 172 | #define CR126 CTL_REG(0x01F8) | ||
| 173 | #define CR127 CTL_REG(0x01FC) | ||
| 174 | #define CR128 CTL_REG(0x0200) | ||
| 175 | #define CR129 CTL_REG(0x0204) | ||
| 176 | #define CR130 CTL_REG(0x0208) | ||
| 177 | #define CR131 CTL_REG(0x020C) | ||
| 178 | #define CR132 CTL_REG(0x0210) | ||
| 179 | #define CR133 CTL_REG(0x0214) | ||
| 180 | #define CR134 CTL_REG(0x0218) | ||
| 181 | #define CR135 CTL_REG(0x021C) | ||
| 182 | #define CR136 CTL_REG(0x0220) | ||
| 183 | #define CR137 CTL_REG(0x0224) | ||
| 184 | #define CR138 CTL_REG(0x0228) | ||
| 185 | #define CR139 CTL_REG(0x022C) | ||
| 186 | #define CR140 CTL_REG(0x0230) | ||
| 187 | #define CR141 CTL_REG(0x0234) | ||
| 188 | #define CR142 CTL_REG(0x0238) | ||
| 189 | #define CR143 CTL_REG(0x023C) | ||
| 190 | #define CR144 CTL_REG(0x0240) | ||
| 191 | #define CR145 CTL_REG(0x0244) | ||
| 192 | #define CR146 CTL_REG(0x0248) | ||
| 193 | #define CR147 CTL_REG(0x024C) | ||
| 194 | #define CR148 CTL_REG(0x0250) | ||
| 195 | #define CR149 CTL_REG(0x0254) | ||
| 196 | #define CR150 CTL_REG(0x0258) | ||
| 197 | #define CR151 CTL_REG(0x025C) | ||
| 198 | #define CR152 CTL_REG(0x0260) | ||
| 199 | #define CR153 CTL_REG(0x0264) | ||
| 200 | #define CR154 CTL_REG(0x0268) | ||
| 201 | #define CR155 CTL_REG(0x026C) | ||
| 202 | #define CR156 CTL_REG(0x0270) | ||
| 203 | #define CR157 CTL_REG(0x0274) | ||
| 204 | #define CR158 CTL_REG(0x0278) | ||
| 205 | #define CR159 CTL_REG(0x027C) | ||
| 206 | #define CR160 CTL_REG(0x0280) | ||
| 207 | #define CR161 CTL_REG(0x0284) | ||
| 208 | #define CR162 CTL_REG(0x0288) | ||
| 209 | #define CR163 CTL_REG(0x028C) | ||
| 210 | #define CR164 CTL_REG(0x0290) | ||
| 211 | #define CR165 CTL_REG(0x0294) | ||
| 212 | #define CR166 CTL_REG(0x0298) | ||
| 213 | #define CR167 CTL_REG(0x029C) | ||
| 214 | #define CR168 CTL_REG(0x02A0) | ||
| 215 | #define CR169 CTL_REG(0x02A4) | ||
| 216 | #define CR170 CTL_REG(0x02A8) | ||
| 217 | #define CR171 CTL_REG(0x02AC) | ||
| 218 | #define CR172 CTL_REG(0x02B0) | ||
| 219 | #define CR173 CTL_REG(0x02B4) | ||
| 220 | #define CR174 CTL_REG(0x02B8) | ||
| 221 | #define CR175 CTL_REG(0x02BC) | ||
| 222 | #define CR176 CTL_REG(0x02C0) | ||
| 223 | #define CR177 CTL_REG(0x02C4) | ||
| 224 | #define CR178 CTL_REG(0x02C8) | ||
| 225 | #define CR179 CTL_REG(0x02CC) | ||
| 226 | #define CR180 CTL_REG(0x02D0) | ||
| 227 | #define CR181 CTL_REG(0x02D4) | ||
| 228 | #define CR182 CTL_REG(0x02D8) | ||
| 229 | #define CR183 CTL_REG(0x02DC) | ||
| 230 | #define CR184 CTL_REG(0x02E0) | ||
| 231 | #define CR185 CTL_REG(0x02E4) | ||
| 232 | #define CR186 CTL_REG(0x02E8) | ||
| 233 | #define CR187 CTL_REG(0x02EC) | ||
| 234 | #define CR188 CTL_REG(0x02F0) | ||
| 235 | #define CR189 CTL_REG(0x02F4) | ||
| 236 | #define CR190 CTL_REG(0x02F8) | ||
| 237 | #define CR191 CTL_REG(0x02FC) | ||
| 238 | #define CR192 CTL_REG(0x0300) | ||
| 239 | #define CR193 CTL_REG(0x0304) | ||
| 240 | #define CR194 CTL_REG(0x0308) | ||
| 241 | #define CR195 CTL_REG(0x030C) | ||
| 242 | #define CR196 CTL_REG(0x0310) | ||
| 243 | #define CR197 CTL_REG(0x0314) | ||
| 244 | #define CR198 CTL_REG(0x0318) | ||
| 245 | #define CR199 CTL_REG(0x031C) | ||
| 246 | #define CR200 CTL_REG(0x0320) | ||
| 247 | #define CR201 CTL_REG(0x0324) | ||
| 248 | #define CR202 CTL_REG(0x0328) | ||
| 249 | #define CR203 CTL_REG(0x032C) /* I2C bus template value & flash control */ | ||
| 250 | #define CR204 CTL_REG(0x0330) | ||
| 251 | #define CR205 CTL_REG(0x0334) | ||
| 252 | #define CR206 CTL_REG(0x0338) | ||
| 253 | #define CR207 CTL_REG(0x033C) | ||
| 254 | #define CR208 CTL_REG(0x0340) | ||
| 255 | #define CR209 CTL_REG(0x0344) | ||
| 256 | #define CR210 CTL_REG(0x0348) | ||
| 257 | #define CR211 CTL_REG(0x034C) | ||
| 258 | #define CR212 CTL_REG(0x0350) | ||
| 259 | #define CR213 CTL_REG(0x0354) | ||
| 260 | #define CR214 CTL_REG(0x0358) | ||
| 261 | #define CR215 CTL_REG(0x035C) | ||
| 262 | #define CR216 CTL_REG(0x0360) | ||
| 263 | #define CR217 CTL_REG(0x0364) | ||
| 264 | #define CR218 CTL_REG(0x0368) | ||
| 265 | #define CR219 CTL_REG(0x036C) | ||
| 266 | #define CR220 CTL_REG(0x0370) | ||
| 267 | #define CR221 CTL_REG(0x0374) | ||
| 268 | #define CR222 CTL_REG(0x0378) | ||
| 269 | #define CR223 CTL_REG(0x037C) | ||
| 270 | #define CR224 CTL_REG(0x0380) | ||
| 271 | #define CR225 CTL_REG(0x0384) | ||
| 272 | #define CR226 CTL_REG(0x0388) | ||
| 273 | #define CR227 CTL_REG(0x038C) | ||
| 274 | #define CR228 CTL_REG(0x0390) | ||
| 275 | #define CR229 CTL_REG(0x0394) | ||
| 276 | #define CR230 CTL_REG(0x0398) | ||
| 277 | #define CR231 CTL_REG(0x039C) | ||
| 278 | #define CR232 CTL_REG(0x03A0) | ||
| 279 | #define CR233 CTL_REG(0x03A4) | ||
| 280 | #define CR234 CTL_REG(0x03A8) | ||
| 281 | #define CR235 CTL_REG(0x03AC) | ||
| 282 | #define CR236 CTL_REG(0x03B0) | ||
| 283 | |||
| 284 | #define CR240 CTL_REG(0x03C0) | ||
| 285 | /* bit 7: host-controlled RF register writes | ||
| 286 | * CR241-CR245: for hardware controlled writing of RF bits, not needed for | ||
| 287 | * USB | ||
| 288 | */ | ||
| 289 | #define CR241 CTL_REG(0x03C4) | ||
| 290 | #define CR242 CTL_REG(0x03C8) | ||
| 291 | #define CR243 CTL_REG(0x03CC) | ||
| 292 | #define CR244 CTL_REG(0x03D0) | ||
| 293 | #define CR245 CTL_REG(0x03D4) | ||
| 294 | |||
| 295 | #define CR251 CTL_REG(0x03EC) /* only used for activation and deactivation of | ||
| 296 | * Airoha RFs AL2230 and AL7230B | ||
| 297 | */ | ||
| 298 | #define CR252 CTL_REG(0x03F0) | ||
| 299 | #define CR253 CTL_REG(0x03F4) | ||
| 300 | #define CR254 CTL_REG(0x03F8) | ||
| 301 | #define CR255 CTL_REG(0x03FC) | ||
| 302 | |||
| 303 | #define CR_MAX_PHY_REG 255 | ||
| 304 | |||
| 305 | /* Taken from the ZYDAS driver, not all of them are relevant for the ZSD1211 | ||
| 306 | * driver. | ||
| 307 | */ | ||
| 308 | |||
| 309 | #define CR_RF_IF_CLK CTL_REG(0x0400) | ||
| 310 | #define CR_RF_IF_DATA CTL_REG(0x0404) | ||
| 311 | #define CR_PE1_PE2 CTL_REG(0x0408) | ||
| 312 | #define CR_PE2_DLY CTL_REG(0x040C) | ||
| 313 | #define CR_LE1 CTL_REG(0x0410) | ||
| 314 | #define CR_LE2 CTL_REG(0x0414) | ||
| 315 | /* Seems to enable/disable GPI (General Purpose IO?) */ | ||
| 316 | #define CR_GPI_EN CTL_REG(0x0418) | ||
| 317 | #define CR_RADIO_PD CTL_REG(0x042C) | ||
| 318 | #define CR_RF2948_PD CTL_REG(0x042C) | ||
| 319 | #define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C) | ||
| 320 | #define CR_CONFIG_PHILIPS CTL_REG(0x0440) | ||
| 321 | #define CR_SA2400_SER_AP CTL_REG(0x0444) | ||
| 322 | #define CR_I2C_WRITE CTL_REG(0x0444) | ||
| 323 | #define CR_SA2400_SER_RP CTL_REG(0x0448) | ||
| 324 | #define CR_RADIO_PE CTL_REG(0x0458) | ||
| 325 | #define CR_RST_BUS_MASTER CTL_REG(0x045C) | ||
| 326 | #define CR_RFCFG CTL_REG(0x0464) | ||
| 327 | #define CR_HSTSCHG CTL_REG(0x046C) | ||
| 328 | #define CR_PHY_ON CTL_REG(0x0474) | ||
| 329 | #define CR_RX_DELAY CTL_REG(0x0478) | ||
| 330 | #define CR_RX_PE_DELAY CTL_REG(0x047C) | ||
| 331 | #define CR_GPIO_1 CTL_REG(0x0490) | ||
| 332 | #define CR_GPIO_2 CTL_REG(0x0494) | ||
| 333 | #define CR_EncryBufMux CTL_REG(0x04A8) | ||
| 334 | #define CR_PS_CTRL CTL_REG(0x0500) | ||
| 335 | #define CR_ADDA_PWR_DWN CTL_REG(0x0504) | ||
| 336 | #define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508) | ||
| 337 | #define CR_MAC_PS_STATE CTL_REG(0x050C) | ||
| 338 | |||
| 339 | #define CR_INTERRUPT CTL_REG(0x0510) | ||
| 340 | #define INT_TX_COMPLETE 0x00000001 | ||
| 341 | #define INT_RX_COMPLETE 0x00000002 | ||
| 342 | #define INT_RETRY_FAIL 0x00000004 | ||
| 343 | #define INT_WAKEUP 0x00000008 | ||
| 344 | #define INT_DTIM_NOTIFY 0x00000020 | ||
| 345 | #define INT_CFG_NEXT_BCN 0x00000040 | ||
| 346 | #define INT_BUS_ABORT 0x00000080 | ||
| 347 | #define INT_TX_FIFO_READY 0x00000100 | ||
| 348 | #define INT_UART 0x00000200 | ||
| 349 | #define INT_TX_COMPLETE_EN 0x00010000 | ||
| 350 | #define INT_RX_COMPLETE_EN 0x00020000 | ||
| 351 | #define INT_RETRY_FAIL_EN 0x00040000 | ||
| 352 | #define INT_WAKEUP_EN 0x00080000 | ||
| 353 | #define INT_DTIM_NOTIFY_EN 0x00200000 | ||
| 354 | #define INT_CFG_NEXT_BCN_EN 0x00400000 | ||
| 355 | #define INT_BUS_ABORT_EN 0x00800000 | ||
| 356 | #define INT_TX_FIFO_READY_EN 0x01000000 | ||
| 357 | #define INT_UART_EN 0x02000000 | ||
| 358 | |||
| 359 | #define CR_TSF_LOW_PART CTL_REG(0x0514) | ||
| 360 | #define CR_TSF_HIGH_PART CTL_REG(0x0518) | ||
| 361 | |||
| 362 | /* Following three values are in time units (1024us) | ||
| 363 | * Following condition must be met: | ||
| 364 | * atim < tbtt < bcn | ||
| 365 | */ | ||
| 366 | #define CR_ATIM_WND_PERIOD CTL_REG(0x051C) | ||
| 367 | #define CR_BCN_INTERVAL CTL_REG(0x0520) | ||
| 368 | #define CR_PRE_TBTT CTL_REG(0x0524) | ||
| 369 | /* in units of TU(1024us) */ | ||
| 370 | |||
| 371 | /* for UART support */ | ||
| 372 | #define CR_UART_RBR_THR_DLL CTL_REG(0x0540) | ||
| 373 | #define CR_UART_DLM_IER CTL_REG(0x0544) | ||
| 374 | #define CR_UART_IIR_FCR CTL_REG(0x0548) | ||
| 375 | #define CR_UART_LCR CTL_REG(0x054c) | ||
| 376 | #define CR_UART_MCR CTL_REG(0x0550) | ||
| 377 | #define CR_UART_LSR CTL_REG(0x0554) | ||
| 378 | #define CR_UART_MSR CTL_REG(0x0558) | ||
| 379 | #define CR_UART_ECR CTL_REG(0x055c) | ||
| 380 | #define CR_UART_STATUS CTL_REG(0x0560) | ||
| 381 | |||
| 382 | #define CR_PCI_TX_ADDR_P1 CTL_REG(0x0600) | ||
| 383 | #define CR_PCI_TX_AddR_P2 CTL_REG(0x0604) | ||
| 384 | #define CR_PCI_RX_AddR_P1 CTL_REG(0x0608) | ||
| 385 | #define CR_PCI_RX_AddR_P2 CTL_REG(0x060C) | ||
| 386 | |||
| 387 | /* must be overwritten if custom MAC address will be used */ | ||
| 388 | #define CR_MAC_ADDR_P1 CTL_REG(0x0610) | ||
| 389 | #define CR_MAC_ADDR_P2 CTL_REG(0x0614) | ||
| 390 | #define CR_BSSID_P1 CTL_REG(0x0618) | ||
| 391 | #define CR_BSSID_P2 CTL_REG(0x061C) | ||
| 392 | #define CR_BCN_PLCP_CFG CTL_REG(0x0620) | ||
| 393 | #define CR_GROUP_HASH_P1 CTL_REG(0x0624) | ||
| 394 | #define CR_GROUP_HASH_P2 CTL_REG(0x0628) | ||
| 395 | #define CR_RX_TIMEOUT CTL_REG(0x062C) | ||
| 396 | |||
| 397 | /* Basic rates supported by the BSS. When producing ACK or CTS messages, the | ||
| 398 | * device will use a rate in this table that is less than or equal to the rate | ||
| 399 | * of the incoming frame which prompted the response */ | ||
| 400 | #define CR_BASIC_RATE_TBL CTL_REG(0x0630) | ||
| 401 | #define CR_RATE_1M 0x0001 /* 802.11b */ | ||
| 402 | #define CR_RATE_2M 0x0002 /* 802.11b */ | ||
| 403 | #define CR_RATE_5_5M 0x0004 /* 802.11b */ | ||
| 404 | #define CR_RATE_11M 0x0008 /* 802.11b */ | ||
| 405 | #define CR_RATE_6M 0x0100 /* 802.11g */ | ||
| 406 | #define CR_RATE_9M 0x0200 /* 802.11g */ | ||
| 407 | #define CR_RATE_12M 0x0400 /* 802.11g */ | ||
| 408 | #define CR_RATE_18M 0x0800 /* 802.11g */ | ||
| 409 | #define CR_RATE_24M 0x1000 /* 802.11g */ | ||
| 410 | #define CR_RATE_36M 0x2000 /* 802.11g */ | ||
| 411 | #define CR_RATE_48M 0x4000 /* 802.11g */ | ||
| 412 | #define CR_RATE_54M 0x8000 /* 802.11g */ | ||
| 413 | #define CR_RATES_80211G 0xff00 | ||
| 414 | #define CR_RATES_80211B 0x000f | ||
| 415 | |||
| 416 | /* Mandatory rates required in the BSS. When producing ACK or CTS messages, if | ||
| 417 | * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will | ||
| 418 | * look for a rate in this table that is less than or equal to the rate of | ||
| 419 | * the incoming frame. */ | ||
| 420 | #define CR_MANDATORY_RATE_TBL CTL_REG(0x0634) | ||
| 421 | #define CR_RTS_CTS_RATE CTL_REG(0x0638) | ||
| 422 | |||
| 423 | #define CR_WEP_PROTECT CTL_REG(0x063C) | ||
| 424 | #define CR_RX_THRESHOLD CTL_REG(0x0640) | ||
| 425 | |||
| 426 | /* register for controlling the LEDS */ | ||
| 427 | #define CR_LED CTL_REG(0x0644) | ||
| 428 | /* masks for controlling LEDs */ | ||
| 429 | #define LED1 0x0100 | ||
| 430 | #define LED2 0x0200 | ||
| 431 | |||
| 432 | /* Seems to indicate that the configuration is over. | ||
| 433 | */ | ||
| 434 | #define CR_AFTER_PNP CTL_REG(0x0648) | ||
| 435 | #define CR_ACK_TIME_80211 CTL_REG(0x0658) | ||
| 436 | |||
| 437 | #define CR_RX_OFFSET CTL_REG(0x065c) | ||
| 438 | |||
| 439 | #define CR_PHY_DELAY CTL_REG(0x066C) | ||
| 440 | #define CR_BCN_FIFO CTL_REG(0x0670) | ||
| 441 | #define CR_SNIFFER_ON CTL_REG(0x0674) | ||
| 442 | |||
| 443 | #define CR_ENCRYPTION_TYPE CTL_REG(0x0678) | ||
| 444 | #define NO_WEP 0 | ||
| 445 | #define WEP64 1 | ||
| 446 | #define WEP128 5 | ||
| 447 | #define WEP256 6 | ||
| 448 | #define ENC_SNIFFER 8 | ||
| 449 | |||
| 450 | #define CR_ZD1211_RETRY_MAX CTL_REG(0x067C) | ||
| 451 | |||
| 452 | #define CR_REG1 CTL_REG(0x0680) | ||
| 453 | /* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical | ||
| 454 | * registers, so one could argue it is a LOCK bit. But calling it | ||
| 455 | * LOCK_PHY_REGS makes it confusing. | ||
| 456 | */ | ||
| 457 | #define UNLOCK_PHY_REGS 0x0080 | ||
| 458 | |||
| 459 | #define CR_DEVICE_STATE CTL_REG(0x0684) | ||
| 460 | #define CR_UNDERRUN_CNT CTL_REG(0x0688) | ||
| 461 | |||
| 462 | #define CR_RX_FILTER CTL_REG(0x068c) | ||
| 463 | #define RX_FILTER_ASSOC_RESPONSE 0x0002 | ||
| 464 | #define RX_FILTER_REASSOC_RESPONSE 0x0008 | ||
| 465 | #define RX_FILTER_PROBE_RESPONSE 0x0020 | ||
| 466 | #define RX_FILTER_BEACON 0x0100 | ||
| 467 | #define RX_FILTER_DISASSOC 0x0400 | ||
| 468 | #define RX_FILTER_AUTH 0x0800 | ||
| 469 | #define AP_RX_FILTER 0x0400feff | ||
| 470 | #define STA_RX_FILTER 0x0000ffff | ||
| 471 | |||
| 472 | /* Monitor mode sets filter to 0xfffff */ | ||
| 473 | |||
| 474 | #define CR_ACK_TIMEOUT_EXT CTL_REG(0x0690) | ||
| 475 | #define CR_BCN_FIFO_SEMAPHORE CTL_REG(0x0694) | ||
| 476 | #define CR_IFS_VALUE CTL_REG(0x0698) | ||
| 477 | #define CR_RX_TIME_OUT CTL_REG(0x069C) | ||
| 478 | #define CR_TOTAL_RX_FRM CTL_REG(0x06A0) | ||
| 479 | #define CR_CRC32_CNT CTL_REG(0x06A4) | ||
| 480 | #define CR_CRC16_CNT CTL_REG(0x06A8) | ||
| 481 | #define CR_DECRYPTION_ERR_UNI CTL_REG(0x06AC) | ||
| 482 | #define CR_RX_FIFO_OVERRUN CTL_REG(0x06B0) | ||
| 483 | |||
| 484 | #define CR_DECRYPTION_ERR_MUL CTL_REG(0x06BC) | ||
| 485 | |||
| 486 | #define CR_NAV_CNT CTL_REG(0x06C4) | ||
| 487 | #define CR_NAV_CCA CTL_REG(0x06C8) | ||
| 488 | #define CR_RETRY_CNT CTL_REG(0x06CC) | ||
| 489 | |||
| 490 | #define CR_READ_TCB_ADDR CTL_REG(0x06E8) | ||
| 491 | #define CR_READ_RFD_ADDR CTL_REG(0x06EC) | ||
| 492 | #define CR_CWMIN_CWMAX CTL_REG(0x06F0) | ||
| 493 | #define CR_TOTAL_TX_FRM CTL_REG(0x06F4) | ||
| 494 | |||
| 495 | /* CAM: Continuous Access Mode (power management) */ | ||
| 496 | #define CR_CAM_MODE CTL_REG(0x0700) | ||
| 497 | #define CR_CAM_ROLL_TB_LOW CTL_REG(0x0704) | ||
| 498 | #define CR_CAM_ROLL_TB_HIGH CTL_REG(0x0708) | ||
| 499 | #define CR_CAM_ADDRESS CTL_REG(0x070C) | ||
| 500 | #define CR_CAM_DATA CTL_REG(0x0710) | ||
| 501 | |||
| 502 | #define CR_ROMDIR CTL_REG(0x0714) | ||
| 503 | |||
| 504 | #define CR_DECRY_ERR_FLG_LOW CTL_REG(0x0714) | ||
| 505 | #define CR_DECRY_ERR_FLG_HIGH CTL_REG(0x0718) | ||
| 506 | |||
| 507 | #define CR_WEPKEY0 CTL_REG(0x0720) | ||
| 508 | #define CR_WEPKEY1 CTL_REG(0x0724) | ||
| 509 | #define CR_WEPKEY2 CTL_REG(0x0728) | ||
| 510 | #define CR_WEPKEY3 CTL_REG(0x072C) | ||
| 511 | #define CR_WEPKEY4 CTL_REG(0x0730) | ||
| 512 | #define CR_WEPKEY5 CTL_REG(0x0734) | ||
| 513 | #define CR_WEPKEY6 CTL_REG(0x0738) | ||
| 514 | #define CR_WEPKEY7 CTL_REG(0x073C) | ||
| 515 | #define CR_WEPKEY8 CTL_REG(0x0740) | ||
| 516 | #define CR_WEPKEY9 CTL_REG(0x0744) | ||
| 517 | #define CR_WEPKEY10 CTL_REG(0x0748) | ||
| 518 | #define CR_WEPKEY11 CTL_REG(0x074C) | ||
| 519 | #define CR_WEPKEY12 CTL_REG(0x0750) | ||
| 520 | #define CR_WEPKEY13 CTL_REG(0x0754) | ||
| 521 | #define CR_WEPKEY14 CTL_REG(0x0758) | ||
| 522 | #define CR_WEPKEY15 CTL_REG(0x075c) | ||
| 523 | #define CR_TKIP_MODE CTL_REG(0x0760) | ||
| 524 | |||
| 525 | #define CR_EEPROM_PROTECT0 CTL_REG(0x0758) | ||
| 526 | #define CR_EEPROM_PROTECT1 CTL_REG(0x075C) | ||
| 527 | |||
| 528 | #define CR_DBG_FIFO_RD CTL_REG(0x0800) | ||
| 529 | #define CR_DBG_SELECT CTL_REG(0x0804) | ||
| 530 | #define CR_FIFO_Length CTL_REG(0x0808) | ||
| 531 | |||
| 532 | |||
| 533 | #define CR_RSSI_MGC CTL_REG(0x0810) | ||
| 534 | |||
| 535 | #define CR_PON CTL_REG(0x0818) | ||
| 536 | #define CR_RX_ON CTL_REG(0x081C) | ||
| 537 | #define CR_TX_ON CTL_REG(0x0820) | ||
| 538 | #define CR_CHIP_EN CTL_REG(0x0824) | ||
| 539 | #define CR_LO_SW CTL_REG(0x0828) | ||
| 540 | #define CR_TXRX_SW CTL_REG(0x082C) | ||
| 541 | #define CR_S_MD CTL_REG(0x0830) | ||
| 542 | |||
| 543 | #define CR_USB_DEBUG_PORT CTL_REG(0x0888) | ||
| 544 | |||
| 545 | #define CR_ZD1211B_TX_PWR_CTL1 CTL_REG(0x0b00) | ||
| 546 | #define CR_ZD1211B_TX_PWR_CTL2 CTL_REG(0x0b04) | ||
| 547 | #define CR_ZD1211B_TX_PWR_CTL3 CTL_REG(0x0b08) | ||
| 548 | #define CR_ZD1211B_TX_PWR_CTL4 CTL_REG(0x0b0c) | ||
| 549 | #define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10) | ||
| 550 | #define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14) | ||
| 551 | #define CR_ZD1211B_TXOP CTL_REG(0x0b20) | ||
| 552 | #define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28) | ||
| 553 | |||
| 554 | #define CWIN_SIZE 0x007f043f | ||
| 555 | |||
| 556 | |||
| 557 | #define HWINT_ENABLED 0x004f0000 | ||
| 558 | #define HWINT_DISABLED 0 | ||
| 559 | |||
| 560 | #define E2P_PWR_INT_GUARD 8 | ||
| 561 | #define E2P_CHANNEL_COUNT 14 | ||
| 562 | |||
| 563 | /* If you compare this addresses with the ZYDAS orignal driver, please notify | ||
| 564 | * that we use word mapping for the EEPROM. | ||
| 565 | */ | ||
| 566 | |||
| 567 | /* | ||
| 568 | * Upper 16 bit contains the regulatory domain. | ||
| 569 | */ | ||
| 570 | #define E2P_SUBID E2P_REG(0x00) | ||
| 571 | #define E2P_POD E2P_REG(0x02) | ||
| 572 | #define E2P_MAC_ADDR_P1 E2P_REG(0x04) | ||
| 573 | #define E2P_MAC_ADDR_P2 E2P_REG(0x06) | ||
| 574 | #define E2P_PWR_CAL_VALUE1 E2P_REG(0x08) | ||
| 575 | #define E2P_PWR_CAL_VALUE2 E2P_REG(0x0a) | ||
| 576 | #define E2P_PWR_CAL_VALUE3 E2P_REG(0x0c) | ||
| 577 | #define E2P_PWR_CAL_VALUE4 E2P_REG(0x0e) | ||
| 578 | #define E2P_PWR_INT_VALUE1 E2P_REG(0x10) | ||
| 579 | #define E2P_PWR_INT_VALUE2 E2P_REG(0x12) | ||
| 580 | #define E2P_PWR_INT_VALUE3 E2P_REG(0x14) | ||
| 581 | #define E2P_PWR_INT_VALUE4 E2P_REG(0x16) | ||
| 582 | |||
| 583 | /* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30) | ||
| 584 | * also only 11 channels. */ | ||
| 585 | #define E2P_ALLOWED_CHANNEL E2P_REG(0x18) | ||
| 586 | |||
| 587 | #define E2P_PHY_REG E2P_REG(0x1a) | ||
| 588 | #define E2P_DEVICE_VER E2P_REG(0x20) | ||
| 589 | #define E2P_36M_CAL_VALUE1 E2P_REG(0x28) | ||
| 590 | #define E2P_36M_CAL_VALUE2 E2P_REG(0x2a) | ||
| 591 | #define E2P_36M_CAL_VALUE3 E2P_REG(0x2c) | ||
| 592 | #define E2P_36M_CAL_VALUE4 E2P_REG(0x2e) | ||
| 593 | #define E2P_11A_INT_VALUE1 E2P_REG(0x30) | ||
| 594 | #define E2P_11A_INT_VALUE2 E2P_REG(0x32) | ||
| 595 | #define E2P_11A_INT_VALUE3 E2P_REG(0x34) | ||
| 596 | #define E2P_11A_INT_VALUE4 E2P_REG(0x36) | ||
| 597 | #define E2P_48M_CAL_VALUE1 E2P_REG(0x38) | ||
| 598 | #define E2P_48M_CAL_VALUE2 E2P_REG(0x3a) | ||
| 599 | #define E2P_48M_CAL_VALUE3 E2P_REG(0x3c) | ||
| 600 | #define E2P_48M_CAL_VALUE4 E2P_REG(0x3e) | ||
| 601 | #define E2P_48M_INT_VALUE1 E2P_REG(0x40) | ||
| 602 | #define E2P_48M_INT_VALUE2 E2P_REG(0x42) | ||
| 603 | #define E2P_48M_INT_VALUE3 E2P_REG(0x44) | ||
| 604 | #define E2P_48M_INT_VALUE4 E2P_REG(0x46) | ||
| 605 | #define E2P_54M_CAL_VALUE1 E2P_REG(0x48) /* ??? */ | ||
| 606 | #define E2P_54M_CAL_VALUE2 E2P_REG(0x4a) | ||
| 607 | #define E2P_54M_CAL_VALUE3 E2P_REG(0x4c) | ||
| 608 | #define E2P_54M_CAL_VALUE4 E2P_REG(0x4e) | ||
| 609 | #define E2P_54M_INT_VALUE1 E2P_REG(0x50) | ||
| 610 | #define E2P_54M_INT_VALUE2 E2P_REG(0x52) | ||
| 611 | #define E2P_54M_INT_VALUE3 E2P_REG(0x54) | ||
| 612 | #define E2P_54M_INT_VALUE4 E2P_REG(0x56) | ||
| 613 | |||
| 614 | /* All 16 bit values */ | ||
| 615 | #define FW_FIRMWARE_VER FW_REG(0) | ||
| 616 | /* non-zero if USB high speed connection */ | ||
| 617 | #define FW_USB_SPEED FW_REG(1) | ||
| 618 | #define FW_FIX_TX_RATE FW_REG(2) | ||
| 619 | /* Seems to be able to control LEDs over the firmware */ | ||
| 620 | #define FW_LINK_STATUS FW_REG(3) | ||
| 621 | #define FW_SOFT_RESET FW_REG(4) | ||
| 622 | #define FW_FLASH_CHK FW_REG(5) | ||
| 623 | |||
| 624 | enum { | ||
| 625 | CR_BASE_OFFSET = 0x9000, | ||
| 626 | FW_START_OFFSET = 0xee00, | ||
| 627 | FW_BASE_ADDR_OFFSET = FW_START_OFFSET + 0x1d, | ||
| 628 | EEPROM_START_OFFSET = 0xf800, | ||
| 629 | EEPROM_SIZE = 0x800, /* words */ | ||
| 630 | LOAD_CODE_SIZE = 0xe, /* words */ | ||
| 631 | LOAD_VECT_SIZE = 0x10000 - 0xfff7, /* words */ | ||
| 632 | EEPROM_REGS_OFFSET = LOAD_CODE_SIZE + LOAD_VECT_SIZE, | ||
| 633 | E2P_BASE_OFFSET = EEPROM_START_OFFSET + | ||
| 634 | EEPROM_REGS_OFFSET, | ||
| 635 | }; | ||
| 636 | |||
| 637 | #define FW_REG_TABLE_ADDR USB_ADDR(FW_START_OFFSET + 0x1d) | ||
| 638 | |||
| 639 | enum { | ||
| 640 | /* indices for ofdm_cal_values */ | ||
| 641 | OFDM_36M_INDEX = 0, | ||
| 642 | OFDM_48M_INDEX = 1, | ||
| 643 | OFDM_54M_INDEX = 2, | ||
| 644 | }; | ||
| 645 | |||
| 646 | struct zd_chip { | ||
| 647 | struct zd_usb usb; | ||
| 648 | struct zd_rf rf; | ||
| 649 | struct mutex mutex; | ||
| 650 | u8 e2p_mac[ETH_ALEN]; | ||
| 651 | /* EepSetPoint in the vendor driver */ | ||
| 652 | u8 pwr_cal_values[E2P_CHANNEL_COUNT]; | ||
| 653 | /* integration values in the vendor driver */ | ||
| 654 | u8 pwr_int_values[E2P_CHANNEL_COUNT]; | ||
| 655 | /* SetPointOFDM in the vendor driver */ | ||
| 656 | u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT]; | ||
| 657 | u8 pa_type:4, patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1, | ||
| 658 | is_zd1211b:1; | ||
| 659 | }; | ||
| 660 | |||
| 661 | static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb) | ||
| 662 | { | ||
| 663 | return container_of(usb, struct zd_chip, usb); | ||
| 664 | } | ||
| 665 | |||
| 666 | static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf) | ||
| 667 | { | ||
| 668 | return container_of(rf, struct zd_chip, rf); | ||
| 669 | } | ||
| 670 | |||
| 671 | #define zd_chip_dev(chip) (&(chip)->usb.intf->dev) | ||
| 672 | |||
| 673 | void zd_chip_init(struct zd_chip *chip, | ||
| 674 | struct net_device *netdev, | ||
| 675 | struct usb_interface *intf); | ||
| 676 | void zd_chip_clear(struct zd_chip *chip); | ||
| 677 | int zd_chip_init_hw(struct zd_chip *chip, u8 device_type); | ||
| 678 | int zd_chip_reset(struct zd_chip *chip); | ||
| 679 | |||
| 680 | static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values, | ||
| 681 | const zd_addr_t *addresses, | ||
| 682 | unsigned int count) | ||
| 683 | { | ||
| 684 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | ||
| 685 | return zd_usb_ioread16v(&chip->usb, values, addresses, count); | ||
| 686 | } | ||
| 687 | |||
| 688 | static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value, | ||
| 689 | const zd_addr_t addr) | ||
| 690 | { | ||
| 691 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | ||
| 692 | return zd_usb_ioread16(&chip->usb, value, addr); | ||
| 693 | } | ||
| 694 | |||
| 695 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, | ||
| 696 | const zd_addr_t *addresses, unsigned int count); | ||
| 697 | |||
| 698 | static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value, | ||
| 699 | const zd_addr_t addr) | ||
| 700 | { | ||
| 701 | return zd_ioread32v_locked(chip, value, (const zd_addr_t *)&addr, 1); | ||
| 702 | } | ||
| 703 | |||
| 704 | static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value, | ||
| 705 | zd_addr_t addr) | ||
| 706 | { | ||
| 707 | struct zd_ioreq16 ioreq; | ||
| 708 | |||
| 709 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | ||
| 710 | ioreq.addr = addr; | ||
| 711 | ioreq.value = value; | ||
| 712 | |||
| 713 | return zd_usb_iowrite16v(&chip->usb, &ioreq, 1); | ||
| 714 | } | ||
| 715 | |||
| 716 | int zd_iowrite16a_locked(struct zd_chip *chip, | ||
| 717 | const struct zd_ioreq16 *ioreqs, unsigned int count); | ||
| 718 | |||
| 719 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | ||
| 720 | unsigned int count); | ||
| 721 | |||
| 722 | static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value, | ||
| 723 | zd_addr_t addr) | ||
| 724 | { | ||
| 725 | struct zd_ioreq32 ioreq; | ||
| 726 | |||
| 727 | ioreq.addr = addr; | ||
| 728 | ioreq.value = value; | ||
| 729 | |||
| 730 | return _zd_iowrite32v_locked(chip, &ioreq, 1); | ||
| 731 | } | ||
| 732 | |||
| 733 | int zd_iowrite32a_locked(struct zd_chip *chip, | ||
| 734 | const struct zd_ioreq32 *ioreqs, unsigned int count); | ||
| 735 | |||
| 736 | static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits) | ||
| 737 | { | ||
| 738 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | ||
| 739 | return zd_usb_rfwrite(&chip->usb, value, bits); | ||
| 740 | } | ||
| 741 | |||
| 742 | int zd_rfwritev_locked(struct zd_chip *chip, | ||
| 743 | const u32* values, unsigned int count, u8 bits); | ||
| 744 | |||
| 745 | /* Locking functions for reading and writing registers. | ||
| 746 | * The different parameters are intentional. | ||
| 747 | */ | ||
| 748 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value); | ||
| 749 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value); | ||
| 750 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value); | ||
| 751 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value); | ||
| 752 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, | ||
| 753 | u32 *values, unsigned int count); | ||
| 754 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | ||
| 755 | unsigned int count); | ||
| 756 | |||
| 757 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel); | ||
| 758 | static inline u8 _zd_chip_get_channel(struct zd_chip *chip) | ||
| 759 | { | ||
| 760 | return chip->rf.channel; | ||
| 761 | } | ||
| 762 | u8 zd_chip_get_channel(struct zd_chip *chip); | ||
| 763 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain); | ||
| 764 | void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr); | ||
| 765 | int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr); | ||
| 766 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr); | ||
| 767 | int zd_chip_switch_radio_on(struct zd_chip *chip); | ||
| 768 | int zd_chip_switch_radio_off(struct zd_chip *chip); | ||
| 769 | int zd_chip_enable_int(struct zd_chip *chip); | ||
| 770 | void zd_chip_disable_int(struct zd_chip *chip); | ||
| 771 | int zd_chip_enable_rx(struct zd_chip *chip); | ||
| 772 | void zd_chip_disable_rx(struct zd_chip *chip); | ||
| 773 | int zd_chip_enable_hwint(struct zd_chip *chip); | ||
| 774 | int zd_chip_disable_hwint(struct zd_chip *chip); | ||
| 775 | |||
| 776 | static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type) | ||
| 777 | { | ||
| 778 | return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type); | ||
| 779 | } | ||
| 780 | |||
| 781 | static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type) | ||
| 782 | { | ||
| 783 | return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type); | ||
| 784 | } | ||
| 785 | |||
| 786 | static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates) | ||
| 787 | { | ||
| 788 | return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates); | ||
| 789 | } | ||
| 790 | |||
| 791 | int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates); | ||
| 792 | |||
| 793 | static inline int zd_chip_set_rx_filter(struct zd_chip *chip, u32 filter) | ||
| 794 | { | ||
| 795 | return zd_iowrite32(chip, CR_RX_FILTER, filter); | ||
| 796 | } | ||
| 797 | |||
| 798 | int zd_chip_lock_phy_regs(struct zd_chip *chip); | ||
| 799 | int zd_chip_unlock_phy_regs(struct zd_chip *chip); | ||
| 800 | |||
| 801 | enum led_status { | ||
| 802 | LED_OFF = 0, | ||
| 803 | LED_ON = 1, | ||
| 804 | LED_FLIP = 2, | ||
| 805 | LED_STATUS = 3, | ||
| 806 | }; | ||
| 807 | |||
| 808 | int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status); | ||
| 809 | int zd_chip_led_flip(struct zd_chip *chip, int led, | ||
| 810 | const unsigned int *phases_msecs, unsigned int count); | ||
| 811 | |||
| 812 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval); | ||
| 813 | |||
| 814 | static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval) | ||
| 815 | { | ||
| 816 | return zd_ioread32(chip, CR_BCN_INTERVAL, interval); | ||
| 817 | } | ||
| 818 | |||
| 819 | struct rx_status; | ||
| 820 | |||
| 821 | u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, | ||
| 822 | const struct rx_status *status); | ||
| 823 | u8 zd_rx_strength_percent(u8 rssi); | ||
| 824 | |||
| 825 | u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status); | ||
| 826 | |||
| 827 | #endif /* _ZD_CHIP_H */ | ||