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diff --git a/drivers/net/wireless/wl12xx/wl1251_reg.h b/drivers/net/wireless/wl12xx/wl1251_reg.h
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1/*
2 * This file is part of wl12xx
3 *
4 * Copyright (c) 1998-2007 Texas Instruments Incorporated
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Contact: Kalle Valo <kalle.valo@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __REG_H__
26#define __REG_H__
27
28#include <linux/bitops.h>
29
30#define REGISTERS_BASE 0x00300000
31#define DRPW_BASE 0x00310000
32
33#define REGISTERS_DOWN_SIZE 0x00008800
34#define REGISTERS_WORK_SIZE 0x0000b000
35
36#define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
37
38/* ELP register commands */
39#define ELPCTRL_WAKE_UP 0x1
40#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
41#define ELPCTRL_SLEEP 0x0
42/* ELP WLAN_READY bit */
43#define ELPCTRL_WLAN_READY 0x2
44
45/*
46 * Interrupt registers.
47 * 64 bit interrupt sources registers ws ced.
48 * sme interupts were removed and new ones were added.
49 * Order was changed.
50 */
51#define FIQ_MASK (REGISTERS_BASE + 0x0400)
52#define FIQ_MASK_L (REGISTERS_BASE + 0x0400)
53#define FIQ_MASK_H (REGISTERS_BASE + 0x0404)
54#define FIQ_MASK_SET (REGISTERS_BASE + 0x0408)
55#define FIQ_MASK_SET_L (REGISTERS_BASE + 0x0408)
56#define FIQ_MASK_SET_H (REGISTERS_BASE + 0x040C)
57#define FIQ_MASK_CLR (REGISTERS_BASE + 0x0410)
58#define FIQ_MASK_CLR_L (REGISTERS_BASE + 0x0410)
59#define FIQ_MASK_CLR_H (REGISTERS_BASE + 0x0414)
60#define IRQ_MASK (REGISTERS_BASE + 0x0418)
61#define IRQ_MASK_L (REGISTERS_BASE + 0x0418)
62#define IRQ_MASK_H (REGISTERS_BASE + 0x041C)
63#define IRQ_MASK_SET (REGISTERS_BASE + 0x0420)
64#define IRQ_MASK_SET_L (REGISTERS_BASE + 0x0420)
65#define IRQ_MASK_SET_H (REGISTERS_BASE + 0x0424)
66#define IRQ_MASK_CLR (REGISTERS_BASE + 0x0428)
67#define IRQ_MASK_CLR_L (REGISTERS_BASE + 0x0428)
68#define IRQ_MASK_CLR_H (REGISTERS_BASE + 0x042C)
69#define ECPU_MASK (REGISTERS_BASE + 0x0448)
70#define FIQ_STS_L (REGISTERS_BASE + 0x044C)
71#define FIQ_STS_H (REGISTERS_BASE + 0x0450)
72#define IRQ_STS_L (REGISTERS_BASE + 0x0454)
73#define IRQ_STS_H (REGISTERS_BASE + 0x0458)
74#define INT_STS_ND (REGISTERS_BASE + 0x0464)
75#define INT_STS_RAW_L (REGISTERS_BASE + 0x0464)
76#define INT_STS_RAW_H (REGISTERS_BASE + 0x0468)
77#define INT_STS_CLR (REGISTERS_BASE + 0x04B4)
78#define INT_STS_CLR_L (REGISTERS_BASE + 0x04B4)
79#define INT_STS_CLR_H (REGISTERS_BASE + 0x04B8)
80#define INT_ACK (REGISTERS_BASE + 0x046C)
81#define INT_ACK_L (REGISTERS_BASE + 0x046C)
82#define INT_ACK_H (REGISTERS_BASE + 0x0470)
83#define INT_TRIG (REGISTERS_BASE + 0x0474)
84#define INT_TRIG_L (REGISTERS_BASE + 0x0474)
85#define INT_TRIG_H (REGISTERS_BASE + 0x0478)
86#define HOST_STS_L (REGISTERS_BASE + 0x045C)
87#define HOST_STS_H (REGISTERS_BASE + 0x0460)
88#define HOST_MASK (REGISTERS_BASE + 0x0430)
89#define HOST_MASK_L (REGISTERS_BASE + 0x0430)
90#define HOST_MASK_H (REGISTERS_BASE + 0x0434)
91#define HOST_MASK_SET (REGISTERS_BASE + 0x0438)
92#define HOST_MASK_SET_L (REGISTERS_BASE + 0x0438)
93#define HOST_MASK_SET_H (REGISTERS_BASE + 0x043C)
94#define HOST_MASK_CLR (REGISTERS_BASE + 0x0440)
95#define HOST_MASK_CLR_L (REGISTERS_BASE + 0x0440)
96#define HOST_MASK_CLR_H (REGISTERS_BASE + 0x0444)
97
98/* Host Interrupts*/
99#define HINT_MASK (REGISTERS_BASE + 0x0494)
100#define HINT_MASK_SET (REGISTERS_BASE + 0x0498)
101#define HINT_MASK_CLR (REGISTERS_BASE + 0x049C)
102#define HINT_STS_ND_MASKED (REGISTERS_BASE + 0x04A0)
103/*1150 spec calls this HINT_STS_RAW*/
104#define HINT_STS_ND (REGISTERS_BASE + 0x04B0)
105#define HINT_STS_CLR (REGISTERS_BASE + 0x04A4)
106#define HINT_ACK (REGISTERS_BASE + 0x04A8)
107#define HINT_TRIG (REGISTERS_BASE + 0x04AC)
108
109/* Device Configuration registers*/
110#define SOR_CFG (REGISTERS_BASE + 0x0800)
111#define ECPU_CTRL (REGISTERS_BASE + 0x0804)
112#define HI_CFG (REGISTERS_BASE + 0x0808)
113#define EE_START (REGISTERS_BASE + 0x080C)
114
115#define CHIP_ID_B (REGISTERS_BASE + 0x5674)
116
117#define CHIP_ID_1251_PG10 (0x7010101)
118#define CHIP_ID_1251_PG11 (0x7020101)
119#define CHIP_ID_1251_PG12 (0x7030101)
120
121#define ENABLE (REGISTERS_BASE + 0x5450)
122
123/* Power Management registers */
124#define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
125#define ELP_CMD (REGISTERS_BASE + 0x5808)
126#define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
127#define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
128#define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
129
130#define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
131
132/* Scratch Pad registers*/
133#define SCR_PAD0 (REGISTERS_BASE + 0x5608)
134#define SCR_PAD1 (REGISTERS_BASE + 0x560C)
135#define SCR_PAD2 (REGISTERS_BASE + 0x5610)
136#define SCR_PAD3 (REGISTERS_BASE + 0x5614)
137#define SCR_PAD4 (REGISTERS_BASE + 0x5618)
138#define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
139#define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
140#define SCR_PAD5 (REGISTERS_BASE + 0x5624)
141#define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
142#define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
143#define SCR_PAD6 (REGISTERS_BASE + 0x5630)
144#define SCR_PAD7 (REGISTERS_BASE + 0x5634)
145#define SCR_PAD8 (REGISTERS_BASE + 0x5638)
146#define SCR_PAD9 (REGISTERS_BASE + 0x563C)
147
148/* Spare registers*/
149#define SPARE_A1 (REGISTERS_BASE + 0x0994)
150#define SPARE_A2 (REGISTERS_BASE + 0x0998)
151#define SPARE_A3 (REGISTERS_BASE + 0x099C)
152#define SPARE_A4 (REGISTERS_BASE + 0x09A0)
153#define SPARE_A5 (REGISTERS_BASE + 0x09A4)
154#define SPARE_A6 (REGISTERS_BASE + 0x09A8)
155#define SPARE_A7 (REGISTERS_BASE + 0x09AC)
156#define SPARE_A8 (REGISTERS_BASE + 0x09B0)
157#define SPARE_B1 (REGISTERS_BASE + 0x5420)
158#define SPARE_B2 (REGISTERS_BASE + 0x5424)
159#define SPARE_B3 (REGISTERS_BASE + 0x5428)
160#define SPARE_B4 (REGISTERS_BASE + 0x542C)
161#define SPARE_B5 (REGISTERS_BASE + 0x5430)
162#define SPARE_B6 (REGISTERS_BASE + 0x5434)
163#define SPARE_B7 (REGISTERS_BASE + 0x5438)
164#define SPARE_B8 (REGISTERS_BASE + 0x543C)
165
166enum wl12xx_acx_int_reg {
167 ACX_REG_INTERRUPT_TRIG,
168 ACX_REG_INTERRUPT_TRIG_H,
169
170/*=============================================
171 Host Interrupt Mask Register - 32bit (RW)
172 ------------------------------------------
173 Setting a bit in this register masks the
174 corresponding interrupt to the host.
175 0 - RX0 - Rx first dubble buffer Data Interrupt
176 1 - TXD - Tx Data Interrupt
177 2 - TXXFR - Tx Transfer Interrupt
178 3 - RX1 - Rx second dubble buffer Data Interrupt
179 4 - RXXFR - Rx Transfer Interrupt
180 5 - EVENT_A - Event Mailbox interrupt
181 6 - EVENT_B - Event Mailbox interrupt
182 7 - WNONHST - Wake On Host Interrupt
183 8 - TRACE_A - Debug Trace interrupt
184 9 - TRACE_B - Debug Trace interrupt
185 10 - CDCMP - Command Complete Interrupt
186 11 -
187 12 -
188 13 -
189 14 - ICOMP - Initialization Complete Interrupt
190 16 - SG SE - Soft Gemini - Sense enable interrupt
191 17 - SG SD - Soft Gemini - Sense disable interrupt
192 18 - -
193 19 - -
194 20 - -
195 21- -
196 Default: 0x0001
197*==============================================*/
198 ACX_REG_INTERRUPT_MASK,
199
200/*=============================================
201 Host Interrupt Mask Set 16bit, (Write only)
202 ------------------------------------------
203 Setting a bit in this register sets
204 the corresponding bin in ACX_HINT_MASK register
205 without effecting the mask
206 state of other bits (0 = no effect).
207==============================================*/
208 ACX_REG_HINT_MASK_SET,
209
210/*=============================================
211 Host Interrupt Mask Clear 16bit,(Write only)
212 ------------------------------------------
213 Setting a bit in this register clears
214 the corresponding bin in ACX_HINT_MASK register
215 without effecting the mask
216 state of other bits (0 = no effect).
217=============================================*/
218 ACX_REG_HINT_MASK_CLR,
219
220/*=============================================
221 Host Interrupt Status Nondestructive Read
222 16bit,(Read only)
223 ------------------------------------------
224 The host can read this register to determine
225 which interrupts are active.
226 Reading this register doesn't
227 effect its content.
228=============================================*/
229 ACX_REG_INTERRUPT_NO_CLEAR,
230
231/*=============================================
232 Host Interrupt Status Clear on Read Register
233 16bit,(Read only)
234 ------------------------------------------
235 The host can read this register to determine
236 which interrupts are active.
237 Reading this register clears it,
238 thus making all interrupts inactive.
239==============================================*/
240 ACX_REG_INTERRUPT_CLEAR,
241
242/*=============================================
243 Host Interrupt Acknowledge Register
244 16bit,(Write only)
245 ------------------------------------------
246 The host can set individual bits in this
247 register to clear (acknowledge) the corresp.
248 interrupt status bits in the HINT_STS_CLR and
249 HINT_STS_ND registers, thus making the
250 assotiated interrupt inactive. (0-no effect)
251==============================================*/
252 ACX_REG_INTERRUPT_ACK,
253
254/*===============================================
255 Host Software Reset - 32bit RW
256 ------------------------------------------
257 [31:1] Reserved
258 0 SOFT_RESET Soft Reset - When this bit is set,
259 it holds the Wlan hardware in a soft reset state.
260 This reset disables all MAC and baseband processor
261 clocks except the CardBus/PCI interface clock.
262 It also initializes all MAC state machines except
263 the host interface. It does not reload the
264 contents of the EEPROM. When this bit is cleared
265 (not self-clearing), the Wlan hardware
266 exits the software reset state.
267===============================================*/
268 ACX_REG_SLV_SOFT_RESET,
269
270/*===============================================
271 EEPROM Burst Read Start - 32bit RW
272 ------------------------------------------
273 [31:1] Reserved
274 0 ACX_EE_START - EEPROM Burst Read Start 0
275 Setting this bit starts a burst read from
276 the external EEPROM.
277 If this bit is set (after reset) before an EEPROM read/write,
278 the burst read starts at EEPROM address 0.
279 Otherwise, it starts at the address
280 following the address of the previous access.
281 TheWlan hardware hardware clears this bit automatically.
282
283 Default: 0x00000000
284*================================================*/
285 ACX_REG_EE_START,
286
287/* Embedded ARM CPU Control */
288
289/*===============================================
290 Halt eCPU - 32bit RW
291 ------------------------------------------
292 0 HALT_ECPU Halt Embedded CPU - This bit is the
293 compliment of bit 1 (MDATA2) in the SOR_CFG register.
294 During a hardware reset, this bit holds
295 the inverse of MDATA2.
296 When downloading firmware from the host,
297 set this bit (pull down MDATA2).
298 The host clears this bit after downloading the firmware into
299 zero-wait-state SSRAM.
300 When loading firmware from Flash, clear this bit (pull up MDATA2)
301 so that the eCPU can run the bootloader code in Flash
302 HALT_ECPU eCPU State
303 --------------------
304 1 halt eCPU
305 0 enable eCPU
306 ===============================================*/
307 ACX_REG_ECPU_CONTROL,
308
309 ACX_REG_TABLE_LEN
310};
311
312#define ACX_SLV_SOFT_RESET_BIT BIT(1)
313#define ACX_REG_EEPROM_START_BIT BIT(1)
314
315/* Command/Information Mailbox Pointers */
316
317/*===============================================
318 Command Mailbox Pointer - 32bit RW
319 ------------------------------------------
320 This register holds the start address of
321 the command mailbox located in the Wlan hardware memory.
322 The host must read this pointer after a reset to
323 find the location of the command mailbox.
324 The Wlan hardware initializes the command mailbox
325 pointer with the default address of the command mailbox.
326 The command mailbox pointer is not valid until after
327 the host receives the Init Complete interrupt from
328 the Wlan hardware.
329 ===============================================*/
330#define REG_COMMAND_MAILBOX_PTR (SCR_PAD0)
331
332/*===============================================
333 Information Mailbox Pointer - 32bit RW
334 ------------------------------------------
335 This register holds the start address of
336 the information mailbox located in the Wlan hardware memory.
337 The host must read this pointer after a reset to find
338 the location of the information mailbox.
339 The Wlan hardware initializes the information mailbox pointer
340 with the default address of the information mailbox.
341 The information mailbox pointer is not valid
342 until after the host receives the Init Complete interrupt from
343 the Wlan hardware.
344 ===============================================*/
345#define REG_EVENT_MAILBOX_PTR (SCR_PAD1)
346
347
348/* Misc */
349
350#define REG_ENABLE_TX_RX (ENABLE)
351/*
352 * Rx configuration (filter) information element
353 * ---------------------------------------------
354 */
355#define REG_RX_CONFIG (RX_CFG)
356#define REG_RX_FILTER (RX_FILTER_CFG)
357
358
359#define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002
360
361/* promiscuous - receives all valid frames */
362#define RX_CFG_PROMISCUOUS 0x0008
363
364/* receives frames from any BSSID */
365#define RX_CFG_BSSID 0x0020
366
367/* receives frames destined to any MAC address */
368#define RX_CFG_MAC 0x0010
369
370#define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010
371#define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000
372#define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020
373#define RX_CFG_ENABLE_ANY_BSSID 0x0000
374
375/* discards all broadcast frames */
376#define RX_CFG_DISABLE_BCAST 0x0200
377
378#define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400
379#define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800
380#define RX_CFG_COPY_RX_STATUS 0x2000
381#define RX_CFG_TSF 0x10000
382
383#define RX_CONFIG_OPTION_ANY_DST_MY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
384 RX_CFG_ENABLE_ONLY_MY_BSSID)
385
386#define RX_CONFIG_OPTION_MY_DST_ANY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
387 | RX_CFG_ENABLE_ANY_BSSID)
388
389#define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
390 RX_CFG_ENABLE_ANY_BSSID)
391
392#define RX_CONFIG_OPTION_MY_DST_MY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
393 | RX_CFG_ENABLE_ONLY_MY_BSSID)
394
395#define RX_CONFIG_OPTION_FOR_SCAN (RX_CFG_ENABLE_PHY_HEADER_PLCP \
396 | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \
397 | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF)
398
399#define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC)
400
401#define RX_CONFIG_OPTION_FOR_JOIN (RX_CFG_ENABLE_ONLY_MY_BSSID | \
402 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
403
404#define RX_CONFIG_OPTION_FOR_IBSS_JOIN (RX_CFG_ENABLE_ONLY_MY_SSID | \
405 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
406
407#define RX_FILTER_OPTION_DEF (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
408 | CFG_RX_CTL_EN | CFG_RX_BCN_EN\
409 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
410
411#define RX_FILTER_OPTION_FILTER_ALL 0
412
413#define RX_FILTER_OPTION_DEF_PRSP_BCN (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\
414 | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN)
415
416#define RX_FILTER_OPTION_JOIN (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
417 | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\
418 | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\
419 | CFG_RX_PRSP_EN)
420
421
422/*===============================================
423 Phy regs
424 ===============================================*/
425#define ACX_PHY_ADDR_REG SBB_ADDR
426#define ACX_PHY_DATA_REG SBB_DATA
427#define ACX_PHY_CTRL_REG SBB_CTL
428#define ACX_PHY_REG_WR_MASK 0x00000001ul
429#define ACX_PHY_REG_RD_MASK 0x00000002ul
430
431
432/*===============================================
433 EEPROM Read/Write Request 32bit RW
434 ------------------------------------------
435 1 EE_READ - EEPROM Read Request 1 - Setting this bit
436 loads a single byte of data into the EE_DATA
437 register from the EEPROM location specified in
438 the EE_ADDR register.
439 The Wlan hardware hardware clears this bit automatically.
440 EE_DATA is valid when this bit is cleared.
441
442 0 EE_WRITE - EEPROM Write Request - Setting this bit
443 writes a single byte of data from the EE_DATA register into the
444 EEPROM location specified in the EE_ADDR register.
445 The Wlan hardware hardware clears this bit automatically.
446*===============================================*/
447#define ACX_EE_CTL_REG EE_CTL
448#define EE_WRITE 0x00000001ul
449#define EE_READ 0x00000002ul
450
451/*===============================================
452 EEPROM Address - 32bit RW
453 ------------------------------------------
454 This register specifies the address
455 within the EEPROM from/to which to read/write data.
456 ===============================================*/
457#define ACX_EE_ADDR_REG EE_ADDR
458
459/*===============================================
460 EEPROM Data - 32bit RW
461 ------------------------------------------
462 This register either holds the read 8 bits of
463 data from the EEPROM or the write data
464 to be written to the EEPROM.
465 ===============================================*/
466#define ACX_EE_DATA_REG EE_DATA
467
468/*===============================================
469 EEPROM Base Address - 32bit RW
470 ------------------------------------------
471 This register holds the upper nine bits
472 [23:15] of the 24-bit Wlan hardware memory
473 address for burst reads from EEPROM accesses.
474 The EEPROM provides the lower 15 bits of this address.
475 The MSB of the address from the EEPROM is ignored.
476 ===============================================*/
477#define ACX_EE_CFG EE_CFG
478
479/*===============================================
480 GPIO Output Values -32bit, RW
481 ------------------------------------------
482 [31:16] Reserved
483 [15: 0] Specify the output values (at the output driver inputs) for
484 GPIO[15:0], respectively.
485 ===============================================*/
486#define ACX_GPIO_OUT_REG GPIO_OUT
487#define ACX_MAX_GPIO_LINES 15
488
489/*===============================================
490 Contention window -32bit, RW
491 ------------------------------------------
492 [31:26] Reserved
493 [25:16] Max (0x3ff)
494 [15:07] Reserved
495 [06:00] Current contention window value - default is 0x1F
496 ===============================================*/
497#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
498#define ACX_CONT_WIND_MIN_MASK 0x0000007f
499#define ACX_CONT_WIND_MAX 0x03ff0000
500
501/*
502 * Indirect slave register/memory registers
503 * ----------------------------------------
504 */
505#define HW_SLAVE_REG_ADDR_REG 0x00000004
506#define HW_SLAVE_REG_DATA_REG 0x00000008
507#define HW_SLAVE_REG_CTRL_REG 0x0000000c
508
509#define SLAVE_AUTO_INC 0x00010000
510#define SLAVE_NO_AUTO_INC 0x00000000
511#define SLAVE_HOST_LITTLE_ENDIAN 0x00000000
512
513#define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR
514#define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA
515#define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL
516#define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL
517
518#define HW_FUNC_EVENT_INT_EN 0x8000
519#define HW_FUNC_EVENT_MASK_REG 0x00000034
520
521#define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP)
522
523/*===============================================
524 HI_CFG Interface Configuration Register Values
525 ------------------------------------------
526 ===============================================*/
527#define HI_CFG_UART_ENABLE 0x00000004
528#define HI_CFG_RST232_ENABLE 0x00000008
529#define HI_CFG_CLOCK_REQ_SELECT 0x00000010
530#define HI_CFG_HOST_INT_ENABLE 0x00000020
531#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
532#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
533#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
534#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
535#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
536
537/*
538 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile
539 * for platforms using active high interrupt level
540 */
541#ifdef USE_ACTIVE_HIGH
542#define HI_CFG_DEF_VAL \
543 (HI_CFG_UART_ENABLE | \
544 HI_CFG_RST232_ENABLE | \
545 HI_CFG_CLOCK_REQ_SELECT | \
546 HI_CFG_HOST_INT_ENABLE)
547#else
548#define HI_CFG_DEF_VAL \
549 (HI_CFG_UART_ENABLE | \
550 HI_CFG_RST232_ENABLE | \
551 HI_CFG_CLOCK_REQ_SELECT | \
552 HI_CFG_HOST_INT_ENABLE)
553
554#endif
555
556#define REF_FREQ_19_2 0
557#define REF_FREQ_26_0 1
558#define REF_FREQ_38_4 2
559#define REF_FREQ_40_0 3
560#define REF_FREQ_33_6 4
561#define REF_FREQ_NUM 5
562
563#define LUT_PARAM_INTEGER_DIVIDER 0
564#define LUT_PARAM_FRACTIONAL_DIVIDER 1
565#define LUT_PARAM_ATTN_BB 2
566#define LUT_PARAM_ALPHA_BB 3
567#define LUT_PARAM_STOP_TIME_BB 4
568#define LUT_PARAM_BB_PLL_LOOP_FILTER 5
569#define LUT_PARAM_NUM 6
570
571#define ACX_EEPROMLESS_IND_REG (SCR_PAD4)
572#define USE_EEPROM 0
573#define SOFT_RESET_MAX_TIME 1000000
574#define SOFT_RESET_STALL_TIME 1000
575#define NVS_DATA_BUNDARY_ALIGNMENT 4
576
577
578/* Firmware image load chunk size */
579#define CHUNK_SIZE 512
580
581/* Firmware image header size */
582#define FW_HDR_SIZE 8
583
584#define ECPU_CONTROL_HALT 0x00000101
585
586
587/******************************************************************************
588
589 CHANNELS, BAND & REG DOMAINS definitions
590
591******************************************************************************/
592
593
594enum {
595 RADIO_BAND_2_4GHZ = 0, /* 2.4 Ghz band */
596 RADIO_BAND_5GHZ = 1, /* 5 Ghz band */
597 RADIO_BAND_JAPAN_4_9_GHZ = 2,
598 DEFAULT_BAND = RADIO_BAND_2_4GHZ,
599 INVALID_BAND = 0xFE,
600 MAX_RADIO_BANDS = 0xFF
601};
602
603enum {
604 NO_RATE = 0,
605 RATE_1MBPS = 0x0A,
606 RATE_2MBPS = 0x14,
607 RATE_5_5MBPS = 0x37,
608 RATE_6MBPS = 0x0B,
609 RATE_9MBPS = 0x0F,
610 RATE_11MBPS = 0x6E,
611 RATE_12MBPS = 0x0A,
612 RATE_18MBPS = 0x0E,
613 RATE_22MBPS = 0xDC,
614 RATE_24MBPS = 0x09,
615 RATE_36MBPS = 0x0D,
616 RATE_48MBPS = 0x08,
617 RATE_54MBPS = 0x0C
618};
619
620enum {
621 RATE_INDEX_1MBPS = 0,
622 RATE_INDEX_2MBPS = 1,
623 RATE_INDEX_5_5MBPS = 2,
624 RATE_INDEX_6MBPS = 3,
625 RATE_INDEX_9MBPS = 4,
626 RATE_INDEX_11MBPS = 5,
627 RATE_INDEX_12MBPS = 6,
628 RATE_INDEX_18MBPS = 7,
629 RATE_INDEX_22MBPS = 8,
630 RATE_INDEX_24MBPS = 9,
631 RATE_INDEX_36MBPS = 10,
632 RATE_INDEX_48MBPS = 11,
633 RATE_INDEX_54MBPS = 12,
634 RATE_INDEX_MAX = RATE_INDEX_54MBPS,
635 MAX_RATE_INDEX,
636 INVALID_RATE_INDEX = MAX_RATE_INDEX,
637 RATE_INDEX_ENUM_MAX_SIZE = 0x7FFFFFFF
638};
639
640enum {
641 RATE_MASK_1MBPS = 0x1,
642 RATE_MASK_2MBPS = 0x2,
643 RATE_MASK_5_5MBPS = 0x4,
644 RATE_MASK_11MBPS = 0x20,
645};
646
647#define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */
648#define OFDM_RATE_BIT BIT(6)
649#define PBCC_RATE_BIT BIT(7)
650
651enum {
652 CCK_LONG = 0,
653 CCK_SHORT = SHORT_PREAMBLE_BIT,
654 PBCC_LONG = PBCC_RATE_BIT,
655 PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,
656 OFDM = OFDM_RATE_BIT
657};
658
659/******************************************************************************
660
661Transmit-Descriptor RATE-SET field definitions...
662
663Define a new "Rate-Set" for TX path that incorporates the
664Rate & Modulation info into a single 16-bit field.
665
666TxdRateSet_t:
667b15 - Indicates Preamble type (1=SHORT, 0=LONG).
668 Notes:
669 Must be LONG (0) for 1Mbps rate.
670 Does not apply (set to 0) for RevG-OFDM rates.
671b14 - Indicates PBCC encoding (1=PBCC, 0=not).
672 Notes:
673 Does not apply (set to 0) for rates 1 and 2 Mbps.
674 Does not apply (set to 0) for RevG-OFDM rates.
675b13 - Unused (set to 0).
676b12-b0 - Supported Rate indicator bits as defined below.
677
678******************************************************************************/
679
680
681#define TNETW1251_CHIP_ID_PG1_0 0x07010101
682#define TNETW1251_CHIP_ID_PG1_1 0x07020101
683#define TNETW1251_CHIP_ID_PG1_2 0x07030101
684
685/*************************************************************************
686
687 Interrupt Trigger Register (Host -> WiLink)
688
689**************************************************************************/
690
691/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
692
693/*
694 * Host Command Interrupt. Setting this bit masks
695 * the interrupt that the host issues to inform
696 * the FW that it has sent a command
697 * to the Wlan hardware Command Mailbox.
698 */
699#define INTR_TRIG_CMD BIT(0)
700
701/*
702 * Host Event Acknowlegde Interrupt. The host
703 * sets this bit to acknowledge that it received
704 * the unsolicited information from the event
705 * mailbox.
706 */
707#define INTR_TRIG_EVENT_ACK BIT(1)
708
709/*
710 * The host sets this bit to inform the Wlan
711 * FW that a TX packet is in the XFER
712 * Buffer #0.
713 */
714#define INTR_TRIG_TX_PROC0 BIT(2)
715
716/*
717 * The host sets this bit to inform the FW
718 * that it read a packet from RX XFER
719 * Buffer #0.
720 */
721#define INTR_TRIG_RX_PROC0 BIT(3)
722
723#define INTR_TRIG_DEBUG_ACK BIT(4)
724
725#define INTR_TRIG_STATE_CHANGED BIT(5)
726
727
728/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
729
730/*
731 * The host sets this bit to inform the FW
732 * that it read a packet from RX XFER
733 * Buffer #1.
734 */
735#define INTR_TRIG_RX_PROC1 BIT(17)
736
737/*
738 * The host sets this bit to inform the Wlan
739 * hardware that a TX packet is in the XFER
740 * Buffer #1.
741 */
742#define INTR_TRIG_TX_PROC1 BIT(18)
743
744#endif
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