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Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8723ae/hw.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hw.c2380
1 files changed, 2380 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
new file mode 100644
index 000000000000..0a8c03863fb2
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
@@ -0,0 +1,2380 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../regd.h"
34#include "../cam.h"
35#include "../ps.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "led.h"
43#include "hw.h"
44#include "pwrseqcmd.h"
45#include "pwrseq.h"
46#include "btc.h"
47
48static void _rtl8723ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
49 u8 set_bits, u8 clear_bits)
50{
51 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
52 struct rtl_priv *rtlpriv = rtl_priv(hw);
53
54 rtlpci->reg_bcn_ctrl_val |= set_bits;
55 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
56
57 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
58}
59
60static void _rtl8723ae_stop_tx_beacon(struct ieee80211_hw *hw)
61{
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 u8 tmp1byte;
64
65 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
66 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
68 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
69 tmp1byte &= ~(BIT(0));
70 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
71}
72
73static void _rtl8723ae_resume_tx_beacon(struct ieee80211_hw *hw)
74{
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
76 u8 tmp1byte;
77
78 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
79 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
81 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
82 tmp1byte |= BIT(1);
83 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
84}
85
86static void _rtl8723ae_enable_bcn_sufunc(struct ieee80211_hw *hw)
87{
88 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
89}
90
91static void _rtl8723ae_disable_bcn_sufunc(struct ieee80211_hw *hw)
92{
93 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
94}
95
96void rtl8723ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
97{
98 struct rtl_priv *rtlpriv = rtl_priv(hw);
99 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
100 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
101
102 switch (variable) {
103 case HW_VAR_RCR:
104 *((u32 *) (val)) = rtlpci->receive_config;
105 break;
106 case HW_VAR_RF_STATE:
107 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
108 break;
109 case HW_VAR_FWLPS_RF_ON:{
110 enum rf_pwrstate rfState;
111 u32 val_rcr;
112
113 rtlpriv->cfg->ops->get_hw_reg(hw,
114 HW_VAR_RF_STATE,
115 (u8 *) (&rfState));
116 if (rfState == ERFOFF) {
117 *((bool *) (val)) = true;
118 } else {
119 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
120 val_rcr &= 0x00070000;
121 if (val_rcr)
122 *((bool *) (val)) = false;
123 else
124 *((bool *) (val)) = true;
125 }
126 break; }
127 case HW_VAR_FW_PSMODE_STATUS:
128 *((bool *) (val)) = ppsc->fw_current_inpsmode;
129 break;
130 case HW_VAR_CORRECT_TSF:{
131 u64 tsf;
132 u32 *ptsf_low = (u32 *)&tsf;
133 u32 *ptsf_high = ((u32 *)&tsf) + 1;
134
135 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
136 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
137
138 *((u64 *) (val)) = tsf;
139
140 break; }
141 default:
142 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
143 "switch case not process\n");
144 break;
145 }
146}
147
148void rtl8723ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
149{
150 struct rtl_priv *rtlpriv = rtl_priv(hw);
151 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
152 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
153 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
154 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
155 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
156 u8 idx;
157
158 switch (variable) {
159 case HW_VAR_ETHER_ADDR:
160 for (idx = 0; idx < ETH_ALEN; idx++) {
161 rtl_write_byte(rtlpriv, (REG_MACID + idx),
162 val[idx]);
163 }
164 break;
165 case HW_VAR_BASIC_RATE:{
166 u16 rate_cfg = ((u16 *) val)[0];
167 u8 rate_index = 0;
168 rate_cfg = rate_cfg & 0x15f;
169 rate_cfg |= 0x01;
170 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
171 rtl_write_byte(rtlpriv, REG_RRSR + 1,
172 (rate_cfg >> 8) & 0xff);
173 while (rate_cfg > 0x1) {
174 rate_cfg = (rate_cfg >> 1);
175 rate_index++;
176 }
177 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
178 rate_index);
179 break; }
180 case HW_VAR_BSSID:
181 for (idx = 0; idx < ETH_ALEN; idx++) {
182 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
183 val[idx]);
184 }
185 break;
186 case HW_VAR_SIFS:
187 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
188 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
189
190 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
191 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
192
193 if (!mac->ht_enable)
194 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
195 0x0e0e);
196 else
197 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
198 *((u16 *) val));
199 break;
200 case HW_VAR_SLOT_TIME:{
201 u8 e_aci;
202
203 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
204 "HW_VAR_SLOT_TIME %x\n", val[0]);
205
206 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
207
208 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
209 rtlpriv->cfg->ops->set_hw_reg(hw,
210 HW_VAR_AC_PARAM,
211 (u8 *) (&e_aci));
212 }
213 break; }
214 case HW_VAR_ACK_PREAMBLE:{
215 u8 reg_tmp;
216 u8 short_preamble = (bool) (*(u8 *) val);
217 reg_tmp = (mac->cur_40_prime_sc) << 5;
218 if (short_preamble)
219 reg_tmp |= 0x80;
220
221 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
222 break; }
223 case HW_VAR_AMPDU_MIN_SPACE:{
224 u8 min_spacing_to_set;
225 u8 sec_min_space;
226
227 min_spacing_to_set = *((u8 *) val);
228 if (min_spacing_to_set <= 7) {
229 sec_min_space = 0;
230
231 if (min_spacing_to_set < sec_min_space)
232 min_spacing_to_set = sec_min_space;
233
234 mac->min_space_cfg = ((mac->min_space_cfg &
235 0xf8) |
236 min_spacing_to_set);
237
238 *val = min_spacing_to_set;
239
240 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
241 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
242 mac->min_space_cfg);
243
244 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
245 mac->min_space_cfg);
246 }
247 break; }
248 case HW_VAR_SHORTGI_DENSITY:{
249 u8 density_to_set;
250
251 density_to_set = *((u8 *) val);
252 mac->min_space_cfg |= (density_to_set << 3);
253
254 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
255 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
256 mac->min_space_cfg);
257
258 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
259 mac->min_space_cfg);
260
261 break; }
262 case HW_VAR_AMPDU_FACTOR:{
263 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
264 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
265 u8 factor_toset;
266 u8 *p_regtoset = NULL;
267 u8 index;
268
269 if ((pcipriv->bt_coexist.bt_coexistence) &&
270 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
271 p_regtoset = regtoset_bt;
272 else
273 p_regtoset = regtoset_normal;
274
275 factor_toset = *((u8 *) val);
276 if (factor_toset <= 3) {
277 factor_toset = (1 << (factor_toset + 2));
278 if (factor_toset > 0xf)
279 factor_toset = 0xf;
280
281 for (index = 0; index < 4; index++) {
282 if ((p_regtoset[index] & 0xf0) >
283 (factor_toset << 4))
284 p_regtoset[index] =
285 (p_regtoset[index] & 0x0f) |
286 (factor_toset << 4);
287
288 if ((p_regtoset[index] & 0x0f) >
289 factor_toset)
290 p_regtoset[index] =
291 (p_regtoset[index] & 0xf0) |
292 (factor_toset);
293
294 rtl_write_byte(rtlpriv,
295 (REG_AGGLEN_LMT + index),
296 p_regtoset[index]);
297
298 }
299
300 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
301 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
302 factor_toset);
303 }
304 break; }
305 case HW_VAR_AC_PARAM:{
306 u8 e_aci = *((u8 *) val);
307 rtl8723ae_dm_init_edca_turbo(hw);
308
309 if (rtlpci->acm_method != eAcmWay2_SW)
310 rtlpriv->cfg->ops->set_hw_reg(hw,
311 HW_VAR_ACM_CTRL,
312 (u8 *) (&e_aci));
313 break; }
314 case HW_VAR_ACM_CTRL:{
315 u8 e_aci = *((u8 *) val);
316 union aci_aifsn *p_aci_aifsn =
317 (union aci_aifsn *)(&(mac->ac[0].aifs));
318 u8 acm = p_aci_aifsn->f.acm;
319 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
320
321 acm_ctrl |= ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
322
323 if (acm) {
324 switch (e_aci) {
325 case AC0_BE:
326 acm_ctrl |= AcmHw_BeqEn;
327 break;
328 case AC2_VI:
329 acm_ctrl |= AcmHw_ViqEn;
330 break;
331 case AC3_VO:
332 acm_ctrl |= AcmHw_VoqEn;
333 break;
334 default:
335 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
336 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
337 acm);
338 break;
339 }
340 } else {
341 switch (e_aci) {
342 case AC0_BE:
343 acm_ctrl &= (~AcmHw_BeqEn);
344 break;
345 case AC2_VI:
346 acm_ctrl &= (~AcmHw_ViqEn);
347 break;
348 case AC3_VO:
349 acm_ctrl &= (~AcmHw_BeqEn);
350 break;
351 default:
352 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
353 "switch case not processed\n");
354 break;
355 }
356 }
357
358 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
359 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
360 acm_ctrl);
361 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
362 break; }
363 case HW_VAR_RCR:
364 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
365 rtlpci->receive_config = ((u32 *) (val))[0];
366 break;
367 case HW_VAR_RETRY_LIMIT:{
368 u8 retry_limit = ((u8 *) (val))[0];
369
370 rtl_write_word(rtlpriv, REG_RL,
371 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
372 retry_limit << RETRY_LIMIT_LONG_SHIFT);
373 break; }
374 case HW_VAR_DUAL_TSF_RST:
375 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
376 break;
377 case HW_VAR_EFUSE_BYTES:
378 rtlefuse->efuse_usedbytes = *((u16 *) val);
379 break;
380 case HW_VAR_EFUSE_USAGE:
381 rtlefuse->efuse_usedpercentage = *((u8 *) val);
382 break;
383 case HW_VAR_IO_CMD:
384 rtl8723ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
385 break;
386 case HW_VAR_WPA_CONFIG:
387 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
388 break;
389 case HW_VAR_SET_RPWM:{
390 u8 rpwm_val;
391
392 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
393 udelay(1);
394
395 if (rpwm_val & BIT(7)) {
396 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
397 (*(u8 *) val));
398 } else {
399 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
400 ((*(u8 *) val) | BIT(7)));
401 }
402
403 break; }
404 case HW_VAR_H2C_FW_PWRMODE:{
405 u8 psmode = (*(u8 *) val);
406
407 if (psmode != FW_PS_ACTIVE_MODE)
408 rtl8723ae_dm_rf_saving(hw, true);
409
410 rtl8723ae_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
411 break; }
412 case HW_VAR_FW_PSMODE_STATUS:
413 ppsc->fw_current_inpsmode = *((bool *) val);
414 break;
415 case HW_VAR_H2C_FW_JOINBSSRPT:{
416 u8 mstatus = (*(u8 *) val);
417 u8 tmp_regcr, tmp_reg422;
418 bool recover = false;
419
420 if (mstatus == RT_MEDIA_CONNECT) {
421 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
422
423 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
424 rtl_write_byte(rtlpriv, REG_CR + 1,
425 (tmp_regcr | BIT(0)));
426
427 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
428 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
429
430 tmp_reg422 = rtl_read_byte(rtlpriv,
431 REG_FWHW_TXQ_CTRL + 2);
432 if (tmp_reg422 & BIT(6))
433 recover = true;
434 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
435 tmp_reg422 & (~BIT(6)));
436
437 rtl8723ae_set_fw_rsvdpagepkt(hw, 0);
438
439 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
440 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
441
442 if (recover)
443 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
444 tmp_reg422);
445
446 rtl_write_byte(rtlpriv, REG_CR + 1,
447 (tmp_regcr & ~(BIT(0))));
448 }
449 rtl8723ae_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
450
451 break; }
452 case HW_VAR_AID:{
453 u16 u2btmp;
454 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
455 u2btmp &= 0xC000;
456 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
457 mac->assoc_id));
458 break; }
459 case HW_VAR_CORRECT_TSF:{
460 u8 btype_ibss = ((u8 *) (val))[0];
461
462 if (btype_ibss == true)
463 _rtl8723ae_stop_tx_beacon(hw);
464
465 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
466
467 rtl_write_dword(rtlpriv, REG_TSFTR,
468 (u32) (mac->tsf & 0xffffffff));
469 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
470 (u32) ((mac->tsf >> 32) & 0xffffffff));
471
472 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
473
474 if (btype_ibss == true)
475 _rtl8723ae_resume_tx_beacon(hw);
476 break; }
477 default:
478 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
479 "switch case not processed\n");
480 break;
481 }
482}
483
484static bool _rtl8723ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
485{
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 bool status = true;
488 long count = 0;
489 u32 value = _LLT_INIT_ADDR(address) |
490 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
491
492 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
493
494 do {
495 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
496 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
497 break;
498
499 if (count > POLLING_LLT_THRESHOLD) {
500 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
501 "Failed to polling write LLT done at address %d!\n",
502 address);
503 status = false;
504 break;
505 }
506 } while (++count);
507
508 return status;
509}
510
511static bool _rtl8723ae_llt_table_init(struct ieee80211_hw *hw)
512{
513 struct rtl_priv *rtlpriv = rtl_priv(hw);
514 unsigned short i;
515 u8 txpktbuf_bndy;
516 u8 maxPage;
517 bool status;
518 u8 ubyte;
519
520 maxPage = 255;
521 txpktbuf_bndy = 246;
522
523 rtl_write_byte(rtlpriv, REG_CR, 0x8B);
524
525 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
526
527 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
528 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
529
530 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
531 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
532
533 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
534 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
535
536 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
537 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
538 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
539
540 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
541 status = _rtl8723ae_llt_write(hw, i, i + 1);
542 if (true != status)
543 return status;
544 }
545
546 status = _rtl8723ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
547 if (true != status)
548 return status;
549
550 for (i = txpktbuf_bndy; i < maxPage; i++) {
551 status = _rtl8723ae_llt_write(hw, i, (i + 1));
552 if (true != status)
553 return status;
554 }
555
556 status = _rtl8723ae_llt_write(hw, maxPage, txpktbuf_bndy);
557 if (true != status)
558 return status;
559
560 rtl_write_byte(rtlpriv, REG_CR, 0xff);
561 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3);
562 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7));
563
564 return true;
565}
566
567static void _rtl8723ae_gen_refresh_led_state(struct ieee80211_hw *hw)
568{
569 struct rtl_priv *rtlpriv = rtl_priv(hw);
570 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
571 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
572 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
573
574 if (rtlpriv->rtlhal.up_first_time)
575 return;
576
577 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
578 rtl8723ae_sw_led_on(hw, pLed0);
579 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
580 rtl8723ae_sw_led_on(hw, pLed0);
581 else
582 rtl8723ae_sw_led_off(hw, pLed0);
583}
584
585static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
586{
587 struct rtl_priv *rtlpriv = rtl_priv(hw);
588 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
589 unsigned char bytetmp;
590 unsigned short wordtmp;
591 u16 retry = 0;
592 u16 tmpu2b;
593 bool mac_func_enable;
594
595 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
596 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
597 if (bytetmp == 0xFF)
598 mac_func_enable = true;
599 else
600 mac_func_enable = false;
601
602
603 /* HW Power on sequence */
604 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
605 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW))
606 return false;
607
608 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
609 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4));
610
611 /* eMAC time out function enable, 0x369[7]=1 */
612 bytetmp = rtl_read_byte(rtlpriv, 0x369);
613 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7));
614
615 /* ePHY reg 0x1e bit[4]=1 using MDIO interface,
616 * we should do this before Enabling ASPM backdoor.
617 */
618 do {
619 rtl_write_word(rtlpriv, 0x358, 0x5e);
620 udelay(100);
621 rtl_write_word(rtlpriv, 0x356, 0xc280);
622 rtl_write_word(rtlpriv, 0x354, 0xc290);
623 rtl_write_word(rtlpriv, 0x358, 0x3e);
624 udelay(100);
625 rtl_write_word(rtlpriv, 0x358, 0x5e);
626 udelay(100);
627 tmpu2b = rtl_read_word(rtlpriv, 0x356);
628 retry++;
629 } while (tmpu2b != 0xc290 && retry < 100);
630
631 if (retry >= 100) {
632 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
633 "InitMAC(): ePHY configure fail!!!\n");
634 return false;
635 }
636
637 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
638 rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
639
640 if (!mac_func_enable) {
641 if (_rtl8723ae_llt_table_init(hw) == false)
642 return false;
643 }
644
645 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
646 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
647
648 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
649
650 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0xf;
651 wordtmp |= 0xF771;
652 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
653
654 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
655 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
656 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
657 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
658
659 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
660
661 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
662 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
663 DMA_BIT_MASK(32));
664 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
665 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
666 DMA_BIT_MASK(32));
667 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
668 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
669 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
670 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
671 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
672 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
673 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
674 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
675 rtl_write_dword(rtlpriv, REG_HQ_DESA,
676 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
677 DMA_BIT_MASK(32));
678 rtl_write_dword(rtlpriv, REG_RX_DESA,
679 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
680 DMA_BIT_MASK(32));
681
682 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74);
683
684 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
685
686 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
687 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
688 do {
689 retry++;
690 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
691 } while ((retry < 200) && (bytetmp & BIT(7)));
692
693 _rtl8723ae_gen_refresh_led_state(hw);
694
695 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
696
697 return true;
698}
699
700static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw)
701{
702 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
703 struct rtl_priv *rtlpriv = rtl_priv(hw);
704 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
705 u8 reg_bw_opmode;
706 u32 reg_ratr, reg_prsr;
707
708 reg_bw_opmode = BW_OPMODE_20MHZ;
709 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
710 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
711 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
712
713 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
714
715 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
716
717 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
718
719 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
720
721 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
722
723 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
724
725 rtl_write_word(rtlpriv, REG_RL, 0x0707);
726
727 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
728
729 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
730
731 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
732 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
733 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
734 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
735
736 if ((pcipriv->bt_coexist.bt_coexistence) &&
737 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
738 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
739 else
740 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
741
742 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
743
744 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
745
746 rtlpci->reg_bcn_ctrl_val = 0x1f;
747 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
748
749 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
750
751 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
752
753 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
754 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
755
756 if ((pcipriv->bt_coexist.bt_coexistence) &&
757 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
758 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
759 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
760 } else {
761 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
762 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
763 }
764
765 if ((pcipriv->bt_coexist.bt_coexistence) &&
766 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
767 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
768 else
769 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
770
771 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
772
773 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
774 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
775
776 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
777
778 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
779
780 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
781 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
782
783 rtl_write_dword(rtlpriv, 0x394, 0x1);
784}
785
786static void _rtl8723ae_enable_aspm_back_door(struct ieee80211_hw *hw)
787{
788 struct rtl_priv *rtlpriv = rtl_priv(hw);
789 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
790
791 rtl_write_byte(rtlpriv, 0x34b, 0x93);
792 rtl_write_word(rtlpriv, 0x350, 0x870c);
793 rtl_write_byte(rtlpriv, 0x352, 0x1);
794
795 if (ppsc->support_backdoor)
796 rtl_write_byte(rtlpriv, 0x349, 0x1b);
797 else
798 rtl_write_byte(rtlpriv, 0x349, 0x03);
799
800 rtl_write_word(rtlpriv, 0x350, 0x2718);
801 rtl_write_byte(rtlpriv, 0x352, 0x1);
802}
803
804void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw)
805{
806 struct rtl_priv *rtlpriv = rtl_priv(hw);
807 u8 sec_reg_value;
808
809 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
810 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
811 rtlpriv->sec.pairwise_enc_algorithm,
812 rtlpriv->sec.group_enc_algorithm);
813
814 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
815 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
816 "not open hw encryption\n");
817 return;
818 }
819
820 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
821
822 if (rtlpriv->sec.use_defaultkey) {
823 sec_reg_value |= SCR_TxUseDK;
824 sec_reg_value |= SCR_RxUseDK;
825 }
826
827 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
828
829 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
830
831 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
832 "The SECR-value %x\n", sec_reg_value);
833
834 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
835
836}
837
838int rtl8723ae_hw_init(struct ieee80211_hw *hw)
839{
840 struct rtl_priv *rtlpriv = rtl_priv(hw);
841 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
842 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
843 struct rtl_phy *rtlphy = &(rtlpriv->phy);
844 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
845 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
846 bool rtstatus = true;
847 int err;
848 u8 tmp_u1b;
849
850 rtlpriv->rtlhal.being_init_adapter = true;
851 rtlpriv->intf_ops->disable_aspm(hw);
852 rtstatus = _rtl8712e_init_mac(hw);
853 if (rtstatus != true) {
854 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
855 err = 1;
856 return err;
857 }
858
859 err = rtl8723ae_download_fw(hw);
860 if (err) {
861 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
862 "Failed to download FW. Init HW without FW now..\n");
863 err = 1;
864 rtlhal->fw_ready = false;
865 return err;
866 } else {
867 rtlhal->fw_ready = true;
868 }
869
870 rtlhal->last_hmeboxnum = 0;
871 rtl8723ae_phy_mac_config(hw);
872 /* because the last function modifies RCR, we update
873 * rcr var here, or TP will be unstable as ther receive_config
874 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
875 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
876 */
877 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
878 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
879 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
880
881 rtl8723ae_phy_bb_config(hw);
882 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
883 rtl8723ae_phy_rf_config(hw);
884 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
885 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
886 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
887 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
888 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
889 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
890 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
891 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
892 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
893 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
894 }
895 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
896 RF_CHNLBW, RFREG_OFFSET_MASK);
897 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
898 RF_CHNLBW, RFREG_OFFSET_MASK);
899 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
900 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
901 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
902 _rtl8723ae_hw_configure(hw);
903 rtl_cam_reset_all_entry(hw);
904 rtl8723ae_enable_hw_security_config(hw);
905
906 ppsc->rfpwr_state = ERFON;
907
908 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
909 _rtl8723ae_enable_aspm_back_door(hw);
910 rtlpriv->intf_ops->enable_aspm(hw);
911
912 rtl8723ae_bt_hw_init(hw);
913
914 if (ppsc->rfpwr_state == ERFON) {
915 rtl8723ae_phy_set_rfpath_switch(hw, 1);
916 if (rtlphy->iqk_initialized) {
917 rtl8723ae_phy_iq_calibrate(hw, true);
918 } else {
919 rtl8723ae_phy_iq_calibrate(hw, false);
920 rtlphy->iqk_initialized = true;
921 }
922
923 rtl8723ae_phy_lc_calibrate(hw);
924 }
925
926 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
927 if (!(tmp_u1b & BIT(0))) {
928 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
929 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
930 }
931
932 if (!(tmp_u1b & BIT(4))) {
933 tmp_u1b = rtl_read_byte(rtlpriv, 0x16) & 0x0F;
934 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
935 udelay(10);
936 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
937 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
938 }
939 rtl8723ae_dm_init(hw);
940 rtlpriv->rtlhal.being_init_adapter = false;
941 return err;
942}
943
944static enum version_8723e _rtl8723ae_read_chip_version(struct ieee80211_hw *hw)
945{
946 struct rtl_priv *rtlpriv = rtl_priv(hw);
947 struct rtl_phy *rtlphy = &(rtlpriv->phy);
948 enum version_8723e version = 0x0000;
949 u32 value32;
950
951 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
952 if (value32 & TRP_VAUX_EN) {
953 version = (enum version_8723e)(version |
954 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
955 /* RTL8723 with BT function. */
956 version = (enum version_8723e)(version |
957 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
958
959 } else {
960 /* Normal mass production chip. */
961 version = (enum version_8723e) NORMAL_CHIP;
962 version = (enum version_8723e)(version |
963 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
964 /* RTL8723 with BT function. */
965 version = (enum version_8723e)(version |
966 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
967 if (IS_CHIP_VENDOR_UMC(version))
968 version = (enum version_8723e)(version |
969 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
970 if (IS_8723_SERIES(version)) {
971 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
972 /* ROM code version */
973 version = (enum version_8723e)(version |
974 ((value32 & RF_RL_ID)>>20));
975 }
976 }
977
978 if (IS_8723_SERIES(version)) {
979 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
980 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
981 RT_POLARITY_HIGH_ACT :
982 RT_POLARITY_LOW_ACT);
983 }
984 switch (version) {
985 case VERSION_TEST_UMC_CHIP_8723:
986 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
987 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
988 break;
989 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
990 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
991 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
992 break;
993 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
994 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
995 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
996 break;
997 default:
998 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
999 "Chip Version ID: Unknown. Bug?\n");
1000 break;
1001 }
1002
1003 if (IS_8723_SERIES(version))
1004 rtlphy->rf_type = RF_1T1R;
1005
1006 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1007 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1008
1009 return version;
1010}
1011
1012static int _rtl8723ae_set_media_status(struct ieee80211_hw *hw,
1013 enum nl80211_iftype type)
1014{
1015 struct rtl_priv *rtlpriv = rtl_priv(hw);
1016 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1017 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1018
1019 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1020 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1021 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1022
1023 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1024 type == NL80211_IFTYPE_STATION) {
1025 _rtl8723ae_stop_tx_beacon(hw);
1026 _rtl8723ae_enable_bcn_sufunc(hw);
1027 } else if (type == NL80211_IFTYPE_ADHOC ||
1028 type == NL80211_IFTYPE_AP) {
1029 _rtl8723ae_resume_tx_beacon(hw);
1030 _rtl8723ae_disable_bcn_sufunc(hw);
1031 } else {
1032 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1033 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1034 type);
1035 }
1036
1037 switch (type) {
1038 case NL80211_IFTYPE_UNSPECIFIED:
1039 bt_msr |= MSR_NOLINK;
1040 ledaction = LED_CTL_LINK;
1041 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1042 "Set Network type to NO LINK!\n");
1043 break;
1044 case NL80211_IFTYPE_ADHOC:
1045 bt_msr |= MSR_ADHOC;
1046 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1047 "Set Network type to Ad Hoc!\n");
1048 break;
1049 case NL80211_IFTYPE_STATION:
1050 bt_msr |= MSR_INFRA;
1051 ledaction = LED_CTL_LINK;
1052 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1053 "Set Network type to STA!\n");
1054 break;
1055 case NL80211_IFTYPE_AP:
1056 bt_msr |= MSR_AP;
1057 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1058 "Set Network type to AP!\n");
1059 break;
1060 default:
1061 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1062 "Network type %d not supported!\n",
1063 type);
1064 return 1;
1065 break;
1066
1067 }
1068
1069 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1070 rtlpriv->cfg->ops->led_control(hw, ledaction);
1071 if ((bt_msr & 0x03) == MSR_AP)
1072 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1073 else
1074 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1075 return 0;
1076}
1077
1078void rtl8723ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1079{
1080 struct rtl_priv *rtlpriv = rtl_priv(hw);
1081 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1082 u32 reg_rcr = rtlpci->receive_config;
1083
1084 if (rtlpriv->psc.rfpwr_state != ERFON)
1085 return;
1086
1087 if (check_bssid == true) {
1088 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1089 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1090 (u8 *)(&reg_rcr));
1091 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
1092 } else if (check_bssid == false) {
1093 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1094 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
1095 rtlpriv->cfg->ops->set_hw_reg(hw,
1096 HW_VAR_RCR, (u8 *) (&reg_rcr));
1097 }
1098}
1099
1100int rtl8723ae_set_network_type(struct ieee80211_hw *hw,
1101 enum nl80211_iftype type)
1102{
1103 struct rtl_priv *rtlpriv = rtl_priv(hw);
1104
1105 if (_rtl8723ae_set_media_status(hw, type))
1106 return -EOPNOTSUPP;
1107
1108 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1109 if (type != NL80211_IFTYPE_AP)
1110 rtl8723ae_set_check_bssid(hw, true);
1111 } else {
1112 rtl8723ae_set_check_bssid(hw, false);
1113 }
1114 return 0;
1115}
1116
1117/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1118void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci)
1119{
1120 struct rtl_priv *rtlpriv = rtl_priv(hw);
1121
1122 rtl8723ae_dm_init_edca_turbo(hw);
1123 switch (aci) {
1124 case AC1_BK:
1125 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1126 break;
1127 case AC0_BE:
1128 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4ac_param); */
1129 break;
1130 case AC2_VI:
1131 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1132 break;
1133 case AC3_VO:
1134 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1135 break;
1136 default:
1137 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1138 break;
1139 }
1140}
1141
1142void rtl8723ae_enable_interrupt(struct ieee80211_hw *hw)
1143{
1144 struct rtl_priv *rtlpriv = rtl_priv(hw);
1145 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1146
1147 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1148 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1149 rtlpci->irq_enabled = true;
1150}
1151
1152void rtl8723ae_disable_interrupt(struct ieee80211_hw *hw)
1153{
1154 struct rtl_priv *rtlpriv = rtl_priv(hw);
1155 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1156
1157 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1158 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1159 rtlpci->irq_enabled = false;
1160 synchronize_irq(rtlpci->pdev->irq);
1161}
1162
1163static void _rtl8723ae_poweroff_adapter(struct ieee80211_hw *hw)
1164{
1165 struct rtl_priv *rtlpriv = rtl_priv(hw);
1166 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1167 u8 u1tmp;
1168
1169 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1170 /* 1. Run LPS WL RFOFF flow */
1171 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1172 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW);
1173
1174 /* 2. 0x1F[7:0] = 0 */
1175 /* turn off RF */
1176 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1177 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1178 rtl8723ae_firmware_selfreset(hw);
1179
1180 /* Reset MCU. Suggested by Filen. */
1181 u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1182 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1tmp & (~BIT(2))));
1183
1184 /* g. MCUFWDL 0x80[1:0]=0 */
1185 /* reset MCU ready status */
1186 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1187
1188 /* HW card disable configuration. */
1189 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1190 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW);
1191
1192 /* Reset MCU IO Wrapper */
1193 u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1194 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1tmp & (~BIT(0))));
1195 u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1196 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1tmp | BIT(0));
1197
1198 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1199 /* lock ISO/CLK/Power control register */
1200 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1201}
1202
1203void rtl8723ae_card_disable(struct ieee80211_hw *hw)
1204{
1205 struct rtl_priv *rtlpriv = rtl_priv(hw);
1206 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1207 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1209 enum nl80211_iftype opmode;
1210
1211 mac->link_state = MAC80211_NOLINK;
1212 opmode = NL80211_IFTYPE_UNSPECIFIED;
1213 _rtl8723ae_set_media_status(hw, opmode);
1214 if (rtlpci->driver_is_goingto_unload ||
1215 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1216 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1217 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1218 _rtl8723ae_poweroff_adapter(hw);
1219
1220 /* after power off we should do iqk again */
1221 rtlpriv->phy.iqk_initialized = false;
1222}
1223
1224void rtl8723ae_interrupt_recognized(struct ieee80211_hw *hw,
1225 u32 *p_inta, u32 *p_intb)
1226{
1227 struct rtl_priv *rtlpriv = rtl_priv(hw);
1228 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1229
1230 *p_inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0];
1231 rtl_write_dword(rtlpriv, 0x3a0, *p_inta);
1232}
1233
1234void rtl8723ae_set_beacon_related_registers(struct ieee80211_hw *hw)
1235{
1236
1237 struct rtl_priv *rtlpriv = rtl_priv(hw);
1238 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1239 u16 bcn_interval, atim_window;
1240
1241 bcn_interval = mac->beacon_interval;
1242 atim_window = 2; /*FIX MERGE */
1243 rtl8723ae_disable_interrupt(hw);
1244 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1245 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1246 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1247 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1248 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1249 rtl_write_byte(rtlpriv, 0x606, 0x30);
1250 rtl8723ae_enable_interrupt(hw);
1251}
1252
1253void rtl8723ae_set_beacon_interval(struct ieee80211_hw *hw)
1254{
1255 struct rtl_priv *rtlpriv = rtl_priv(hw);
1256 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1257 u16 bcn_interval = mac->beacon_interval;
1258
1259 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1260 "beacon_interval:%d\n", bcn_interval);
1261 rtl8723ae_disable_interrupt(hw);
1262 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1263 rtl8723ae_enable_interrupt(hw);
1264}
1265
1266void rtl8723ae_update_interrupt_mask(struct ieee80211_hw *hw,
1267 u32 add_msr, u32 rm_msr)
1268{
1269 struct rtl_priv *rtlpriv = rtl_priv(hw);
1270 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1271
1272 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1273 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1274
1275 if (add_msr)
1276 rtlpci->irq_mask[0] |= add_msr;
1277 if (rm_msr)
1278 rtlpci->irq_mask[0] &= (~rm_msr);
1279 rtl8723ae_disable_interrupt(hw);
1280 rtl8723ae_enable_interrupt(hw);
1281}
1282
1283static u8 _rtl8723ae_get_chnl_group(u8 chnl)
1284{
1285 u8 group;
1286
1287 if (chnl < 3)
1288 group = 0;
1289 else if (chnl < 9)
1290 group = 1;
1291 else
1292 group = 2;
1293 return group;
1294}
1295
1296static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1297 bool autoload_fail,
1298 u8 *hwinfo)
1299{
1300 struct rtl_priv *rtlpriv = rtl_priv(hw);
1301 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1302 u8 rf_path, index, tempval;
1303 u16 i;
1304
1305 for (rf_path = 0; rf_path < 1; rf_path++) {
1306 for (i = 0; i < 3; i++) {
1307 if (!autoload_fail) {
1308 rtlefuse->eeprom_chnlarea_txpwr_cck
1309 [rf_path][i] =
1310 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1311 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1312 [rf_path][i] =
1313 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path *
1314 3 + i];
1315 } else {
1316 rtlefuse->eeprom_chnlarea_txpwr_cck
1317 [rf_path][i] =
1318 EEPROM_DEFAULT_TXPOWERLEVEL;
1319 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1320 [rf_path][i] =
1321 EEPROM_DEFAULT_TXPOWERLEVEL;
1322 }
1323 }
1324 }
1325
1326 for (i = 0; i < 3; i++) {
1327 if (!autoload_fail)
1328 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1329 else
1330 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1331 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1332 (tempval & 0xf);
1333 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1334 ((tempval & 0xf0) >> 4);
1335 }
1336
1337 for (rf_path = 0; rf_path < 2; rf_path++)
1338 for (i = 0; i < 3; i++)
1339 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1340 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1341 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1342 [rf_path][i]);
1343 for (rf_path = 0; rf_path < 2; rf_path++)
1344 for (i = 0; i < 3; i++)
1345 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1346 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1347 rf_path, i,
1348 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1349 [rf_path][i]);
1350 for (rf_path = 0; rf_path < 2; rf_path++)
1351 for (i = 0; i < 3; i++)
1352 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1353 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1354 rf_path, i,
1355 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1356 [rf_path][i]);
1357
1358 for (rf_path = 0; rf_path < 2; rf_path++) {
1359 for (i = 0; i < 14; i++) {
1360 index = _rtl8723ae_get_chnl_group((u8) i);
1361
1362 rtlefuse->txpwrlevel_cck[rf_path][i] =
1363 rtlefuse->eeprom_chnlarea_txpwr_cck
1364 [rf_path][index];
1365 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1366 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1367 [rf_path][index];
1368
1369 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1370 [rf_path][index] -
1371 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path]
1372 [index]) > 0) {
1373 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1374 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1375 [rf_path][index] -
1376 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1377 [rf_path][index];
1378 } else {
1379 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1380 }
1381 }
1382
1383 for (i = 0; i < 14; i++) {
1384 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1385 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1386 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1387 rtlefuse->txpwrlevel_cck[rf_path][i],
1388 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1389 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1390 }
1391 }
1392
1393 for (i = 0; i < 3; i++) {
1394 if (!autoload_fail) {
1395 rtlefuse->eeprom_pwrlimit_ht40[i] =
1396 hwinfo[EEPROM_TXPWR_GROUP + i];
1397 rtlefuse->eeprom_pwrlimit_ht20[i] =
1398 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1399 } else {
1400 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1401 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1402 }
1403 }
1404
1405 for (rf_path = 0; rf_path < 2; rf_path++) {
1406 for (i = 0; i < 14; i++) {
1407 index = _rtl8723ae_get_chnl_group((u8) i);
1408
1409 if (rf_path == RF90_PATH_A) {
1410 rtlefuse->pwrgroup_ht20[rf_path][i] =
1411 (rtlefuse->eeprom_pwrlimit_ht20[index] &
1412 0xf);
1413 rtlefuse->pwrgroup_ht40[rf_path][i] =
1414 (rtlefuse->eeprom_pwrlimit_ht40[index] &
1415 0xf);
1416 } else if (rf_path == RF90_PATH_B) {
1417 rtlefuse->pwrgroup_ht20[rf_path][i] =
1418 ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1419 0xf0) >> 4);
1420 rtlefuse->pwrgroup_ht40[rf_path][i] =
1421 ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1422 0xf0) >> 4);
1423 }
1424
1425 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1426 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i,
1427 rtlefuse->pwrgroup_ht20[rf_path][i]);
1428 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1429 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i,
1430 rtlefuse->pwrgroup_ht40[rf_path][i]);
1431 }
1432 }
1433
1434 for (i = 0; i < 14; i++) {
1435 index = _rtl8723ae_get_chnl_group((u8) i);
1436
1437 if (!autoload_fail)
1438 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1439 else
1440 tempval = EEPROM_DEFAULT_HT20_DIFF;
1441
1442 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1443 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1444 ((tempval >> 4) & 0xF);
1445
1446 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1447 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1448
1449 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1450 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1451
1452 index = _rtl8723ae_get_chnl_group((u8) i);
1453
1454 if (!autoload_fail)
1455 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1456 else
1457 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1458
1459 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1460 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1461 ((tempval >> 4) & 0xF);
1462 }
1463
1464 rtlefuse->legacy_ht_txpowerdiff =
1465 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1466
1467 for (i = 0; i < 14; i++)
1468 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1469 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1470 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1471 for (i = 0; i < 14; i++)
1472 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1473 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1474 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1475 for (i = 0; i < 14; i++)
1476 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1477 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1478 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1479 for (i = 0; i < 14; i++)
1480 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1481 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1482 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1483
1484 if (!autoload_fail)
1485 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1486 else
1487 rtlefuse->eeprom_regulatory = 0;
1488 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1489 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1490
1491 if (!autoload_fail)
1492 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1493 else
1494 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1495 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1496 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1497 rtlefuse->eeprom_tssi[RF90_PATH_A],
1498 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1499
1500 if (!autoload_fail)
1501 tempval = hwinfo[EEPROM_THERMAL_METER];
1502 else
1503 tempval = EEPROM_DEFAULT_THERMALMETER;
1504 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1505
1506 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1507 rtlefuse->apk_thermalmeterignore = true;
1508
1509 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1510 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1511 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1512}
1513
1514static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1515 bool pseudo_test)
1516{
1517 struct rtl_priv *rtlpriv = rtl_priv(hw);
1518 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1519 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1520 u16 i, usvalue;
1521 u8 hwinfo[HWSET_MAX_SIZE];
1522 u16 eeprom_id;
1523
1524 if (pseudo_test) {
1525 /* need add */
1526 return;
1527 }
1528 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1529 rtl_efuse_shadow_map_update(hw);
1530
1531 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1532 HWSET_MAX_SIZE);
1533 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1534 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1535 "RTL819X Not boot from eeprom, check it !!");
1536 }
1537
1538 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1539 hwinfo, HWSET_MAX_SIZE);
1540
1541 eeprom_id = *((u16 *)&hwinfo[0]);
1542 if (eeprom_id != RTL8190_EEPROM_ID) {
1543 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1544 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1545 rtlefuse->autoload_failflag = true;
1546 } else {
1547 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1548 rtlefuse->autoload_failflag = false;
1549 }
1550
1551 if (rtlefuse->autoload_failflag == true)
1552 return;
1553
1554 rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
1555 rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
1556 rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
1557 rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
1558 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1559 "EEPROMId = 0x%4x\n", eeprom_id);
1560 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1561 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1562 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1563 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1564 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1565 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1566 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1567 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1568
1569 for (i = 0; i < 6; i += 2) {
1570 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1571 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1572 }
1573
1574 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1575 "dev_addr: %pM\n", rtlefuse->dev_addr);
1576
1577 _rtl8723ae_read_txpower_info_from_hwpg(hw,
1578 rtlefuse->autoload_failflag, hwinfo);
1579
1580 rtl8723ae_read_bt_coexist_info_from_hwpg(hw,
1581 rtlefuse->autoload_failflag, hwinfo);
1582
1583 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1584 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1585 rtlefuse->txpwr_fromeprom = true;
1586 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1587
1588 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1589 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1590
1591 /* set channel paln to world wide 13 */
1592 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1593
1594 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1595 switch (rtlefuse->eeprom_oemid) {
1596 case EEPROM_CID_DEFAULT:
1597 if (rtlefuse->eeprom_did == 0x8176) {
1598 if (CHK_SVID_SMID(0x10EC, 0x6151) ||
1599 CHK_SVID_SMID(0x10EC, 0x6152) ||
1600 CHK_SVID_SMID(0x10EC, 0x6154) ||
1601 CHK_SVID_SMID(0x10EC, 0x6155) ||
1602 CHK_SVID_SMID(0x10EC, 0x6177) ||
1603 CHK_SVID_SMID(0x10EC, 0x6178) ||
1604 CHK_SVID_SMID(0x10EC, 0x6179) ||
1605 CHK_SVID_SMID(0x10EC, 0x6180) ||
1606 CHK_SVID_SMID(0x10EC, 0x8151) ||
1607 CHK_SVID_SMID(0x10EC, 0x8152) ||
1608 CHK_SVID_SMID(0x10EC, 0x8154) ||
1609 CHK_SVID_SMID(0x10EC, 0x8155) ||
1610 CHK_SVID_SMID(0x10EC, 0x8181) ||
1611 CHK_SVID_SMID(0x10EC, 0x8182) ||
1612 CHK_SVID_SMID(0x10EC, 0x8184) ||
1613 CHK_SVID_SMID(0x10EC, 0x8185) ||
1614 CHK_SVID_SMID(0x10EC, 0x9151) ||
1615 CHK_SVID_SMID(0x10EC, 0x9152) ||
1616 CHK_SVID_SMID(0x10EC, 0x9154) ||
1617 CHK_SVID_SMID(0x10EC, 0x9155) ||
1618 CHK_SVID_SMID(0x10EC, 0x9181) ||
1619 CHK_SVID_SMID(0x10EC, 0x9182) ||
1620 CHK_SVID_SMID(0x10EC, 0x9184) ||
1621 CHK_SVID_SMID(0x10EC, 0x9185))
1622 rtlhal->oem_id = RT_CID_TOSHIBA;
1623 else if (rtlefuse->eeprom_svid == 0x1025)
1624 rtlhal->oem_id = RT_CID_819x_Acer;
1625 else if (CHK_SVID_SMID(0x10EC, 0x6191) ||
1626 CHK_SVID_SMID(0x10EC, 0x6192) ||
1627 CHK_SVID_SMID(0x10EC, 0x6193) ||
1628 CHK_SVID_SMID(0x10EC, 0x7191) ||
1629 CHK_SVID_SMID(0x10EC, 0x7192) ||
1630 CHK_SVID_SMID(0x10EC, 0x7193) ||
1631 CHK_SVID_SMID(0x10EC, 0x8191) ||
1632 CHK_SVID_SMID(0x10EC, 0x8192) ||
1633 CHK_SVID_SMID(0x10EC, 0x8193))
1634 rtlhal->oem_id = RT_CID_819x_SAMSUNG;
1635 else if (CHK_SVID_SMID(0x10EC, 0x8195) ||
1636 CHK_SVID_SMID(0x10EC, 0x9195) ||
1637 CHK_SVID_SMID(0x10EC, 0x7194) ||
1638 CHK_SVID_SMID(0x10EC, 0x8200) ||
1639 CHK_SVID_SMID(0x10EC, 0x8201) ||
1640 CHK_SVID_SMID(0x10EC, 0x8202) ||
1641 CHK_SVID_SMID(0x10EC, 0x9200))
1642 rtlhal->oem_id = RT_CID_819x_Lenovo;
1643 else if (CHK_SVID_SMID(0x10EC, 0x8197) ||
1644 CHK_SVID_SMID(0x10EC, 0x9196))
1645 rtlhal->oem_id = RT_CID_819x_CLEVO;
1646 else if (CHK_SVID_SMID(0x1028, 0x8194) ||
1647 CHK_SVID_SMID(0x1028, 0x8198) ||
1648 CHK_SVID_SMID(0x1028, 0x9197) ||
1649 CHK_SVID_SMID(0x1028, 0x9198))
1650 rtlhal->oem_id = RT_CID_819x_DELL;
1651 else if (CHK_SVID_SMID(0x103C, 0x1629))
1652 rtlhal->oem_id = RT_CID_819x_HP;
1653 else if (CHK_SVID_SMID(0x1A32, 0x2315))
1654 rtlhal->oem_id = RT_CID_819x_QMI;
1655 else if (CHK_SVID_SMID(0x10EC, 0x8203))
1656 rtlhal->oem_id = RT_CID_819x_PRONETS;
1657 else if (CHK_SVID_SMID(0x1043, 0x84B5))
1658 rtlhal->oem_id =
1659 RT_CID_819x_Edimax_ASUS;
1660 else
1661 rtlhal->oem_id = RT_CID_DEFAULT;
1662 } else if (rtlefuse->eeprom_did == 0x8178) {
1663 if (CHK_SVID_SMID(0x10EC, 0x6181) ||
1664 CHK_SVID_SMID(0x10EC, 0x6182) ||
1665 CHK_SVID_SMID(0x10EC, 0x6184) ||
1666 CHK_SVID_SMID(0x10EC, 0x6185) ||
1667 CHK_SVID_SMID(0x10EC, 0x7181) ||
1668 CHK_SVID_SMID(0x10EC, 0x7182) ||
1669 CHK_SVID_SMID(0x10EC, 0x7184) ||
1670 CHK_SVID_SMID(0x10EC, 0x7185) ||
1671 CHK_SVID_SMID(0x10EC, 0x8181) ||
1672 CHK_SVID_SMID(0x10EC, 0x8182) ||
1673 CHK_SVID_SMID(0x10EC, 0x8184) ||
1674 CHK_SVID_SMID(0x10EC, 0x8185) ||
1675 CHK_SVID_SMID(0x10EC, 0x9181) ||
1676 CHK_SVID_SMID(0x10EC, 0x9182) ||
1677 CHK_SVID_SMID(0x10EC, 0x9184) ||
1678 CHK_SVID_SMID(0x10EC, 0x9185))
1679 rtlhal->oem_id = RT_CID_TOSHIBA;
1680 else if (rtlefuse->eeprom_svid == 0x1025)
1681 rtlhal->oem_id = RT_CID_819x_Acer;
1682 else if (CHK_SVID_SMID(0x10EC, 0x8186))
1683 rtlhal->oem_id = RT_CID_819x_PRONETS;
1684 else if (CHK_SVID_SMID(0x1043, 0x8486))
1685 rtlhal->oem_id =
1686 RT_CID_819x_Edimax_ASUS;
1687 else
1688 rtlhal->oem_id = RT_CID_DEFAULT;
1689 } else {
1690 rtlhal->oem_id = RT_CID_DEFAULT;
1691 }
1692 break;
1693 case EEPROM_CID_TOSHIBA:
1694 rtlhal->oem_id = RT_CID_TOSHIBA;
1695 break;
1696 case EEPROM_CID_CCX:
1697 rtlhal->oem_id = RT_CID_CCX;
1698 break;
1699 case EEPROM_CID_QMI:
1700 rtlhal->oem_id = RT_CID_819x_QMI;
1701 break;
1702 case EEPROM_CID_WHQL:
1703 break;
1704 default:
1705 rtlhal->oem_id = RT_CID_DEFAULT;
1706 break;
1707
1708 }
1709 }
1710}
1711
1712static void _rtl8723ae_hal_customized_behavior(struct ieee80211_hw *hw)
1713{
1714 struct rtl_priv *rtlpriv = rtl_priv(hw);
1715 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1716 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1717
1718 switch (rtlhal->oem_id) {
1719 case RT_CID_819x_HP:
1720 pcipriv->ledctl.led_opendrain = true;
1721 break;
1722 case RT_CID_819x_Lenovo:
1723 case RT_CID_DEFAULT:
1724 case RT_CID_TOSHIBA:
1725 case RT_CID_CCX:
1726 case RT_CID_819x_Acer:
1727 case RT_CID_WHQL:
1728 default:
1729 break;
1730 }
1731 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1732 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1733}
1734
1735void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw)
1736{
1737 struct rtl_priv *rtlpriv = rtl_priv(hw);
1738 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1739 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1740 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1741 u8 tmp_u1b;
1742 u32 value32;
1743
1744 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]);
1745 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1746 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1747
1748 rtlhal->version = _rtl8723ae_read_chip_version(hw);
1749
1750 if (get_rf_type(rtlphy) == RF_1T1R)
1751 rtlpriv->dm.rfpath_rxenable[0] = true;
1752 else
1753 rtlpriv->dm.rfpath_rxenable[0] =
1754 rtlpriv->dm.rfpath_rxenable[1] = true;
1755 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1756 rtlhal->version);
1757
1758 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1759 if (tmp_u1b & BIT(4)) {
1760 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1761 rtlefuse->epromtype = EEPROM_93C46;
1762 } else {
1763 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1764 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1765 }
1766 if (tmp_u1b & BIT(5)) {
1767 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1768 rtlefuse->autoload_failflag = false;
1769 _rtl8723ae_read_adapter_info(hw, false);
1770 } else {
1771 rtlefuse->autoload_failflag = true;
1772 _rtl8723ae_read_adapter_info(hw, false);
1773 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1774 }
1775 _rtl8723ae_hal_customized_behavior(hw);
1776}
1777
1778static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw,
1779 struct ieee80211_sta *sta)
1780{
1781 struct rtl_priv *rtlpriv = rtl_priv(hw);
1782 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1783 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1784 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1785 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1786 u32 ratr_value;
1787 u8 ratr_index = 0;
1788 u8 nmode = mac->ht_enable;
1789 u8 mimo_ps = IEEE80211_SMPS_OFF;
1790 u8 curtxbw_40mhz = mac->bw_40;
1791 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1792 1 : 0;
1793 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1794 1 : 0;
1795 enum wireless_mode wirelessmode = mac->mode;
1796
1797 if (rtlhal->current_bandtype == BAND_ON_5G)
1798 ratr_value = sta->supp_rates[1] << 4;
1799 else
1800 ratr_value = sta->supp_rates[0];
1801 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1802 ratr_value = 0xfff;
1803 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1804 sta->ht_cap.mcs.rx_mask[0] << 12);
1805 switch (wirelessmode) {
1806 case WIRELESS_MODE_B:
1807 if (ratr_value & 0x0000000c)
1808 ratr_value &= 0x0000000d;
1809 else
1810 ratr_value &= 0x0000000f;
1811 break;
1812 case WIRELESS_MODE_G:
1813 ratr_value &= 0x00000FF5;
1814 break;
1815 case WIRELESS_MODE_N_24G:
1816 case WIRELESS_MODE_N_5G:
1817 nmode = 1;
1818 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1819 ratr_value &= 0x0007F005;
1820 } else {
1821 u32 ratr_mask;
1822
1823 if (get_rf_type(rtlphy) == RF_1T2R ||
1824 get_rf_type(rtlphy) == RF_1T1R)
1825 ratr_mask = 0x000ff005;
1826 else
1827 ratr_mask = 0x0f0ff005;
1828
1829 ratr_value &= ratr_mask;
1830 }
1831 break;
1832 default:
1833 if (rtlphy->rf_type == RF_1T2R)
1834 ratr_value &= 0x000ff0ff;
1835 else
1836 ratr_value &= 0x0f0ff0ff;
1837
1838 break;
1839 }
1840
1841 if ((pcipriv->bt_coexist.bt_coexistence) &&
1842 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1843 (pcipriv->bt_coexist.bt_cur_state) &&
1844 (pcipriv->bt_coexist.bt_ant_isolation) &&
1845 ((pcipriv->bt_coexist.bt_service == BT_SCO) ||
1846 (pcipriv->bt_coexist.bt_service == BT_BUSY)))
1847 ratr_value &= 0x0fffcfc0;
1848 else
1849 ratr_value &= 0x0FFFFFFF;
1850
1851 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1852 (!curtxbw_40mhz && curshortgi_20mhz)))
1853 ratr_value |= 0x10000000;
1854
1855 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1856
1857 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1858 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1859}
1860
1861static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw,
1862 struct ieee80211_sta *sta, u8 rssi_level)
1863{
1864 struct rtl_priv *rtlpriv = rtl_priv(hw);
1865 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1866 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1867 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1868 struct rtl_sta_info *sta_entry = NULL;
1869 u32 ratr_bitmap;
1870 u8 ratr_index;
1871 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1872 ? 1 : 0;
1873 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1874 1 : 0;
1875 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1876 1 : 0;
1877 enum wireless_mode wirelessmode = 0;
1878 bool shortgi = false;
1879 u8 rate_mask[5];
1880 u8 macid = 0;
1881 u8 mimo_ps = IEEE80211_SMPS_OFF;
1882
1883 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1884 wirelessmode = sta_entry->wireless_mode;
1885 if (mac->opmode == NL80211_IFTYPE_STATION)
1886 curtxbw_40mhz = mac->bw_40;
1887 else if (mac->opmode == NL80211_IFTYPE_AP ||
1888 mac->opmode == NL80211_IFTYPE_ADHOC)
1889 macid = sta->aid + 1;
1890
1891 if (rtlhal->current_bandtype == BAND_ON_5G)
1892 ratr_bitmap = sta->supp_rates[1] << 4;
1893 else
1894 ratr_bitmap = sta->supp_rates[0];
1895 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1896 ratr_bitmap = 0xfff;
1897 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1898 sta->ht_cap.mcs.rx_mask[0] << 12);
1899 switch (wirelessmode) {
1900 case WIRELESS_MODE_B:
1901 ratr_index = RATR_INX_WIRELESS_B;
1902 if (ratr_bitmap & 0x0000000c)
1903 ratr_bitmap &= 0x0000000d;
1904 else
1905 ratr_bitmap &= 0x0000000f;
1906 break;
1907 case WIRELESS_MODE_G:
1908 ratr_index = RATR_INX_WIRELESS_GB;
1909
1910 if (rssi_level == 1)
1911 ratr_bitmap &= 0x00000f00;
1912 else if (rssi_level == 2)
1913 ratr_bitmap &= 0x00000ff0;
1914 else
1915 ratr_bitmap &= 0x00000ff5;
1916 break;
1917 case WIRELESS_MODE_A:
1918 ratr_index = RATR_INX_WIRELESS_A;
1919 ratr_bitmap &= 0x00000ff0;
1920 break;
1921 case WIRELESS_MODE_N_24G:
1922 case WIRELESS_MODE_N_5G:
1923 ratr_index = RATR_INX_WIRELESS_NGB;
1924
1925 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1926 if (rssi_level == 1)
1927 ratr_bitmap &= 0x00070000;
1928 else if (rssi_level == 2)
1929 ratr_bitmap &= 0x0007f000;
1930 else
1931 ratr_bitmap &= 0x0007f005;
1932 } else {
1933 if (rtlphy->rf_type == RF_1T2R ||
1934 rtlphy->rf_type == RF_1T1R) {
1935 if (curtxbw_40mhz) {
1936 if (rssi_level == 1)
1937 ratr_bitmap &= 0x000f0000;
1938 else if (rssi_level == 2)
1939 ratr_bitmap &= 0x000ff000;
1940 else
1941 ratr_bitmap &= 0x000ff015;
1942 } else {
1943 if (rssi_level == 1)
1944 ratr_bitmap &= 0x000f0000;
1945 else if (rssi_level == 2)
1946 ratr_bitmap &= 0x000ff000;
1947 else
1948 ratr_bitmap &= 0x000ff005;
1949 }
1950 } else {
1951 if (curtxbw_40mhz) {
1952 if (rssi_level == 1)
1953 ratr_bitmap &= 0x0f0f0000;
1954 else if (rssi_level == 2)
1955 ratr_bitmap &= 0x0f0ff000;
1956 else
1957 ratr_bitmap &= 0x0f0ff015;
1958 } else {
1959 if (rssi_level == 1)
1960 ratr_bitmap &= 0x0f0f0000;
1961 else if (rssi_level == 2)
1962 ratr_bitmap &= 0x0f0ff000;
1963 else
1964 ratr_bitmap &= 0x0f0ff005;
1965 }
1966 }
1967 }
1968
1969 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1970 (!curtxbw_40mhz && curshortgi_20mhz)) {
1971 if (macid == 0)
1972 shortgi = true;
1973 else if (macid == 1)
1974 shortgi = false;
1975 }
1976 break;
1977 default:
1978 ratr_index = RATR_INX_WIRELESS_NGB;
1979
1980 if (rtlphy->rf_type == RF_1T2R)
1981 ratr_bitmap &= 0x000ff0ff;
1982 else
1983 ratr_bitmap &= 0x0f0ff0ff;
1984 break;
1985 }
1986 sta_entry->ratr_index = ratr_index;
1987
1988 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1989 "ratr_bitmap :%x\n", ratr_bitmap);
1990 /* convert ratr_bitmap to le byte array */
1991 rate_mask[0] = ratr_bitmap;
1992 rate_mask[1] = (ratr_bitmap >>= 8);
1993 rate_mask[2] = (ratr_bitmap >>= 8);
1994 rate_mask[3] = ((ratr_bitmap >> 8) & 0x0f) | (ratr_index << 4);
1995 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1996 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1997 "Rate_index:%x, ratr_bitmap: %*phC\n",
1998 ratr_index, 5, rate_mask);
1999 rtl8723ae_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2000}
2001
2002void rtl8723ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
2003 struct ieee80211_sta *sta, u8 rssi_level)
2004{
2005 struct rtl_priv *rtlpriv = rtl_priv(hw);
2006
2007 if (rtlpriv->dm.useramask)
2008 rtl8723ae_update_hal_rate_mask(hw, sta, rssi_level);
2009 else
2010 rtl8723ae_update_hal_rate_table(hw, sta);
2011}
2012
2013void rtl8723ae_update_channel_access_setting(struct ieee80211_hw *hw)
2014{
2015 struct rtl_priv *rtlpriv = rtl_priv(hw);
2016 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2017 u16 sifs_timer;
2018
2019 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2020 (u8 *)&mac->slot_time);
2021 if (!mac->ht_enable)
2022 sifs_timer = 0x0a0a;
2023 else
2024 sifs_timer = 0x1010;
2025 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2026}
2027
2028bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2029{
2030 struct rtl_priv *rtlpriv = rtl_priv(hw);
2031 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2032 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2033 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2034 u8 u1tmp;
2035 bool actuallyset = false;
2036
2037 if (rtlpriv->rtlhal.being_init_adapter)
2038 return false;
2039
2040 if (ppsc->swrf_processing)
2041 return false;
2042
2043 spin_lock(&rtlpriv->locks.rf_ps_lock);
2044 if (ppsc->rfchange_inprogress) {
2045 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2046 return false;
2047 } else {
2048 ppsc->rfchange_inprogress = true;
2049 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2050 }
2051
2052 cur_rfstate = ppsc->rfpwr_state;
2053
2054 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2055 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2056
2057 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2058
2059 if (rtlphy->polarity_ctl)
2060 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2061 else
2062 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2063
2064 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
2065 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2066 "GPIOChangeRF - HW Radio ON, RF ON\n");
2067
2068 e_rfpowerstate_toset = ERFON;
2069 ppsc->hwradiooff = false;
2070 actuallyset = true;
2071 } else if ((ppsc->hwradiooff == false)
2072 && (e_rfpowerstate_toset == ERFOFF)) {
2073 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2074 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2075
2076 e_rfpowerstate_toset = ERFOFF;
2077 ppsc->hwradiooff = true;
2078 actuallyset = true;
2079 }
2080
2081 if (actuallyset) {
2082 spin_lock(&rtlpriv->locks.rf_ps_lock);
2083 ppsc->rfchange_inprogress = false;
2084 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2085 } else {
2086 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2087 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2088
2089 spin_lock(&rtlpriv->locks.rf_ps_lock);
2090 ppsc->rfchange_inprogress = false;
2091 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2092 }
2093
2094 *valid = 1;
2095 return !ppsc->hwradiooff;
2096}
2097
2098void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2099 u8 *p_macaddr, bool is_group, u8 enc_algo,
2100 bool is_wepkey, bool clear_all)
2101{
2102 struct rtl_priv *rtlpriv = rtl_priv(hw);
2103 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2104 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2105 u8 *macaddr = p_macaddr;
2106 u32 entry_id = 0;
2107 bool is_pairwise = false;
2108 static u8 cam_const_addr[4][6] = {
2109 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2110 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2111 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2112 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2113 };
2114 static u8 cam_const_broad[] = {
2115 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2116 };
2117
2118 if (clear_all) {
2119 u8 idx = 0;
2120 u8 cam_offset = 0;
2121 u8 clear_number = 5;
2122
2123 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2124
2125 for (idx = 0; idx < clear_number; idx++) {
2126 rtl_cam_mark_invalid(hw, cam_offset + idx);
2127 rtl_cam_empty_entry(hw, cam_offset + idx);
2128
2129 if (idx < 5) {
2130 memset(rtlpriv->sec.key_buf[idx], 0,
2131 MAX_KEY_LEN);
2132 rtlpriv->sec.key_len[idx] = 0;
2133 }
2134 }
2135 } else {
2136 switch (enc_algo) {
2137 case WEP40_ENCRYPTION:
2138 enc_algo = CAM_WEP40;
2139 break;
2140 case WEP104_ENCRYPTION:
2141 enc_algo = CAM_WEP104;
2142 break;
2143 case TKIP_ENCRYPTION:
2144 enc_algo = CAM_TKIP;
2145 break;
2146 case AESCCMP_ENCRYPTION:
2147 enc_algo = CAM_AES;
2148 break;
2149 default:
2150 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2151 "switch case not processed\n");
2152 enc_algo = CAM_TKIP;
2153 break;
2154 }
2155
2156 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2157 macaddr = cam_const_addr[key_index];
2158 entry_id = key_index;
2159 } else {
2160 if (is_group) {
2161 macaddr = cam_const_broad;
2162 entry_id = key_index;
2163 } else {
2164 if (mac->opmode == NL80211_IFTYPE_AP) {
2165 entry_id = rtl_cam_get_free_entry(hw,
2166 macaddr);
2167 if (entry_id >= TOTAL_CAM_ENTRY) {
2168 RT_TRACE(rtlpriv, COMP_SEC,
2169 DBG_EMERG,
2170 "Can not find free hw security cam entry\n");
2171 return;
2172 }
2173 } else {
2174 entry_id = CAM_PAIRWISE_KEY_POSITION;
2175 }
2176
2177 key_index = PAIRWISE_KEYIDX;
2178 is_pairwise = true;
2179 }
2180 }
2181
2182 if (rtlpriv->sec.key_len[key_index] == 0) {
2183 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2184 "delete one entry, entry_id is %d\n",
2185 entry_id);
2186 if (mac->opmode == NL80211_IFTYPE_AP)
2187 rtl_cam_del_entry(hw, p_macaddr);
2188 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2189 } else {
2190 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2191 "add one entry\n");
2192 if (is_pairwise) {
2193 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2194 "set Pairwiase key\n");
2195
2196 rtl_cam_add_one_entry(hw, macaddr, key_index,
2197 entry_id, enc_algo,
2198 CAM_CONFIG_NO_USEDK,
2199 rtlpriv->sec.key_buf[key_index]);
2200 } else {
2201 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2202 "set group key\n");
2203
2204 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2205 rtl_cam_add_one_entry(hw,
2206 rtlefuse->dev_addr,
2207 PAIRWISE_KEYIDX,
2208 CAM_PAIRWISE_KEY_POSITION,
2209 enc_algo,
2210 CAM_CONFIG_NO_USEDK,
2211 rtlpriv->sec.key_buf
2212 [entry_id]);
2213 }
2214
2215 rtl_cam_add_one_entry(hw, macaddr, key_index,
2216 entry_id, enc_algo,
2217 CAM_CONFIG_NO_USEDK,
2218 rtlpriv->sec.key_buf[entry_id]);
2219 }
2220
2221 }
2222 }
2223}
2224
2225static void rtl8723ae_bt_var_init(struct ieee80211_hw *hw)
2226{
2227 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2228 struct rtl_priv *rtlpriv = rtl_priv(hw);
2229
2230 pcipriv->bt_coexist.bt_coexistence =
2231 pcipriv->bt_coexist.eeprom_bt_coexist;
2232 pcipriv->bt_coexist.bt_ant_num =
2233 pcipriv->bt_coexist.eeprom_bt_ant_num;
2234 pcipriv->bt_coexist.bt_coexist_type =
2235 pcipriv->bt_coexist.eeprom_bt_type;
2236
2237 pcipriv->bt_coexist.bt_ant_isolation =
2238 pcipriv->bt_coexist.eeprom_bt_ant_isol;
2239
2240 pcipriv->bt_coexist.bt_radio_shared_type =
2241 pcipriv->bt_coexist.eeprom_bt_radio_shared;
2242
2243 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2244 "BT Coexistance = 0x%x\n",
2245 pcipriv->bt_coexist.bt_coexistence);
2246
2247 if (pcipriv->bt_coexist.bt_coexistence) {
2248 pcipriv->bt_coexist.bt_busy_traffic = false;
2249 pcipriv->bt_coexist.bt_traffic_mode_set = false;
2250 pcipriv->bt_coexist.bt_non_traffic_mode_set = false;
2251
2252 pcipriv->bt_coexist.cstate = 0;
2253 pcipriv->bt_coexist.previous_state = 0;
2254
2255 if (pcipriv->bt_coexist.bt_ant_num == ANT_X2) {
2256 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2257 "BlueTooth BT_Ant_Num = Antx2\n");
2258 } else if (pcipriv->bt_coexist.bt_ant_num == ANT_X1) {
2259 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2260 "BlueTooth BT_Ant_Num = Antx1\n");
2261 }
2262
2263 switch (pcipriv->bt_coexist.bt_coexist_type) {
2264 case BT_2WIRE:
2265 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2266 "BlueTooth BT_CoexistType = BT_2Wire\n");
2267 break;
2268 case BT_ISSC_3WIRE:
2269 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2270 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2271 break;
2272 case BT_ACCEL:
2273 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2274 "BlueTooth BT_CoexistType = BT_ACCEL\n");
2275 break;
2276 case BT_CSR_BC4:
2277 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2278 "BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2279 break;
2280 case BT_CSR_BC8:
2281 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2282 "BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2283 break;
2284 case BT_RTL8756:
2285 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2286 "BlueTooth BT_CoexistType = BT_RTL8756\n");
2287 break;
2288 default:
2289 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2290 "BlueTooth BT_CoexistType = Unknown\n");
2291 break;
2292 }
2293 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2294 "BlueTooth BT_Ant_isolation = %d\n",
2295 pcipriv->bt_coexist.bt_ant_isolation);
2296 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2297 "BT_RadioSharedType = 0x%x\n",
2298 pcipriv->bt_coexist.bt_radio_shared_type);
2299 pcipriv->bt_coexist.bt_active_zero_cnt = 0;
2300 pcipriv->bt_coexist.cur_bt_disabled = false;
2301 pcipriv->bt_coexist.pre_bt_disabled = false;
2302 }
2303}
2304
2305void rtl8723ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2306 bool auto_load_fail, u8 *hwinfo)
2307{
2308 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2309 struct rtl_priv *rtlpriv = rtl_priv(hw);
2310 u8 value;
2311 u32 tmpu_32;
2312
2313 if (!auto_load_fail) {
2314 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2315 if (tmpu_32 & BIT(18))
2316 pcipriv->bt_coexist.eeprom_bt_coexist = 1;
2317 else
2318 pcipriv->bt_coexist.eeprom_bt_coexist = 0;
2319 value = hwinfo[RF_OPTION4];
2320 pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A;
2321 pcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2322 pcipriv->bt_coexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2323 pcipriv->bt_coexist.eeprom_bt_radio_shared =
2324 ((value & 0x20) >> 5);
2325 } else {
2326 pcipriv->bt_coexist.eeprom_bt_coexist = 0;
2327 pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A;
2328 pcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2329 pcipriv->bt_coexist.eeprom_bt_ant_isol = 0;
2330 pcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2331 }
2332
2333 rtl8723ae_bt_var_init(hw);
2334}
2335
2336void rtl8723ae_bt_reg_init(struct ieee80211_hw *hw)
2337{
2338 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2339
2340 /* 0:Low, 1:High, 2:From Efuse. */
2341 pcipriv->bt_coexist.reg_bt_iso = 2;
2342 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2343 pcipriv->bt_coexist.reg_bt_sco = 3;
2344 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2345 pcipriv->bt_coexist.reg_bt_sco = 0;
2346}
2347
2348
2349void rtl8723ae_bt_hw_init(struct ieee80211_hw *hw)
2350{
2351}
2352
2353void rtl8723ae_suspend(struct ieee80211_hw *hw)
2354{
2355}
2356
2357void rtl8723ae_resume(struct ieee80211_hw *hw)
2358{
2359}
2360
2361/* Turn on AAP (RCR:bit 0) for promicuous mode. */
2362void rtl8723ae_allow_all_destaddr(struct ieee80211_hw *hw,
2363 bool allow_all_da, bool write_into_reg)
2364{
2365 struct rtl_priv *rtlpriv = rtl_priv(hw);
2366 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2367
2368 if (allow_all_da) /* Set BIT0 */
2369 rtlpci->receive_config |= RCR_AAP;
2370 else /* Clear BIT0 */
2371 rtlpci->receive_config &= ~RCR_AAP;
2372
2373 if (write_into_reg)
2374 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2375
2376
2377 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2378 "receive_config=0x%08X, write_into_reg=%d\n",
2379 rtlpci->receive_config, write_into_reg);
2380}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-27 19:10:51 -0500