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-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/Makefile14
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/def.h62
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/dm.c113
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/dm.h32
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/hw.c2507
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/hw.h117
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/led.c142
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/led.h37
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/mac.c1144
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/mac.h180
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/phy.c607
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/phy.h50
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/reg.h30
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/rf.c493
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/rf.h51
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/sw.c357
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/sw.h53
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/table.c1888
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/table.h71
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/trx.c687
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/trx.h433
21 files changed, 9068 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/Makefile b/drivers/net/wireless/rtlwifi/rtl8192cu/Makefile
new file mode 100644
index 000000000000..ad2de6b839ef
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/Makefile
@@ -0,0 +1,14 @@
1rtl8192cu-objs := \
2 dm.o \
3 hw.o \
4 led.o \
5 mac.o \
6 phy.o \
7 rf.o \
8 sw.o \
9 table.o \
10 trx.o
11
12obj-$(CONFIG_RTL8192CU) += rtl8192cu.o
13
14ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/def.h b/drivers/net/wireless/rtlwifi/rtl8192cu/def.h
new file mode 100644
index 000000000000..c54940ea72fe
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/def.h
@@ -0,0 +1,62 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../rtl8192ce/def.h"
31
32/*-------------------------------------------------------------------------
33 * Chip specific
34 *-------------------------------------------------------------------------*/
35#define CHIP_8723 BIT(2) /* RTL8723 With BT feature */
36#define CHIP_8723_DRV_REV BIT(3) /* RTL8723 Driver Revised */
37#define NORMAL_CHIP BIT(4)
38#define CHIP_VENDOR_UMC BIT(5)
39#define CHIP_VENDOR_UMC_B_CUT BIT(6)
40
41#define IS_NORMAL_CHIP(version) \
42 (((version) & NORMAL_CHIP) ? true : false)
43
44#define IS_8723_SERIES(version) \
45 (((version) & CHIP_8723) ? true : false)
46
47#define IS_92C_1T2R(version) \
48 (((version) & CHIP_92C) && ((version) & CHIP_92C_1T2R))
49
50#define IS_VENDOR_UMC(version) \
51 (((version) & CHIP_VENDOR_UMC) ? true : false)
52
53#define IS_VENDOR_UMC_A_CUT(version) \
54 (((version) & CHIP_VENDOR_UMC) ? (((version) & (BIT(6) | BIT(7))) ? \
55 false : true) : false)
56
57#define IS_VENDOR_8723_A_CUT(version) \
58 (((version) & CHIP_VENDOR_UMC) ? (((version) & (BIT(6))) ? \
59 false : true) : false)
60
61#define CHIP_BONDING_92C_1T2R 0x1
62#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/dm.c b/drivers/net/wireless/rtlwifi/rtl8192cu/dm.c
new file mode 100644
index 000000000000..f311baee668d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/dm.c
@@ -0,0 +1,113 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../base.h"
32#include "reg.h"
33#include "def.h"
34#include "phy.h"
35#include "dm.h"
36
37void rtl92cu_dm_dynamic_txpower(struct ieee80211_hw *hw)
38{
39 struct rtl_priv *rtlpriv = rtl_priv(hw);
40 struct rtl_phy *rtlphy = &(rtlpriv->phy);
41 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
42 long undecorated_smoothed_pwdb;
43
44 if (!rtlpriv->dm.dynamic_txpower_enable)
45 return;
46
47 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
48 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
49 return;
50 }
51
52 if ((mac->link_state < MAC80211_LINKED) &&
53 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
54 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
55 ("Not connected to any\n"));
56
57 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
58
59 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
60 return;
61 }
62
63 if (mac->link_state >= MAC80211_LINKED) {
64 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
65 undecorated_smoothed_pwdb =
66 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
67 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
68 ("AP Client PWDB = 0x%lx\n",
69 undecorated_smoothed_pwdb));
70 } else {
71 undecorated_smoothed_pwdb =
72 rtlpriv->dm.undecorated_smoothed_pwdb;
73 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
74 ("STA Default Port PWDB = 0x%lx\n",
75 undecorated_smoothed_pwdb));
76 }
77 } else {
78 undecorated_smoothed_pwdb =
79 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
80
81 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
82 ("AP Ext Port PWDB = 0x%lx\n",
83 undecorated_smoothed_pwdb));
84 }
85
86 if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
87 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
88 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
89 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
90 } else if ((undecorated_smoothed_pwdb <
91 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
92 (undecorated_smoothed_pwdb >=
93 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
94
95 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
96 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
97 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
98 } else if (undecorated_smoothed_pwdb <
99 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
100 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
101 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
102 ("TXHIGHPWRLEVEL_NORMAL\n"));
103 }
104
105 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
106 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
107 ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
108 rtlphy->current_channel));
109 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
110 }
111
112 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
113}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/dm.h b/drivers/net/wireless/rtlwifi/rtl8192cu/dm.h
new file mode 100644
index 000000000000..7f966c666b5a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/dm.h
@@ -0,0 +1,32 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../rtl8192ce/dm.h"
31
32void rtl92cu_dm_dynamic_txpower(struct ieee80211_hw *hw);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
new file mode 100644
index 000000000000..52e2af58c1ed
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
@@ -0,0 +1,2507 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../cam.h"
34#include "../ps.h"
35#include "../usb.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "mac.h"
40#include "dm.h"
41#include "hw.h"
42#include "../rtl8192ce/hw.h"
43#include "trx.h"
44#include "led.h"
45#include "table.h"
46
47static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
48{
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 struct rtl_phy *rtlphy = &(rtlpriv->phy);
51 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
52
53 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
54 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
55 if (IS_HIGHT_PA(rtlefuse->board_type)) {
56 rtlphy->hwparam_tables[PHY_REG_PG].length =
57 RTL8192CUPHY_REG_Array_PG_HPLength;
58 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
59 RTL8192CUPHY_REG_Array_PG_HP;
60 } else {
61 rtlphy->hwparam_tables[PHY_REG_PG].length =
62 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
63 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
64 RTL8192CUPHY_REG_ARRAY_PG;
65 }
66 /* 2T */
67 rtlphy->hwparam_tables[PHY_REG_2T].length =
68 RTL8192CUPHY_REG_2TARRAY_LENGTH;
69 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
70 RTL8192CUPHY_REG_2TARRAY;
71 rtlphy->hwparam_tables[RADIOA_2T].length =
72 RTL8192CURADIOA_2TARRAYLENGTH;
73 rtlphy->hwparam_tables[RADIOA_2T].pdata =
74 RTL8192CURADIOA_2TARRAY;
75 rtlphy->hwparam_tables[RADIOB_2T].length =
76 RTL8192CURADIOB_2TARRAYLENGTH;
77 rtlphy->hwparam_tables[RADIOB_2T].pdata =
78 RTL8192CU_RADIOB_2TARRAY;
79 rtlphy->hwparam_tables[AGCTAB_2T].length =
80 RTL8192CUAGCTAB_2TARRAYLENGTH;
81 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
82 RTL8192CUAGCTAB_2TARRAY;
83 /* 1T */
84 if (IS_HIGHT_PA(rtlefuse->board_type)) {
85 rtlphy->hwparam_tables[PHY_REG_1T].length =
86 RTL8192CUPHY_REG_1T_HPArrayLength;
87 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
88 RTL8192CUPHY_REG_1T_HPArray;
89 rtlphy->hwparam_tables[RADIOA_1T].length =
90 RTL8192CURadioA_1T_HPArrayLength;
91 rtlphy->hwparam_tables[RADIOA_1T].pdata =
92 RTL8192CURadioA_1T_HPArray;
93 rtlphy->hwparam_tables[RADIOB_1T].length =
94 RTL8192CURADIOB_1TARRAYLENGTH;
95 rtlphy->hwparam_tables[RADIOB_1T].pdata =
96 RTL8192CU_RADIOB_1TARRAY;
97 rtlphy->hwparam_tables[AGCTAB_1T].length =
98 RTL8192CUAGCTAB_1T_HPArrayLength;
99 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
100 Rtl8192CUAGCTAB_1T_HPArray;
101 } else {
102 rtlphy->hwparam_tables[PHY_REG_1T].length =
103 RTL8192CUPHY_REG_1TARRAY_LENGTH;
104 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
105 RTL8192CUPHY_REG_1TARRAY;
106 rtlphy->hwparam_tables[RADIOA_1T].length =
107 RTL8192CURADIOA_1TARRAYLENGTH;
108 rtlphy->hwparam_tables[RADIOA_1T].pdata =
109 RTL8192CU_RADIOA_1TARRAY;
110 rtlphy->hwparam_tables[RADIOB_1T].length =
111 RTL8192CURADIOB_1TARRAYLENGTH;
112 rtlphy->hwparam_tables[RADIOB_1T].pdata =
113 RTL8192CU_RADIOB_1TARRAY;
114 rtlphy->hwparam_tables[AGCTAB_1T].length =
115 RTL8192CUAGCTAB_1TARRAYLENGTH;
116 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
117 RTL8192CUAGCTAB_1TARRAY;
118 }
119}
120
121static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
122 bool autoload_fail,
123 u8 *hwinfo)
124{
125 struct rtl_priv *rtlpriv = rtl_priv(hw);
126 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
127 u8 rf_path, index, tempval;
128 u16 i;
129
130 for (rf_path = 0; rf_path < 2; rf_path++) {
131 for (i = 0; i < 3; i++) {
132 if (!autoload_fail) {
133 rtlefuse->
134 eeprom_chnlarea_txpwr_cck[rf_path][i] =
135 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
136 rtlefuse->
137 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
138 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
139 i];
140 } else {
141 rtlefuse->
142 eeprom_chnlarea_txpwr_cck[rf_path][i] =
143 EEPROM_DEFAULT_TXPOWERLEVEL;
144 rtlefuse->
145 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
146 EEPROM_DEFAULT_TXPOWERLEVEL;
147 }
148 }
149 }
150 for (i = 0; i < 3; i++) {
151 if (!autoload_fail)
152 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
153 else
154 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
155 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
156 (tempval & 0xf);
157 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
158 ((tempval & 0xf0) >> 4);
159 }
160 for (rf_path = 0; rf_path < 2; rf_path++)
161 for (i = 0; i < 3; i++)
162 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
163 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
164 i, rtlefuse->
165 eeprom_chnlarea_txpwr_cck[rf_path][i]));
166 for (rf_path = 0; rf_path < 2; rf_path++)
167 for (i = 0; i < 3; i++)
168 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
169 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
170 rf_path, i,
171 rtlefuse->
172 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
173 for (rf_path = 0; rf_path < 2; rf_path++)
174 for (i = 0; i < 3; i++)
175 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
176 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
177 rf_path, i,
178 rtlefuse->
179 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
180 [i]));
181 for (rf_path = 0; rf_path < 2; rf_path++) {
182 for (i = 0; i < 14; i++) {
183 index = _rtl92c_get_chnl_group((u8) i);
184 rtlefuse->txpwrlevel_cck[rf_path][i] =
185 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
186 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
187 rtlefuse->
188 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
189 if ((rtlefuse->
190 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
191 rtlefuse->
192 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
193 > 0) {
194 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
195 rtlefuse->
196 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
197 [index] - rtlefuse->
198 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
199 [index];
200 } else {
201 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
202 }
203 }
204 for (i = 0; i < 14; i++) {
205 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
206 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
207 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
208 rtlefuse->txpwrlevel_cck[rf_path][i],
209 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
210 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
211 }
212 }
213 for (i = 0; i < 3; i++) {
214 if (!autoload_fail) {
215 rtlefuse->eeprom_pwrlimit_ht40[i] =
216 hwinfo[EEPROM_TXPWR_GROUP + i];
217 rtlefuse->eeprom_pwrlimit_ht20[i] =
218 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
219 } else {
220 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
221 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
222 }
223 }
224 for (rf_path = 0; rf_path < 2; rf_path++) {
225 for (i = 0; i < 14; i++) {
226 index = _rtl92c_get_chnl_group((u8) i);
227 if (rf_path == RF90_PATH_A) {
228 rtlefuse->pwrgroup_ht20[rf_path][i] =
229 (rtlefuse->eeprom_pwrlimit_ht20[index]
230 & 0xf);
231 rtlefuse->pwrgroup_ht40[rf_path][i] =
232 (rtlefuse->eeprom_pwrlimit_ht40[index]
233 & 0xf);
234 } else if (rf_path == RF90_PATH_B) {
235 rtlefuse->pwrgroup_ht20[rf_path][i] =
236 ((rtlefuse->eeprom_pwrlimit_ht20[index]
237 & 0xf0) >> 4);
238 rtlefuse->pwrgroup_ht40[rf_path][i] =
239 ((rtlefuse->eeprom_pwrlimit_ht40[index]
240 & 0xf0) >> 4);
241 }
242 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
243 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
244 rf_path, i,
245 rtlefuse->pwrgroup_ht20[rf_path][i]));
246 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
247 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
248 rf_path, i,
249 rtlefuse->pwrgroup_ht40[rf_path][i]));
250 }
251 }
252 for (i = 0; i < 14; i++) {
253 index = _rtl92c_get_chnl_group((u8) i);
254 if (!autoload_fail)
255 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
256 else
257 tempval = EEPROM_DEFAULT_HT20_DIFF;
258 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
259 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
260 ((tempval >> 4) & 0xF);
261 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
262 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
263 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
264 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
265 index = _rtl92c_get_chnl_group((u8) i);
266 if (!autoload_fail)
267 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
268 else
269 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
270 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
271 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
272 ((tempval >> 4) & 0xF);
273 }
274 rtlefuse->legacy_ht_txpowerdiff =
275 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
276 for (i = 0; i < 14; i++)
277 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
278 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
279 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
280 for (i = 0; i < 14; i++)
281 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
282 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
283 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
284 for (i = 0; i < 14; i++)
285 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
286 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
287 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
288 for (i = 0; i < 14; i++)
289 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
290 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
291 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
292 if (!autoload_fail)
293 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
294 else
295 rtlefuse->eeprom_regulatory = 0;
296 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
297 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
298 if (!autoload_fail) {
299 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
300 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
301 } else {
302 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
303 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
304 }
305 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
306 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
307 rtlefuse->eeprom_tssi[RF90_PATH_A],
308 rtlefuse->eeprom_tssi[RF90_PATH_B]));
309 if (!autoload_fail)
310 tempval = hwinfo[EEPROM_THERMAL_METER];
311 else
312 tempval = EEPROM_DEFAULT_THERMALMETER;
313 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
314 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
315 rtlefuse->eeprom_thermalmeter > 0x1c)
316 rtlefuse->eeprom_thermalmeter = 0x12;
317 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
318 rtlefuse->apk_thermalmeterignore = true;
319 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
320 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
321 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
322}
323
324static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
325{
326 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
327 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
328 u8 boardType;
329
330 if (IS_NORMAL_CHIP(rtlhal->version)) {
331 boardType = ((contents[EEPROM_RF_OPT1]) &
332 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
333 } else {
334 boardType = contents[EEPROM_RF_OPT4];
335 boardType &= BOARD_TYPE_TEST_MASK;
336 }
337 rtlefuse->board_type = boardType;
338 if (IS_HIGHT_PA(rtlefuse->board_type))
339 rtlefuse->external_pa = 1;
340 printk(KERN_INFO "rtl8192cu: Board Type %x\n", rtlefuse->board_type);
341
342#ifdef CONFIG_ANTENNA_DIVERSITY
343 /* Antenna Diversity setting. */
344 if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
345 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
346 else
347 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
348
349 printk(KERN_INFO "rtl8192cu: Antenna Config %x\n",
350 rtl_efuse->antenna_cfg);
351#endif
352}
353
354#ifdef CONFIG_BT_COEXIST
355static void _update_bt_param(_adapter *padapter)
356{
357 struct btcoexist_priv *pbtpriv = &(padapter->halpriv.bt_coexist);
358 struct registry_priv *registry_par = &padapter->registrypriv;
359 if (2 != registry_par->bt_iso) {
360 /* 0:Low, 1:High, 2:From Efuse */
361 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
362 }
363 if (registry_par->bt_sco == 1) {
364 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
365 * 5.OtherBusy */
366 pbtpriv->BT_Service = BT_OtherAction;
367 } else if (registry_par->bt_sco == 2) {
368 pbtpriv->BT_Service = BT_SCO;
369 } else if (registry_par->bt_sco == 4) {
370 pbtpriv->BT_Service = BT_Busy;
371 } else if (registry_par->bt_sco == 5) {
372 pbtpriv->BT_Service = BT_OtherBusy;
373 } else {
374 pbtpriv->BT_Service = BT_Idle;
375 }
376 pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
377 pbtpriv->bCOBT = _TRUE;
378 pbtpriv->BtEdcaUL = 0;
379 pbtpriv->BtEdcaDL = 0;
380 pbtpriv->BtRssiState = 0xff;
381 pbtpriv->bInitSet = _FALSE;
382 pbtpriv->bBTBusyTraffic = _FALSE;
383 pbtpriv->bBTTrafficModeSet = _FALSE;
384 pbtpriv->bBTNonTrafficModeSet = _FALSE;
385 pbtpriv->CurrentState = 0;
386 pbtpriv->PreviousState = 0;
387 printk(KERN_INFO "rtl8192cu: BT Coexistance = %s\n",
388 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
389 if (pbtpriv->BT_Coexist) {
390 if (pbtpriv->BT_Ant_Num == Ant_x2)
391 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
392 "Ant_Num = Antx2\n");
393 else if (pbtpriv->BT_Ant_Num == Ant_x1)
394 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
395 "Ant_Num = Antx1\n");
396 switch (pbtpriv->BT_CoexistType) {
397 case BT_2Wire:
398 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
399 "CoexistType = BT_2Wire\n");
400 break;
401 case BT_ISSC_3Wire:
402 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
403 "CoexistType = BT_ISSC_3Wire\n");
404 break;
405 case BT_Accel:
406 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
407 "CoexistType = BT_Accel\n");
408 break;
409 case BT_CSR_BC4:
410 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
411 "CoexistType = BT_CSR_BC4\n");
412 break;
413 case BT_CSR_BC8:
414 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
415 "CoexistType = BT_CSR_BC8\n");
416 break;
417 case BT_RTL8756:
418 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
419 "CoexistType = BT_RTL8756\n");
420 break;
421 default:
422 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
423 "CoexistType = Unknown\n");
424 break;
425 }
426 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Ant_isolation = %d\n",
427 pbtpriv->BT_Ant_isolation);
428 switch (pbtpriv->BT_Service) {
429 case BT_OtherAction:
430 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
431 "BT_OtherAction\n");
432 break;
433 case BT_SCO:
434 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
435 "BT_SCO\n");
436 break;
437 case BT_Busy:
438 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
439 "BT_Busy\n");
440 break;
441 case BT_OtherBusy:
442 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
443 "BT_OtherBusy\n");
444 break;
445 default:
446 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
447 "BT_Idle\n");
448 break;
449 }
450 printk(KERN_INFO "rtl8192cu: BT_RadioSharedType = 0x%x\n",
451 pbtpriv->BT_RadioSharedType);
452 }
453}
454
455#define GET_BT_COEXIST(priv) (&priv->bt_coexist)
456
457static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
458 u8 *contents,
459 bool bautoloadfailed);
460{
461 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
462 bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
463 struct btcoexist_priv *pbtpriv = &pHalData->bt_coexist;
464 u8 rf_opt4;
465
466 _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
467 if (AutoloadFail) {
468 pbtpriv->BT_Coexist = _FALSE;
469 pbtpriv->BT_CoexistType = BT_2Wire;
470 pbtpriv->BT_Ant_Num = Ant_x2;
471 pbtpriv->BT_Ant_isolation = 0;
472 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
473 return;
474 }
475 if (isNormal) {
476 if (pHalData->BoardType == BOARD_USB_COMBO)
477 pbtpriv->BT_Coexist = _TRUE;
478 else
479 pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
480 0x20) >> 5); /* bit[5] */
481 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
482 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
483 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
484 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
485 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
486 } else {
487 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
488 _TRUE : _FALSE;
489 }
490 _update_bt_param(Adapter);
491}
492#endif
493
494static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
495{
496 struct rtl_priv *rtlpriv = rtl_priv(hw);
497 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
498 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
499 u16 i, usvalue;
500 u8 hwinfo[HWSET_MAX_SIZE] = {0};
501 u16 eeprom_id;
502
503 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
504 rtl_efuse_shadow_map_update(hw);
505 memcpy((void *)hwinfo,
506 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
507 HWSET_MAX_SIZE);
508 } else if (rtlefuse->epromtype == EEPROM_93C46) {
509 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
510 ("RTL819X Not boot from eeprom, check it !!"));
511 }
512 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
513 hwinfo, HWSET_MAX_SIZE);
514 eeprom_id = *((u16 *)&hwinfo[0]);
515 if (eeprom_id != RTL8190_EEPROM_ID) {
516 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
517 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
518 rtlefuse->autoload_failflag = true;
519 } else {
520 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
521 rtlefuse->autoload_failflag = false;
522 }
523 if (rtlefuse->autoload_failflag == true)
524 return;
525 for (i = 0; i < 6; i += 2) {
526 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
527 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
528 }
529 printk(KERN_INFO "rtl8192cu: MAC address: %pM\n", rtlefuse->dev_addr);
530 _rtl92cu_read_txpower_info_from_hwpg(hw,
531 rtlefuse->autoload_failflag, hwinfo);
532 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
533 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
534 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
535 (" VID = 0x%02x PID = 0x%02x\n",
536 rtlefuse->eeprom_vid, rtlefuse->eeprom_did));
537 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
538 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
539 rtlefuse->txpwr_fromeprom = true;
540 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
541 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
542 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
543 if (rtlhal->oem_id == RT_CID_DEFAULT) {
544 switch (rtlefuse->eeprom_oemid) {
545 case EEPROM_CID_DEFAULT:
546 if (rtlefuse->eeprom_did == 0x8176) {
547 if ((rtlefuse->eeprom_svid == 0x103C &&
548 rtlefuse->eeprom_smid == 0x1629))
549 rtlhal->oem_id = RT_CID_819x_HP;
550 else
551 rtlhal->oem_id = RT_CID_DEFAULT;
552 } else {
553 rtlhal->oem_id = RT_CID_DEFAULT;
554 }
555 break;
556 case EEPROM_CID_TOSHIBA:
557 rtlhal->oem_id = RT_CID_TOSHIBA;
558 break;
559 case EEPROM_CID_QMI:
560 rtlhal->oem_id = RT_CID_819x_QMI;
561 break;
562 case EEPROM_CID_WHQL:
563 default:
564 rtlhal->oem_id = RT_CID_DEFAULT;
565 break;
566 }
567 }
568 _rtl92cu_read_board_type(hw, hwinfo);
569#ifdef CONFIG_BT_COEXIST
570 _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
571 rtlefuse->autoload_failflag);
572#endif
573}
574
575static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
576{
577 struct rtl_priv *rtlpriv = rtl_priv(hw);
578 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
579 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
580
581 switch (rtlhal->oem_id) {
582 case RT_CID_819x_HP:
583 usb_priv->ledctl.led_opendrain = true;
584 break;
585 case RT_CID_819x_Lenovo:
586 case RT_CID_DEFAULT:
587 case RT_CID_TOSHIBA:
588 case RT_CID_CCX:
589 case RT_CID_819x_Acer:
590 case RT_CID_WHQL:
591 default:
592 break;
593 }
594 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
595 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
596}
597
598void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
599{
600
601 struct rtl_priv *rtlpriv = rtl_priv(hw);
602 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
603 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
604 u8 tmp_u1b;
605
606 if (!IS_NORMAL_CHIP(rtlhal->version))
607 return;
608 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
609 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
610 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
611 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from %s\n",
612 (tmp_u1b & BOOT_FROM_EEPROM) ? "EERROM" : "EFUSE"));
613 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
614 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload %s\n",
615 (tmp_u1b & EEPROM_EN) ? "OK!!" : "ERR!!"));
616 _rtl92cu_read_adapter_info(hw);
617 _rtl92cu_hal_customized_behavior(hw);
618 return;
619}
620
621static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
622{
623 struct rtl_priv *rtlpriv = rtl_priv(hw);
624 int status = 0;
625 u16 value16;
626 u8 value8;
627 /* polling autoload done. */
628 u32 pollingCount = 0;
629
630 do {
631 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
632 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
633 ("Autoload Done!\n"));
634 break;
635 }
636 if (pollingCount++ > 100) {
637 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
638 ("Failed to polling REG_APS_FSMCO[PFM_ALDN]"
639 " done!\n"));
640 return -ENODEV;
641 }
642 } while (true);
643 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
644 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
645 /* Power on when re-enter from IPS/Radio off/card disable */
646 /* enable SPS into PWM mode */
647 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
648 udelay(100);
649 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
650 if (0 == (value8 & LDV12_EN)) {
651 value8 |= LDV12_EN;
652 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
653 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
654 (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",
655 value8));
656 udelay(100);
657 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
658 value8 &= ~ISO_MD2PP;
659 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
660 }
661 /* auto enable WLAN */
662 pollingCount = 0;
663 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
664 value16 |= APFM_ONMAC;
665 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
666 do {
667 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
668 printk(KERN_INFO "rtl8192cu: MAC auto ON okay!\n");
669 break;
670 }
671 if (pollingCount++ > 100) {
672 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
673 ("Failed to polling REG_APS_FSMCO[APFM_ONMAC]"
674 " done!\n"));
675 return -ENODEV;
676 }
677 } while (true);
678 /* Enable Radio ,GPIO ,and LED function */
679 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
680 /* release RF digital isolation */
681 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
682 value16 &= ~ISO_DIOR;
683 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
684 /* Reconsider when to do this operation after asking HWSD. */
685 pollingCount = 0;
686 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
687 REG_APSD_CTRL) & ~BIT(6)));
688 do {
689 pollingCount++;
690 } while ((pollingCount < 200) &&
691 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
692 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
693 value16 = rtl_read_word(rtlpriv, REG_CR);
694 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
695 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
696 rtl_write_word(rtlpriv, REG_CR, value16);
697 return status;
698}
699
700static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
701 bool wmm_enable,
702 u8 out_ep_num,
703 u8 queue_sel)
704{
705 struct rtl_priv *rtlpriv = rtl_priv(hw);
706 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
707 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
708 u32 outEPNum = (u32)out_ep_num;
709 u32 numHQ = 0;
710 u32 numLQ = 0;
711 u32 numNQ = 0;
712 u32 numPubQ;
713 u32 value32;
714 u8 value8;
715 u32 txQPageNum, txQPageUnit, txQRemainPage;
716
717 if (!wmm_enable) {
718 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
719 CHIP_A_PAGE_NUM_PUBQ;
720 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
721
722 txQPageUnit = txQPageNum/outEPNum;
723 txQRemainPage = txQPageNum % outEPNum;
724 if (queue_sel & TX_SELE_HQ)
725 numHQ = txQPageUnit;
726 if (queue_sel & TX_SELE_LQ)
727 numLQ = txQPageUnit;
728 /* HIGH priority queue always present in the configuration of
729 * 2 out-ep. Remainder pages have assigned to High queue */
730 if ((outEPNum > 1) && (txQRemainPage))
731 numHQ += txQRemainPage;
732 /* NOTE: This step done before writting REG_RQPN. */
733 if (isChipN) {
734 if (queue_sel & TX_SELE_NQ)
735 numNQ = txQPageUnit;
736 value8 = (u8)_NPQ(numNQ);
737 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
738 }
739 } else {
740 /* for WMM ,number of out-ep must more than or equal to 2! */
741 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
742 WMM_CHIP_A_PAGE_NUM_PUBQ;
743 if (queue_sel & TX_SELE_HQ) {
744 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
745 WMM_CHIP_A_PAGE_NUM_HPQ;
746 }
747 if (queue_sel & TX_SELE_LQ) {
748 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
749 WMM_CHIP_A_PAGE_NUM_LPQ;
750 }
751 /* NOTE: This step done before writting REG_RQPN. */
752 if (isChipN) {
753 if (queue_sel & TX_SELE_NQ)
754 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
755 value8 = (u8)_NPQ(numNQ);
756 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
757 }
758 }
759 /* TX DMA */
760 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
761 rtl_write_dword(rtlpriv, REG_RQPN, value32);
762}
763
764static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
765{
766 struct rtl_priv *rtlpriv = rtl_priv(hw);
767 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
768 u8 txpktbuf_bndy;
769 u8 value8;
770
771 if (!wmm_enable)
772 txpktbuf_bndy = TX_PAGE_BOUNDARY;
773 else /* for WMM */
774 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
775 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
776 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
777 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
778 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
779 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
780 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
781 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
782 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
783 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
784 rtl_write_byte(rtlpriv, REG_PBP, value8);
785}
786
787static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
788 u16 bkQ, u16 viQ, u16 voQ,
789 u16 mgtQ, u16 hiQ)
790{
791 struct rtl_priv *rtlpriv = rtl_priv(hw);
792 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
793
794 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
795 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
796 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
797 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
798}
799
800static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
801 bool wmm_enable,
802 u8 queue_sel)
803{
804 u16 uninitialized_var(value);
805
806 switch (queue_sel) {
807 case TX_SELE_HQ:
808 value = QUEUE_HIGH;
809 break;
810 case TX_SELE_LQ:
811 value = QUEUE_LOW;
812 break;
813 case TX_SELE_NQ:
814 value = QUEUE_NORMAL;
815 break;
816 default:
817 WARN_ON(1); /* Shall not reach here! */
818 break;
819 }
820 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
821 value, value);
822 printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
823}
824
825static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
826 bool wmm_enable,
827 u8 queue_sel)
828{
829 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
830 u16 uninitialized_var(valueHi);
831 u16 uninitialized_var(valueLow);
832
833 switch (queue_sel) {
834 case (TX_SELE_HQ | TX_SELE_LQ):
835 valueHi = QUEUE_HIGH;
836 valueLow = QUEUE_LOW;
837 break;
838 case (TX_SELE_NQ | TX_SELE_LQ):
839 valueHi = QUEUE_NORMAL;
840 valueLow = QUEUE_LOW;
841 break;
842 case (TX_SELE_HQ | TX_SELE_NQ):
843 valueHi = QUEUE_HIGH;
844 valueLow = QUEUE_NORMAL;
845 break;
846 default:
847 WARN_ON(1);
848 break;
849 }
850 if (!wmm_enable) {
851 beQ = valueLow;
852 bkQ = valueLow;
853 viQ = valueHi;
854 voQ = valueHi;
855 mgtQ = valueHi;
856 hiQ = valueHi;
857 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
858 beQ = valueHi;
859 bkQ = valueLow;
860 viQ = valueLow;
861 voQ = valueHi;
862 mgtQ = valueHi;
863 hiQ = valueHi;
864 }
865 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
866 printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
867}
868
869static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
870 bool wmm_enable,
871 u8 queue_sel)
872{
873 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
874 struct rtl_priv *rtlpriv = rtl_priv(hw);
875
876 if (!wmm_enable) { /* typical setting */
877 beQ = QUEUE_LOW;
878 bkQ = QUEUE_LOW;
879 viQ = QUEUE_NORMAL;
880 voQ = QUEUE_HIGH;
881 mgtQ = QUEUE_HIGH;
882 hiQ = QUEUE_HIGH;
883 } else { /* for WMM */
884 beQ = QUEUE_LOW;
885 bkQ = QUEUE_NORMAL;
886 viQ = QUEUE_NORMAL;
887 voQ = QUEUE_HIGH;
888 mgtQ = QUEUE_HIGH;
889 hiQ = QUEUE_HIGH;
890 }
891 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
892 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
893 ("Tx queue select :0x%02x..\n", queue_sel));
894}
895
896static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
897 bool wmm_enable,
898 u8 out_ep_num,
899 u8 queue_sel)
900{
901 switch (out_ep_num) {
902 case 1:
903 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
904 queue_sel);
905 break;
906 case 2:
907 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
908 queue_sel);
909 break;
910 case 3:
911 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
912 queue_sel);
913 break;
914 default:
915 WARN_ON(1); /* Shall not reach here! */
916 break;
917 }
918}
919
920static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
921 bool wmm_enable,
922 u8 out_ep_num,
923 u8 queue_sel)
924{
925 u8 hq_sele = 0;
926 struct rtl_priv *rtlpriv = rtl_priv(hw);
927
928 switch (out_ep_num) {
929 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
930 if (!wmm_enable) /* typical setting */
931 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
932 HQSEL_HIQ;
933 else /* for WMM */
934 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
935 HQSEL_HIQ;
936 break;
937 case 1:
938 if (TX_SELE_LQ == queue_sel) {
939 /* map all endpoint to Low queue */
940 hq_sele = 0;
941 } else if (TX_SELE_HQ == queue_sel) {
942 /* map all endpoint to High queue */
943 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
944 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
945 }
946 break;
947 default:
948 WARN_ON(1); /* Shall not reach here! */
949 break;
950 }
951 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
952 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
953 ("Tx queue select :0x%02x..\n", hq_sele));
954}
955
956static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
957 bool wmm_enable,
958 u8 out_ep_num,
959 u8 queue_sel)
960{
961 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
962 if (IS_NORMAL_CHIP(rtlhal->version))
963 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
964 queue_sel);
965 else
966 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
967 queue_sel);
968}
969
970static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
971{
972}
973
974static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
975{
976 u16 value16;
977
978 struct rtl_priv *rtlpriv = rtl_priv(hw);
979 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
980
981 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
982 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
983 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
984 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
985 /* Accept all multicast address */
986 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
987 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
988 /* Accept all management frames */
989 value16 = 0xFFFF;
990 rtl92c_set_mgt_filter(hw, value16);
991 /* Reject all control frame - default value is 0 */
992 rtl92c_set_ctrl_filter(hw, 0x0);
993 /* Accept all data frames */
994 value16 = 0xFFFF;
995 rtl92c_set_data_filter(hw, value16);
996}
997
998static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
999{
1000 struct rtl_priv *rtlpriv = rtl_priv(hw);
1001 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1002 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
1003 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
1004 int err = 0;
1005 u32 boundary = 0;
1006 u8 wmm_enable = false; /* TODO */
1007 u8 out_ep_nums = rtlusb->out_ep_nums;
1008 u8 queue_sel = rtlusb->out_queue_sel;
1009 err = _rtl92cu_init_power_on(hw);
1010
1011 if (err) {
1012 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1013 ("Failed to init power on!\n"));
1014 return err;
1015 }
1016 if (!wmm_enable) {
1017 boundary = TX_PAGE_BOUNDARY;
1018 } else { /* for WMM */
1019 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1020 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1021 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1022 }
1023 if (false == rtl92c_init_llt_table(hw, boundary)) {
1024 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1025 ("Failed to init LLT Table!\n"));
1026 return -EINVAL;
1027 }
1028 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1029 queue_sel);
1030 _rtl92c_init_trx_buffer(hw, wmm_enable);
1031 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1032 queue_sel);
1033 /* Get Rx PHY status in order to report RSSI and others. */
1034 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1035 rtl92c_init_interrupt(hw);
1036 rtl92c_init_network_type(hw);
1037 _rtl92cu_init_wmac_setting(hw);
1038 rtl92c_init_adaptive_ctrl(hw);
1039 rtl92c_init_edca(hw);
1040 rtl92c_init_rate_fallback(hw);
1041 rtl92c_init_retry_function(hw);
1042 _rtl92cu_init_usb_aggregation(hw);
1043 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1044 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1045 rtl92c_init_beacon_parameters(hw, rtlhal->version);
1046 rtl92c_init_ampdu_aggregation(hw);
1047 rtl92c_init_beacon_max_error(hw, true);
1048 return err;
1049}
1050
1051void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1052{
1053 struct rtl_priv *rtlpriv = rtl_priv(hw);
1054 u8 sec_reg_value = 0x0;
1055 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1056
1057 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1058 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1059 rtlpriv->sec.pairwise_enc_algorithm,
1060 rtlpriv->sec.group_enc_algorithm));
1061 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1062 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1063 ("not open sw encryption\n"));
1064 return;
1065 }
1066 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1067 if (rtlpriv->sec.use_defaultkey) {
1068 sec_reg_value |= SCR_TxUseDK;
1069 sec_reg_value |= SCR_RxUseDK;
1070 }
1071 if (IS_NORMAL_CHIP(rtlhal->version))
1072 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1073 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1074 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
1075 ("The SECR-value %x\n", sec_reg_value));
1076 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1077}
1078
1079static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1080{
1081 struct rtl_priv *rtlpriv = rtl_priv(hw);
1082 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1083
1084 /* To Fix MAC loopback mode fail. */
1085 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1086 rtl_write_byte(rtlpriv, 0x15, 0xe9);
1087 /* HW SEQ CTRL */
1088 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1089 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1090 /* fixed USB interface interference issue */
1091 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1092 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1093 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1094 rtlusb->reg_bcn_ctrl_val = 0x18;
1095 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1096}
1097
1098static void _InitPABias(struct ieee80211_hw *hw)
1099{
1100 struct rtl_priv *rtlpriv = rtl_priv(hw);
1101 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1102 u8 pa_setting;
1103
1104 /* FIXED PA current issue */
1105 pa_setting = efuse_read_1byte(hw, 0x1FA);
1106 if (!(pa_setting & BIT(0))) {
1107 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1108 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1109 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1110 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1111 }
1112 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1113 IS_92C_SERIAL(rtlhal->version)) {
1114 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1115 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1116 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1117 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1118 }
1119 if (!(pa_setting & BIT(4))) {
1120 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1121 pa_setting &= 0x0F;
1122 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1123 }
1124}
1125
1126static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1127{
1128#ifdef CONFIG_ANTENNA_DIVERSITY
1129 struct rtl_priv *rtlpriv = rtl_priv(hw);
1130 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1131 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1132
1133 if (pHalData->AntDivCfg == 0)
1134 return;
1135
1136 if (rtlphy->rf_type == RF_1T1R) {
1137 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1138 rtl_read_dword(rtlpriv,
1139 REG_LEDCFG0)|BIT(23));
1140 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1141 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1142 Antenna_A)
1143 pHalData->CurAntenna = Antenna_A;
1144 else
1145 pHalData->CurAntenna = Antenna_B;
1146 }
1147#endif
1148}
1149
1150static void _dump_registers(struct ieee80211_hw *hw)
1151{
1152}
1153
1154static void _update_mac_setting(struct ieee80211_hw *hw)
1155{
1156 struct rtl_priv *rtlpriv = rtl_priv(hw);
1157 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1158
1159 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1160 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1161 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1162 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1163}
1164
1165int rtl92cu_hw_init(struct ieee80211_hw *hw)
1166{
1167 struct rtl_priv *rtlpriv = rtl_priv(hw);
1168 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1169 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1170 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1171 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1172 int err = 0;
1173 static bool iqk_initialized;
1174
1175 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1176 err = _rtl92cu_init_mac(hw);
1177 if (err) {
1178 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("init mac failed!\n"));
1179 return err;
1180 }
1181 err = rtl92c_download_fw(hw);
1182 if (err) {
1183 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1184 ("Failed to download FW. Init HW without FW now..\n"));
1185 err = 1;
1186 rtlhal->fw_ready = false;
1187 return err;
1188 } else {
1189 rtlhal->fw_ready = true;
1190 }
1191 rtlhal->last_hmeboxnum = 0; /* h2c */
1192 _rtl92cu_phy_param_tab_init(hw);
1193 rtl92cu_phy_mac_config(hw);
1194 rtl92cu_phy_bb_config(hw);
1195 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1196 rtl92c_phy_rf_config(hw);
1197 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1198 !IS_92C_SERIAL(rtlhal->version)) {
1199 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1200 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1201 }
1202 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1203 RF_CHNLBW, RFREG_OFFSET_MASK);
1204 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1205 RF_CHNLBW, RFREG_OFFSET_MASK);
1206 rtl92cu_bb_block_on(hw);
1207 rtl_cam_reset_all_entry(hw);
1208 rtl92cu_enable_hw_security_config(hw);
1209 ppsc->rfpwr_state = ERFON;
1210 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1211 if (ppsc->rfpwr_state == ERFON) {
1212 rtl92c_phy_set_rfpath_switch(hw, 1);
1213 if (iqk_initialized) {
1214 rtl92c_phy_iq_calibrate(hw, false);
1215 } else {
1216 rtl92c_phy_iq_calibrate(hw, false);
1217 iqk_initialized = true;
1218 }
1219 rtl92c_dm_check_txpower_tracking(hw);
1220 rtl92c_phy_lc_calibrate(hw);
1221 }
1222 _rtl92cu_hw_configure(hw);
1223 _InitPABias(hw);
1224 _InitAntenna_Selection(hw);
1225 _update_mac_setting(hw);
1226 rtl92c_dm_init(hw);
1227 _dump_registers(hw);
1228 return err;
1229}
1230
1231static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1232{
1233 struct rtl_priv *rtlpriv = rtl_priv(hw);
1234/**************************************
1235a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1236b. RF path 0 offset 0x00 = 0x00 disable RF
1237c. APSD_CTRL 0x600[7:0] = 0x40
1238d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1239e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1240***************************************/
1241 u8 eRFPath = 0, value8 = 0;
1242 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1243 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1244
1245 value8 |= APSDOFF;
1246 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1247 value8 = 0;
1248 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1249 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1250 value8 &= (~FEN_BB_GLB_RSTn);
1251 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1252}
1253
1254static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1255{
1256 struct rtl_priv *rtlpriv = rtl_priv(hw);
1257 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1258
1259 if (rtlhal->fw_version <= 0x20) {
1260 /*****************************
1261 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1262 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1263 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1264 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1265 ******************************/
1266 u16 valu16 = 0;
1267
1268 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1269 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1270 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1271 (~FEN_CPUEN))); /* reset MCU ,8051 */
1272 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1273 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1274 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1275 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1276 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1277 FEN_CPUEN)); /* enable MCU ,8051 */
1278 } else {
1279 u8 retry_cnts = 0;
1280
1281 /* IF fw in RAM code, do reset */
1282 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1283 /* reset MCU ready status */
1284 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1285 if (rtlhal->fw_ready) {
1286 /* 8051 reset by self */
1287 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1288 while ((retry_cnts++ < 100) &&
1289 (FEN_CPUEN & rtl_read_word(rtlpriv,
1290 REG_SYS_FUNC_EN))) {
1291 udelay(50);
1292 }
1293 if (retry_cnts >= 100) {
1294 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1295 ("#####=> 8051 reset failed!.."
1296 ".......................\n"););
1297 /* if 8051 reset fail, reset MAC. */
1298 rtl_write_byte(rtlpriv,
1299 REG_SYS_FUNC_EN + 1,
1300 0x50);
1301 udelay(100);
1302 }
1303 }
1304 }
1305 /* Reset MAC and Enable 8051 */
1306 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1307 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1308 }
1309 if (bWithoutHWSM) {
1310 /*****************************
1311 Without HW auto state machine
1312 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1313 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1314 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1315 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1316 ******************************/
1317 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1318 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1319 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1320 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1321 }
1322}
1323
1324static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1325{
1326 struct rtl_priv *rtlpriv = rtl_priv(hw);
1327/*****************************
1328k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1329l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1330m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1331******************************/
1332 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1333 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1334}
1335
1336static void _DisableGPIO(struct ieee80211_hw *hw)
1337{
1338 struct rtl_priv *rtlpriv = rtl_priv(hw);
1339/***************************************
1340j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1341k. Value = GPIO_PIN_CTRL[7:0]
1342l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1343m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1344n. LEDCFG 0x4C[15:0] = 0x8080
1345***************************************/
1346 u8 value8;
1347 u16 value16;
1348 u32 value32;
1349
1350 /* 1. Disable GPIO[7:0] */
1351 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1352 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1353 value8 = (u8) (value32&0x000000FF);
1354 value32 |= ((value8<<8) | 0x00FF0000);
1355 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1356 /* 2. Disable GPIO[10:8] */
1357 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1358 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1359 value8 = (u8) (value16&0x000F);
1360 value16 |= ((value8<<4) | 0x0780);
1361 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1362 /* 3. Disable LED0 & 1 */
1363 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1364}
1365
1366static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1367{
1368 struct rtl_priv *rtlpriv = rtl_priv(hw);
1369 u16 value16 = 0;
1370 u8 value8 = 0;
1371
1372 if (bWithoutHWSM) {
1373 /*****************************
1374 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1375 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1376 r. When driver call disable, the ASIC will turn off remaining
1377 clock automatically
1378 ******************************/
1379 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1380 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1381 value8 &= (~LDV12_EN);
1382 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1383 }
1384
1385/*****************************
1386h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1387i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1388******************************/
1389 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1390 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1391 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1392 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1393}
1394
1395static void _CardDisableHWSM(struct ieee80211_hw *hw)
1396{
1397 /* ==== RF Off Sequence ==== */
1398 _DisableRFAFEAndResetBB(hw);
1399 /* ==== Reset digital sequence ====== */
1400 _ResetDigitalProcedure1(hw, false);
1401 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1402 _DisableGPIO(hw);
1403 /* ==== Disable analog sequence === */
1404 _DisableAnalog(hw, false);
1405}
1406
1407static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1408{
1409 /*==== RF Off Sequence ==== */
1410 _DisableRFAFEAndResetBB(hw);
1411 /* ==== Reset digital sequence ====== */
1412 _ResetDigitalProcedure1(hw, true);
1413 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1414 _DisableGPIO(hw);
1415 /* ==== Reset digital sequence ====== */
1416 _ResetDigitalProcedure2(hw);
1417 /* ==== Disable analog sequence === */
1418 _DisableAnalog(hw, true);
1419}
1420
1421static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1422 u8 set_bits, u8 clear_bits)
1423{
1424 struct rtl_priv *rtlpriv = rtl_priv(hw);
1425 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1426
1427 rtlusb->reg_bcn_ctrl_val |= set_bits;
1428 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1429 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1430}
1431
1432static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1433{
1434 struct rtl_priv *rtlpriv = rtl_priv(hw);
1435 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1436 u8 tmp1byte = 0;
1437 if (IS_NORMAL_CHIP(rtlhal->version)) {
1438 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1439 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1440 tmp1byte & (~BIT(6)));
1441 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1442 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1443 tmp1byte &= ~(BIT(0));
1444 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1445 } else {
1446 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1447 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1448 }
1449}
1450
1451static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1452{
1453 struct rtl_priv *rtlpriv = rtl_priv(hw);
1454 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1455 u8 tmp1byte = 0;
1456
1457 if (IS_NORMAL_CHIP(rtlhal->version)) {
1458 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1459 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1460 tmp1byte | BIT(6));
1461 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1462 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1463 tmp1byte |= BIT(0);
1464 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1465 } else {
1466 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1467 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1468 }
1469}
1470
1471static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1472{
1473 struct rtl_priv *rtlpriv = rtl_priv(hw);
1474 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1475
1476 if (IS_NORMAL_CHIP(rtlhal->version))
1477 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1478 else
1479 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1480}
1481
1482static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1483{
1484 struct rtl_priv *rtlpriv = rtl_priv(hw);
1485 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1486
1487 if (IS_NORMAL_CHIP(rtlhal->version))
1488 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1489 else
1490 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1491}
1492
1493static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1494 enum nl80211_iftype type)
1495{
1496 struct rtl_priv *rtlpriv = rtl_priv(hw);
1497 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1498 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1499
1500 bt_msr &= 0xfc;
1501 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1502 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1503 NL80211_IFTYPE_STATION) {
1504 _rtl92cu_stop_tx_beacon(hw);
1505 _rtl92cu_enable_bcn_sub_func(hw);
1506 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1507 _rtl92cu_resume_tx_beacon(hw);
1508 _rtl92cu_disable_bcn_sub_func(hw);
1509 } else {
1510 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("Set HW_VAR_MEDIA_"
1511 "STATUS:No such media status(%x).\n", type));
1512 }
1513 switch (type) {
1514 case NL80211_IFTYPE_UNSPECIFIED:
1515 bt_msr |= MSR_NOLINK;
1516 ledaction = LED_CTL_LINK;
1517 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1518 ("Set Network type to NO LINK!\n"));
1519 break;
1520 case NL80211_IFTYPE_ADHOC:
1521 bt_msr |= MSR_ADHOC;
1522 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1523 ("Set Network type to Ad Hoc!\n"));
1524 break;
1525 case NL80211_IFTYPE_STATION:
1526 bt_msr |= MSR_INFRA;
1527 ledaction = LED_CTL_LINK;
1528 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1529 ("Set Network type to STA!\n"));
1530 break;
1531 case NL80211_IFTYPE_AP:
1532 bt_msr |= MSR_AP;
1533 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1534 ("Set Network type to AP!\n"));
1535 break;
1536 default:
1537 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1538 ("Network type %d not support!\n", type));
1539 goto error_out;
1540 }
1541 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1542 rtlpriv->cfg->ops->led_control(hw, ledaction);
1543 if ((bt_msr & 0xfc) == MSR_AP)
1544 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1545 else
1546 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1547 return 0;
1548error_out:
1549 return 1;
1550}
1551
1552void rtl92cu_card_disable(struct ieee80211_hw *hw)
1553{
1554 struct rtl_priv *rtlpriv = rtl_priv(hw);
1555 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1556 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1557 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1558 enum nl80211_iftype opmode;
1559
1560 mac->link_state = MAC80211_NOLINK;
1561 opmode = NL80211_IFTYPE_UNSPECIFIED;
1562 _rtl92cu_set_media_status(hw, opmode);
1563 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1564 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1565 if (rtlusb->disableHWSM)
1566 _CardDisableHWSM(hw);
1567 else
1568 _CardDisableWithoutHWSM(hw);
1569}
1570
1571void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1572{
1573 /* dummy routine needed for callback from rtl_op_configure_filter() */
1574}
1575
1576/*========================================================================== */
1577
1578static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1579 enum nl80211_iftype type)
1580{
1581 struct rtl_priv *rtlpriv = rtl_priv(hw);
1582 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1583 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1584 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1585 u8 filterout_non_associated_bssid = false;
1586
1587 switch (type) {
1588 case NL80211_IFTYPE_ADHOC:
1589 case NL80211_IFTYPE_STATION:
1590 filterout_non_associated_bssid = true;
1591 break;
1592 case NL80211_IFTYPE_UNSPECIFIED:
1593 case NL80211_IFTYPE_AP:
1594 default:
1595 break;
1596 }
1597 if (filterout_non_associated_bssid == true) {
1598 if (IS_NORMAL_CHIP(rtlhal->version)) {
1599 switch (rtlphy->current_io_type) {
1600 case IO_CMD_RESUME_DM_BY_SCAN:
1601 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1602 rtlpriv->cfg->ops->set_hw_reg(hw,
1603 HW_VAR_RCR, (u8 *)(&reg_rcr));
1604 /* enable update TSF */
1605 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1606 break;
1607 case IO_CMD_PAUSE_DM_BY_SCAN:
1608 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1609 rtlpriv->cfg->ops->set_hw_reg(hw,
1610 HW_VAR_RCR, (u8 *)(&reg_rcr));
1611 /* disable update TSF */
1612 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1613 break;
1614 }
1615 } else {
1616 reg_rcr |= (RCR_CBSSID);
1617 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1618 (u8 *)(&reg_rcr));
1619 _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1620 }
1621 } else if (filterout_non_associated_bssid == false) {
1622 if (IS_NORMAL_CHIP(rtlhal->version)) {
1623 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1624 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1625 (u8 *)(&reg_rcr));
1626 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1627 } else {
1628 reg_rcr &= (~RCR_CBSSID);
1629 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1630 (u8 *)(&reg_rcr));
1631 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1632 }
1633 }
1634}
1635
1636int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1637{
1638 if (_rtl92cu_set_media_status(hw, type))
1639 return -EOPNOTSUPP;
1640 _rtl92cu_set_check_bssid(hw, type);
1641 return 0;
1642}
1643
1644static void _InitBeaconParameters(struct ieee80211_hw *hw)
1645{
1646 struct rtl_priv *rtlpriv = rtl_priv(hw);
1647 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1648
1649 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1650
1651 /* TODO: Remove these magic number */
1652 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1653 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1654 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1655 /* Change beacon AIFS to the largest number
1656 * beacause test chip does not contension before sending beacon. */
1657 if (IS_NORMAL_CHIP(rtlhal->version))
1658 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1659 else
1660 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1661}
1662
1663static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1664 bool Linked)
1665{
1666 struct rtl_priv *rtlpriv = rtl_priv(hw);
1667
1668 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1669 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1670}
1671
1672void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1673{
1674
1675 struct rtl_priv *rtlpriv = rtl_priv(hw);
1676 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1677 u16 bcn_interval, atim_window;
1678 u32 value32;
1679
1680 bcn_interval = mac->beacon_interval;
1681 atim_window = 2; /*FIX MERGE */
1682 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1683 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1684 _InitBeaconParameters(hw);
1685 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1686 /*
1687 * Force beacon frame transmission even after receiving beacon frame
1688 * from other ad hoc STA
1689 *
1690 *
1691 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1692 */
1693 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1694 value32 &= ~TSFRST;
1695 rtl_write_dword(rtlpriv, REG_TCR, value32);
1696 value32 |= TSFRST;
1697 rtl_write_dword(rtlpriv, REG_TCR, value32);
1698 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1699 ("SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1700 value32));
1701 /* TODO: Modify later (Find the right parameters)
1702 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1703 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1704 (mac->opmode == NL80211_IFTYPE_AP)) {
1705 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1706 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1707 }
1708 _beacon_function_enable(hw, true, true);
1709}
1710
1711void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1712{
1713 struct rtl_priv *rtlpriv = rtl_priv(hw);
1714 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1715 u16 bcn_interval = mac->beacon_interval;
1716
1717 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1718 ("beacon_interval:%d\n", bcn_interval));
1719 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1720}
1721
1722void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1723 u32 add_msr, u32 rm_msr)
1724{
1725}
1726
1727void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1728{
1729 struct rtl_priv *rtlpriv = rtl_priv(hw);
1730 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1731 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1732
1733 switch (variable) {
1734 case HW_VAR_RCR:
1735 *((u32 *)(val)) = mac->rx_conf;
1736 break;
1737 case HW_VAR_RF_STATE:
1738 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1739 break;
1740 case HW_VAR_FWLPS_RF_ON:{
1741 enum rf_pwrstate rfState;
1742 u32 val_rcr;
1743
1744 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1745 (u8 *)(&rfState));
1746 if (rfState == ERFOFF) {
1747 *((bool *) (val)) = true;
1748 } else {
1749 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1750 val_rcr &= 0x00070000;
1751 if (val_rcr)
1752 *((bool *) (val)) = false;
1753 else
1754 *((bool *) (val)) = true;
1755 }
1756 break;
1757 }
1758 case HW_VAR_FW_PSMODE_STATUS:
1759 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1760 break;
1761 case HW_VAR_CORRECT_TSF:{
1762 u64 tsf;
1763 u32 *ptsf_low = (u32 *)&tsf;
1764 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1765
1766 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1767 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1768 *((u64 *)(val)) = tsf;
1769 break;
1770 }
1771 case HW_VAR_MGT_FILTER:
1772 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1773 break;
1774 case HW_VAR_CTRL_FILTER:
1775 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1776 break;
1777 case HW_VAR_DATA_FILTER:
1778 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1779 break;
1780 default:
1781 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1782 ("switch case not process\n"));
1783 break;
1784 }
1785}
1786
1787void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1788{
1789 struct rtl_priv *rtlpriv = rtl_priv(hw);
1790 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1791 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1792 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1793 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1794 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1795 enum wireless_mode wirelessmode = mac->mode;
1796 u8 idx = 0;
1797
1798 switch (variable) {
1799 case HW_VAR_ETHER_ADDR:{
1800 for (idx = 0; idx < ETH_ALEN; idx++) {
1801 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1802 val[idx]);
1803 }
1804 break;
1805 }
1806 case HW_VAR_BASIC_RATE:{
1807 u16 rate_cfg = ((u16 *) val)[0];
1808 u8 rate_index = 0;
1809
1810 rate_cfg &= 0x15f;
1811 /* TODO */
1812 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1813 * && ((rate_cfg & 0x150) == 0)) {
1814 * rate_cfg |= 0x010;
1815 * } */
1816 rate_cfg |= 0x01;
1817 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1818 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1819 (rate_cfg >> 8) & 0xff);
1820 while (rate_cfg > 0x1) {
1821 rate_cfg >>= 1;
1822 rate_index++;
1823 }
1824 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1825 rate_index);
1826 break;
1827 }
1828 case HW_VAR_BSSID:{
1829 for (idx = 0; idx < ETH_ALEN; idx++) {
1830 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1831 val[idx]);
1832 }
1833 break;
1834 }
1835 case HW_VAR_SIFS:{
1836 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1837 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1838 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1839 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1840 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1841 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1842 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1843 ("HW_VAR_SIFS\n"));
1844 break;
1845 }
1846 case HW_VAR_SLOT_TIME:{
1847 u8 e_aci;
1848 u8 QOS_MODE = 1;
1849
1850 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1851 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1852 ("HW_VAR_SLOT_TIME %x\n", val[0]));
1853 if (QOS_MODE) {
1854 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1855 rtlpriv->cfg->ops->set_hw_reg(hw,
1856 HW_VAR_AC_PARAM,
1857 (u8 *)(&e_aci));
1858 } else {
1859 u8 sifstime = 0;
1860 u8 u1bAIFS;
1861
1862 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1863 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1864 IS_WIRELESS_MODE_N_5G(wirelessmode))
1865 sifstime = 16;
1866 else
1867 sifstime = 10;
1868 u1bAIFS = sifstime + (2 * val[0]);
1869 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1870 u1bAIFS);
1871 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1872 u1bAIFS);
1873 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1874 u1bAIFS);
1875 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1876 u1bAIFS);
1877 }
1878 break;
1879 }
1880 case HW_VAR_ACK_PREAMBLE:{
1881 u8 reg_tmp;
1882 u8 short_preamble = (bool) (*(u8 *) val);
1883 reg_tmp = 0;
1884 if (short_preamble)
1885 reg_tmp |= 0x80;
1886 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1887 break;
1888 }
1889 case HW_VAR_AMPDU_MIN_SPACE:{
1890 u8 min_spacing_to_set;
1891 u8 sec_min_space;
1892
1893 min_spacing_to_set = *((u8 *) val);
1894 if (min_spacing_to_set <= 7) {
1895 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1896 case NO_ENCRYPTION:
1897 case AESCCMP_ENCRYPTION:
1898 sec_min_space = 0;
1899 break;
1900 case WEP40_ENCRYPTION:
1901 case WEP104_ENCRYPTION:
1902 case TKIP_ENCRYPTION:
1903 sec_min_space = 6;
1904 break;
1905 default:
1906 sec_min_space = 7;
1907 break;
1908 }
1909 if (min_spacing_to_set < sec_min_space)
1910 min_spacing_to_set = sec_min_space;
1911 mac->min_space_cfg = ((mac->min_space_cfg &
1912 0xf8) |
1913 min_spacing_to_set);
1914 *val = min_spacing_to_set;
1915 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1916 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1917 mac->min_space_cfg));
1918 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1919 mac->min_space_cfg);
1920 }
1921 break;
1922 }
1923 case HW_VAR_SHORTGI_DENSITY:{
1924 u8 density_to_set;
1925
1926 density_to_set = *((u8 *) val);
1927 density_to_set &= 0x1f;
1928 mac->min_space_cfg &= 0x07;
1929 mac->min_space_cfg |= (density_to_set << 3);
1930 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1931 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1932 mac->min_space_cfg));
1933 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1934 mac->min_space_cfg);
1935 break;
1936 }
1937 case HW_VAR_AMPDU_FACTOR:{
1938 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1939 u8 factor_toset;
1940 u8 *p_regtoset = NULL;
1941 u8 index = 0;
1942
1943 p_regtoset = regtoset_normal;
1944 factor_toset = *((u8 *) val);
1945 if (factor_toset <= 3) {
1946 factor_toset = (1 << (factor_toset + 2));
1947 if (factor_toset > 0xf)
1948 factor_toset = 0xf;
1949 for (index = 0; index < 4; index++) {
1950 if ((p_regtoset[index] & 0xf0) >
1951 (factor_toset << 4))
1952 p_regtoset[index] =
1953 (p_regtoset[index] & 0x0f)
1954 | (factor_toset << 4);
1955 if ((p_regtoset[index] & 0x0f) >
1956 factor_toset)
1957 p_regtoset[index] =
1958 (p_regtoset[index] & 0xf0)
1959 | (factor_toset);
1960 rtl_write_byte(rtlpriv,
1961 (REG_AGGLEN_LMT + index),
1962 p_regtoset[index]);
1963 }
1964 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1965 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
1966 factor_toset));
1967 }
1968 break;
1969 }
1970 case HW_VAR_AC_PARAM:{
1971 u8 e_aci = *((u8 *) val);
1972 u32 u4b_ac_param;
1973 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1974 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1975 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1976
1977 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1978 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1979 AC_PARAM_ECW_MIN_OFFSET);
1980 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1981 AC_PARAM_ECW_MAX_OFFSET);
1982 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1983 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1984 ("queue:%x, ac_param:%x\n", e_aci,
1985 u4b_ac_param));
1986 switch (e_aci) {
1987 case AC1_BK:
1988 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1989 u4b_ac_param);
1990 break;
1991 case AC0_BE:
1992 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1993 u4b_ac_param);
1994 break;
1995 case AC2_VI:
1996 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1997 u4b_ac_param);
1998 break;
1999 case AC3_VO:
2000 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
2001 u4b_ac_param);
2002 break;
2003 default:
2004 RT_ASSERT(false, ("SetHwReg8185(): invalid"
2005 " aci: %d !\n", e_aci));
2006 break;
2007 }
2008 if (rtlusb->acm_method != eAcmWay2_SW)
2009 rtlpriv->cfg->ops->set_hw_reg(hw,
2010 HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
2011 break;
2012 }
2013 case HW_VAR_ACM_CTRL:{
2014 u8 e_aci = *((u8 *) val);
2015 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
2016 (&(mac->ac[0].aifs));
2017 u8 acm = p_aci_aifsn->f.acm;
2018 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2019
2020 acm_ctrl =
2021 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2022 if (acm) {
2023 switch (e_aci) {
2024 case AC0_BE:
2025 acm_ctrl |= AcmHw_BeqEn;
2026 break;
2027 case AC2_VI:
2028 acm_ctrl |= AcmHw_ViqEn;
2029 break;
2030 case AC3_VO:
2031 acm_ctrl |= AcmHw_VoqEn;
2032 break;
2033 default:
2034 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2035 ("HW_VAR_ACM_CTRL acm set "
2036 "failed: eACI is %d\n", acm));
2037 break;
2038 }
2039 } else {
2040 switch (e_aci) {
2041 case AC0_BE:
2042 acm_ctrl &= (~AcmHw_BeqEn);
2043 break;
2044 case AC2_VI:
2045 acm_ctrl &= (~AcmHw_ViqEn);
2046 break;
2047 case AC3_VO:
2048 acm_ctrl &= (~AcmHw_BeqEn);
2049 break;
2050 default:
2051 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2052 ("switch case not process\n"));
2053 break;
2054 }
2055 }
2056 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2057 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
2058 "Write 0x%X\n", acm_ctrl));
2059 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2060 break;
2061 }
2062 case HW_VAR_RCR:{
2063 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2064 mac->rx_conf = ((u32 *) (val))[0];
2065 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2066 ("### Set RCR(0x%08x) ###\n", mac->rx_conf));
2067 break;
2068 }
2069 case HW_VAR_RETRY_LIMIT:{
2070 u8 retry_limit = ((u8 *) (val))[0];
2071
2072 rtl_write_word(rtlpriv, REG_RL,
2073 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2074 retry_limit << RETRY_LIMIT_LONG_SHIFT);
2075 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, ("Set HW_VAR_R"
2076 "ETRY_LIMIT(0x%08x)\n", retry_limit));
2077 break;
2078 }
2079 case HW_VAR_DUAL_TSF_RST:
2080 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2081 break;
2082 case HW_VAR_EFUSE_BYTES:
2083 rtlefuse->efuse_usedbytes = *((u16 *) val);
2084 break;
2085 case HW_VAR_EFUSE_USAGE:
2086 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2087 break;
2088 case HW_VAR_IO_CMD:
2089 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2090 break;
2091 case HW_VAR_WPA_CONFIG:
2092 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2093 break;
2094 case HW_VAR_SET_RPWM:{
2095 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2096
2097 if (rpwm_val & BIT(7))
2098 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2099 (*(u8 *)val));
2100 else
2101 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2102 ((*(u8 *)val) | BIT(7)));
2103 break;
2104 }
2105 case HW_VAR_H2C_FW_PWRMODE:{
2106 u8 psmode = (*(u8 *) val);
2107
2108 if ((psmode != FW_PS_ACTIVE_MODE) &&
2109 (!IS_92C_SERIAL(rtlhal->version)))
2110 rtl92c_dm_rf_saving(hw, true);
2111 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2112 break;
2113 }
2114 case HW_VAR_FW_PSMODE_STATUS:
2115 ppsc->fw_current_inpsmode = *((bool *) val);
2116 break;
2117 case HW_VAR_H2C_FW_JOINBSSRPT:{
2118 u8 mstatus = (*(u8 *) val);
2119 u8 tmp_reg422;
2120 bool recover = false;
2121
2122 if (mstatus == RT_MEDIA_CONNECT) {
2123 rtlpriv->cfg->ops->set_hw_reg(hw,
2124 HW_VAR_AID, NULL);
2125 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2126 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2127 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2128 tmp_reg422 = rtl_read_byte(rtlpriv,
2129 REG_FWHW_TXQ_CTRL + 2);
2130 if (tmp_reg422 & BIT(6))
2131 recover = true;
2132 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2133 tmp_reg422 & (~BIT(6)));
2134 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2135 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2136 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2137 if (recover)
2138 rtl_write_byte(rtlpriv,
2139 REG_FWHW_TXQ_CTRL + 2,
2140 tmp_reg422 | BIT(6));
2141 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2142 }
2143 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2144 break;
2145 }
2146 case HW_VAR_AID:{
2147 u16 u2btmp;
2148
2149 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2150 u2btmp &= 0xC000;
2151 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2152 (u2btmp | mac->assoc_id));
2153 break;
2154 }
2155 case HW_VAR_CORRECT_TSF:{
2156 u8 btype_ibss = ((u8 *) (val))[0];
2157
2158 if (btype_ibss == true)
2159 _rtl92cu_stop_tx_beacon(hw);
2160 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2161 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2162 0xffffffff));
2163 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2164 (u32)((mac->tsf >> 32) & 0xffffffff));
2165 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2166 if (btype_ibss == true)
2167 _rtl92cu_resume_tx_beacon(hw);
2168 break;
2169 }
2170 case HW_VAR_MGT_FILTER:
2171 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2172 break;
2173 case HW_VAR_CTRL_FILTER:
2174 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2175 break;
2176 case HW_VAR_DATA_FILTER:
2177 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2178 break;
2179 default:
2180 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2181 "not process\n"));
2182 break;
2183 }
2184}
2185
2186void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
2187 struct ieee80211_sta *sta,
2188 u8 rssi_level)
2189{
2190 struct rtl_priv *rtlpriv = rtl_priv(hw);
2191 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2192 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2193 u32 ratr_value = (u32) mac->basic_rates;
2194 u8 *mcsrate = mac->mcs;
2195 u8 ratr_index = 0;
2196 u8 nmode = mac->ht_enable;
2197 u8 mimo_ps = 1;
2198 u16 shortgi_rate = 0;
2199 u32 tmp_ratr_value = 0;
2200 u8 curtxbw_40mhz = mac->bw_40;
2201 u8 curshortgi_40mhz = mac->sgi_40;
2202 u8 curshortgi_20mhz = mac->sgi_20;
2203 enum wireless_mode wirelessmode = mac->mode;
2204
2205 ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2206 switch (wirelessmode) {
2207 case WIRELESS_MODE_B:
2208 if (ratr_value & 0x0000000c)
2209 ratr_value &= 0x0000000d;
2210 else
2211 ratr_value &= 0x0000000f;
2212 break;
2213 case WIRELESS_MODE_G:
2214 ratr_value &= 0x00000FF5;
2215 break;
2216 case WIRELESS_MODE_N_24G:
2217 case WIRELESS_MODE_N_5G:
2218 nmode = 1;
2219 if (mimo_ps == 0) {
2220 ratr_value &= 0x0007F005;
2221 } else {
2222 u32 ratr_mask;
2223
2224 if (get_rf_type(rtlphy) == RF_1T2R ||
2225 get_rf_type(rtlphy) == RF_1T1R)
2226 ratr_mask = 0x000ff005;
2227 else
2228 ratr_mask = 0x0f0ff005;
2229 if (curtxbw_40mhz)
2230 ratr_mask |= 0x00000010;
2231 ratr_value &= ratr_mask;
2232 }
2233 break;
2234 default:
2235 if (rtlphy->rf_type == RF_1T2R)
2236 ratr_value &= 0x000ff0ff;
2237 else
2238 ratr_value &= 0x0f0ff0ff;
2239 break;
2240 }
2241 ratr_value &= 0x0FFFFFFF;
2242 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2243 (!curtxbw_40mhz && curshortgi_20mhz))) {
2244 ratr_value |= 0x10000000;
2245 tmp_ratr_value = (ratr_value >> 12);
2246 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2247 if ((1 << shortgi_rate) & tmp_ratr_value)
2248 break;
2249 }
2250 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2251 (shortgi_rate << 4) | (shortgi_rate);
2252 }
2253 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2254 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("%x\n", rtl_read_dword(rtlpriv,
2255 REG_ARFR0)));
2256}
2257
2258void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2259{
2260 struct rtl_priv *rtlpriv = rtl_priv(hw);
2261 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2262 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2263 u32 ratr_bitmap = (u32) mac->basic_rates;
2264 u8 *p_mcsrate = mac->mcs;
2265 u8 ratr_index = 0;
2266 u8 curtxbw_40mhz = mac->bw_40;
2267 u8 curshortgi_40mhz = mac->sgi_40;
2268 u8 curshortgi_20mhz = mac->sgi_20;
2269 enum wireless_mode wirelessmode = mac->mode;
2270 bool shortgi = false;
2271 u8 rate_mask[5];
2272 u8 macid = 0;
2273 u8 mimops = 1;
2274
2275 ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2276 switch (wirelessmode) {
2277 case WIRELESS_MODE_B:
2278 ratr_index = RATR_INX_WIRELESS_B;
2279 if (ratr_bitmap & 0x0000000c)
2280 ratr_bitmap &= 0x0000000d;
2281 else
2282 ratr_bitmap &= 0x0000000f;
2283 break;
2284 case WIRELESS_MODE_G:
2285 ratr_index = RATR_INX_WIRELESS_GB;
2286 if (rssi_level == 1)
2287 ratr_bitmap &= 0x00000f00;
2288 else if (rssi_level == 2)
2289 ratr_bitmap &= 0x00000ff0;
2290 else
2291 ratr_bitmap &= 0x00000ff5;
2292 break;
2293 case WIRELESS_MODE_A:
2294 ratr_index = RATR_INX_WIRELESS_A;
2295 ratr_bitmap &= 0x00000ff0;
2296 break;
2297 case WIRELESS_MODE_N_24G:
2298 case WIRELESS_MODE_N_5G:
2299 ratr_index = RATR_INX_WIRELESS_NGB;
2300 if (mimops == 0) {
2301 if (rssi_level == 1)
2302 ratr_bitmap &= 0x00070000;
2303 else if (rssi_level == 2)
2304 ratr_bitmap &= 0x0007f000;
2305 else
2306 ratr_bitmap &= 0x0007f005;
2307 } else {
2308 if (rtlphy->rf_type == RF_1T2R ||
2309 rtlphy->rf_type == RF_1T1R) {
2310 if (curtxbw_40mhz) {
2311 if (rssi_level == 1)
2312 ratr_bitmap &= 0x000f0000;
2313 else if (rssi_level == 2)
2314 ratr_bitmap &= 0x000ff000;
2315 else
2316 ratr_bitmap &= 0x000ff015;
2317 } else {
2318 if (rssi_level == 1)
2319 ratr_bitmap &= 0x000f0000;
2320 else if (rssi_level == 2)
2321 ratr_bitmap &= 0x000ff000;
2322 else
2323 ratr_bitmap &= 0x000ff005;
2324 }
2325 } else {
2326 if (curtxbw_40mhz) {
2327 if (rssi_level == 1)
2328 ratr_bitmap &= 0x0f0f0000;
2329 else if (rssi_level == 2)
2330 ratr_bitmap &= 0x0f0ff000;
2331 else
2332 ratr_bitmap &= 0x0f0ff015;
2333 } else {
2334 if (rssi_level == 1)
2335 ratr_bitmap &= 0x0f0f0000;
2336 else if (rssi_level == 2)
2337 ratr_bitmap &= 0x0f0ff000;
2338 else
2339 ratr_bitmap &= 0x0f0ff005;
2340 }
2341 }
2342 }
2343 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2344 (!curtxbw_40mhz && curshortgi_20mhz)) {
2345 if (macid == 0)
2346 shortgi = true;
2347 else if (macid == 1)
2348 shortgi = false;
2349 }
2350 break;
2351 default:
2352 ratr_index = RATR_INX_WIRELESS_NGB;
2353 if (rtlphy->rf_type == RF_1T2R)
2354 ratr_bitmap &= 0x000ff0ff;
2355 else
2356 ratr_bitmap &= 0x0f0ff0ff;
2357 break;
2358 }
2359 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("ratr_bitmap :%x\n",
2360 ratr_bitmap));
2361 *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2362 ratr_index << 28);
2363 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2364 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
2365 "ratr_val:%x, %x:%x:%x:%x:%x\n",
2366 ratr_index, ratr_bitmap,
2367 rate_mask[0], rate_mask[1],
2368 rate_mask[2], rate_mask[3],
2369 rate_mask[4]));
2370 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2371}
2372
2373void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2374{
2375 struct rtl_priv *rtlpriv = rtl_priv(hw);
2376 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2377 u16 sifs_timer;
2378
2379 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2380 (u8 *)&mac->slot_time);
2381 if (!mac->ht_enable)
2382 sifs_timer = 0x0a0a;
2383 else
2384 sifs_timer = 0x0e0e;
2385 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2386}
2387
2388bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2389{
2390 struct rtl_priv *rtlpriv = rtl_priv(hw);
2391 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2392 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2393 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2394 u8 u1tmp = 0;
2395 bool actuallyset = false;
2396 unsigned long flag = 0;
2397 /* to do - usb autosuspend */
2398 u8 usb_autosuspend = 0;
2399
2400 if (ppsc->swrf_processing)
2401 return false;
2402 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2403 if (ppsc->rfchange_inprogress) {
2404 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2405 return false;
2406 } else {
2407 ppsc->rfchange_inprogress = true;
2408 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2409 }
2410 cur_rfstate = ppsc->rfpwr_state;
2411 if (usb_autosuspend) {
2412 /* to do................... */
2413 } else {
2414 if (ppsc->pwrdown_mode) {
2415 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2416 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2417 ERFOFF : ERFON;
2418 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2419 ("pwrdown, 0x5c(BIT7)=%02x\n", u1tmp));
2420 } else {
2421 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2422 rtl_read_byte(rtlpriv,
2423 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2424 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2425 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2426 ERFON : ERFOFF;
2427 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2428 ("GPIO_IN=%02x\n", u1tmp));
2429 }
2430 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("N-SS RF =%x\n",
2431 e_rfpowerstate_toset));
2432 }
2433 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2434 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW "
2435 "Radio ON, RF ON\n"));
2436 ppsc->hwradiooff = false;
2437 actuallyset = true;
2438 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2439 ERFOFF)) {
2440 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW"
2441 " Radio OFF\n"));
2442 ppsc->hwradiooff = true;
2443 actuallyset = true;
2444 } else {
2445 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
2446 ("pHalData->bHwRadioOff and eRfPowerStateToSet do not"
2447 " match: pHalData->bHwRadioOff %x, eRfPowerStateToSet "
2448 "%x\n", ppsc->hwradiooff, e_rfpowerstate_toset));
2449 }
2450 if (actuallyset) {
2451 ppsc->hwradiooff = 1;
2452 if (e_rfpowerstate_toset == ERFON) {
2453 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2454 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2455 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2456 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2457 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2458 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2459 }
2460 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2461 ppsc->rfchange_inprogress = false;
2462 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2463 /* For power down module, we need to enable register block
2464 * contrl reg at 0x1c. Then enable power down control bit
2465 * of register 0x04 BIT4 and BIT15 as 1.
2466 */
2467 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2468 /* Enable register area 0x0-0xc. */
2469 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2470 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2471 /*
2472 * We should configure HW PDn source for WiFi
2473 * ONLY, and then our HW will be set in
2474 * power-down mode if PDn source from all
2475 * functions are configured.
2476 */
2477 u1tmp = rtl_read_byte(rtlpriv,
2478 REG_MULTI_FUNC_CTRL);
2479 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2480 (u1tmp|WL_HWPDN_EN));
2481 } else {
2482 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2483 }
2484 }
2485 if (e_rfpowerstate_toset == ERFOFF) {
2486 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2487 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2488 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2489 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2490 }
2491 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2492 /* Enter D3 or ASPM after GPIO had been done. */
2493 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2494 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2495 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2496 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2497 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2498 ppsc->rfchange_inprogress = false;
2499 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2500 } else {
2501 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2502 ppsc->rfchange_inprogress = false;
2503 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2504 }
2505 *valid = 1;
2506 return !ppsc->hwradiooff;
2507}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
new file mode 100644
index 000000000000..32f85cba106a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
@@ -0,0 +1,117 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_HW_H__
31#define __RTL92CU_HW_H__
32
33#define H2C_RA_MASK 6
34
35#define LLT_POLLING_LLT_THRESHOLD 20
36#define LLT_POLLING_READY_TIMEOUT_COUNT 100
37#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
38
39#define RX_PAGE_SIZE_REG_VALUE PBP_128
40/* Note: We will divide number of page equally for each queue
41 * other than public queue! */
42#define TX_TOTAL_PAGE_NUMBER 0xF8
43#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
44
45
46#define CHIP_B_PAGE_NUM_PUBQ 0xE7
47
48/* For Test Chip Setting
49 * (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
50#define CHIP_A_PAGE_NUM_PUBQ 0x7E
51
52
53/* For Chip A Setting */
54#define WMM_CHIP_A_TX_TOTAL_PAGE_NUMBER 0xF5
55#define WMM_CHIP_A_TX_PAGE_BOUNDARY \
56 (WMM_CHIP_A_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
57
58#define WMM_CHIP_A_PAGE_NUM_PUBQ 0xA3
59#define WMM_CHIP_A_PAGE_NUM_HPQ 0x29
60#define WMM_CHIP_A_PAGE_NUM_LPQ 0x29
61
62
63
64/* Note: For Chip B Setting ,modify later */
65#define WMM_CHIP_B_TX_TOTAL_PAGE_NUMBER 0xF5
66#define WMM_CHIP_B_TX_PAGE_BOUNDARY \
67 (WMM_CHIP_B_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
68
69#define WMM_CHIP_B_PAGE_NUM_PUBQ 0xB0
70#define WMM_CHIP_B_PAGE_NUM_HPQ 0x29
71#define WMM_CHIP_B_PAGE_NUM_LPQ 0x1C
72#define WMM_CHIP_B_PAGE_NUM_NPQ 0x1C
73
74#define BOARD_TYPE_NORMAL_MASK 0xE0
75#define BOARD_TYPE_TEST_MASK 0x0F
76
77/* should be renamed and moved to another file */
78enum _BOARD_TYPE_8192CUSB {
79 BOARD_USB_DONGLE = 0, /* USB dongle */
80 BOARD_USB_High_PA = 1, /* USB dongle - high power PA */
81 BOARD_MINICARD = 2, /* Minicard */
82 BOARD_USB_SOLO = 3, /* USB solo-Slim module */
83 BOARD_USB_COMBO = 4, /* USB Combo-Slim module */
84};
85
86#define IS_HIGHT_PA(boardtype) \
87 ((boardtype == BOARD_USB_High_PA) ? true : false)
88
89#define RTL92C_DRIVER_INFO_SIZE 4
90void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw);
91void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw);
92int rtl92cu_hw_init(struct ieee80211_hw *hw);
93void rtl92cu_card_disable(struct ieee80211_hw *hw);
94int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
95void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw);
96void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw);
97void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
98 u32 add_msr, u32 rm_msr);
99void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
100void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
101void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
102 struct ieee80211_sta *sta,
103 u8 rssi_level);
104void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level);
105
106void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw);
107bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid);
108void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
109int rtl92c_download_fw(struct ieee80211_hw *hw);
110void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
111void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished);
112void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
113void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
114 u8 element_id, u32 cmd_len, u8 *p_cmdbuffer);
115bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw);
116
117#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/led.c b/drivers/net/wireless/rtlwifi/rtl8192cu/led.c
new file mode 100644
index 000000000000..332c74348a69
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/led.c
@@ -0,0 +1,142 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 *****************************************************************************/
27
28#include "../wifi.h"
29#include "../usb.h"
30#include "reg.h"
31#include "led.h"
32
33static void _rtl92cu_init_led(struct ieee80211_hw *hw,
34 struct rtl_led *pled, enum rtl_led_pin ledpin)
35{
36 pled->hw = hw;
37 pled->ledpin = ledpin;
38 pled->ledon = false;
39}
40
41static void _rtl92cu_deInit_led(struct rtl_led *pled)
42{
43}
44
45void rtl92cu_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
46{
47 u8 ledcfg;
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49
50 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
51 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
52 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
53 switch (pled->ledpin) {
54 case LED_PIN_GPIO0:
55 break;
56 case LED_PIN_LED0:
57 rtl_write_byte(rtlpriv,
58 REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5) | BIT(6));
59 break;
60 case LED_PIN_LED1:
61 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
62 break;
63 default:
64 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
65 ("switch case not process\n"));
66 break;
67 }
68 pled->ledon = true;
69}
70
71void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw);
75 u8 ledcfg;
76
77 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
78 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
79 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
80 switch (pled->ledpin) {
81 case LED_PIN_GPIO0:
82 break;
83 case LED_PIN_LED0:
84 ledcfg &= 0xf0;
85 if (usbpriv->ledctl.led_opendrain == true)
86 rtl_write_byte(rtlpriv, REG_LEDCFG2,
87 (ledcfg | BIT(1) | BIT(5) | BIT(6)));
88 else
89 rtl_write_byte(rtlpriv, REG_LEDCFG2,
90 (ledcfg | BIT(3) | BIT(5) | BIT(6)));
91 break;
92 case LED_PIN_LED1:
93 ledcfg &= 0x0f;
94 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
95 break;
96 default:
97 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
98 ("switch case not process\n"));
99 break;
100 }
101 pled->ledon = false;
102}
103
104void rtl92cu_init_sw_leds(struct ieee80211_hw *hw)
105{
106 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw);
107 _rtl92cu_init_led(hw, &(usbpriv->ledctl.sw_led0), LED_PIN_LED0);
108 _rtl92cu_init_led(hw, &(usbpriv->ledctl.sw_led1), LED_PIN_LED1);
109}
110
111void rtl92cu_deinit_sw_leds(struct ieee80211_hw *hw)
112{
113 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw);
114 _rtl92cu_deInit_led(&(usbpriv->ledctl.sw_led0));
115 _rtl92cu_deInit_led(&(usbpriv->ledctl.sw_led1));
116}
117
118static void _rtl92cu_sw_led_control(struct ieee80211_hw *hw,
119 enum led_ctl_mode ledaction)
120{
121}
122
123void rtl92cu_led_control(struct ieee80211_hw *hw,
124 enum led_ctl_mode ledaction)
125{
126 struct rtl_priv *rtlpriv = rtl_priv(hw);
127 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
128
129 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
130 (ledaction == LED_CTL_TX ||
131 ledaction == LED_CTL_RX ||
132 ledaction == LED_CTL_SITE_SURVEY ||
133 ledaction == LED_CTL_LINK ||
134 ledaction == LED_CTL_NO_LINK ||
135 ledaction == LED_CTL_START_TO_LINK ||
136 ledaction == LED_CTL_POWER_ON)) {
137 return;
138 }
139 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, ("ledaction %d,\n",
140 ledaction));
141 _rtl92cu_sw_led_control(hw, ledaction);
142}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/led.h b/drivers/net/wireless/rtlwifi/rtl8192cu/led.h
new file mode 100644
index 000000000000..decaee4d1eb1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/led.h
@@ -0,0 +1,37 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 *****************************************************************************/
27
28#ifndef __RTL92CU_LED_H__
29#define __RTL92CU_LED_H__
30
31void rtl92cu_init_sw_leds(struct ieee80211_hw *hw);
32void rtl92cu_deinit_sw_leds(struct ieee80211_hw *hw);
33void rtl92cu_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
34void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
35void rtl92cu_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
36
37#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
new file mode 100644
index 000000000000..f8514cba17b6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -0,0 +1,1144 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28****************************************************************************/
29#include <linux/module.h>
30
31#include "../wifi.h"
32#include "../pci.h"
33#include "../usb.h"
34#include "../ps.h"
35#include "../cam.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "rf.h"
40#include "dm.h"
41#include "mac.h"
42#include "trx.h"
43
44/* macro to shorten lines */
45
46#define LINK_Q ui_link_quality
47#define RX_EVM rx_evm_percentage
48#define RX_SIGQ rx_mimo_signalquality
49
50
51void rtl92c_read_chip_version(struct ieee80211_hw *hw)
52{
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
54 struct rtl_phy *rtlphy = &(rtlpriv->phy);
55 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
56 enum version_8192c chip_version = VERSION_UNKNOWN;
57 u32 value32;
58
59 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
60 if (value32 & TRP_VAUX_EN) {
61 chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
62 VERSION_TEST_CHIP_88C;
63 } else {
64 /* Normal mass production chip. */
65 chip_version = NORMAL_CHIP;
66 chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
67 chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
68 /* RTL8723 with BT function. */
69 chip_version |= ((value32 & BT_FUNC) ? CHIP_8723 : 0);
70 if (IS_VENDOR_UMC(chip_version))
71 chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
72 CHIP_VENDOR_UMC_B_CUT : 0);
73 if (IS_92C_SERIAL(chip_version)) {
74 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
75 chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
76 CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
77 } else if (IS_8723_SERIES(chip_version)) {
78 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
79 chip_version |= ((value32 & RF_RL_ID) ?
80 CHIP_8723_DRV_REV : 0);
81 }
82 }
83 rtlhal->version = (enum version_8192c)chip_version;
84 switch (rtlhal->version) {
85 case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
86 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
87 ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
88 break;
89 case VERSION_NORMAL_TSMC_CHIP_92C:
90 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
91 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_92C.\n"));
92 break;
93 case VERSION_NORMAL_TSMC_CHIP_88C:
94 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
95 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_88C.\n"));
96 break;
97 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
98 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
99 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP_i"
100 "92C_1T2R_A_CUT.\n"));
101 break;
102 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
103 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
104 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP_"
105 "92C_A_CUT.\n"));
106 break;
107 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
108 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
109 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP"
110 "_88C_A_CUT.\n"));
111 break;
112 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
113 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
114 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP"
115 "_92C_1T2R_B_CUT.\n"));
116 break;
117 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
118 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
119 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP"
120 "_92C_B_CUT.\n"));
121 break;
122 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
123 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
124 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP"
125 "_88C_B_CUT.\n"));
126 break;
127 case VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT:
128 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
129 ("Chip Version ID: VERSION_NORMA_UMC_CHIP"
130 "_8723_1T1R_A_CUT.\n"));
131 break;
132 case VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT:
133 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
134 ("Chip Version ID: VERSION_NORMA_UMC_CHIP"
135 "_8723_1T1R_B_CUT.\n"));
136 break;
137 case VERSION_TEST_CHIP_92C:
138 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
139 ("Chip Version ID: VERSION_TEST_CHIP_92C.\n"));
140 break;
141 case VERSION_TEST_CHIP_88C:
142 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
143 ("Chip Version ID: VERSION_TEST_CHIP_88C.\n"));
144 break;
145 default:
146 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
147 ("Chip Version ID: ???????????????.\n"));
148 break;
149 }
150 if (IS_92C_SERIAL(rtlhal->version))
151 rtlphy->rf_type =
152 (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
153 else
154 rtlphy->rf_type = RF_1T1R;
155 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
156 ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
157 "RF_2T2R" : "RF_1T1R"));
158 if (get_rf_type(rtlphy) == RF_1T1R)
159 rtlpriv->dm.rfpath_rxenable[0] = true;
160 else
161 rtlpriv->dm.rfpath_rxenable[0] =
162 rtlpriv->dm.rfpath_rxenable[1] = true;
163 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
164 rtlhal->version));
165}
166
167/**
168 * writeLLT - LLT table write access
169 * @io: io callback
170 * @address: LLT logical address.
171 * @data: LLT data content
172 *
173 * Realtek hardware access function.
174 *
175 */
176bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
177{
178 struct rtl_priv *rtlpriv = rtl_priv(hw);
179 bool status = true;
180 long count = 0;
181 u32 value = _LLT_INIT_ADDR(address) |
182 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
183
184 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
185 do {
186 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
187 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
188 break;
189 if (count > POLLING_LLT_THRESHOLD) {
190 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
191 ("Failed to polling write LLT done at"
192 " address %d! _LLT_OP_VALUE(%x)\n",
193 address, _LLT_OP_VALUE(value)));
194 status = false;
195 break;
196 }
197 } while (++count);
198 return status;
199}
200/**
201 * rtl92c_init_LLT_table - Init LLT table
202 * @io: io callback
203 * @boundary:
204 *
205 * Realtek hardware access function.
206 *
207 */
208bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
209{
210 bool rst = true;
211 u32 i;
212
213 for (i = 0; i < (boundary - 1); i++) {
214 rst = rtl92c_llt_write(hw, i , i + 1);
215 if (true != rst) {
216 printk(KERN_ERR "===> %s #1 fail\n", __func__);
217 return rst;
218 }
219 }
220 /* end of list */
221 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
222 if (true != rst) {
223 printk(KERN_ERR "===> %s #2 fail\n", __func__);
224 return rst;
225 }
226 /* Make the other pages as ring buffer
227 * This ring buffer is used as beacon buffer if we config this MAC
228 * as two MAC transfer.
229 * Otherwise used as local loopback buffer.
230 */
231 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
232 rst = rtl92c_llt_write(hw, i, (i + 1));
233 if (true != rst) {
234 printk(KERN_ERR "===> %s #3 fail\n", __func__);
235 return rst;
236 }
237 }
238 /* Let last entry point to the start entry of ring buffer */
239 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
240 if (true != rst) {
241 printk(KERN_ERR "===> %s #4 fail\n", __func__);
242 return rst;
243 }
244 return rst;
245}
246void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
247 u8 *p_macaddr, bool is_group, u8 enc_algo,
248 bool is_wepkey, bool clear_all)
249{
250 struct rtl_priv *rtlpriv = rtl_priv(hw);
251 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
252 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
253 u8 *macaddr = p_macaddr;
254 u32 entry_id = 0;
255 bool is_pairwise = false;
256 static u8 cam_const_addr[4][6] = {
257 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
258 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
259 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
260 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
261 };
262 static u8 cam_const_broad[] = {
263 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
264 };
265
266 if (clear_all) {
267 u8 idx = 0;
268 u8 cam_offset = 0;
269 u8 clear_number = 5;
270
271 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
272 for (idx = 0; idx < clear_number; idx++) {
273 rtl_cam_mark_invalid(hw, cam_offset + idx);
274 rtl_cam_empty_entry(hw, cam_offset + idx);
275 if (idx < 5) {
276 memset(rtlpriv->sec.key_buf[idx], 0,
277 MAX_KEY_LEN);
278 rtlpriv->sec.key_len[idx] = 0;
279 }
280 }
281 } else {
282 switch (enc_algo) {
283 case WEP40_ENCRYPTION:
284 enc_algo = CAM_WEP40;
285 break;
286 case WEP104_ENCRYPTION:
287 enc_algo = CAM_WEP104;
288 break;
289 case TKIP_ENCRYPTION:
290 enc_algo = CAM_TKIP;
291 break;
292 case AESCCMP_ENCRYPTION:
293 enc_algo = CAM_AES;
294 break;
295 default:
296 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
297 ("iillegal switch case\n"));
298 enc_algo = CAM_TKIP;
299 break;
300 }
301 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
302 macaddr = cam_const_addr[key_index];
303 entry_id = key_index;
304 } else {
305 if (is_group) {
306 macaddr = cam_const_broad;
307 entry_id = key_index;
308 } else {
309 key_index = PAIRWISE_KEYIDX;
310 entry_id = CAM_PAIRWISE_KEY_POSITION;
311 is_pairwise = true;
312 }
313 }
314 if (rtlpriv->sec.key_len[key_index] == 0) {
315 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
316 ("delete one entry\n"));
317 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
318 } else {
319 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
320 ("The insert KEY length is %d\n",
321 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
322 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
323 ("The insert KEY is %x %x\n",
324 rtlpriv->sec.key_buf[0][0],
325 rtlpriv->sec.key_buf[0][1]));
326 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
327 ("add one entry\n"));
328 if (is_pairwise) {
329 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
330 "Pairwiase Key content :",
331 rtlpriv->sec.pairwise_key,
332 rtlpriv->sec.
333 key_len[PAIRWISE_KEYIDX]);
334 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
335 ("set Pairwiase key\n"));
336
337 rtl_cam_add_one_entry(hw, macaddr, key_index,
338 entry_id, enc_algo,
339 CAM_CONFIG_NO_USEDK,
340 rtlpriv->sec.
341 key_buf[key_index]);
342 } else {
343 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
344 ("set group key\n"));
345 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
346 rtl_cam_add_one_entry(hw,
347 rtlefuse->dev_addr,
348 PAIRWISE_KEYIDX,
349 CAM_PAIRWISE_KEY_POSITION,
350 enc_algo,
351 CAM_CONFIG_NO_USEDK,
352 rtlpriv->sec.key_buf
353 [entry_id]);
354 }
355 rtl_cam_add_one_entry(hw, macaddr, key_index,
356 entry_id, enc_algo,
357 CAM_CONFIG_NO_USEDK,
358 rtlpriv->sec.key_buf[entry_id]);
359 }
360 }
361 }
362}
363
364u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw)
365{
366 struct rtl_priv *rtlpriv = rtl_priv(hw);
367
368 return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS);
369}
370
371void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
372{
373 struct rtl_priv *rtlpriv = rtl_priv(hw);
374 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
375 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
376 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
377
378 if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
379 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
380 0xFFFFFFFF);
381 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
382 0xFFFFFFFF);
383 rtlpci->irq_enabled = true;
384 } else {
385 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
386 0xFFFFFFFF);
387 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
388 0xFFFFFFFF);
389 rtlusb->irq_enabled = true;
390 }
391}
392
393void rtl92c_init_interrupt(struct ieee80211_hw *hw)
394{
395 rtl92c_enable_interrupt(hw);
396}
397
398void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
399{
400 struct rtl_priv *rtlpriv = rtl_priv(hw);
401 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
402 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
403 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
404
405 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
406 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
407 if (IS_HARDWARE_TYPE_8192CE(rtlhal))
408 rtlpci->irq_enabled = false;
409 else if (IS_HARDWARE_TYPE_8192CU(rtlhal))
410 rtlusb->irq_enabled = false;
411}
412
413void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
414{
415 struct rtl_priv *rtlpriv = rtl_priv(hw);
416 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
417 u32 u4b_ac_param;
418
419 rtl92c_dm_init_edca_turbo(hw);
420 u4b_ac_param = (u32) mac->ac[aci].aifs;
421 u4b_ac_param |=
422 ((u32) le16_to_cpu(mac->ac[aci].cw_min) & 0xF) <<
423 AC_PARAM_ECW_MIN_OFFSET;
424 u4b_ac_param |=
425 ((u32) le16_to_cpu(mac->ac[aci].cw_max) & 0xF) <<
426 AC_PARAM_ECW_MAX_OFFSET;
427 u4b_ac_param |= (u32) le16_to_cpu(mac->ac[aci].tx_op) <<
428 AC_PARAM_TXOP_OFFSET;
429 RT_TRACE(rtlpriv, COMP_QOS, DBG_LOUD,
430 ("queue:%x, ac_param:%x\n", aci, u4b_ac_param));
431 switch (aci) {
432 case AC1_BK:
433 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
434 break;
435 case AC0_BE:
436 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
437 break;
438 case AC2_VI:
439 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
440 break;
441 case AC3_VO:
442 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
443 break;
444 default:
445 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
446 break;
447 }
448}
449
450/*-------------------------------------------------------------------------
451 * HW MAC Address
452 *-------------------------------------------------------------------------*/
453void rtl92c_set_mac_addr(struct ieee80211_hw *hw, const u8 *addr)
454{
455 u32 i;
456 struct rtl_priv *rtlpriv = rtl_priv(hw);
457
458 for (i = 0 ; i < ETH_ALEN ; i++)
459 rtl_write_byte(rtlpriv, (REG_MACID + i), *(addr+i));
460
461 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("MAC Address: %02X-%02X-%02X-"
462 "%02X-%02X-%02X\n",
463 rtl_read_byte(rtlpriv, REG_MACID),
464 rtl_read_byte(rtlpriv, REG_MACID+1),
465 rtl_read_byte(rtlpriv, REG_MACID+2),
466 rtl_read_byte(rtlpriv, REG_MACID+3),
467 rtl_read_byte(rtlpriv, REG_MACID+4),
468 rtl_read_byte(rtlpriv, REG_MACID+5)));
469}
470
471void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size)
472{
473 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size);
475}
476
477int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
478{
479 u8 value;
480 struct rtl_priv *rtlpriv = rtl_priv(hw);
481
482 switch (type) {
483 case NL80211_IFTYPE_UNSPECIFIED:
484 value = NT_NO_LINK;
485 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
486 ("Set Network type to NO LINK!\n"));
487 break;
488 case NL80211_IFTYPE_ADHOC:
489 value = NT_LINK_AD_HOC;
490 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
491 ("Set Network type to Ad Hoc!\n"));
492 break;
493 case NL80211_IFTYPE_STATION:
494 value = NT_LINK_AP;
495 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
496 ("Set Network type to STA!\n"));
497 break;
498 case NL80211_IFTYPE_AP:
499 value = NT_AS_AP;
500 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
501 ("Set Network type to AP!\n"));
502 break;
503 default:
504 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
505 ("Network type %d not support!\n", type));
506 return -EOPNOTSUPP;
507 }
508 rtl_write_byte(rtlpriv, (REG_CR + 2), value);
509 return 0;
510}
511
512void rtl92c_init_network_type(struct ieee80211_hw *hw)
513{
514 rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED);
515}
516
517void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
518{
519 u16 value16;
520 u32 value32;
521 struct rtl_priv *rtlpriv = rtl_priv(hw);
522
523 /* Response Rate Set */
524 value32 = rtl_read_dword(rtlpriv, REG_RRSR);
525 value32 &= ~RATE_BITMAP_ALL;
526 value32 |= RATE_RRSR_CCK_ONLY_1M;
527 rtl_write_dword(rtlpriv, REG_RRSR, value32);
528 /* SIFS (used in NAV) */
529 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
530 rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16);
531 /* Retry Limit */
532 value16 = _LRL(0x30) | _SRL(0x30);
533 rtl_write_dword(rtlpriv, REG_RL, value16);
534}
535
536void rtl92c_init_rate_fallback(struct ieee80211_hw *hw)
537{
538 struct rtl_priv *rtlpriv = rtl_priv(hw);
539
540 /* Set Data Auto Rate Fallback Retry Count register. */
541 rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000);
542 rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404);
543 rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201);
544 rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605);
545}
546
547static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
548 u8 ctx_sifs)
549{
550 struct rtl_priv *rtlpriv = rtl_priv(hw);
551
552 rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs);
553 rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs);
554}
555
556static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
557 u8 ctx_sifs)
558{
559 struct rtl_priv *rtlpriv = rtl_priv(hw);
560
561 rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs);
562 rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs);
563}
564
565void rtl92c_init_edca_param(struct ieee80211_hw *hw,
566 u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
567{
568 /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
569 * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
570 */
571 u32 value;
572 struct rtl_priv *rtlpriv = rtl_priv(hw);
573
574 value = (u32)aifs;
575 value |= ((u32)cw_min & 0xF) << 8;
576 value |= ((u32)cw_max & 0xF) << 12;
577 value |= (u32)txop << 16;
578 /* 92C hardware register sequence is the same as queue number. */
579 rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
580}
581
582void rtl92c_init_edca(struct ieee80211_hw *hw)
583{
584 u16 value16;
585 struct rtl_priv *rtlpriv = rtl_priv(hw);
586
587 /* disable EDCCA count down, to reduce collison and retry */
588 value16 = rtl_read_word(rtlpriv, REG_RD_CTRL);
589 value16 |= DIS_EDCA_CNT_DWN;
590 rtl_write_word(rtlpriv, REG_RD_CTRL, value16);
591 /* Update SIFS timing. ??????????
592 * pHalData->SifsTime = 0x0e0e0a0a; */
593 rtl92c_set_cck_sifs(hw, 0xa, 0xa);
594 rtl92c_set_ofdm_sifs(hw, 0xe, 0xe);
595 /* Set CCK/OFDM SIFS to be 10us. */
596 rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a);
597 rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010);
598 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204);
599 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);
600 /* TXOP */
601 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);
602 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);
603 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);
604 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);
605 /* PIFS */
606 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
607 /* AGGR BREAK TIME Register */
608 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
609 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
610 rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02);
611 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02);
612}
613
614void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
615{
616 struct rtl_priv *rtlpriv = rtl_priv(hw);
617
618 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
619 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
620 /* init AMPDU aggregation number, tuning for Tx's TP, */
621 rtl_write_word(rtlpriv, 0x4CA, 0x0708);
622}
623
624void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw, bool infra_mode)
625{
626 struct rtl_priv *rtlpriv = rtl_priv(hw);
627
628 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
629}
630
631void rtl92c_init_rdg_setting(struct ieee80211_hw *hw)
632{
633 struct rtl_priv *rtlpriv = rtl_priv(hw);
634
635 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF);
636 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
637 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
638}
639
640void rtl92c_init_retry_function(struct ieee80211_hw *hw)
641{
642 u8 value8;
643 struct rtl_priv *rtlpriv = rtl_priv(hw);
644
645 value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL);
646 value8 |= EN_AMPDU_RTY_NEW;
647 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8);
648 /* Set ACK timeout */
649 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
650}
651
652void rtl92c_init_beacon_parameters(struct ieee80211_hw *hw,
653 enum version_8192c version)
654{
655 struct rtl_priv *rtlpriv = rtl_priv(hw);
656 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
657
658 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);/* ms */
659 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/*ms*/
660 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
661 if (IS_NORMAL_CHIP(rtlhal->version))
662 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
663 else
664 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
665}
666
667void rtl92c_disable_fast_edca(struct ieee80211_hw *hw)
668{
669 struct rtl_priv *rtlpriv = rtl_priv(hw);
670
671 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0);
672}
673
674void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T)
675{
676 struct rtl_priv *rtlpriv = rtl_priv(hw);
677 u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T;
678
679 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value);
680}
681
682u16 rtl92c_get_mgt_filter(struct ieee80211_hw *hw)
683{
684 struct rtl_priv *rtlpriv = rtl_priv(hw);
685
686 return rtl_read_word(rtlpriv, REG_RXFLTMAP0);
687}
688
689void rtl92c_set_mgt_filter(struct ieee80211_hw *hw, u16 filter)
690{
691 struct rtl_priv *rtlpriv = rtl_priv(hw);
692
693 rtl_write_word(rtlpriv, REG_RXFLTMAP0, filter);
694}
695
696u16 rtl92c_get_ctrl_filter(struct ieee80211_hw *hw)
697{
698 struct rtl_priv *rtlpriv = rtl_priv(hw);
699
700 return rtl_read_word(rtlpriv, REG_RXFLTMAP1);
701}
702
703void rtl92c_set_ctrl_filter(struct ieee80211_hw *hw, u16 filter)
704{
705 struct rtl_priv *rtlpriv = rtl_priv(hw);
706
707 rtl_write_word(rtlpriv, REG_RXFLTMAP1, filter);
708}
709
710u16 rtl92c_get_data_filter(struct ieee80211_hw *hw)
711{
712 struct rtl_priv *rtlpriv = rtl_priv(hw);
713
714 return rtl_read_word(rtlpriv, REG_RXFLTMAP2);
715}
716
717void rtl92c_set_data_filter(struct ieee80211_hw *hw, u16 filter)
718{
719 struct rtl_priv *rtlpriv = rtl_priv(hw);
720
721 rtl_write_word(rtlpriv, REG_RXFLTMAP2, filter);
722}
723/*==============================================================*/
724
725static u8 _rtl92c_query_rxpwrpercentage(char antpower)
726{
727 if ((antpower <= -100) || (antpower >= 20))
728 return 0;
729 else if (antpower >= 0)
730 return 100;
731 else
732 return 100 + antpower;
733}
734
735static u8 _rtl92c_evm_db_to_percentage(char value)
736{
737 char ret_val;
738
739 ret_val = value;
740 if (ret_val >= 0)
741 ret_val = 0;
742 if (ret_val <= -33)
743 ret_val = -33;
744 ret_val = 0 - ret_val;
745 ret_val *= 3;
746 if (ret_val == 99)
747 ret_val = 100;
748 return ret_val;
749}
750
751static long _rtl92c_translate_todbm(struct ieee80211_hw *hw,
752 u8 signal_strength_index)
753{
754 long signal_power;
755
756 signal_power = (long)((signal_strength_index + 1) >> 1);
757 signal_power -= 95;
758 return signal_power;
759}
760
761static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw,
762 long currsig)
763{
764 long retsig;
765
766 if (currsig >= 61 && currsig <= 100)
767 retsig = 90 + ((currsig - 60) / 4);
768 else if (currsig >= 41 && currsig <= 60)
769 retsig = 78 + ((currsig - 40) / 2);
770 else if (currsig >= 31 && currsig <= 40)
771 retsig = 66 + (currsig - 30);
772 else if (currsig >= 21 && currsig <= 30)
773 retsig = 54 + (currsig - 20);
774 else if (currsig >= 5 && currsig <= 20)
775 retsig = 42 + (((currsig - 5) * 2) / 3);
776 else if (currsig == 4)
777 retsig = 36;
778 else if (currsig == 3)
779 retsig = 27;
780 else if (currsig == 2)
781 retsig = 18;
782 else if (currsig == 1)
783 retsig = 9;
784 else
785 retsig = currsig;
786 return retsig;
787}
788
789static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
790 struct rtl_stats *pstats,
791 struct rx_desc_92c *pdesc,
792 struct rx_fwinfo_92c *p_drvinfo,
793 bool packet_match_bssid,
794 bool packet_toself,
795 bool packet_beacon)
796{
797 struct rtl_priv *rtlpriv = rtl_priv(hw);
798 struct rtl_phy *rtlphy = &(rtlpriv->phy);
799 struct phy_sts_cck_8192s_t *cck_buf;
800 s8 rx_pwr_all = 0, rx_pwr[4];
801 u8 rf_rx_num = 0, evm, pwdb_all;
802 u8 i, max_spatial_stream;
803 u32 rssi, total_rssi = 0;
804 bool in_powersavemode = false;
805 bool is_cck_rate;
806
807 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
808 pstats->packet_matchbssid = packet_match_bssid;
809 pstats->packet_toself = packet_toself;
810 pstats->is_cck = is_cck_rate;
811 pstats->packet_beacon = packet_beacon;
812 pstats->is_cck = is_cck_rate;
813 pstats->RX_SIGQ[0] = -1;
814 pstats->RX_SIGQ[1] = -1;
815 if (is_cck_rate) {
816 u8 report, cck_highpwr;
817 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
818 if (!in_powersavemode)
819 cck_highpwr = rtlphy->cck_high_power;
820 else
821 cck_highpwr = false;
822 if (!cck_highpwr) {
823 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
824 report = cck_buf->cck_agc_rpt & 0xc0;
825 report = report >> 6;
826 switch (report) {
827 case 0x3:
828 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
829 break;
830 case 0x2:
831 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
832 break;
833 case 0x1:
834 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
835 break;
836 case 0x0:
837 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
838 break;
839 }
840 } else {
841 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
842 report = p_drvinfo->cfosho[0] & 0x60;
843 report = report >> 5;
844 switch (report) {
845 case 0x3:
846 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
847 break;
848 case 0x2:
849 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
850 break;
851 case 0x1:
852 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
853 break;
854 case 0x0:
855 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
856 break;
857 }
858 }
859 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
860 pstats->rx_pwdb_all = pwdb_all;
861 pstats->recvsignalpower = rx_pwr_all;
862 if (packet_match_bssid) {
863 u8 sq;
864 if (pstats->rx_pwdb_all > 40)
865 sq = 100;
866 else {
867 sq = cck_buf->sq_rpt;
868 if (sq > 64)
869 sq = 0;
870 else if (sq < 20)
871 sq = 100;
872 else
873 sq = ((64 - sq) * 100) / 44;
874 }
875 pstats->signalquality = sq;
876 pstats->RX_SIGQ[0] = sq;
877 pstats->RX_SIGQ[1] = -1;
878 }
879 } else {
880 rtlpriv->dm.rfpath_rxenable[0] =
881 rtlpriv->dm.rfpath_rxenable[1] = true;
882 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
883 if (rtlpriv->dm.rfpath_rxenable[i])
884 rf_rx_num++;
885 rx_pwr[i] =
886 ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
887 rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
888 total_rssi += rssi;
889 rtlpriv->stats.rx_snr_db[i] =
890 (long)(p_drvinfo->rxsnr[i] / 2);
891
892 if (packet_match_bssid)
893 pstats->rx_mimo_signalstrength[i] = (u8) rssi;
894 }
895 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
896 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
897 pstats->rx_pwdb_all = pwdb_all;
898 pstats->rxpower = rx_pwr_all;
899 pstats->recvsignalpower = rx_pwr_all;
900 if (GET_RX_DESC_RX_MCS(pdesc) &&
901 GET_RX_DESC_RX_MCS(pdesc) >= DESC92C_RATEMCS8 &&
902 GET_RX_DESC_RX_MCS(pdesc) <= DESC92C_RATEMCS15)
903 max_spatial_stream = 2;
904 else
905 max_spatial_stream = 1;
906 for (i = 0; i < max_spatial_stream; i++) {
907 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
908 if (packet_match_bssid) {
909 if (i == 0)
910 pstats->signalquality =
911 (u8) (evm & 0xff);
912 pstats->RX_SIGQ[i] =
913 (u8) (evm & 0xff);
914 }
915 }
916 }
917 if (is_cck_rate)
918 pstats->signalstrength =
919 (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all));
920 else if (rf_rx_num != 0)
921 pstats->signalstrength =
922 (u8) (_rtl92c_signal_scale_mapping
923 (hw, total_rssi /= rf_rx_num));
924}
925
926static void _rtl92c_process_ui_rssi(struct ieee80211_hw *hw,
927 struct rtl_stats *pstats)
928{
929 struct rtl_priv *rtlpriv = rtl_priv(hw);
930 struct rtl_phy *rtlphy = &(rtlpriv->phy);
931 u8 rfpath;
932 u32 last_rssi, tmpval;
933
934 if (pstats->packet_toself || pstats->packet_beacon) {
935 rtlpriv->stats.rssi_calculate_cnt++;
936 if (rtlpriv->stats.ui_rssi.total_num++ >=
937 PHY_RSSI_SLID_WIN_MAX) {
938 rtlpriv->stats.ui_rssi.total_num =
939 PHY_RSSI_SLID_WIN_MAX;
940 last_rssi =
941 rtlpriv->stats.ui_rssi.elements[rtlpriv->
942 stats.ui_rssi.index];
943 rtlpriv->stats.ui_rssi.total_val -= last_rssi;
944 }
945 rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength;
946 rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.
947 index++] = pstats->signalstrength;
948 if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
949 rtlpriv->stats.ui_rssi.index = 0;
950 tmpval = rtlpriv->stats.ui_rssi.total_val /
951 rtlpriv->stats.ui_rssi.total_num;
952 rtlpriv->stats.signal_strength =
953 _rtl92c_translate_todbm(hw, (u8) tmpval);
954 pstats->rssi = rtlpriv->stats.signal_strength;
955 }
956 if (!pstats->is_cck && pstats->packet_toself) {
957 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
958 rfpath++) {
959 if (!rtl8192_phy_check_is_legal_rfpath(hw, rfpath))
960 continue;
961 if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
962 rtlpriv->stats.rx_rssi_percentage[rfpath] =
963 pstats->rx_mimo_signalstrength[rfpath];
964 }
965 if (pstats->rx_mimo_signalstrength[rfpath] >
966 rtlpriv->stats.rx_rssi_percentage[rfpath]) {
967 rtlpriv->stats.rx_rssi_percentage[rfpath] =
968 ((rtlpriv->stats.
969 rx_rssi_percentage[rfpath] *
970 (RX_SMOOTH_FACTOR - 1)) +
971 (pstats->rx_mimo_signalstrength[rfpath])) /
972 (RX_SMOOTH_FACTOR);
973
974 rtlpriv->stats.rx_rssi_percentage[rfpath] =
975 rtlpriv->stats.rx_rssi_percentage[rfpath] +
976 1;
977 } else {
978 rtlpriv->stats.rx_rssi_percentage[rfpath] =
979 ((rtlpriv->stats.
980 rx_rssi_percentage[rfpath] *
981 (RX_SMOOTH_FACTOR - 1)) +
982 (pstats->rx_mimo_signalstrength[rfpath])) /
983 (RX_SMOOTH_FACTOR);
984 }
985 }
986 }
987}
988
989static void _rtl92c_update_rxsignalstatistics(struct ieee80211_hw *hw,
990 struct rtl_stats *pstats)
991{
992 struct rtl_priv *rtlpriv = rtl_priv(hw);
993 int weighting = 0;
994
995 if (rtlpriv->stats.recv_signal_power == 0)
996 rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
997 if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power)
998 weighting = 5;
999 else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power)
1000 weighting = (-5);
1001 rtlpriv->stats.recv_signal_power =
1002 (rtlpriv->stats.recv_signal_power * 5 +
1003 pstats->recvsignalpower + weighting) / 6;
1004}
1005
1006static void _rtl92c_process_pwdb(struct ieee80211_hw *hw,
1007 struct rtl_stats *pstats)
1008{
1009 struct rtl_priv *rtlpriv = rtl_priv(hw);
1010 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1011 long undecorated_smoothed_pwdb = 0;
1012
1013 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1014 return;
1015 } else {
1016 undecorated_smoothed_pwdb =
1017 rtlpriv->dm.undecorated_smoothed_pwdb;
1018 }
1019 if (pstats->packet_toself || pstats->packet_beacon) {
1020 if (undecorated_smoothed_pwdb < 0)
1021 undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
1022 if (pstats->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
1023 undecorated_smoothed_pwdb =
1024 (((undecorated_smoothed_pwdb) *
1025 (RX_SMOOTH_FACTOR - 1)) +
1026 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
1027 undecorated_smoothed_pwdb = undecorated_smoothed_pwdb
1028 + 1;
1029 } else {
1030 undecorated_smoothed_pwdb =
1031 (((undecorated_smoothed_pwdb) *
1032 (RX_SMOOTH_FACTOR - 1)) +
1033 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
1034 }
1035 rtlpriv->dm.undecorated_smoothed_pwdb =
1036 undecorated_smoothed_pwdb;
1037 _rtl92c_update_rxsignalstatistics(hw, pstats);
1038 }
1039}
1040
1041static void _rtl92c_process_LINK_Q(struct ieee80211_hw *hw,
1042 struct rtl_stats *pstats)
1043{
1044 struct rtl_priv *rtlpriv = rtl_priv(hw);
1045 u32 last_evm = 0, n_stream, tmpval;
1046
1047 if (pstats->signalquality != 0) {
1048 if (pstats->packet_toself || pstats->packet_beacon) {
1049 if (rtlpriv->stats.LINK_Q.total_num++ >=
1050 PHY_LINKQUALITY_SLID_WIN_MAX) {
1051 rtlpriv->stats.LINK_Q.total_num =
1052 PHY_LINKQUALITY_SLID_WIN_MAX;
1053 last_evm =
1054 rtlpriv->stats.LINK_Q.elements
1055 [rtlpriv->stats.LINK_Q.index];
1056 rtlpriv->stats.LINK_Q.total_val -=
1057 last_evm;
1058 }
1059 rtlpriv->stats.LINK_Q.total_val +=
1060 pstats->signalquality;
1061 rtlpriv->stats.LINK_Q.elements
1062 [rtlpriv->stats.LINK_Q.index++] =
1063 pstats->signalquality;
1064 if (rtlpriv->stats.LINK_Q.index >=
1065 PHY_LINKQUALITY_SLID_WIN_MAX)
1066 rtlpriv->stats.LINK_Q.index = 0;
1067 tmpval = rtlpriv->stats.LINK_Q.total_val /
1068 rtlpriv->stats.LINK_Q.total_num;
1069 rtlpriv->stats.signal_quality = tmpval;
1070 rtlpriv->stats.last_sigstrength_inpercent = tmpval;
1071 for (n_stream = 0; n_stream < 2;
1072 n_stream++) {
1073 if (pstats->RX_SIGQ[n_stream] != -1) {
1074 if (!rtlpriv->stats.RX_EVM[n_stream]) {
1075 rtlpriv->stats.RX_EVM[n_stream]
1076 = pstats->RX_SIGQ[n_stream];
1077 }
1078 rtlpriv->stats.RX_EVM[n_stream] =
1079 ((rtlpriv->stats.RX_EVM
1080 [n_stream] *
1081 (RX_SMOOTH_FACTOR - 1)) +
1082 (pstats->RX_SIGQ
1083 [n_stream] * 1)) /
1084 (RX_SMOOTH_FACTOR);
1085 }
1086 }
1087 }
1088 } else {
1089 ;
1090 }
1091}
1092
1093static void _rtl92c_process_phyinfo(struct ieee80211_hw *hw,
1094 u8 *buffer,
1095 struct rtl_stats *pcurrent_stats)
1096{
1097 if (!pcurrent_stats->packet_matchbssid &&
1098 !pcurrent_stats->packet_beacon)
1099 return;
1100 _rtl92c_process_ui_rssi(hw, pcurrent_stats);
1101 _rtl92c_process_pwdb(hw, pcurrent_stats);
1102 _rtl92c_process_LINK_Q(hw, pcurrent_stats);
1103}
1104
1105void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
1106 struct sk_buff *skb,
1107 struct rtl_stats *pstats,
1108 struct rx_desc_92c *pdesc,
1109 struct rx_fwinfo_92c *p_drvinfo)
1110{
1111 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1112 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1113 struct ieee80211_hdr *hdr;
1114 u8 *tmp_buf;
1115 u8 *praddr;
1116 u8 *psaddr;
1117 __le16 fc;
1118 u16 type, cpu_fc;
1119 bool packet_matchbssid, packet_toself, packet_beacon;
1120
1121 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
1122 hdr = (struct ieee80211_hdr *)tmp_buf;
1123 fc = hdr->frame_control;
1124 cpu_fc = le16_to_cpu(fc);
1125 type = WLAN_FC_GET_TYPE(fc);
1126 praddr = hdr->addr1;
1127 psaddr = hdr->addr2;
1128 packet_matchbssid =
1129 ((IEEE80211_FTYPE_CTL != type) &&
1130 (!compare_ether_addr(mac->bssid,
1131 (cpu_fc & IEEE80211_FCTL_TODS) ?
1132 hdr->addr1 : (cpu_fc & IEEE80211_FCTL_FROMDS) ?
1133 hdr->addr2 : hdr->addr3)) &&
1134 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
1135
1136 packet_toself = packet_matchbssid &&
1137 (!compare_ether_addr(praddr, rtlefuse->dev_addr));
1138 if (ieee80211_is_beacon(fc))
1139 packet_beacon = true;
1140 _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
1141 packet_matchbssid, packet_toself,
1142 packet_beacon);
1143 _rtl92c_process_phyinfo(hw, tmp_buf, pstats);
1144}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.h b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.h
new file mode 100644
index 000000000000..298fdb724aa5
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.h
@@ -0,0 +1,180 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_MAC_H__
31#define __RTL92C_MAC_H__
32
33#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
34#define DRIVER_EARLY_INT_TIME 0x05
35#define BCN_DMA_ATIME_INT_TIME 0x02
36
37void rtl92c_read_chip_version(struct ieee80211_hw *hw);
38bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data);
39bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary);
40void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
41 u8 *p_macaddr, bool is_group, u8 enc_algo,
42 bool is_wepkey, bool clear_all);
43void rtl92c_enable_interrupt(struct ieee80211_hw *hw);
44void rtl92c_disable_interrupt(struct ieee80211_hw *hw);
45void rtl92c_set_qos(struct ieee80211_hw *hw, int aci);
46
47
48/*---------------------------------------------------------------
49 * Hardware init functions
50 *---------------------------------------------------------------*/
51void rtl92c_set_mac_addr(struct ieee80211_hw *hw, const u8 *addr);
52void rtl92c_init_interrupt(struct ieee80211_hw *hw);
53void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size);
54
55int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
56void rtl92c_init_network_type(struct ieee80211_hw *hw);
57void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw);
58void rtl92c_init_rate_fallback(struct ieee80211_hw *hw);
59
60void rtl92c_init_edca_param(struct ieee80211_hw *hw,
61 u16 queue,
62 u16 txop,
63 u8 ecwmax,
64 u8 ecwmin,
65 u8 aifs);
66
67void rtl92c_init_edca(struct ieee80211_hw *hw);
68void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw);
69void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw, bool infra_mode);
70void rtl92c_init_rdg_setting(struct ieee80211_hw *hw);
71void rtl92c_init_retry_function(struct ieee80211_hw *hw);
72
73void rtl92c_init_beacon_parameters(struct ieee80211_hw *hw,
74 enum version_8192c version);
75
76void rtl92c_disable_fast_edca(struct ieee80211_hw *hw);
77void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T);
78
79/* For filter */
80u16 rtl92c_get_mgt_filter(struct ieee80211_hw *hw);
81void rtl92c_set_mgt_filter(struct ieee80211_hw *hw, u16 filter);
82u16 rtl92c_get_ctrl_filter(struct ieee80211_hw *hw);
83void rtl92c_set_ctrl_filter(struct ieee80211_hw *hw, u16 filter);
84u16 rtl92c_get_data_filter(struct ieee80211_hw *hw);
85void rtl92c_set_data_filter(struct ieee80211_hw *hw, u16 filter);
86
87
88u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw);
89
90#define RX_HAL_IS_CCK_RATE(_pdesc)\
91 (GET_RX_DESC_RX_MCS(_pdesc) == DESC92C_RATE1M ||\
92 GET_RX_DESC_RX_MCS(_pdesc) == DESC92C_RATE2M ||\
93 GET_RX_DESC_RX_MCS(_pdesc) == DESC92C_RATE5_5M ||\
94 GET_RX_DESC_RX_MCS(_pdesc) == DESC92C_RATE11M)
95
96struct rx_fwinfo_92c {
97 u8 gain_trsw[4];
98 u8 pwdb_all;
99 u8 cfosho[4];
100 u8 cfotail[4];
101 char rxevm[2];
102 char rxsnr[4];
103 u8 pdsnr[2];
104 u8 csi_current[2];
105 u8 csi_target[2];
106 u8 sigevm;
107 u8 max_ex_pwr;
108 u8 ex_intf_flag:1;
109 u8 sgi_en:1;
110 u8 rxsc:2;
111 u8 reserve:4;
112} __packed;
113
114struct rx_desc_92c {
115 u32 length:14;
116 u32 crc32:1;
117 u32 icverror:1;
118 u32 drv_infosize:4;
119 u32 security:3;
120 u32 qos:1;
121 u32 shift:2;
122 u32 phystatus:1;
123 u32 swdec:1;
124 u32 lastseg:1;
125 u32 firstseg:1;
126 u32 eor:1;
127 u32 own:1;
128 u32 macid:5; /* word 1 */
129 u32 tid:4;
130 u32 hwrsvd:5;
131 u32 paggr:1;
132 u32 faggr:1;
133 u32 a1_fit:4;
134 u32 a2_fit:4;
135 u32 pam:1;
136 u32 pwr:1;
137 u32 moredata:1;
138 u32 morefrag:1;
139 u32 type:2;
140 u32 mc:1;
141 u32 bc:1;
142 u32 seq:12; /* word 2 */
143 u32 frag:4;
144 u32 nextpktlen:14;
145 u32 nextind:1;
146 u32 rsvd:1;
147 u32 rxmcs:6; /* word 3 */
148 u32 rxht:1;
149 u32 amsdu:1;
150 u32 splcp:1;
151 u32 bandwidth:1;
152 u32 htc:1;
153 u32 tcpchk_rpt:1;
154 u32 ipcchk_rpt:1;
155 u32 tcpchk_valid:1;
156 u32 hwpcerr:1;
157 u32 hwpcind:1;
158 u32 iv0:16;
159 u32 iv1; /* word 4 */
160 u32 tsfl; /* word 5 */
161 u32 bufferaddress; /* word 6 */
162 u32 bufferaddress64; /* word 7 */
163} __packed;
164
165enum rtl_desc_qsel rtl92c_map_hwqueue_to_fwqueue(u16 fc,
166 unsigned int
167 skb_queue);
168void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
169 struct sk_buff *skb,
170 struct rtl_stats *pstats,
171 struct rx_desc_92c *pdesc,
172 struct rx_fwinfo_92c *p_drvinfo);
173
174/*---------------------------------------------------------------
175 * Card disable functions
176 *---------------------------------------------------------------*/
177
178
179
180#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
new file mode 100644
index 000000000000..9a3d0239e27e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
@@ -0,0 +1,607 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39
40u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
41 enum radio_path rfpath, u32 regaddr, u32 bitmask)
42{
43 struct rtl_priv *rtlpriv = rtl_priv(hw);
44 u32 original_value, readback_value, bitshift;
45 struct rtl_phy *rtlphy = &(rtlpriv->phy);
46
47 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
48 "rfpath(%#x), bitmask(%#x)\n",
49 regaddr, rfpath, bitmask));
50 if (rtlphy->rf_mode != RF_OP_BY_FW) {
51 original_value = _rtl92c_phy_rf_serial_read(hw,
52 rfpath, regaddr);
53 } else {
54 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
55 rfpath, regaddr);
56 }
57 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
58 readback_value = (original_value & bitmask) >> bitshift;
59 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
60 ("regaddr(%#x), rfpath(%#x), "
61 "bitmask(%#x), original_value(%#x)\n",
62 regaddr, rfpath, bitmask, original_value));
63 return readback_value;
64}
65
66void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
67 enum radio_path rfpath,
68 u32 regaddr, u32 bitmask, u32 data)
69{
70 struct rtl_priv *rtlpriv = rtl_priv(hw);
71 struct rtl_phy *rtlphy = &(rtlpriv->phy);
72 u32 original_value, bitshift;
73
74 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
75 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
76 regaddr, bitmask, data, rfpath));
77 if (rtlphy->rf_mode != RF_OP_BY_FW) {
78 if (bitmask != RFREG_OFFSET_MASK) {
79 original_value = _rtl92c_phy_rf_serial_read(hw,
80 rfpath,
81 regaddr);
82 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
83 data =
84 ((original_value & (~bitmask)) |
85 (data << bitshift));
86 }
87 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
88 } else {
89 if (bitmask != RFREG_OFFSET_MASK) {
90 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
91 rfpath,
92 regaddr);
93 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
94 data =
95 ((original_value & (~bitmask)) |
96 (data << bitshift));
97 }
98 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
99 }
100 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
101 "bitmask(%#x), data(%#x), rfpath(%#x)\n",
102 regaddr, bitmask, data, rfpath));
103}
104
105bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw)
106{
107 bool rtstatus;
108 struct rtl_priv *rtlpriv = rtl_priv(hw);
109 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
110 bool is92c = IS_92C_SERIAL(rtlhal->version);
111
112 rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw);
113 if (is92c && IS_HARDWARE_TYPE_8192CE(rtlhal))
114 rtl_write_byte(rtlpriv, 0x14, 0x71);
115 return rtstatus;
116}
117
118bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
119{
120 bool rtstatus = true;
121 struct rtl_priv *rtlpriv = rtl_priv(hw);
122 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
123 u16 regval;
124 u8 b_reg_hwparafile = 1;
125
126 _rtl92c_phy_init_bb_rf_register_definition(hw);
127 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
128 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
129 BIT(0) | BIT(1));
130 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
131 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
132 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
133 if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
134 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
135 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
136 } else if (IS_HARDWARE_TYPE_8192CU(rtlhal)) {
137 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
138 FEN_BB_GLB_RSTn | FEN_BBRSTB);
139 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
140 }
141 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
142 if (b_reg_hwparafile == 1)
143 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
144 return rtstatus;
145}
146
147bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
148{
149 struct rtl_priv *rtlpriv = rtl_priv(hw);
150 struct rtl_phy *rtlphy = &(rtlpriv->phy);
151 u32 i;
152 u32 arraylength;
153 u32 *ptrarray;
154
155 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
156 arraylength = rtlphy->hwparam_tables[MAC_REG].length ;
157 ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
158 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
159 ("Img:RTL8192CEMAC_2T_ARRAY\n"));
160 for (i = 0; i < arraylength; i = i + 2)
161 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
162 return true;
163}
164
165bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
166 u8 configtype)
167{
168 int i;
169 u32 *phy_regarray_table;
170 u32 *agctab_array_table;
171 u16 phy_reg_arraylen, agctab_arraylen;
172 struct rtl_priv *rtlpriv = rtl_priv(hw);
173 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
174 struct rtl_phy *rtlphy = &(rtlpriv->phy);
175
176 if (IS_92C_SERIAL(rtlhal->version)) {
177 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
178 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_2T].pdata;
179 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
180 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
181 } else {
182 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
183 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_1T].pdata;
184 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
185 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
186 }
187 if (configtype == BASEBAND_CONFIG_PHY_REG) {
188 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
189 if (phy_regarray_table[i] == 0xfe)
190 mdelay(50);
191 else if (phy_regarray_table[i] == 0xfd)
192 mdelay(5);
193 else if (phy_regarray_table[i] == 0xfc)
194 mdelay(1);
195 else if (phy_regarray_table[i] == 0xfb)
196 udelay(50);
197 else if (phy_regarray_table[i] == 0xfa)
198 udelay(5);
199 else if (phy_regarray_table[i] == 0xf9)
200 udelay(1);
201 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
202 phy_regarray_table[i + 1]);
203 udelay(1);
204 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
205 ("The phy_regarray_table[0] is %x"
206 " Rtl819XPHY_REGArray[1] is %x\n",
207 phy_regarray_table[i],
208 phy_regarray_table[i + 1]));
209 }
210 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
211 for (i = 0; i < agctab_arraylen; i = i + 2) {
212 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
213 agctab_array_table[i + 1]);
214 udelay(1);
215 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
216 ("The agctab_array_table[0] is "
217 "%x Rtl819XPHY_REGArray[1] is %x\n",
218 agctab_array_table[i],
219 agctab_array_table[i + 1]));
220 }
221 }
222 return true;
223}
224
225bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
226 u8 configtype)
227{
228 struct rtl_priv *rtlpriv = rtl_priv(hw);
229 struct rtl_phy *rtlphy = &(rtlpriv->phy);
230 int i;
231 u32 *phy_regarray_table_pg;
232 u16 phy_regarray_pg_len;
233
234 rtlphy->pwrgroup_cnt = 0;
235 phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
236 phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
237 if (configtype == BASEBAND_CONFIG_PHY_REG) {
238 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
239 if (phy_regarray_table_pg[i] == 0xfe)
240 mdelay(50);
241 else if (phy_regarray_table_pg[i] == 0xfd)
242 mdelay(5);
243 else if (phy_regarray_table_pg[i] == 0xfc)
244 mdelay(1);
245 else if (phy_regarray_table_pg[i] == 0xfb)
246 udelay(50);
247 else if (phy_regarray_table_pg[i] == 0xfa)
248 udelay(5);
249 else if (phy_regarray_table_pg[i] == 0xf9)
250 udelay(1);
251 _rtl92c_store_pwrIndex_diffrate_offset(hw,
252 phy_regarray_table_pg[i],
253 phy_regarray_table_pg[i + 1],
254 phy_regarray_table_pg[i + 2]);
255 }
256 } else {
257 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
258 ("configtype != BaseBand_Config_PHY_REG\n"));
259 }
260 return true;
261}
262
263bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
264 enum radio_path rfpath)
265{
266 int i;
267 u32 *radioa_array_table;
268 u32 *radiob_array_table;
269 u16 radioa_arraylen, radiob_arraylen;
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
272 struct rtl_phy *rtlphy = &(rtlpriv->phy);
273
274 if (IS_92C_SERIAL(rtlhal->version)) {
275 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
276 radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
277 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
278 radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
279 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
280 ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
281 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
282 ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
283 } else {
284 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
285 radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
286 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
287 radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
288 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
289 ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
290 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
291 ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
292 }
293 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
294 switch (rfpath) {
295 case RF90_PATH_A:
296 for (i = 0; i < radioa_arraylen; i = i + 2) {
297 if (radioa_array_table[i] == 0xfe)
298 mdelay(50);
299 else if (radioa_array_table[i] == 0xfd)
300 mdelay(5);
301 else if (radioa_array_table[i] == 0xfc)
302 mdelay(1);
303 else if (radioa_array_table[i] == 0xfb)
304 udelay(50);
305 else if (radioa_array_table[i] == 0xfa)
306 udelay(5);
307 else if (radioa_array_table[i] == 0xf9)
308 udelay(1);
309 else {
310 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
311 RFREG_OFFSET_MASK,
312 radioa_array_table[i + 1]);
313 udelay(1);
314 }
315 }
316 break;
317 case RF90_PATH_B:
318 for (i = 0; i < radiob_arraylen; i = i + 2) {
319 if (radiob_array_table[i] == 0xfe) {
320 mdelay(50);
321 } else if (radiob_array_table[i] == 0xfd)
322 mdelay(5);
323 else if (radiob_array_table[i] == 0xfc)
324 mdelay(1);
325 else if (radiob_array_table[i] == 0xfb)
326 udelay(50);
327 else if (radiob_array_table[i] == 0xfa)
328 udelay(5);
329 else if (radiob_array_table[i] == 0xf9)
330 udelay(1);
331 else {
332 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
333 RFREG_OFFSET_MASK,
334 radiob_array_table[i + 1]);
335 udelay(1);
336 }
337 }
338 break;
339 case RF90_PATH_C:
340 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
341 ("switch case not process\n"));
342 break;
343 case RF90_PATH_D:
344 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
345 ("switch case not process\n"));
346 break;
347 }
348 return true;
349}
350
351void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
352{
353 struct rtl_priv *rtlpriv = rtl_priv(hw);
354 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
355 struct rtl_phy *rtlphy = &(rtlpriv->phy);
356 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
357 u8 reg_bw_opmode;
358 u8 reg_prsr_rsc;
359
360 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
361 ("Switch to %s bandwidth\n",
362 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
363 "20MHz" : "40MHz"))
364 if (is_hal_stop(rtlhal)) {
365 rtlphy->set_bwmode_inprogress = false;
366 return;
367 }
368 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
369 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
370 switch (rtlphy->current_chan_bw) {
371 case HT_CHANNEL_WIDTH_20:
372 reg_bw_opmode |= BW_OPMODE_20MHZ;
373 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
374 break;
375 case HT_CHANNEL_WIDTH_20_40:
376 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
377 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
378 reg_prsr_rsc =
379 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
380 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
381 break;
382 default:
383 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
384 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
385 break;
386 }
387 switch (rtlphy->current_chan_bw) {
388 case HT_CHANNEL_WIDTH_20:
389 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
390 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
391 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
392 break;
393 case HT_CHANNEL_WIDTH_20_40:
394 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
395 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
396 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
397 (mac->cur_40_prime_sc >> 1));
398 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
399 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
400 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
401 (mac->cur_40_prime_sc ==
402 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
403 break;
404 default:
405 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
406 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
407 break;
408 }
409 rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
410 rtlphy->set_bwmode_inprogress = false;
411 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
412}
413
414void rtl92cu_bb_block_on(struct ieee80211_hw *hw)
415{
416 struct rtl_priv *rtlpriv = rtl_priv(hw);
417
418 mutex_lock(&rtlpriv->io.bb_mutex);
419 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
420 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
421 mutex_unlock(&rtlpriv->io.bb_mutex);
422}
423
424void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
425{
426 u8 tmpreg;
427 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
428 struct rtl_priv *rtlpriv = rtl_priv(hw);
429
430 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
431
432 if ((tmpreg & 0x70) != 0)
433 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
434 else
435 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
436
437 if ((tmpreg & 0x70) != 0) {
438 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
439 if (is2t)
440 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
441 MASK12BITS);
442 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
443 (rf_a_mode & 0x8FFFF) | 0x10000);
444 if (is2t)
445 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
446 (rf_b_mode & 0x8FFFF) | 0x10000);
447 }
448 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
449 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
450 mdelay(100);
451 if ((tmpreg & 0x70) != 0) {
452 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
453 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
454 if (is2t)
455 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
456 rf_b_mode);
457 } else {
458 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
459 }
460}
461
462static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
463 enum rf_pwrstate rfpwr_state)
464{
465 struct rtl_priv *rtlpriv = rtl_priv(hw);
466 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
467 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
468 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
469 bool bresult = true;
470 u8 i, queue_id;
471 struct rtl8192_tx_ring *ring = NULL;
472
473 ppsc->set_rfpowerstate_inprogress = true;
474 switch (rfpwr_state) {
475 case ERFON:
476 if ((ppsc->rfpwr_state == ERFOFF) &&
477 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
478 bool rtstatus;
479 u32 InitializeCount = 0;
480
481 do {
482 InitializeCount++;
483 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
484 ("IPS Set eRf nic enable\n"));
485 rtstatus = rtl_ps_enable_nic(hw);
486 } while ((rtstatus != true)
487 && (InitializeCount < 10));
488 RT_CLEAR_PS_LEVEL(ppsc,
489 RT_RF_OFF_LEVL_HALT_NIC);
490 } else {
491 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
492 ("Set ERFON sleeped:%d ms\n",
493 jiffies_to_msecs(jiffies -
494 ppsc->
495 last_sleep_jiffies)));
496 ppsc->last_awake_jiffies = jiffies;
497 rtl92ce_phy_set_rf_on(hw);
498 }
499 if (mac->link_state == MAC80211_LINKED) {
500 rtlpriv->cfg->ops->led_control(hw,
501 LED_CTL_LINK);
502 } else {
503 rtlpriv->cfg->ops->led_control(hw,
504 LED_CTL_NO_LINK);
505 }
506 break;
507 case ERFOFF:
508 for (queue_id = 0, i = 0;
509 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
510 ring = &pcipriv->dev.tx_ring[queue_id];
511 if (skb_queue_len(&ring->queue) == 0 ||
512 queue_id == BEACON_QUEUE) {
513 queue_id++;
514 continue;
515 } else {
516 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
517 ("eRf Off/Sleep: %d times "
518 "TcbBusyQueue[%d] "
519 "=%d before doze!\n", (i + 1),
520 queue_id,
521 skb_queue_len(&ring->queue)));
522 udelay(10);
523 i++;
524 }
525 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
526 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
527 ("\nERFOFF: %d times "
528 "TcbBusyQueue[%d] = %d !\n",
529 MAX_DOZE_WAITING_TIMES_9x,
530 queue_id,
531 skb_queue_len(&ring->queue)));
532 break;
533 }
534 }
535 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
536 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
537 ("IPS Set eRf nic disable\n"));
538 rtl_ps_disable_nic(hw);
539 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
540 } else {
541 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
542 rtlpriv->cfg->ops->led_control(hw,
543 LED_CTL_NO_LINK);
544 } else {
545 rtlpriv->cfg->ops->led_control(hw,
546 LED_CTL_POWER_OFF);
547 }
548 }
549 break;
550 case ERFSLEEP:
551 if (ppsc->rfpwr_state == ERFOFF)
552 break;
553 for (queue_id = 0, i = 0;
554 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
555 ring = &pcipriv->dev.tx_ring[queue_id];
556 if (skb_queue_len(&ring->queue) == 0) {
557 queue_id++;
558 continue;
559 } else {
560 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
561 ("eRf Off/Sleep: %d times "
562 "TcbBusyQueue[%d] =%d before "
563 "doze!\n", (i + 1), queue_id,
564 skb_queue_len(&ring->queue)));
565 udelay(10);
566 i++;
567 }
568 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
569 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
570 ("\n ERFSLEEP: %d times "
571 "TcbBusyQueue[%d] = %d !\n",
572 MAX_DOZE_WAITING_TIMES_9x,
573 queue_id,
574 skb_queue_len(&ring->queue)));
575 break;
576 }
577 }
578 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
579 ("Set ERFSLEEP awaked:%d ms\n",
580 jiffies_to_msecs(jiffies -
581 ppsc->last_awake_jiffies)));
582 ppsc->last_sleep_jiffies = jiffies;
583 _rtl92c_phy_set_rf_sleep(hw);
584 break;
585 default:
586 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
587 ("switch case not process\n"));
588 bresult = false;
589 break;
590 }
591 if (bresult)
592 ppsc->rfpwr_state = rfpwr_state;
593 ppsc->set_rfpowerstate_inprogress = false;
594 return bresult;
595}
596
597bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
598 enum rf_pwrstate rfpwr_state)
599{
600 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
601 bool bresult = false;
602
603 if (rfpwr_state == ppsc->rfpwr_state)
604 return bresult;
605 bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state);
606 return bresult;
607}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.h b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.h
new file mode 100644
index 000000000000..ff81a61729d7
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.h
@@ -0,0 +1,50 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../rtl8192ce/phy.h"
31
32void rtl92cu_bb_block_on(struct ieee80211_hw *hw);
33bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath);
34void rtl92c_phy_set_io(struct ieee80211_hw *hw);
35bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
36bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw);
37u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
38 enum radio_path rfpath, u32 regaddr, u32 bitmask);
39void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
40 enum radio_path rfpath,
41 u32 regaddr, u32 bitmask, u32 data);
42bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw);
43bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
44 u8 configtype);
45void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
46bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
47 u8 configtype);
48void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
49bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
50 enum rf_pwrstate rfpwr_state);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/reg.h b/drivers/net/wireless/rtlwifi/rtl8192cu/reg.h
new file mode 100644
index 000000000000..7f1be614c998
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/reg.h
@@ -0,0 +1,30 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../rtl8192ce/reg.h"
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
new file mode 100644
index 000000000000..c7576ec4744e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
@@ -0,0 +1,493 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "reg.h"
32#include "def.h"
33#include "phy.h"
34#include "rf.h"
35#include "dm.h"
36
37static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
38
39void rtl92cu_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 struct rtl_phy *rtlphy = &(rtlpriv->phy);
43
44 switch (bandwidth) {
45 case HT_CHANNEL_WIDTH_20:
46 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
47 0xfffff3ff) | 0x0400);
48 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
49 rtlphy->rfreg_chnlval[0]);
50 break;
51 case HT_CHANNEL_WIDTH_20_40:
52 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
53 0xfffff3ff));
54 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
55 rtlphy->rfreg_chnlval[0]);
56 break;
57 default:
58 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
59 ("unknown bandwidth: %#X\n", bandwidth));
60 break;
61 }
62}
63
64void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
65 u8 *ppowerlevel)
66{
67 struct rtl_priv *rtlpriv = rtl_priv(hw);
68 struct rtl_phy *rtlphy = &(rtlpriv->phy);
69 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
70 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
71 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
72 u32 tx_agc[2] = { 0, 0 }, tmpval = 0;
73 bool turbo_scanoff = false;
74 u8 idx1, idx2;
75 u8 *ptr;
76
77 if (rtlhal->interface == INTF_PCI) {
78 if (rtlefuse->eeprom_regulatory != 0)
79 turbo_scanoff = true;
80 } else {
81 if ((rtlefuse->eeprom_regulatory != 0) ||
82 (rtlefuse->external_pa))
83 turbo_scanoff = true;
84 }
85 if (mac->act_scanning == true) {
86 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
87 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
88 if (turbo_scanoff) {
89 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
90 tx_agc[idx1] = ppowerlevel[idx1] |
91 (ppowerlevel[idx1] << 8) |
92 (ppowerlevel[idx1] << 16) |
93 (ppowerlevel[idx1] << 24);
94 if (rtlhal->interface == INTF_USB) {
95 if (tx_agc[idx1] > 0x20 &&
96 rtlefuse->external_pa)
97 tx_agc[idx1] = 0x20;
98 }
99 }
100 }
101 } else {
102 if (rtlpriv->dm.dynamic_txhighpower_lvl ==
103 TXHIGHPWRLEVEL_LEVEL1) {
104 tx_agc[RF90_PATH_A] = 0x10101010;
105 tx_agc[RF90_PATH_B] = 0x10101010;
106 } else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
107 TXHIGHPWRLEVEL_LEVEL1) {
108 tx_agc[RF90_PATH_A] = 0x00000000;
109 tx_agc[RF90_PATH_B] = 0x00000000;
110 } else{
111 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
112 tx_agc[idx1] = ppowerlevel[idx1] |
113 (ppowerlevel[idx1] << 8) |
114 (ppowerlevel[idx1] << 16) |
115 (ppowerlevel[idx1] << 24);
116 }
117 if (rtlefuse->eeprom_regulatory == 0) {
118 tmpval = (rtlphy->mcs_txpwrlevel_origoffset
119 [0][6]) +
120 (rtlphy->mcs_txpwrlevel_origoffset
121 [0][7] << 8);
122 tx_agc[RF90_PATH_A] += tmpval;
123 tmpval = (rtlphy->mcs_txpwrlevel_origoffset
124 [0][14]) +
125 (rtlphy->mcs_txpwrlevel_origoffset
126 [0][15] << 24);
127 tx_agc[RF90_PATH_B] += tmpval;
128 }
129 }
130 }
131 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
132 ptr = (u8 *) (&(tx_agc[idx1]));
133 for (idx2 = 0; idx2 < 4; idx2++) {
134 if (*ptr > RF6052_MAX_TX_PWR)
135 *ptr = RF6052_MAX_TX_PWR;
136 ptr++;
137 }
138 }
139 tmpval = tx_agc[RF90_PATH_A] & 0xff;
140 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
141
142 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
143 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
144 RTXAGC_A_CCK1_MCS32));
145
146 tmpval = tx_agc[RF90_PATH_A] >> 8;
147 if (mac->mode == WIRELESS_MODE_B)
148 tmpval = tmpval & 0xff00ffff;
149 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
150 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
151 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
152 RTXAGC_B_CCK11_A_CCK2_11));
153 tmpval = tx_agc[RF90_PATH_B] >> 24;
154 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
155 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
156 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
157 RTXAGC_B_CCK11_A_CCK2_11));
158 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
159 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
160 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
161 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
162 RTXAGC_B_CCK1_55_MCS32));
163}
164
165static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
166 u8 *ppowerlevel, u8 channel,
167 u32 *ofdmbase, u32 *mcsbase)
168{
169 struct rtl_priv *rtlpriv = rtl_priv(hw);
170 struct rtl_phy *rtlphy = &(rtlpriv->phy);
171 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
172 u32 powerBase0, powerBase1;
173 u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0;
174 u8 i, powerlevel[2];
175
176 for (i = 0; i < 2; i++) {
177 powerlevel[i] = ppowerlevel[i];
178 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
179 powerBase0 = powerlevel[i] + legacy_pwrdiff;
180 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
181 (powerBase0 << 8) | powerBase0;
182 *(ofdmbase + i) = powerBase0;
183 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
184 (" [OFDM power base index rf(%c) = 0x%x]\n",
185 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
186 }
187 for (i = 0; i < 2; i++) {
188 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
189 ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
190 powerlevel[i] += ht20_pwrdiff;
191 }
192 powerBase1 = powerlevel[i];
193 powerBase1 = (powerBase1 << 24) |
194 (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
195 *(mcsbase + i) = powerBase1;
196 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
197 (" [MCS power base index rf(%c) = 0x%x]\n",
198 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
199 }
200}
201
202static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
203 u8 channel, u8 index,
204 u32 *powerBase0,
205 u32 *powerBase1,
206 u32 *p_outwriteval)
207{
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209 struct rtl_phy *rtlphy = &(rtlpriv->phy);
210 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
211 u8 i, chnlgroup = 0, pwr_diff_limit[4];
212 u32 writeVal, customer_limit, rf;
213
214 for (rf = 0; rf < 2; rf++) {
215 switch (rtlefuse->eeprom_regulatory) {
216 case 0:
217 chnlgroup = 0;
218 writeVal = rtlphy->mcs_txpwrlevel_origoffset
219 [chnlgroup][index + (rf ? 8 : 0)]
220 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
221 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
222 ("RTK better performance,writeVal(%c) = 0x%x\n",
223 ((rf == 0) ? 'A' : 'B'), writeVal));
224 break;
225 case 1:
226 if (rtlphy->pwrgroup_cnt == 1)
227 chnlgroup = 0;
228 if (rtlphy->pwrgroup_cnt >= 3) {
229 if (channel <= 3)
230 chnlgroup = 0;
231 else if (channel >= 4 && channel <= 9)
232 chnlgroup = 1;
233 else if (channel > 9)
234 chnlgroup = 2;
235 if (rtlphy->current_chan_bw ==
236 HT_CHANNEL_WIDTH_20)
237 chnlgroup++;
238 else
239 chnlgroup += 4;
240 }
241 writeVal = rtlphy->mcs_txpwrlevel_origoffset
242 [chnlgroup][index +
243 (rf ? 8 : 0)] +
244 ((index < 2) ? powerBase0[rf] :
245 powerBase1[rf]);
246 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
247 ("Realtek regulatory, 20MHz, "
248 "writeVal(%c) = 0x%x\n",
249 ((rf == 0) ? 'A' : 'B'), writeVal));
250 break;
251 case 2:
252 writeVal = ((index < 2) ? powerBase0[rf] :
253 powerBase1[rf]);
254 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
255 ("Better regulatory,writeVal(%c) = 0x%x\n",
256 ((rf == 0) ? 'A' : 'B'), writeVal));
257 break;
258 case 3:
259 chnlgroup = 0;
260 if (rtlphy->current_chan_bw ==
261 HT_CHANNEL_WIDTH_20_40) {
262 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
263 ("customer's limit, 40MHzrf(%c) = "
264 "0x%x\n", ((rf == 0) ? 'A' : 'B'),
265 rtlefuse->pwrgroup_ht40[rf]
266 [channel - 1]));
267 } else {
268 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
269 ("customer's limit, 20MHz rf(%c) = "
270 "0x%x\n", ((rf == 0) ? 'A' : 'B'),
271 rtlefuse->pwrgroup_ht20[rf]
272 [channel - 1]));
273 }
274 for (i = 0; i < 4; i++) {
275 pwr_diff_limit[i] =
276 (u8) ((rtlphy->mcs_txpwrlevel_origoffset
277 [chnlgroup][index + (rf ? 8 : 0)]
278 & (0x7f << (i * 8))) >> (i * 8));
279 if (rtlphy->current_chan_bw ==
280 HT_CHANNEL_WIDTH_20_40) {
281 if (pwr_diff_limit[i] >
282 rtlefuse->pwrgroup_ht40[rf]
283 [channel - 1])
284 pwr_diff_limit[i] = rtlefuse->
285 pwrgroup_ht40[rf]
286 [channel - 1];
287 } else {
288 if (pwr_diff_limit[i] >
289 rtlefuse->pwrgroup_ht20[rf]
290 [channel - 1])
291 pwr_diff_limit[i] =
292 rtlefuse->pwrgroup_ht20[rf]
293 [channel - 1];
294 }
295 }
296 customer_limit = (pwr_diff_limit[3] << 24) |
297 (pwr_diff_limit[2] << 16) |
298 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
299 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
300 ("Customer's limit rf(%c) = 0x%x\n",
301 ((rf == 0) ? 'A' : 'B'), customer_limit));
302 writeVal = customer_limit + ((index < 2) ?
303 powerBase0[rf] : powerBase1[rf]);
304 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
305 ("Customer, writeVal rf(%c)= 0x%x\n",
306 ((rf == 0) ? 'A' : 'B'), writeVal));
307 break;
308 default:
309 chnlgroup = 0;
310 writeVal = rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
311 [index + (rf ? 8 : 0)] + ((index < 2) ?
312 powerBase0[rf] : powerBase1[rf]);
313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("RTK better "
314 "performance, writeValrf(%c) = 0x%x\n",
315 ((rf == 0) ? 'A' : 'B'), writeVal));
316 break;
317 }
318 if (rtlpriv->dm.dynamic_txhighpower_lvl ==
319 TXHIGHPWRLEVEL_LEVEL1)
320 writeVal = 0x14141414;
321 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
322 TXHIGHPWRLEVEL_LEVEL2)
323 writeVal = 0x00000000;
324 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
325 writeVal = writeVal - 0x06060606;
326 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
327 TXHIGHPWRLEVEL_BT2)
328 writeVal = writeVal;
329 *(p_outwriteval + rf) = writeVal;
330 }
331}
332
333static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
334 u8 index, u32 *pValue)
335{
336 struct rtl_priv *rtlpriv = rtl_priv(hw);
337 struct rtl_phy *rtlphy = &(rtlpriv->phy);
338 u16 regoffset_a[6] = {
339 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
340 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
341 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
342 };
343 u16 regoffset_b[6] = {
344 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
345 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
346 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
347 };
348 u8 i, rf, pwr_val[4];
349 u32 writeVal;
350 u16 regoffset;
351
352 for (rf = 0; rf < 2; rf++) {
353 writeVal = pValue[rf];
354 for (i = 0; i < 4; i++) {
355 pwr_val[i] = (u8)((writeVal & (0x7f << (i * 8))) >>
356 (i * 8));
357 if (pwr_val[i] > RF6052_MAX_TX_PWR)
358 pwr_val[i] = RF6052_MAX_TX_PWR;
359 }
360 writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
361 (pwr_val[1] << 8) | pwr_val[0];
362 if (rf == 0)
363 regoffset = regoffset_a[index];
364 else
365 regoffset = regoffset_b[index];
366 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
367 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
368 ("Set 0x%x = %08x\n", regoffset, writeVal));
369 if (((get_rf_type(rtlphy) == RF_2T2R) &&
370 (regoffset == RTXAGC_A_MCS15_MCS12 ||
371 regoffset == RTXAGC_B_MCS15_MCS12)) ||
372 ((get_rf_type(rtlphy) != RF_2T2R) &&
373 (regoffset == RTXAGC_A_MCS07_MCS04 ||
374 regoffset == RTXAGC_B_MCS07_MCS04))) {
375 writeVal = pwr_val[3];
376 if (regoffset == RTXAGC_A_MCS15_MCS12 ||
377 regoffset == RTXAGC_A_MCS07_MCS04)
378 regoffset = 0xc90;
379 if (regoffset == RTXAGC_B_MCS15_MCS12 ||
380 regoffset == RTXAGC_B_MCS07_MCS04)
381 regoffset = 0xc98;
382 for (i = 0; i < 3; i++) {
383 writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
384 rtl_write_byte(rtlpriv, (u32)(regoffset + i),
385 (u8)writeVal);
386 }
387 }
388 }
389}
390
391void rtl92cu_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
392 u8 *ppowerlevel, u8 channel)
393{
394 u32 writeVal[2], powerBase0[2], powerBase1[2];
395 u8 index = 0;
396
397 rtl92c_phy_get_power_base(hw, ppowerlevel,
398 channel, &powerBase0[0], &powerBase1[0]);
399 for (index = 0; index < 6; index++) {
400 _rtl92c_get_txpower_writeval_by_regulatory(hw,
401 channel, index,
402 &powerBase0[0],
403 &powerBase1[0],
404 &writeVal[0]);
405 _rtl92c_write_ofdm_power_reg(hw, index, &writeVal[0]);
406 }
407}
408
409bool rtl92cu_phy_rf6052_config(struct ieee80211_hw *hw)
410{
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412 struct rtl_phy *rtlphy = &(rtlpriv->phy);
413 bool rtstatus = true;
414 u8 b_reg_hwparafile = 1;
415
416 if (rtlphy->rf_type == RF_1T1R)
417 rtlphy->num_total_rfpath = 1;
418 else
419 rtlphy->num_total_rfpath = 2;
420 if (b_reg_hwparafile == 1)
421 rtstatus = _rtl92c_phy_rf6052_config_parafile(hw);
422 return rtstatus;
423}
424
425static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
426{
427 struct rtl_priv *rtlpriv = rtl_priv(hw);
428 struct rtl_phy *rtlphy = &(rtlpriv->phy);
429 u32 u4_regvalue = 0;
430 u8 rfpath;
431 bool rtstatus = true;
432 struct bb_reg_def *pphyreg;
433
434 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
435 pphyreg = &rtlphy->phyreg_def[rfpath];
436 switch (rfpath) {
437 case RF90_PATH_A:
438 case RF90_PATH_C:
439 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
440 BRFSI_RFENV);
441 break;
442 case RF90_PATH_B:
443 case RF90_PATH_D:
444 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
445 BRFSI_RFENV << 16);
446 break;
447 }
448 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
449 udelay(1);
450 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
451 udelay(1);
452 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
453 B3WIREADDREAALENGTH, 0x0);
454 udelay(1);
455 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
456 udelay(1);
457 switch (rfpath) {
458 case RF90_PATH_A:
459 rtstatus = rtl92cu_phy_config_rf_with_headerfile(hw,
460 (enum radio_path) rfpath);
461 break;
462 case RF90_PATH_B:
463 rtstatus = rtl92cu_phy_config_rf_with_headerfile(hw,
464 (enum radio_path) rfpath);
465 break;
466 case RF90_PATH_C:
467 break;
468 case RF90_PATH_D:
469 break;
470 }
471 switch (rfpath) {
472 case RF90_PATH_A:
473 case RF90_PATH_C:
474 rtl_set_bbreg(hw, pphyreg->rfintfs,
475 BRFSI_RFENV, u4_regvalue);
476 break;
477 case RF90_PATH_B:
478 case RF90_PATH_D:
479 rtl_set_bbreg(hw, pphyreg->rfintfs,
480 BRFSI_RFENV << 16, u4_regvalue);
481 break;
482 }
483 if (rtstatus != true) {
484 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
485 ("Radio[%d] Fail!!", rfpath));
486 goto phy_rf_cfg_fail;
487 }
488 }
489 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
490 return rtstatus;
491phy_rf_cfg_fail:
492 return rtstatus;
493}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/rf.h b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.h
new file mode 100644
index 000000000000..500a2094b6bb
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.h
@@ -0,0 +1,51 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_RF_H__
31#define __RTL92CU_RF_H__
32
33#define RF6052_MAX_TX_PWR 0x3F
34#define RF6052_MAX_REG 0x3F
35#define RF6052_MAX_PATH 2
36
37extern void rtl92cu_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
38 u8 bandwidth);
39extern void rtl92c_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
40 u8 *ppowerlevel);
41extern void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
42 u8 *ppowerlevel, u8 channel);
43bool rtl92cu_phy_rf6052_config(struct ieee80211_hw *hw);
44bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
45 enum radio_path rfpath);
46void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
47 u8 *ppowerlevel);
48void rtl92cu_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
49 u8 *ppowerlevel, u8 channel);
50
51#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
new file mode 100644
index 000000000000..942f7a3969a7
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -0,0 +1,357 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../core.h"
32#include "../usb.h"
33#include "../efuse.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "mac.h"
38#include "dm.h"
39#include "rf.h"
40#include "sw.h"
41#include "trx.h"
42#include "led.h"
43#include "hw.h"
44#include <linux/vmalloc.h>
45
46MODULE_AUTHOR("Georgia <georgia@realtek.com>");
47MODULE_AUTHOR("Ziv Huang <ziv_huang@realtek.com>");
48MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
49MODULE_LICENSE("GPL");
50MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n USB wireless");
51MODULE_FIRMWARE("rtlwifi/rtl8192cufw.bin");
52
53static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw)
54{
55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56 const struct firmware *firmware;
57 int err;
58
59 rtlpriv->dm.dm_initialgain_enable = 1;
60 rtlpriv->dm.dm_flag = 0;
61 rtlpriv->dm.disable_framebursting = 0;
62 rtlpriv->dm.thermalvalue = 0;
63 rtlpriv->rtlhal.pfirmware = vmalloc(0x4000);
64 if (!rtlpriv->rtlhal.pfirmware) {
65 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
66 ("Can't alloc buffer for fw.\n"));
67 return 1;
68 }
69 /* request fw */
70 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
71 rtlpriv->io.dev);
72 if (err) {
73 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
74 ("Failed to request firmware!\n"));
75 return 1;
76 }
77 if (firmware->size > 0x4000) {
78 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
79 ("Firmware is too big!\n"));
80 release_firmware(firmware);
81 return 1;
82 }
83 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
84 rtlpriv->rtlhal.fwsize = firmware->size;
85 release_firmware(firmware);
86
87 return 0;
88}
89
90static void rtl92cu_deinit_sw_vars(struct ieee80211_hw *hw)
91{
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93
94 if (rtlpriv->rtlhal.pfirmware) {
95 vfree(rtlpriv->rtlhal.pfirmware);
96 rtlpriv->rtlhal.pfirmware = NULL;
97 }
98}
99
100static struct rtl_hal_ops rtl8192cu_hal_ops = {
101 .init_sw_vars = rtl92cu_init_sw_vars,
102 .deinit_sw_vars = rtl92cu_deinit_sw_vars,
103 .read_chip_version = rtl92c_read_chip_version,
104 .read_eeprom_info = rtl92cu_read_eeprom_info,
105 .enable_interrupt = rtl92c_enable_interrupt,
106 .disable_interrupt = rtl92c_disable_interrupt,
107 .hw_init = rtl92cu_hw_init,
108 .hw_disable = rtl92cu_card_disable,
109 .set_network_type = rtl92cu_set_network_type,
110 .set_chk_bssid = rtl92cu_set_check_bssid,
111 .set_qos = rtl92c_set_qos,
112 .set_bcn_reg = rtl92cu_set_beacon_related_registers,
113 .set_bcn_intv = rtl92cu_set_beacon_interval,
114 .update_interrupt_mask = rtl92cu_update_interrupt_mask,
115 .get_hw_reg = rtl92cu_get_hw_reg,
116 .set_hw_reg = rtl92cu_set_hw_reg,
117 .update_rate_tbl = rtl92cu_update_hal_rate_table,
118 .update_rate_mask = rtl92cu_update_hal_rate_mask,
119 .fill_tx_desc = rtl92cu_tx_fill_desc,
120 .fill_fake_txdesc = rtl92cu_fill_fake_txdesc,
121 .fill_tx_cmddesc = rtl92cu_tx_fill_cmddesc,
122 .cmd_send_packet = rtl92cu_cmd_send_packet,
123 .query_rx_desc = rtl92cu_rx_query_desc,
124 .set_channel_access = rtl92cu_update_channel_access_setting,
125 .radio_onoff_checking = rtl92cu_gpio_radio_on_off_checking,
126 .set_bw_mode = rtl92c_phy_set_bw_mode,
127 .switch_channel = rtl92c_phy_sw_chnl,
128 .dm_watchdog = rtl92c_dm_watchdog,
129 .scan_operation_backup = rtl92c_phy_scan_operation_backup,
130 .set_rf_power_state = rtl92cu_phy_set_rf_power_state,
131 .led_control = rtl92cu_led_control,
132 .enable_hw_sec = rtl92cu_enable_hw_security_config,
133 .set_key = rtl92c_set_key,
134 .init_sw_leds = rtl92cu_init_sw_leds,
135 .deinit_sw_leds = rtl92cu_deinit_sw_leds,
136 .get_bbreg = rtl92c_phy_query_bb_reg,
137 .set_bbreg = rtl92c_phy_set_bb_reg,
138 .get_rfreg = rtl92cu_phy_query_rf_reg,
139 .set_rfreg = rtl92cu_phy_set_rf_reg,
140 .phy_rf6052_config = rtl92cu_phy_rf6052_config,
141 .phy_rf6052_set_cck_txpower = rtl92cu_phy_rf6052_set_cck_txpower,
142 .phy_rf6052_set_ofdm_txpower = rtl92cu_phy_rf6052_set_ofdm_txpower,
143 .config_bb_with_headerfile = _rtl92cu_phy_config_bb_with_headerfile,
144 .config_bb_with_pgheaderfile = _rtl92cu_phy_config_bb_with_pgheaderfile,
145 .phy_lc_calibrate = _rtl92cu_phy_lc_calibrate,
146 .phy_set_bw_mode_callback = rtl92cu_phy_set_bw_mode_callback,
147 .dm_dynamic_txpower = rtl92cu_dm_dynamic_txpower,
148};
149
150static struct rtl_mod_params rtl92cu_mod_params = {
151 .sw_crypto = 0,
152};
153
154static struct rtl_hal_usbint_cfg rtl92cu_interface_cfg = {
155 /* rx */
156 .in_ep_num = RTL92C_USB_BULK_IN_NUM,
157 .rx_urb_num = RTL92C_NUM_RX_URBS,
158 .rx_max_size = RTL92C_SIZE_MAX_RX_BUFFER,
159 .usb_rx_hdl = rtl8192cu_rx_hdl,
160 .usb_rx_segregate_hdl = NULL, /* rtl8192c_rx_segregate_hdl; */
161 /* tx */
162 .usb_tx_cleanup = rtl8192c_tx_cleanup,
163 .usb_tx_post_hdl = rtl8192c_tx_post_hdl,
164 .usb_tx_aggregate_hdl = rtl8192c_tx_aggregate_hdl,
165 /* endpoint mapping */
166 .usb_endpoint_mapping = rtl8192cu_endpoint_mapping,
167 .usb_mq_to_hwq = rtl8192cu_mq_to_hwq,
168};
169
170static struct rtl_hal_cfg rtl92cu_hal_cfg = {
171 .name = "rtl92c_usb",
172 .fw_name = "rtlwifi/rtl8192cufw.bin",
173 .ops = &rtl8192cu_hal_ops,
174 .mod_params = &rtl92cu_mod_params,
175 .usb_interface_cfg = &rtl92cu_interface_cfg,
176
177 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
178 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
179 .maps[SYS_CLK] = REG_SYS_CLKR,
180 .maps[MAC_RCR_AM] = AM,
181 .maps[MAC_RCR_AB] = AB,
182 .maps[MAC_RCR_ACRC32] = ACRC32,
183 .maps[MAC_RCR_ACF] = ACF,
184 .maps[MAC_RCR_AAP] = AAP,
185
186 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
187 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
188 .maps[EFUSE_CLK] = 0,
189 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
190 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
191 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
192 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
193 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
194 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
195 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
196 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
197
198 .maps[RWCAM] = REG_CAMCMD,
199 .maps[WCAMI] = REG_CAMWRITE,
200 .maps[RCAMO] = REG_CAMREAD,
201 .maps[CAMDBG] = REG_CAMDBG,
202 .maps[SECR] = REG_SECCFG,
203 .maps[SEC_CAM_NONE] = CAM_NONE,
204 .maps[SEC_CAM_WEP40] = CAM_WEP40,
205 .maps[SEC_CAM_TKIP] = CAM_TKIP,
206 .maps[SEC_CAM_AES] = CAM_AES,
207 .maps[SEC_CAM_WEP104] = CAM_WEP104,
208
209 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
210 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
211 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
212 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
213 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
214 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
215 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
216 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
217 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
218 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
219 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
220 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
221 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
222 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
223 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
224 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
225
226 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
227 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
228 .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
229 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
230 .maps[RTL_IMR_RDU] = IMR_RDU,
231 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
232 .maps[RTL_IMR_BDOK] = IMR_BDOK,
233 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
234 .maps[RTL_IMR_TBDER] = IMR_TBDER,
235 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
236 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
237 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
238 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
239 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
240 .maps[RTL_IMR_VODOK] = IMR_VODOK,
241 .maps[RTL_IMR_ROK] = IMR_ROK,
242 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
243
244 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
245 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
246 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
247 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
248 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
249 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
250 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
251 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
252 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
253 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
254 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
255 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
256 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
257 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
258};
259
260#define USB_VENDER_ID_REALTEK 0x0bda
261
262/* 2010-10-19 DID_USB_V3.4 */
263static struct usb_device_id rtl8192c_usb_ids[] = {
264
265 /*=== Realtek demoboard ===*/
266 /* Default ID */
267 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8191, rtl92cu_hal_cfg)},
268
269 /****** 8188CU ********/
270 /* 8188CE-VAU USB minCard */
271 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8170, rtl92cu_hal_cfg)},
272 /* 8188cu 1*1 dongle */
273 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8176, rtl92cu_hal_cfg)},
274 /* 8188cu 1*1 dongle, (b/g mode only) */
275 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8177, rtl92cu_hal_cfg)},
276 /* 8188cu Slim Solo */
277 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817a, rtl92cu_hal_cfg)},
278 /* 8188cu Slim Combo */
279 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817b, rtl92cu_hal_cfg)},
280 /* 8188RU High-power USB Dongle */
281 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817d, rtl92cu_hal_cfg)},
282 /* 8188CE-VAU USB minCard (b/g mode only) */
283 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817e, rtl92cu_hal_cfg)},
284 /* 8188 Combo for BC4 */
285 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8754, rtl92cu_hal_cfg)},
286
287 /****** 8192CU ********/
288 /* 8191cu 1*2 */
289 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8177, rtl92cu_hal_cfg)},
290 /* 8192cu 2*2 */
291 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817b, rtl92cu_hal_cfg)},
292 /* 8192CE-VAU USB minCard */
293 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817c, rtl92cu_hal_cfg)},
294
295 /*=== Customer ID ===*/
296 /****** 8188CU ********/
297 {RTL_USB_DEVICE(0x050d, 0x1102, rtl92cu_hal_cfg)}, /*Belkin - Edimax*/
298 {RTL_USB_DEVICE(0x06f8, 0xe033, rtl92cu_hal_cfg)}, /*Hercules - Edimax*/
299 {RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/
300 {RTL_USB_DEVICE(0x07b8, 0x8189, rtl92cu_hal_cfg)}, /*Funai - Abocom*/
301 {RTL_USB_DEVICE(0x0846, 0x9041, rtl92cu_hal_cfg)}, /*NetGear WNA1000M*/
302 {RTL_USB_DEVICE(0x0Df6, 0x0052, rtl92cu_hal_cfg)}, /*Sitecom - Edimax*/
303 {RTL_USB_DEVICE(0x0eb0, 0x9071, rtl92cu_hal_cfg)}, /*NO Brand - Etop*/
304 /* HP - Lite-On ,8188CUS Slim Combo */
305 {RTL_USB_DEVICE(0x103c, 0x1629, rtl92cu_hal_cfg)},
306 {RTL_USB_DEVICE(0x2001, 0x3308, rtl92cu_hal_cfg)}, /*D-Link - Alpha*/
307 {RTL_USB_DEVICE(0x2019, 0xab2a, rtl92cu_hal_cfg)}, /*Planex - Abocom*/
308 {RTL_USB_DEVICE(0x2019, 0xed17, rtl92cu_hal_cfg)}, /*PCI - Edimax*/
309 {RTL_USB_DEVICE(0x20f4, 0x648b, rtl92cu_hal_cfg)}, /*TRENDnet - Cameo*/
310 {RTL_USB_DEVICE(0x7392, 0x7811, rtl92cu_hal_cfg)}, /*Edimax - Edimax*/
311 {RTL_USB_DEVICE(0x3358, 0x13d3, rtl92cu_hal_cfg)}, /*Azwave 8188CE-VAU*/
312 /* Russian customer -Azwave (8188CE-VAU b/g mode only) */
313 {RTL_USB_DEVICE(0x3359, 0x13d3, rtl92cu_hal_cfg)},
314
315 /****** 8192CU ********/
316 {RTL_USB_DEVICE(0x0586, 0x341f, rtl92cu_hal_cfg)}, /*Zyxel -Abocom*/
317 {RTL_USB_DEVICE(0x07aa, 0x0056, rtl92cu_hal_cfg)}, /*ATKK-Gemtek*/
318 {RTL_USB_DEVICE(0x07b8, 0x8178, rtl92cu_hal_cfg)}, /*Funai -Abocom*/
319 {RTL_USB_DEVICE(0x07b8, 0x8178, rtl92cu_hal_cfg)}, /*Abocom -Abocom*/
320 {RTL_USB_DEVICE(0x2001, 0x3307, rtl92cu_hal_cfg)}, /*D-Link-Cameo*/
321 {RTL_USB_DEVICE(0x2001, 0x3309, rtl92cu_hal_cfg)}, /*D-Link-Alpha*/
322 {RTL_USB_DEVICE(0x2001, 0x330a, rtl92cu_hal_cfg)}, /*D-Link-Alpha*/
323 {RTL_USB_DEVICE(0x2019, 0xab2b, rtl92cu_hal_cfg)}, /*Planex -Abocom*/
324 {RTL_USB_DEVICE(0x7392, 0x7822, rtl92cu_hal_cfg)}, /*Edimax -Edimax*/
325 {}
326};
327
328MODULE_DEVICE_TABLE(usb, rtl8192c_usb_ids);
329
330static struct usb_driver rtl8192cu_driver = {
331 .name = "rtl8192cu",
332 .probe = rtl_usb_probe,
333 .disconnect = rtl_usb_disconnect,
334 .id_table = rtl8192c_usb_ids,
335
336#ifdef CONFIG_PM
337 /* .suspend = rtl_usb_suspend, */
338 /* .resume = rtl_usb_resume, */
339 /* .reset_resume = rtl8192c_resume, */
340#endif /* CONFIG_PM */
341#ifdef CONFIG_AUTOSUSPEND
342 .supports_autosuspend = 1,
343#endif
344};
345
346static int __init rtl8192cu_init(void)
347{
348 return usb_register(&rtl8192cu_driver);
349}
350
351static void __exit rtl8192cu_exit(void)
352{
353 usb_deregister(&rtl8192cu_driver);
354}
355
356module_init(rtl8192cu_init);
357module_exit(rtl8192cu_exit);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
new file mode 100644
index 000000000000..43b1177924ab
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
@@ -0,0 +1,53 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_SW_H__
31#define __RTL92CU_SW_H__
32
33#define EFUSE_MAX_SECTION 16
34
35void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
36 u8 *powerlevel);
37void rtl92cu_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
38 u8 *ppowerlevel, u8 channel);
39bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
40 u8 configtype);
41bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
42 u8 configtype);
43void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
44void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
45 enum radio_path rfpath,
46 u32 regaddr, u32 bitmask, u32 data);
47bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
48 enum rf_pwrstate rfpwr_state);
49u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
50 enum radio_path rfpath, u32 regaddr, u32 bitmask);
51void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
52
53#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/table.c b/drivers/net/wireless/rtlwifi/rtl8192cu/table.c
new file mode 100644
index 000000000000..d57ef5e88a9e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/table.c
@@ -0,0 +1,1888 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "table.h"
31
32u32 RTL8192CUPHY_REG_2TARRAY[RTL8192CUPHY_REG_2TARRAY_LENGTH] = {
33 0x024, 0x0011800f,
34 0x028, 0x00ffdb83,
35 0x800, 0x80040002,
36 0x804, 0x00000003,
37 0x808, 0x0000fc00,
38 0x80c, 0x0000000a,
39 0x810, 0x10005388,
40 0x814, 0x020c3d10,
41 0x818, 0x02200385,
42 0x81c, 0x00000000,
43 0x820, 0x01000100,
44 0x824, 0x00390004,
45 0x828, 0x01000100,
46 0x82c, 0x00390004,
47 0x830, 0x27272727,
48 0x834, 0x27272727,
49 0x838, 0x27272727,
50 0x83c, 0x27272727,
51 0x840, 0x00010000,
52 0x844, 0x00010000,
53 0x848, 0x27272727,
54 0x84c, 0x27272727,
55 0x850, 0x00000000,
56 0x854, 0x00000000,
57 0x858, 0x569a569a,
58 0x85c, 0x0c1b25a4,
59 0x860, 0x66e60230,
60 0x864, 0x061f0130,
61 0x868, 0x27272727,
62 0x86c, 0x2b2b2b27,
63 0x870, 0x07000700,
64 0x874, 0x22184000,
65 0x878, 0x08080808,
66 0x87c, 0x00000000,
67 0x880, 0xc0083070,
68 0x884, 0x000004d5,
69 0x888, 0x00000000,
70 0x88c, 0xcc0000c0,
71 0x890, 0x00000800,
72 0x894, 0xfffffffe,
73 0x898, 0x40302010,
74 0x89c, 0x00706050,
75 0x900, 0x00000000,
76 0x904, 0x00000023,
77 0x908, 0x00000000,
78 0x90c, 0x81121313,
79 0xa00, 0x00d047c8,
80 0xa04, 0x80ff000c,
81 0xa08, 0x8c838300,
82 0xa0c, 0x2e68120f,
83 0xa10, 0x9500bb78,
84 0xa14, 0x11144028,
85 0xa18, 0x00881117,
86 0xa1c, 0x89140f00,
87 0xa20, 0x1a1b0000,
88 0xa24, 0x090e1317,
89 0xa28, 0x00000204,
90 0xa2c, 0x00d30000,
91 0xa70, 0x101fbf00,
92 0xa74, 0x00000007,
93 0xc00, 0x48071d40,
94 0xc04, 0x03a05633,
95 0xc08, 0x000000e4,
96 0xc0c, 0x6c6c6c6c,
97 0xc10, 0x08800000,
98 0xc14, 0x40000100,
99 0xc18, 0x08800000,
100 0xc1c, 0x40000100,
101 0xc20, 0x00000000,
102 0xc24, 0x00000000,
103 0xc28, 0x00000000,
104 0xc2c, 0x00000000,
105 0xc30, 0x69e9ac44,
106 0xc34, 0x469652cf,
107 0xc38, 0x49795994,
108 0xc3c, 0x0a97971c,
109 0xc40, 0x1f7c403f,
110 0xc44, 0x000100b7,
111 0xc48, 0xec020107,
112 0xc4c, 0x007f037f,
113 0xc50, 0x6954341e,
114 0xc54, 0x43bc0094,
115 0xc58, 0x6954341e,
116 0xc5c, 0x433c0094,
117 0xc60, 0x00000000,
118 0xc64, 0x5116848b,
119 0xc68, 0x47c00bff,
120 0xc6c, 0x00000036,
121 0xc70, 0x2c7f000d,
122 0xc74, 0x0186115b,
123 0xc78, 0x0000001f,
124 0xc7c, 0x00b99612,
125 0xc80, 0x40000100,
126 0xc84, 0x20f60000,
127 0xc88, 0x40000100,
128 0xc8c, 0x20200000,
129 0xc90, 0x00121820,
130 0xc94, 0x00000000,
131 0xc98, 0x00121820,
132 0xc9c, 0x00007f7f,
133 0xca0, 0x00000000,
134 0xca4, 0x00000080,
135 0xca8, 0x00000000,
136 0xcac, 0x00000000,
137 0xcb0, 0x00000000,
138 0xcb4, 0x00000000,
139 0xcb8, 0x00000000,
140 0xcbc, 0x28000000,
141 0xcc0, 0x00000000,
142 0xcc4, 0x00000000,
143 0xcc8, 0x00000000,
144 0xccc, 0x00000000,
145 0xcd0, 0x00000000,
146 0xcd4, 0x00000000,
147 0xcd8, 0x64b22427,
148 0xcdc, 0x00766932,
149 0xce0, 0x00222222,
150 0xce4, 0x00000000,
151 0xce8, 0x37644302,
152 0xcec, 0x2f97d40c,
153 0xd00, 0x00080740,
154 0xd04, 0x00020403,
155 0xd08, 0x0000907f,
156 0xd0c, 0x20010201,
157 0xd10, 0xa0633333,
158 0xd14, 0x3333bc43,
159 0xd18, 0x7a8f5b6b,
160 0xd2c, 0xcc979975,
161 0xd30, 0x00000000,
162 0xd34, 0x80608000,
163 0xd38, 0x00000000,
164 0xd3c, 0x00027293,
165 0xd40, 0x00000000,
166 0xd44, 0x00000000,
167 0xd48, 0x00000000,
168 0xd4c, 0x00000000,
169 0xd50, 0x6437140a,
170 0xd54, 0x00000000,
171 0xd58, 0x00000000,
172 0xd5c, 0x30032064,
173 0xd60, 0x4653de68,
174 0xd64, 0x04518a3c,
175 0xd68, 0x00002101,
176 0xd6c, 0x2a201c16,
177 0xd70, 0x1812362e,
178 0xd74, 0x322c2220,
179 0xd78, 0x000e3c24,
180 0xe00, 0x2a2a2a2a,
181 0xe04, 0x2a2a2a2a,
182 0xe08, 0x03902a2a,
183 0xe10, 0x2a2a2a2a,
184 0xe14, 0x2a2a2a2a,
185 0xe18, 0x2a2a2a2a,
186 0xe1c, 0x2a2a2a2a,
187 0xe28, 0x00000000,
188 0xe30, 0x1000dc1f,
189 0xe34, 0x10008c1f,
190 0xe38, 0x02140102,
191 0xe3c, 0x681604c2,
192 0xe40, 0x01007c00,
193 0xe44, 0x01004800,
194 0xe48, 0xfb000000,
195 0xe4c, 0x000028d1,
196 0xe50, 0x1000dc1f,
197 0xe54, 0x10008c1f,
198 0xe58, 0x02140102,
199 0xe5c, 0x28160d05,
200 0xe60, 0x00000010,
201 0xe68, 0x001b25a4,
202 0xe6c, 0x63db25a4,
203 0xe70, 0x63db25a4,
204 0xe74, 0x0c1b25a4,
205 0xe78, 0x0c1b25a4,
206 0xe7c, 0x0c1b25a4,
207 0xe80, 0x0c1b25a4,
208 0xe84, 0x63db25a4,
209 0xe88, 0x0c1b25a4,
210 0xe8c, 0x63db25a4,
211 0xed0, 0x63db25a4,
212 0xed4, 0x63db25a4,
213 0xed8, 0x63db25a4,
214 0xedc, 0x001b25a4,
215 0xee0, 0x001b25a4,
216 0xeec, 0x6fdb25a4,
217 0xf14, 0x00000003,
218 0xf4c, 0x00000000,
219 0xf00, 0x00000300,
220};
221
222u32 RTL8192CUPHY_REG_1TARRAY[RTL8192CUPHY_REG_1TARRAY_LENGTH] = {
223 0x024, 0x0011800f,
224 0x028, 0x00ffdb83,
225 0x800, 0x80040000,
226 0x804, 0x00000001,
227 0x808, 0x0000fc00,
228 0x80c, 0x0000000a,
229 0x810, 0x10005388,
230 0x814, 0x020c3d10,
231 0x818, 0x02200385,
232 0x81c, 0x00000000,
233 0x820, 0x01000100,
234 0x824, 0x00390004,
235 0x828, 0x00000000,
236 0x82c, 0x00000000,
237 0x830, 0x00000000,
238 0x834, 0x00000000,
239 0x838, 0x00000000,
240 0x83c, 0x00000000,
241 0x840, 0x00010000,
242 0x844, 0x00000000,
243 0x848, 0x00000000,
244 0x84c, 0x00000000,
245 0x850, 0x00000000,
246 0x854, 0x00000000,
247 0x858, 0x569a569a,
248 0x85c, 0x001b25a4,
249 0x860, 0x66e60230,
250 0x864, 0x061f0130,
251 0x868, 0x00000000,
252 0x86c, 0x32323200,
253 0x870, 0x07000700,
254 0x874, 0x22004000,
255 0x878, 0x00000808,
256 0x87c, 0x00000000,
257 0x880, 0xc0083070,
258 0x884, 0x000004d5,
259 0x888, 0x00000000,
260 0x88c, 0xccc000c0,
261 0x890, 0x00000800,
262 0x894, 0xfffffffe,
263 0x898, 0x40302010,
264 0x89c, 0x00706050,
265 0x900, 0x00000000,
266 0x904, 0x00000023,
267 0x908, 0x00000000,
268 0x90c, 0x81121111,
269 0xa00, 0x00d047c8,
270 0xa04, 0x80ff000c,
271 0xa08, 0x8c838300,
272 0xa0c, 0x2e68120f,
273 0xa10, 0x9500bb78,
274 0xa14, 0x11144028,
275 0xa18, 0x00881117,
276 0xa1c, 0x89140f00,
277 0xa20, 0x1a1b0000,
278 0xa24, 0x090e1317,
279 0xa28, 0x00000204,
280 0xa2c, 0x00d30000,
281 0xa70, 0x101fbf00,
282 0xa74, 0x00000007,
283 0xc00, 0x48071d40,
284 0xc04, 0x03a05611,
285 0xc08, 0x000000e4,
286 0xc0c, 0x6c6c6c6c,
287 0xc10, 0x08800000,
288 0xc14, 0x40000100,
289 0xc18, 0x08800000,
290 0xc1c, 0x40000100,
291 0xc20, 0x00000000,
292 0xc24, 0x00000000,
293 0xc28, 0x00000000,
294 0xc2c, 0x00000000,
295 0xc30, 0x69e9ac44,
296 0xc34, 0x469652cf,
297 0xc38, 0x49795994,
298 0xc3c, 0x0a97971c,
299 0xc40, 0x1f7c403f,
300 0xc44, 0x000100b7,
301 0xc48, 0xec020107,
302 0xc4c, 0x007f037f,
303 0xc50, 0x6954341e,
304 0xc54, 0x43bc0094,
305 0xc58, 0x6954341e,
306 0xc5c, 0x433c0094,
307 0xc60, 0x00000000,
308 0xc64, 0x5116848b,
309 0xc68, 0x47c00bff,
310 0xc6c, 0x00000036,
311 0xc70, 0x2c7f000d,
312 0xc74, 0x018610db,
313 0xc78, 0x0000001f,
314 0xc7c, 0x00b91612,
315 0xc80, 0x40000100,
316 0xc84, 0x20f60000,
317 0xc88, 0x40000100,
318 0xc8c, 0x20200000,
319 0xc90, 0x00121820,
320 0xc94, 0x00000000,
321 0xc98, 0x00121820,
322 0xc9c, 0x00007f7f,
323 0xca0, 0x00000000,
324 0xca4, 0x00000080,
325 0xca8, 0x00000000,
326 0xcac, 0x00000000,
327 0xcb0, 0x00000000,
328 0xcb4, 0x00000000,
329 0xcb8, 0x00000000,
330 0xcbc, 0x28000000,
331 0xcc0, 0x00000000,
332 0xcc4, 0x00000000,
333 0xcc8, 0x00000000,
334 0xccc, 0x00000000,
335 0xcd0, 0x00000000,
336 0xcd4, 0x00000000,
337 0xcd8, 0x64b22427,
338 0xcdc, 0x00766932,
339 0xce0, 0x00222222,
340 0xce4, 0x00000000,
341 0xce8, 0x37644302,
342 0xcec, 0x2f97d40c,
343 0xd00, 0x00080740,
344 0xd04, 0x00020401,
345 0xd08, 0x0000907f,
346 0xd0c, 0x20010201,
347 0xd10, 0xa0633333,
348 0xd14, 0x3333bc43,
349 0xd18, 0x7a8f5b6b,
350 0xd2c, 0xcc979975,
351 0xd30, 0x00000000,
352 0xd34, 0x80608000,
353 0xd38, 0x00000000,
354 0xd3c, 0x00027293,
355 0xd40, 0x00000000,
356 0xd44, 0x00000000,
357 0xd48, 0x00000000,
358 0xd4c, 0x00000000,
359 0xd50, 0x6437140a,
360 0xd54, 0x00000000,
361 0xd58, 0x00000000,
362 0xd5c, 0x30032064,
363 0xd60, 0x4653de68,
364 0xd64, 0x04518a3c,
365 0xd68, 0x00002101,
366 0xd6c, 0x2a201c16,
367 0xd70, 0x1812362e,
368 0xd74, 0x322c2220,
369 0xd78, 0x000e3c24,
370 0xe00, 0x2a2a2a2a,
371 0xe04, 0x2a2a2a2a,
372 0xe08, 0x03902a2a,
373 0xe10, 0x2a2a2a2a,
374 0xe14, 0x2a2a2a2a,
375 0xe18, 0x2a2a2a2a,
376 0xe1c, 0x2a2a2a2a,
377 0xe28, 0x00000000,
378 0xe30, 0x1000dc1f,
379 0xe34, 0x10008c1f,
380 0xe38, 0x02140102,
381 0xe3c, 0x681604c2,
382 0xe40, 0x01007c00,
383 0xe44, 0x01004800,
384 0xe48, 0xfb000000,
385 0xe4c, 0x000028d1,
386 0xe50, 0x1000dc1f,
387 0xe54, 0x10008c1f,
388 0xe58, 0x02140102,
389 0xe5c, 0x28160d05,
390 0xe60, 0x00000008,
391 0xe68, 0x001b25a4,
392 0xe6c, 0x631b25a0,
393 0xe70, 0x631b25a0,
394 0xe74, 0x081b25a0,
395 0xe78, 0x081b25a0,
396 0xe7c, 0x081b25a0,
397 0xe80, 0x081b25a0,
398 0xe84, 0x631b25a0,
399 0xe88, 0x081b25a0,
400 0xe8c, 0x631b25a0,
401 0xed0, 0x631b25a0,
402 0xed4, 0x631b25a0,
403 0xed8, 0x631b25a0,
404 0xedc, 0x001b25a0,
405 0xee0, 0x001b25a0,
406 0xeec, 0x6b1b25a0,
407 0xf14, 0x00000003,
408 0xf4c, 0x00000000,
409 0xf00, 0x00000300,
410};
411
412u32 RTL8192CUPHY_REG_ARRAY_PG[RTL8192CUPHY_REG_ARRAY_PGLENGTH] = {
413 0xe00, 0xffffffff, 0x07090c0c,
414 0xe04, 0xffffffff, 0x01020405,
415 0xe08, 0x0000ff00, 0x00000000,
416 0x86c, 0xffffff00, 0x00000000,
417 0xe10, 0xffffffff, 0x0b0c0c0e,
418 0xe14, 0xffffffff, 0x01030506,
419 0xe18, 0xffffffff, 0x0b0c0d0e,
420 0xe1c, 0xffffffff, 0x01030509,
421 0x830, 0xffffffff, 0x07090c0c,
422 0x834, 0xffffffff, 0x01020405,
423 0x838, 0xffffff00, 0x00000000,
424 0x86c, 0x000000ff, 0x00000000,
425 0x83c, 0xffffffff, 0x0b0c0d0e,
426 0x848, 0xffffffff, 0x01030509,
427 0x84c, 0xffffffff, 0x0b0c0d0e,
428 0x868, 0xffffffff, 0x01030509,
429 0xe00, 0xffffffff, 0x00000000,
430 0xe04, 0xffffffff, 0x00000000,
431 0xe08, 0x0000ff00, 0x00000000,
432 0x86c, 0xffffff00, 0x00000000,
433 0xe10, 0xffffffff, 0x00000000,
434 0xe14, 0xffffffff, 0x00000000,
435 0xe18, 0xffffffff, 0x00000000,
436 0xe1c, 0xffffffff, 0x00000000,
437 0x830, 0xffffffff, 0x00000000,
438 0x834, 0xffffffff, 0x00000000,
439 0x838, 0xffffff00, 0x00000000,
440 0x86c, 0x000000ff, 0x00000000,
441 0x83c, 0xffffffff, 0x00000000,
442 0x848, 0xffffffff, 0x00000000,
443 0x84c, 0xffffffff, 0x00000000,
444 0x868, 0xffffffff, 0x00000000,
445 0xe00, 0xffffffff, 0x04040404,
446 0xe04, 0xffffffff, 0x00020204,
447 0xe08, 0x0000ff00, 0x00000000,
448 0x86c, 0xffffff00, 0x00000000,
449 0xe10, 0xffffffff, 0x06060606,
450 0xe14, 0xffffffff, 0x00020406,
451 0xe18, 0xffffffff, 0x00000000,
452 0xe1c, 0xffffffff, 0x00000000,
453 0x830, 0xffffffff, 0x04040404,
454 0x834, 0xffffffff, 0x00020204,
455 0x838, 0xffffff00, 0x00000000,
456 0x86c, 0x000000ff, 0x00000000,
457 0x83c, 0xffffffff, 0x06060606,
458 0x848, 0xffffffff, 0x00020406,
459 0x84c, 0xffffffff, 0x00000000,
460 0x868, 0xffffffff, 0x00000000,
461 0xe00, 0xffffffff, 0x00000000,
462 0xe04, 0xffffffff, 0x00000000,
463 0xe08, 0x0000ff00, 0x00000000,
464 0x86c, 0xffffff00, 0x00000000,
465 0xe10, 0xffffffff, 0x00000000,
466 0xe14, 0xffffffff, 0x00000000,
467 0xe18, 0xffffffff, 0x00000000,
468 0xe1c, 0xffffffff, 0x00000000,
469 0x830, 0xffffffff, 0x00000000,
470 0x834, 0xffffffff, 0x00000000,
471 0x838, 0xffffff00, 0x00000000,
472 0x86c, 0x000000ff, 0x00000000,
473 0x83c, 0xffffffff, 0x00000000,
474 0x848, 0xffffffff, 0x00000000,
475 0x84c, 0xffffffff, 0x00000000,
476 0x868, 0xffffffff, 0x00000000,
477 0xe00, 0xffffffff, 0x00000000,
478 0xe04, 0xffffffff, 0x00000000,
479 0xe08, 0x0000ff00, 0x00000000,
480 0x86c, 0xffffff00, 0x00000000,
481 0xe10, 0xffffffff, 0x00000000,
482 0xe14, 0xffffffff, 0x00000000,
483 0xe18, 0xffffffff, 0x00000000,
484 0xe1c, 0xffffffff, 0x00000000,
485 0x830, 0xffffffff, 0x00000000,
486 0x834, 0xffffffff, 0x00000000,
487 0x838, 0xffffff00, 0x00000000,
488 0x86c, 0x000000ff, 0x00000000,
489 0x83c, 0xffffffff, 0x00000000,
490 0x848, 0xffffffff, 0x00000000,
491 0x84c, 0xffffffff, 0x00000000,
492 0x868, 0xffffffff, 0x00000000,
493 0xe00, 0xffffffff, 0x04040404,
494 0xe04, 0xffffffff, 0x00020204,
495 0xe08, 0x0000ff00, 0x00000000,
496 0x86c, 0xffffff00, 0x00000000,
497 0xe10, 0xffffffff, 0x00000000,
498 0xe14, 0xffffffff, 0x00000000,
499 0xe18, 0xffffffff, 0x00000000,
500 0xe1c, 0xffffffff, 0x00000000,
501 0x830, 0xffffffff, 0x04040404,
502 0x834, 0xffffffff, 0x00020204,
503 0x838, 0xffffff00, 0x00000000,
504 0x86c, 0x000000ff, 0x00000000,
505 0x83c, 0xffffffff, 0x00000000,
506 0x848, 0xffffffff, 0x00000000,
507 0x84c, 0xffffffff, 0x00000000,
508 0x868, 0xffffffff, 0x00000000,
509 0xe00, 0xffffffff, 0x00000000,
510 0xe04, 0xffffffff, 0x00000000,
511 0xe08, 0x0000ff00, 0x00000000,
512 0x86c, 0xffffff00, 0x00000000,
513 0xe10, 0xffffffff, 0x00000000,
514 0xe14, 0xffffffff, 0x00000000,
515 0xe18, 0xffffffff, 0x00000000,
516 0xe1c, 0xffffffff, 0x00000000,
517 0x830, 0xffffffff, 0x00000000,
518 0x834, 0xffffffff, 0x00000000,
519 0x838, 0xffffff00, 0x00000000,
520 0x86c, 0x000000ff, 0x00000000,
521 0x83c, 0xffffffff, 0x00000000,
522 0x848, 0xffffffff, 0x00000000,
523 0x84c, 0xffffffff, 0x00000000,
524 0x868, 0xffffffff, 0x00000000,
525};
526
527u32 RTL8192CURADIOA_2TARRAY[RTL8192CURADIOA_2TARRAYLENGTH] = {
528 0x000, 0x00030159,
529 0x001, 0x00031284,
530 0x002, 0x00098000,
531 0x003, 0x00018c63,
532 0x004, 0x000210e7,
533 0x009, 0x0002044f,
534 0x00a, 0x0001adb1,
535 0x00b, 0x00054867,
536 0x00c, 0x0008992e,
537 0x00d, 0x0000e52c,
538 0x00e, 0x00039ce7,
539 0x00f, 0x00000451,
540 0x019, 0x00000000,
541 0x01a, 0x00010255,
542 0x01b, 0x00060a00,
543 0x01c, 0x000fc378,
544 0x01d, 0x000a1250,
545 0x01e, 0x0004445f,
546 0x01f, 0x00080001,
547 0x020, 0x0000b614,
548 0x021, 0x0006c000,
549 0x022, 0x00000000,
550 0x023, 0x00001558,
551 0x024, 0x00000060,
552 0x025, 0x00000483,
553 0x026, 0x0004f000,
554 0x027, 0x000ec7d9,
555 0x028, 0x000577c0,
556 0x029, 0x00004783,
557 0x02a, 0x00000001,
558 0x02b, 0x00021334,
559 0x02a, 0x00000000,
560 0x02b, 0x00000054,
561 0x02a, 0x00000001,
562 0x02b, 0x00000808,
563 0x02b, 0x00053333,
564 0x02c, 0x0000000c,
565 0x02a, 0x00000002,
566 0x02b, 0x00000808,
567 0x02b, 0x0005b333,
568 0x02c, 0x0000000d,
569 0x02a, 0x00000003,
570 0x02b, 0x00000808,
571 0x02b, 0x00063333,
572 0x02c, 0x0000000d,
573 0x02a, 0x00000004,
574 0x02b, 0x00000808,
575 0x02b, 0x0006b333,
576 0x02c, 0x0000000d,
577 0x02a, 0x00000005,
578 0x02b, 0x00000808,
579 0x02b, 0x00073333,
580 0x02c, 0x0000000d,
581 0x02a, 0x00000006,
582 0x02b, 0x00000709,
583 0x02b, 0x0005b333,
584 0x02c, 0x0000000d,
585 0x02a, 0x00000007,
586 0x02b, 0x00000709,
587 0x02b, 0x00063333,
588 0x02c, 0x0000000d,
589 0x02a, 0x00000008,
590 0x02b, 0x0000060a,
591 0x02b, 0x0004b333,
592 0x02c, 0x0000000d,
593 0x02a, 0x00000009,
594 0x02b, 0x0000060a,
595 0x02b, 0x00053333,
596 0x02c, 0x0000000d,
597 0x02a, 0x0000000a,
598 0x02b, 0x0000060a,
599 0x02b, 0x0005b333,
600 0x02c, 0x0000000d,
601 0x02a, 0x0000000b,
602 0x02b, 0x0000060a,
603 0x02b, 0x00063333,
604 0x02c, 0x0000000d,
605 0x02a, 0x0000000c,
606 0x02b, 0x0000060a,
607 0x02b, 0x0006b333,
608 0x02c, 0x0000000d,
609 0x02a, 0x0000000d,
610 0x02b, 0x0000060a,
611 0x02b, 0x00073333,
612 0x02c, 0x0000000d,
613 0x02a, 0x0000000e,
614 0x02b, 0x0000050b,
615 0x02b, 0x00066666,
616 0x02c, 0x0000001a,
617 0x02a, 0x000e0000,
618 0x010, 0x0004000f,
619 0x011, 0x000e31fc,
620 0x010, 0x0006000f,
621 0x011, 0x000ff9f8,
622 0x010, 0x0002000f,
623 0x011, 0x000203f9,
624 0x010, 0x0003000f,
625 0x011, 0x000ff500,
626 0x010, 0x00000000,
627 0x011, 0x00000000,
628 0x010, 0x0008000f,
629 0x011, 0x0003f100,
630 0x010, 0x0009000f,
631 0x011, 0x00023100,
632 0x012, 0x00032000,
633 0x012, 0x00071000,
634 0x012, 0x000b0000,
635 0x012, 0x000fc000,
636 0x013, 0x000287af,
637 0x013, 0x000244b7,
638 0x013, 0x000204ab,
639 0x013, 0x0001c49f,
640 0x013, 0x00018493,
641 0x013, 0x00014297,
642 0x013, 0x00010295,
643 0x013, 0x0000c298,
644 0x013, 0x0000819c,
645 0x013, 0x000040a8,
646 0x013, 0x0000001c,
647 0x014, 0x0001944c,
648 0x014, 0x00059444,
649 0x014, 0x0009944c,
650 0x014, 0x000d9444,
651 0x015, 0x0000f424,
652 0x015, 0x0004f424,
653 0x015, 0x0008f424,
654 0x015, 0x000cf424,
655 0x016, 0x000e0330,
656 0x016, 0x000a0330,
657 0x016, 0x00060330,
658 0x016, 0x00020330,
659 0x000, 0x00010159,
660 0x018, 0x0000f401,
661 0x0fe, 0x00000000,
662 0x0fe, 0x00000000,
663 0x01f, 0x00080003,
664 0x0fe, 0x00000000,
665 0x0fe, 0x00000000,
666 0x01e, 0x00044457,
667 0x01f, 0x00080000,
668 0x000, 0x00030159,
669};
670
671u32 RTL8192CU_RADIOB_2TARRAY[RTL8192CURADIOB_2TARRAYLENGTH] = {
672 0x000, 0x00030159,
673 0x001, 0x00031284,
674 0x002, 0x00098000,
675 0x003, 0x00018c63,
676 0x004, 0x000210e7,
677 0x009, 0x0002044f,
678 0x00a, 0x0001adb1,
679 0x00b, 0x00054867,
680 0x00c, 0x0008992e,
681 0x00d, 0x0000e52c,
682 0x00e, 0x00039ce7,
683 0x00f, 0x00000451,
684 0x012, 0x00032000,
685 0x012, 0x00071000,
686 0x012, 0x000b0000,
687 0x012, 0x000fc000,
688 0x013, 0x000287af,
689 0x013, 0x000244b7,
690 0x013, 0x000204ab,
691 0x013, 0x0001c49f,
692 0x013, 0x00018493,
693 0x013, 0x00014297,
694 0x013, 0x00010295,
695 0x013, 0x0000c298,
696 0x013, 0x0000819c,
697 0x013, 0x000040a8,
698 0x013, 0x0000001c,
699 0x014, 0x0001944c,
700 0x014, 0x00059444,
701 0x014, 0x0009944c,
702 0x014, 0x000d9444,
703 0x015, 0x0000f424,
704 0x015, 0x0004f424,
705 0x015, 0x0008f424,
706 0x015, 0x000cf424,
707 0x016, 0x000e0330,
708 0x016, 0x000a0330,
709 0x016, 0x00060330,
710 0x016, 0x00020330,
711};
712
713u32 RTL8192CU_RADIOA_1TARRAY[RTL8192CURADIOA_1TARRAYLENGTH] = {
714 0x000, 0x00030159,
715 0x001, 0x00031284,
716 0x002, 0x00098000,
717 0x003, 0x00018c63,
718 0x004, 0x000210e7,
719 0x009, 0x0002044f,
720 0x00a, 0x0001adb1,
721 0x00b, 0x00054867,
722 0x00c, 0x0008992e,
723 0x00d, 0x0000e52c,
724 0x00e, 0x00039ce7,
725 0x00f, 0x00000451,
726 0x019, 0x00000000,
727 0x01a, 0x00010255,
728 0x01b, 0x00060a00,
729 0x01c, 0x000fc378,
730 0x01d, 0x000a1250,
731 0x01e, 0x0004445f,
732 0x01f, 0x00080001,
733 0x020, 0x0000b614,
734 0x021, 0x0006c000,
735 0x022, 0x00000000,
736 0x023, 0x00001558,
737 0x024, 0x00000060,
738 0x025, 0x00000483,
739 0x026, 0x0004f000,
740 0x027, 0x000ec7d9,
741 0x028, 0x000577c0,
742 0x029, 0x00004783,
743 0x02a, 0x00000001,
744 0x02b, 0x00021334,
745 0x02a, 0x00000000,
746 0x02b, 0x00000054,
747 0x02a, 0x00000001,
748 0x02b, 0x00000808,
749 0x02b, 0x00053333,
750 0x02c, 0x0000000c,
751 0x02a, 0x00000002,
752 0x02b, 0x00000808,
753 0x02b, 0x0005b333,
754 0x02c, 0x0000000d,
755 0x02a, 0x00000003,
756 0x02b, 0x00000808,
757 0x02b, 0x00063333,
758 0x02c, 0x0000000d,
759 0x02a, 0x00000004,
760 0x02b, 0x00000808,
761 0x02b, 0x0006b333,
762 0x02c, 0x0000000d,
763 0x02a, 0x00000005,
764 0x02b, 0x00000808,
765 0x02b, 0x00073333,
766 0x02c, 0x0000000d,
767 0x02a, 0x00000006,
768 0x02b, 0x00000709,
769 0x02b, 0x0005b333,
770 0x02c, 0x0000000d,
771 0x02a, 0x00000007,
772 0x02b, 0x00000709,
773 0x02b, 0x00063333,
774 0x02c, 0x0000000d,
775 0x02a, 0x00000008,
776 0x02b, 0x0000060a,
777 0x02b, 0x0004b333,
778 0x02c, 0x0000000d,
779 0x02a, 0x00000009,
780 0x02b, 0x0000060a,
781 0x02b, 0x00053333,
782 0x02c, 0x0000000d,
783 0x02a, 0x0000000a,
784 0x02b, 0x0000060a,
785 0x02b, 0x0005b333,
786 0x02c, 0x0000000d,
787 0x02a, 0x0000000b,
788 0x02b, 0x0000060a,
789 0x02b, 0x00063333,
790 0x02c, 0x0000000d,
791 0x02a, 0x0000000c,
792 0x02b, 0x0000060a,
793 0x02b, 0x0006b333,
794 0x02c, 0x0000000d,
795 0x02a, 0x0000000d,
796 0x02b, 0x0000060a,
797 0x02b, 0x00073333,
798 0x02c, 0x0000000d,
799 0x02a, 0x0000000e,
800 0x02b, 0x0000050b,
801 0x02b, 0x00066666,
802 0x02c, 0x0000001a,
803 0x02a, 0x000e0000,
804 0x010, 0x0004000f,
805 0x011, 0x000e31fc,
806 0x010, 0x0006000f,
807 0x011, 0x000ff9f8,
808 0x010, 0x0002000f,
809 0x011, 0x000203f9,
810 0x010, 0x0003000f,
811 0x011, 0x000ff500,
812 0x010, 0x00000000,
813 0x011, 0x00000000,
814 0x010, 0x0008000f,
815 0x011, 0x0003f100,
816 0x010, 0x0009000f,
817 0x011, 0x00023100,
818 0x012, 0x00032000,
819 0x012, 0x00071000,
820 0x012, 0x000b0000,
821 0x012, 0x000fc000,
822 0x013, 0x000287b3,
823 0x013, 0x000244b7,
824 0x013, 0x000204ab,
825 0x013, 0x0001c49f,
826 0x013, 0x00018493,
827 0x013, 0x0001429b,
828 0x013, 0x00010299,
829 0x013, 0x0000c29c,
830 0x013, 0x000081a0,
831 0x013, 0x000040ac,
832 0x013, 0x00000020,
833 0x014, 0x0001944c,
834 0x014, 0x00059444,
835 0x014, 0x0009944c,
836 0x014, 0x000d9444,
837 0x015, 0x0000f405,
838 0x015, 0x0004f405,
839 0x015, 0x0008f405,
840 0x015, 0x000cf405,
841 0x016, 0x000e0330,
842 0x016, 0x000a0330,
843 0x016, 0x00060330,
844 0x016, 0x00020330,
845 0x000, 0x00010159,
846 0x018, 0x0000f401,
847 0x0fe, 0x00000000,
848 0x0fe, 0x00000000,
849 0x01f, 0x00080003,
850 0x0fe, 0x00000000,
851 0x0fe, 0x00000000,
852 0x01e, 0x00044457,
853 0x01f, 0x00080000,
854 0x000, 0x00030159,
855};
856
857u32 RTL8192CU_RADIOB_1TARRAY[RTL8192CURADIOB_1TARRAYLENGTH] = {
858 0x0,
859};
860
861u32 RTL8192CUMAC_2T_ARRAY[RTL8192CUMAC_2T_ARRAYLENGTH] = {
862 0x420, 0x00000080,
863 0x423, 0x00000000,
864 0x430, 0x00000000,
865 0x431, 0x00000000,
866 0x432, 0x00000000,
867 0x433, 0x00000001,
868 0x434, 0x00000004,
869 0x435, 0x00000005,
870 0x436, 0x00000006,
871 0x437, 0x00000007,
872 0x438, 0x00000000,
873 0x439, 0x00000000,
874 0x43a, 0x00000000,
875 0x43b, 0x00000001,
876 0x43c, 0x00000004,
877 0x43d, 0x00000005,
878 0x43e, 0x00000006,
879 0x43f, 0x00000007,
880 0x440, 0x0000005d,
881 0x441, 0x00000001,
882 0x442, 0x00000000,
883 0x444, 0x00000015,
884 0x445, 0x000000f0,
885 0x446, 0x0000000f,
886 0x447, 0x00000000,
887 0x458, 0x00000041,
888 0x459, 0x000000a8,
889 0x45a, 0x00000072,
890 0x45b, 0x000000b9,
891 0x460, 0x00000066,
892 0x461, 0x00000066,
893 0x462, 0x00000008,
894 0x463, 0x00000003,
895 0x4c8, 0x000000ff,
896 0x4c9, 0x00000008,
897 0x4cc, 0x000000ff,
898 0x4cd, 0x000000ff,
899 0x4ce, 0x00000001,
900 0x500, 0x00000026,
901 0x501, 0x000000a2,
902 0x502, 0x0000002f,
903 0x503, 0x00000000,
904 0x504, 0x00000028,
905 0x505, 0x000000a3,
906 0x506, 0x0000005e,
907 0x507, 0x00000000,
908 0x508, 0x0000002b,
909 0x509, 0x000000a4,
910 0x50a, 0x0000005e,
911 0x50b, 0x00000000,
912 0x50c, 0x0000004f,
913 0x50d, 0x000000a4,
914 0x50e, 0x00000000,
915 0x50f, 0x00000000,
916 0x512, 0x0000001c,
917 0x514, 0x0000000a,
918 0x515, 0x00000010,
919 0x516, 0x0000000a,
920 0x517, 0x00000010,
921 0x51a, 0x00000016,
922 0x524, 0x0000000f,
923 0x525, 0x0000004f,
924 0x546, 0x00000040,
925 0x547, 0x00000000,
926 0x550, 0x00000010,
927 0x551, 0x00000010,
928 0x559, 0x00000002,
929 0x55a, 0x00000002,
930 0x55d, 0x000000ff,
931 0x605, 0x00000030,
932 0x608, 0x0000000e,
933 0x609, 0x0000002a,
934 0x652, 0x00000020,
935 0x63c, 0x0000000a,
936 0x63d, 0x0000000e,
937 0x63e, 0x0000000a,
938 0x63f, 0x0000000e,
939 0x66e, 0x00000005,
940 0x700, 0x00000021,
941 0x701, 0x00000043,
942 0x702, 0x00000065,
943 0x703, 0x00000087,
944 0x708, 0x00000021,
945 0x709, 0x00000043,
946 0x70a, 0x00000065,
947 0x70b, 0x00000087,
948};
949
950u32 RTL8192CUAGCTAB_2TARRAY[RTL8192CUAGCTAB_2TARRAYLENGTH] = {
951 0xc78, 0x7b000001,
952 0xc78, 0x7b010001,
953 0xc78, 0x7b020001,
954 0xc78, 0x7b030001,
955 0xc78, 0x7b040001,
956 0xc78, 0x7b050001,
957 0xc78, 0x7a060001,
958 0xc78, 0x79070001,
959 0xc78, 0x78080001,
960 0xc78, 0x77090001,
961 0xc78, 0x760a0001,
962 0xc78, 0x750b0001,
963 0xc78, 0x740c0001,
964 0xc78, 0x730d0001,
965 0xc78, 0x720e0001,
966 0xc78, 0x710f0001,
967 0xc78, 0x70100001,
968 0xc78, 0x6f110001,
969 0xc78, 0x6e120001,
970 0xc78, 0x6d130001,
971 0xc78, 0x6c140001,
972 0xc78, 0x6b150001,
973 0xc78, 0x6a160001,
974 0xc78, 0x69170001,
975 0xc78, 0x68180001,
976 0xc78, 0x67190001,
977 0xc78, 0x661a0001,
978 0xc78, 0x651b0001,
979 0xc78, 0x641c0001,
980 0xc78, 0x631d0001,
981 0xc78, 0x621e0001,
982 0xc78, 0x611f0001,
983 0xc78, 0x60200001,
984 0xc78, 0x49210001,
985 0xc78, 0x48220001,
986 0xc78, 0x47230001,
987 0xc78, 0x46240001,
988 0xc78, 0x45250001,
989 0xc78, 0x44260001,
990 0xc78, 0x43270001,
991 0xc78, 0x42280001,
992 0xc78, 0x41290001,
993 0xc78, 0x402a0001,
994 0xc78, 0x262b0001,
995 0xc78, 0x252c0001,
996 0xc78, 0x242d0001,
997 0xc78, 0x232e0001,
998 0xc78, 0x222f0001,
999 0xc78, 0x21300001,
1000 0xc78, 0x20310001,
1001 0xc78, 0x06320001,
1002 0xc78, 0x05330001,
1003 0xc78, 0x04340001,
1004 0xc78, 0x03350001,
1005 0xc78, 0x02360001,
1006 0xc78, 0x01370001,
1007 0xc78, 0x00380001,
1008 0xc78, 0x00390001,
1009 0xc78, 0x003a0001,
1010 0xc78, 0x003b0001,
1011 0xc78, 0x003c0001,
1012 0xc78, 0x003d0001,
1013 0xc78, 0x003e0001,
1014 0xc78, 0x003f0001,
1015 0xc78, 0x7b400001,
1016 0xc78, 0x7b410001,
1017 0xc78, 0x7b420001,
1018 0xc78, 0x7b430001,
1019 0xc78, 0x7b440001,
1020 0xc78, 0x7b450001,
1021 0xc78, 0x7a460001,
1022 0xc78, 0x79470001,
1023 0xc78, 0x78480001,
1024 0xc78, 0x77490001,
1025 0xc78, 0x764a0001,
1026 0xc78, 0x754b0001,
1027 0xc78, 0x744c0001,
1028 0xc78, 0x734d0001,
1029 0xc78, 0x724e0001,
1030 0xc78, 0x714f0001,
1031 0xc78, 0x70500001,
1032 0xc78, 0x6f510001,
1033 0xc78, 0x6e520001,
1034 0xc78, 0x6d530001,
1035 0xc78, 0x6c540001,
1036 0xc78, 0x6b550001,
1037 0xc78, 0x6a560001,
1038 0xc78, 0x69570001,
1039 0xc78, 0x68580001,
1040 0xc78, 0x67590001,
1041 0xc78, 0x665a0001,
1042 0xc78, 0x655b0001,
1043 0xc78, 0x645c0001,
1044 0xc78, 0x635d0001,
1045 0xc78, 0x625e0001,
1046 0xc78, 0x615f0001,
1047 0xc78, 0x60600001,
1048 0xc78, 0x49610001,
1049 0xc78, 0x48620001,
1050 0xc78, 0x47630001,
1051 0xc78, 0x46640001,
1052 0xc78, 0x45650001,
1053 0xc78, 0x44660001,
1054 0xc78, 0x43670001,
1055 0xc78, 0x42680001,
1056 0xc78, 0x41690001,
1057 0xc78, 0x406a0001,
1058 0xc78, 0x266b0001,
1059 0xc78, 0x256c0001,
1060 0xc78, 0x246d0001,
1061 0xc78, 0x236e0001,
1062 0xc78, 0x226f0001,
1063 0xc78, 0x21700001,
1064 0xc78, 0x20710001,
1065 0xc78, 0x06720001,
1066 0xc78, 0x05730001,
1067 0xc78, 0x04740001,
1068 0xc78, 0x03750001,
1069 0xc78, 0x02760001,
1070 0xc78, 0x01770001,
1071 0xc78, 0x00780001,
1072 0xc78, 0x00790001,
1073 0xc78, 0x007a0001,
1074 0xc78, 0x007b0001,
1075 0xc78, 0x007c0001,
1076 0xc78, 0x007d0001,
1077 0xc78, 0x007e0001,
1078 0xc78, 0x007f0001,
1079 0xc78, 0x3800001e,
1080 0xc78, 0x3801001e,
1081 0xc78, 0x3802001e,
1082 0xc78, 0x3803001e,
1083 0xc78, 0x3804001e,
1084 0xc78, 0x3805001e,
1085 0xc78, 0x3806001e,
1086 0xc78, 0x3807001e,
1087 0xc78, 0x3808001e,
1088 0xc78, 0x3c09001e,
1089 0xc78, 0x3e0a001e,
1090 0xc78, 0x400b001e,
1091 0xc78, 0x440c001e,
1092 0xc78, 0x480d001e,
1093 0xc78, 0x4c0e001e,
1094 0xc78, 0x500f001e,
1095 0xc78, 0x5210001e,
1096 0xc78, 0x5611001e,
1097 0xc78, 0x5a12001e,
1098 0xc78, 0x5e13001e,
1099 0xc78, 0x6014001e,
1100 0xc78, 0x6015001e,
1101 0xc78, 0x6016001e,
1102 0xc78, 0x6217001e,
1103 0xc78, 0x6218001e,
1104 0xc78, 0x6219001e,
1105 0xc78, 0x621a001e,
1106 0xc78, 0x621b001e,
1107 0xc78, 0x621c001e,
1108 0xc78, 0x621d001e,
1109 0xc78, 0x621e001e,
1110 0xc78, 0x621f001e,
1111};
1112
1113u32 RTL8192CUAGCTAB_1TARRAY[RTL8192CUAGCTAB_1TARRAYLENGTH] = {
1114 0xc78, 0x7b000001,
1115 0xc78, 0x7b010001,
1116 0xc78, 0x7b020001,
1117 0xc78, 0x7b030001,
1118 0xc78, 0x7b040001,
1119 0xc78, 0x7b050001,
1120 0xc78, 0x7a060001,
1121 0xc78, 0x79070001,
1122 0xc78, 0x78080001,
1123 0xc78, 0x77090001,
1124 0xc78, 0x760a0001,
1125 0xc78, 0x750b0001,
1126 0xc78, 0x740c0001,
1127 0xc78, 0x730d0001,
1128 0xc78, 0x720e0001,
1129 0xc78, 0x710f0001,
1130 0xc78, 0x70100001,
1131 0xc78, 0x6f110001,
1132 0xc78, 0x6e120001,
1133 0xc78, 0x6d130001,
1134 0xc78, 0x6c140001,
1135 0xc78, 0x6b150001,
1136 0xc78, 0x6a160001,
1137 0xc78, 0x69170001,
1138 0xc78, 0x68180001,
1139 0xc78, 0x67190001,
1140 0xc78, 0x661a0001,
1141 0xc78, 0x651b0001,
1142 0xc78, 0x641c0001,
1143 0xc78, 0x631d0001,
1144 0xc78, 0x621e0001,
1145 0xc78, 0x611f0001,
1146 0xc78, 0x60200001,
1147 0xc78, 0x49210001,
1148 0xc78, 0x48220001,
1149 0xc78, 0x47230001,
1150 0xc78, 0x46240001,
1151 0xc78, 0x45250001,
1152 0xc78, 0x44260001,
1153 0xc78, 0x43270001,
1154 0xc78, 0x42280001,
1155 0xc78, 0x41290001,
1156 0xc78, 0x402a0001,
1157 0xc78, 0x262b0001,
1158 0xc78, 0x252c0001,
1159 0xc78, 0x242d0001,
1160 0xc78, 0x232e0001,
1161 0xc78, 0x222f0001,
1162 0xc78, 0x21300001,
1163 0xc78, 0x20310001,
1164 0xc78, 0x06320001,
1165 0xc78, 0x05330001,
1166 0xc78, 0x04340001,
1167 0xc78, 0x03350001,
1168 0xc78, 0x02360001,
1169 0xc78, 0x01370001,
1170 0xc78, 0x00380001,
1171 0xc78, 0x00390001,
1172 0xc78, 0x003a0001,
1173 0xc78, 0x003b0001,
1174 0xc78, 0x003c0001,
1175 0xc78, 0x003d0001,
1176 0xc78, 0x003e0001,
1177 0xc78, 0x003f0001,
1178 0xc78, 0x7b400001,
1179 0xc78, 0x7b410001,
1180 0xc78, 0x7b420001,
1181 0xc78, 0x7b430001,
1182 0xc78, 0x7b440001,
1183 0xc78, 0x7b450001,
1184 0xc78, 0x7a460001,
1185 0xc78, 0x79470001,
1186 0xc78, 0x78480001,
1187 0xc78, 0x77490001,
1188 0xc78, 0x764a0001,
1189 0xc78, 0x754b0001,
1190 0xc78, 0x744c0001,
1191 0xc78, 0x734d0001,
1192 0xc78, 0x724e0001,
1193 0xc78, 0x714f0001,
1194 0xc78, 0x70500001,
1195 0xc78, 0x6f510001,
1196 0xc78, 0x6e520001,
1197 0xc78, 0x6d530001,
1198 0xc78, 0x6c540001,
1199 0xc78, 0x6b550001,
1200 0xc78, 0x6a560001,
1201 0xc78, 0x69570001,
1202 0xc78, 0x68580001,
1203 0xc78, 0x67590001,
1204 0xc78, 0x665a0001,
1205 0xc78, 0x655b0001,
1206 0xc78, 0x645c0001,
1207 0xc78, 0x635d0001,
1208 0xc78, 0x625e0001,
1209 0xc78, 0x615f0001,
1210 0xc78, 0x60600001,
1211 0xc78, 0x49610001,
1212 0xc78, 0x48620001,
1213 0xc78, 0x47630001,
1214 0xc78, 0x46640001,
1215 0xc78, 0x45650001,
1216 0xc78, 0x44660001,
1217 0xc78, 0x43670001,
1218 0xc78, 0x42680001,
1219 0xc78, 0x41690001,
1220 0xc78, 0x406a0001,
1221 0xc78, 0x266b0001,
1222 0xc78, 0x256c0001,
1223 0xc78, 0x246d0001,
1224 0xc78, 0x236e0001,
1225 0xc78, 0x226f0001,
1226 0xc78, 0x21700001,
1227 0xc78, 0x20710001,
1228 0xc78, 0x06720001,
1229 0xc78, 0x05730001,
1230 0xc78, 0x04740001,
1231 0xc78, 0x03750001,
1232 0xc78, 0x02760001,
1233 0xc78, 0x01770001,
1234 0xc78, 0x00780001,
1235 0xc78, 0x00790001,
1236 0xc78, 0x007a0001,
1237 0xc78, 0x007b0001,
1238 0xc78, 0x007c0001,
1239 0xc78, 0x007d0001,
1240 0xc78, 0x007e0001,
1241 0xc78, 0x007f0001,
1242 0xc78, 0x3800001e,
1243 0xc78, 0x3801001e,
1244 0xc78, 0x3802001e,
1245 0xc78, 0x3803001e,
1246 0xc78, 0x3804001e,
1247 0xc78, 0x3805001e,
1248 0xc78, 0x3806001e,
1249 0xc78, 0x3807001e,
1250 0xc78, 0x3808001e,
1251 0xc78, 0x3c09001e,
1252 0xc78, 0x3e0a001e,
1253 0xc78, 0x400b001e,
1254 0xc78, 0x440c001e,
1255 0xc78, 0x480d001e,
1256 0xc78, 0x4c0e001e,
1257 0xc78, 0x500f001e,
1258 0xc78, 0x5210001e,
1259 0xc78, 0x5611001e,
1260 0xc78, 0x5a12001e,
1261 0xc78, 0x5e13001e,
1262 0xc78, 0x6014001e,
1263 0xc78, 0x6015001e,
1264 0xc78, 0x6016001e,
1265 0xc78, 0x6217001e,
1266 0xc78, 0x6218001e,
1267 0xc78, 0x6219001e,
1268 0xc78, 0x621a001e,
1269 0xc78, 0x621b001e,
1270 0xc78, 0x621c001e,
1271 0xc78, 0x621d001e,
1272 0xc78, 0x621e001e,
1273 0xc78, 0x621f001e,
1274};
1275
1276u32 RTL8192CUPHY_REG_1T_HPArray[RTL8192CUPHY_REG_1T_HPArrayLength] = {
1277 0x024, 0x0011800f,
1278 0x028, 0x00ffdb83,
1279 0x040, 0x000c0004,
1280 0x800, 0x80040000,
1281 0x804, 0x00000001,
1282 0x808, 0x0000fc00,
1283 0x80c, 0x0000000a,
1284 0x810, 0x10005388,
1285 0x814, 0x020c3d10,
1286 0x818, 0x02200385,
1287 0x81c, 0x00000000,
1288 0x820, 0x01000100,
1289 0x824, 0x00390204,
1290 0x828, 0x00000000,
1291 0x82c, 0x00000000,
1292 0x830, 0x00000000,
1293 0x834, 0x00000000,
1294 0x838, 0x00000000,
1295 0x83c, 0x00000000,
1296 0x840, 0x00010000,
1297 0x844, 0x00000000,
1298 0x848, 0x00000000,
1299 0x84c, 0x00000000,
1300 0x850, 0x00000000,
1301 0x854, 0x00000000,
1302 0x858, 0x569a569a,
1303 0x85c, 0x001b25a4,
1304 0x860, 0x66e60230,
1305 0x864, 0x061f0130,
1306 0x868, 0x00000000,
1307 0x86c, 0x20202000,
1308 0x870, 0x03000300,
1309 0x874, 0x22004000,
1310 0x878, 0x00000808,
1311 0x87c, 0x00ffc3f1,
1312 0x880, 0xc0083070,
1313 0x884, 0x000004d5,
1314 0x888, 0x00000000,
1315 0x88c, 0xccc000c0,
1316 0x890, 0x00000800,
1317 0x894, 0xfffffffe,
1318 0x898, 0x40302010,
1319 0x89c, 0x00706050,
1320 0x900, 0x00000000,
1321 0x904, 0x00000023,
1322 0x908, 0x00000000,
1323 0x90c, 0x81121111,
1324 0xa00, 0x00d047c8,
1325 0xa04, 0x80ff000c,
1326 0xa08, 0x8c838300,
1327 0xa0c, 0x2e68120f,
1328 0xa10, 0x9500bb78,
1329 0xa14, 0x11144028,
1330 0xa18, 0x00881117,
1331 0xa1c, 0x89140f00,
1332 0xa20, 0x15160000,
1333 0xa24, 0x070b0f12,
1334 0xa28, 0x00000104,
1335 0xa2c, 0x00d30000,
1336 0xa70, 0x101fbf00,
1337 0xa74, 0x00000007,
1338 0xc00, 0x48071d40,
1339 0xc04, 0x03a05611,
1340 0xc08, 0x000000e4,
1341 0xc0c, 0x6c6c6c6c,
1342 0xc10, 0x08800000,
1343 0xc14, 0x40000100,
1344 0xc18, 0x08800000,
1345 0xc1c, 0x40000100,
1346 0xc20, 0x00000000,
1347 0xc24, 0x00000000,
1348 0xc28, 0x00000000,
1349 0xc2c, 0x00000000,
1350 0xc30, 0x69e9ac44,
1351 0xc34, 0x469652cf,
1352 0xc38, 0x49795994,
1353 0xc3c, 0x0a97971c,
1354 0xc40, 0x1f7c403f,
1355 0xc44, 0x000100b7,
1356 0xc48, 0xec020107,
1357 0xc4c, 0x007f037f,
1358 0xc50, 0x6954342e,
1359 0xc54, 0x43bc0094,
1360 0xc58, 0x6954342f,
1361 0xc5c, 0x433c0094,
1362 0xc60, 0x00000000,
1363 0xc64, 0x5116848b,
1364 0xc68, 0x47c00bff,
1365 0xc6c, 0x00000036,
1366 0xc70, 0x2c46000d,
1367 0xc74, 0x018610db,
1368 0xc78, 0x0000001f,
1369 0xc7c, 0x00b91612,
1370 0xc80, 0x24000090,
1371 0xc84, 0x20f60000,
1372 0xc88, 0x24000090,
1373 0xc8c, 0x20200000,
1374 0xc90, 0x00121820,
1375 0xc94, 0x00000000,
1376 0xc98, 0x00121820,
1377 0xc9c, 0x00007f7f,
1378 0xca0, 0x00000000,
1379 0xca4, 0x00000080,
1380 0xca8, 0x00000000,
1381 0xcac, 0x00000000,
1382 0xcb0, 0x00000000,
1383 0xcb4, 0x00000000,
1384 0xcb8, 0x00000000,
1385 0xcbc, 0x28000000,
1386 0xcc0, 0x00000000,
1387 0xcc4, 0x00000000,
1388 0xcc8, 0x00000000,
1389 0xccc, 0x00000000,
1390 0xcd0, 0x00000000,
1391 0xcd4, 0x00000000,
1392 0xcd8, 0x64b22427,
1393 0xcdc, 0x00766932,
1394 0xce0, 0x00222222,
1395 0xce4, 0x00000000,
1396 0xce8, 0x37644302,
1397 0xcec, 0x2f97d40c,
1398 0xd00, 0x00080740,
1399 0xd04, 0x00020401,
1400 0xd08, 0x0000907f,
1401 0xd0c, 0x20010201,
1402 0xd10, 0xa0633333,
1403 0xd14, 0x3333bc43,
1404 0xd18, 0x7a8f5b6b,
1405 0xd2c, 0xcc979975,
1406 0xd30, 0x00000000,
1407 0xd34, 0x80608000,
1408 0xd38, 0x00000000,
1409 0xd3c, 0x00027293,
1410 0xd40, 0x00000000,
1411 0xd44, 0x00000000,
1412 0xd48, 0x00000000,
1413 0xd4c, 0x00000000,
1414 0xd50, 0x6437140a,
1415 0xd54, 0x00000000,
1416 0xd58, 0x00000000,
1417 0xd5c, 0x30032064,
1418 0xd60, 0x4653de68,
1419 0xd64, 0x04518a3c,
1420 0xd68, 0x00002101,
1421 0xd6c, 0x2a201c16,
1422 0xd70, 0x1812362e,
1423 0xd74, 0x322c2220,
1424 0xd78, 0x000e3c24,
1425 0xe00, 0x24242424,
1426 0xe04, 0x24242424,
1427 0xe08, 0x03902024,
1428 0xe10, 0x24242424,
1429 0xe14, 0x24242424,
1430 0xe18, 0x24242424,
1431 0xe1c, 0x24242424,
1432 0xe28, 0x00000000,
1433 0xe30, 0x1000dc1f,
1434 0xe34, 0x10008c1f,
1435 0xe38, 0x02140102,
1436 0xe3c, 0x681604c2,
1437 0xe40, 0x01007c00,
1438 0xe44, 0x01004800,
1439 0xe48, 0xfb000000,
1440 0xe4c, 0x000028d1,
1441 0xe50, 0x1000dc1f,
1442 0xe54, 0x10008c1f,
1443 0xe58, 0x02140102,
1444 0xe5c, 0x28160d05,
1445 0xe60, 0x00000008,
1446 0xe68, 0x001b25a4,
1447 0xe6c, 0x631b25a0,
1448 0xe70, 0x631b25a0,
1449 0xe74, 0x081b25a0,
1450 0xe78, 0x081b25a0,
1451 0xe7c, 0x081b25a0,
1452 0xe80, 0x081b25a0,
1453 0xe84, 0x631b25a0,
1454 0xe88, 0x081b25a0,
1455 0xe8c, 0x631b25a0,
1456 0xed0, 0x631b25a0,
1457 0xed4, 0x631b25a0,
1458 0xed8, 0x631b25a0,
1459 0xedc, 0x001b25a0,
1460 0xee0, 0x001b25a0,
1461 0xeec, 0x6b1b25a0,
1462 0xee8, 0x31555448,
1463 0xf14, 0x00000003,
1464 0xf4c, 0x00000000,
1465 0xf00, 0x00000300,
1466};
1467
1468u32 RTL8192CUPHY_REG_Array_PG_HP[RTL8192CUPHY_REG_Array_PG_HPLength] = {
1469 0xe00, 0xffffffff, 0x06080808,
1470 0xe04, 0xffffffff, 0x00040406,
1471 0xe08, 0x0000ff00, 0x00000000,
1472 0x86c, 0xffffff00, 0x00000000,
1473 0xe10, 0xffffffff, 0x04060608,
1474 0xe14, 0xffffffff, 0x00020204,
1475 0xe18, 0xffffffff, 0x04060608,
1476 0xe1c, 0xffffffff, 0x00020204,
1477 0x830, 0xffffffff, 0x06080808,
1478 0x834, 0xffffffff, 0x00040406,
1479 0x838, 0xffffff00, 0x00000000,
1480 0x86c, 0x000000ff, 0x00000000,
1481 0x83c, 0xffffffff, 0x04060608,
1482 0x848, 0xffffffff, 0x00020204,
1483 0x84c, 0xffffffff, 0x04060608,
1484 0x868, 0xffffffff, 0x00020204,
1485 0xe00, 0xffffffff, 0x00000000,
1486 0xe04, 0xffffffff, 0x00000000,
1487 0xe08, 0x0000ff00, 0x00000000,
1488 0x86c, 0xffffff00, 0x00000000,
1489 0xe10, 0xffffffff, 0x00000000,
1490 0xe14, 0xffffffff, 0x00000000,
1491 0xe18, 0xffffffff, 0x00000000,
1492 0xe1c, 0xffffffff, 0x00000000,
1493 0x830, 0xffffffff, 0x00000000,
1494 0x834, 0xffffffff, 0x00000000,
1495 0x838, 0xffffff00, 0x00000000,
1496 0x86c, 0x000000ff, 0x00000000,
1497 0x83c, 0xffffffff, 0x00000000,
1498 0x848, 0xffffffff, 0x00000000,
1499 0x84c, 0xffffffff, 0x00000000,
1500 0x868, 0xffffffff, 0x00000000,
1501 0xe00, 0xffffffff, 0x00000000,
1502 0xe04, 0xffffffff, 0x00000000,
1503 0xe08, 0x0000ff00, 0x00000000,
1504 0x86c, 0xffffff00, 0x00000000,
1505 0xe10, 0xffffffff, 0x00000000,
1506 0xe14, 0xffffffff, 0x00000000,
1507 0xe18, 0xffffffff, 0x00000000,
1508 0xe1c, 0xffffffff, 0x00000000,
1509 0x830, 0xffffffff, 0x00000000,
1510 0x834, 0xffffffff, 0x00000000,
1511 0x838, 0xffffff00, 0x00000000,
1512 0x86c, 0x000000ff, 0x00000000,
1513 0x83c, 0xffffffff, 0x00000000,
1514 0x848, 0xffffffff, 0x00000000,
1515 0x84c, 0xffffffff, 0x00000000,
1516 0x868, 0xffffffff, 0x00000000,
1517 0xe00, 0xffffffff, 0x00000000,
1518 0xe04, 0xffffffff, 0x00000000,
1519 0xe08, 0x0000ff00, 0x00000000,
1520 0x86c, 0xffffff00, 0x00000000,
1521 0xe10, 0xffffffff, 0x00000000,
1522 0xe14, 0xffffffff, 0x00000000,
1523 0xe18, 0xffffffff, 0x00000000,
1524 0xe1c, 0xffffffff, 0x00000000,
1525 0x830, 0xffffffff, 0x00000000,
1526 0x834, 0xffffffff, 0x00000000,
1527 0x838, 0xffffff00, 0x00000000,
1528 0x86c, 0x000000ff, 0x00000000,
1529 0x83c, 0xffffffff, 0x00000000,
1530 0x848, 0xffffffff, 0x00000000,
1531 0x84c, 0xffffffff, 0x00000000,
1532 0x868, 0xffffffff, 0x00000000,
1533 0xe00, 0xffffffff, 0x00000000,
1534 0xe04, 0xffffffff, 0x00000000,
1535 0xe08, 0x0000ff00, 0x00000000,
1536 0x86c, 0xffffff00, 0x00000000,
1537 0xe10, 0xffffffff, 0x00000000,
1538 0xe14, 0xffffffff, 0x00000000,
1539 0xe18, 0xffffffff, 0x00000000,
1540 0xe1c, 0xffffffff, 0x00000000,
1541 0x830, 0xffffffff, 0x00000000,
1542 0x834, 0xffffffff, 0x00000000,
1543 0x838, 0xffffff00, 0x00000000,
1544 0x86c, 0x000000ff, 0x00000000,
1545 0x83c, 0xffffffff, 0x00000000,
1546 0x848, 0xffffffff, 0x00000000,
1547 0x84c, 0xffffffff, 0x00000000,
1548 0x868, 0xffffffff, 0x00000000,
1549 0xe00, 0xffffffff, 0x00000000,
1550 0xe04, 0xffffffff, 0x00000000,
1551 0xe08, 0x0000ff00, 0x00000000,
1552 0x86c, 0xffffff00, 0x00000000,
1553 0xe10, 0xffffffff, 0x00000000,
1554 0xe14, 0xffffffff, 0x00000000,
1555 0xe18, 0xffffffff, 0x00000000,
1556 0xe1c, 0xffffffff, 0x00000000,
1557 0x830, 0xffffffff, 0x00000000,
1558 0x834, 0xffffffff, 0x00000000,
1559 0x838, 0xffffff00, 0x00000000,
1560 0x86c, 0x000000ff, 0x00000000,
1561 0x83c, 0xffffffff, 0x00000000,
1562 0x848, 0xffffffff, 0x00000000,
1563 0x84c, 0xffffffff, 0x00000000,
1564 0x868, 0xffffffff, 0x00000000,
1565 0xe00, 0xffffffff, 0x00000000,
1566 0xe04, 0xffffffff, 0x00000000,
1567 0xe08, 0x0000ff00, 0x00000000,
1568 0x86c, 0xffffff00, 0x00000000,
1569 0xe10, 0xffffffff, 0x00000000,
1570 0xe14, 0xffffffff, 0x00000000,
1571 0xe18, 0xffffffff, 0x00000000,
1572 0xe1c, 0xffffffff, 0x00000000,
1573 0x830, 0xffffffff, 0x00000000,
1574 0x834, 0xffffffff, 0x00000000,
1575 0x838, 0xffffff00, 0x00000000,
1576 0x86c, 0x000000ff, 0x00000000,
1577 0x83c, 0xffffffff, 0x00000000,
1578 0x848, 0xffffffff, 0x00000000,
1579 0x84c, 0xffffffff, 0x00000000,
1580 0x868, 0xffffffff, 0x00000000,
1581};
1582
1583u32 RTL8192CURadioA_1T_HPArray[RTL8192CURadioA_1T_HPArrayLength] = {
1584 0x000, 0x00030159,
1585 0x001, 0x00031284,
1586 0x002, 0x00098000,
1587 0x003, 0x00018c63,
1588 0x004, 0x000210e7,
1589 0x009, 0x0002044f,
1590 0x00a, 0x0001adb0,
1591 0x00b, 0x00054867,
1592 0x00c, 0x0008992e,
1593 0x00d, 0x0000e529,
1594 0x00e, 0x00039ce7,
1595 0x00f, 0x00000451,
1596 0x019, 0x00000000,
1597 0x01a, 0x00000255,
1598 0x01b, 0x00060a00,
1599 0x01c, 0x000fc378,
1600 0x01d, 0x000a1250,
1601 0x01e, 0x0004445f,
1602 0x01f, 0x00080001,
1603 0x020, 0x0000b614,
1604 0x021, 0x0006c000,
1605 0x022, 0x0000083c,
1606 0x023, 0x00001558,
1607 0x024, 0x00000060,
1608 0x025, 0x00000483,
1609 0x026, 0x0004f000,
1610 0x027, 0x000ec7d9,
1611 0x028, 0x000977c0,
1612 0x029, 0x00004783,
1613 0x02a, 0x00000001,
1614 0x02b, 0x00021334,
1615 0x02a, 0x00000000,
1616 0x02b, 0x00000054,
1617 0x02a, 0x00000001,
1618 0x02b, 0x00000808,
1619 0x02b, 0x00053333,
1620 0x02c, 0x0000000c,
1621 0x02a, 0x00000002,
1622 0x02b, 0x00000808,
1623 0x02b, 0x0005b333,
1624 0x02c, 0x0000000d,
1625 0x02a, 0x00000003,
1626 0x02b, 0x00000808,
1627 0x02b, 0x00063333,
1628 0x02c, 0x0000000d,
1629 0x02a, 0x00000004,
1630 0x02b, 0x00000808,
1631 0x02b, 0x0006b333,
1632 0x02c, 0x0000000d,
1633 0x02a, 0x00000005,
1634 0x02b, 0x00000808,
1635 0x02b, 0x00073333,
1636 0x02c, 0x0000000d,
1637 0x02a, 0x00000006,
1638 0x02b, 0x00000709,
1639 0x02b, 0x0005b333,
1640 0x02c, 0x0000000d,
1641 0x02a, 0x00000007,
1642 0x02b, 0x00000709,
1643 0x02b, 0x00063333,
1644 0x02c, 0x0000000d,
1645 0x02a, 0x00000008,
1646 0x02b, 0x0000060a,
1647 0x02b, 0x0004b333,
1648 0x02c, 0x0000000d,
1649 0x02a, 0x00000009,
1650 0x02b, 0x0000060a,
1651 0x02b, 0x00053333,
1652 0x02c, 0x0000000d,
1653 0x02a, 0x0000000a,
1654 0x02b, 0x0000060a,
1655 0x02b, 0x0005b333,
1656 0x02c, 0x0000000d,
1657 0x02a, 0x0000000b,
1658 0x02b, 0x0000060a,
1659 0x02b, 0x00063333,
1660 0x02c, 0x0000000d,
1661 0x02a, 0x0000000c,
1662 0x02b, 0x0000060a,
1663 0x02b, 0x0006b333,
1664 0x02c, 0x0000000d,
1665 0x02a, 0x0000000d,
1666 0x02b, 0x0000060a,
1667 0x02b, 0x00073333,
1668 0x02c, 0x0000000d,
1669 0x02a, 0x0000000e,
1670 0x02b, 0x0000050b,
1671 0x02b, 0x00066666,
1672 0x02c, 0x0000001a,
1673 0x02a, 0x000e0000,
1674 0x010, 0x0004000f,
1675 0x011, 0x000e31fc,
1676 0x010, 0x0006000f,
1677 0x011, 0x000ff9f8,
1678 0x010, 0x0002000f,
1679 0x011, 0x000203f9,
1680 0x010, 0x0003000f,
1681 0x011, 0x000ff500,
1682 0x010, 0x00000000,
1683 0x011, 0x00000000,
1684 0x010, 0x0008000f,
1685 0x011, 0x0003f100,
1686 0x010, 0x0009000f,
1687 0x011, 0x00023100,
1688 0x012, 0x000d8000,
1689 0x012, 0x00090000,
1690 0x012, 0x00051000,
1691 0x012, 0x00012000,
1692 0x013, 0x00028fb4,
1693 0x013, 0x00024fa8,
1694 0x013, 0x000207a4,
1695 0x013, 0x0001c798,
1696 0x013, 0x000183a4,
1697 0x013, 0x00014398,
1698 0x013, 0x000101a4,
1699 0x013, 0x0000c198,
1700 0x013, 0x000080a4,
1701 0x013, 0x00004098,
1702 0x013, 0x00000000,
1703 0x014, 0x0001944c,
1704 0x014, 0x00059444,
1705 0x014, 0x0009944c,
1706 0x014, 0x000d9444,
1707 0x015, 0x0000f405,
1708 0x015, 0x0004f405,
1709 0x015, 0x0008f405,
1710 0x015, 0x000cf405,
1711 0x016, 0x000e0330,
1712 0x016, 0x000a0330,
1713 0x016, 0x00060330,
1714 0x016, 0x00020330,
1715 0x000, 0x00010159,
1716 0x018, 0x0000f401,
1717 0x0fe, 0x00000000,
1718 0x0fe, 0x00000000,
1719 0x01f, 0x00080003,
1720 0x0fe, 0x00000000,
1721 0x0fe, 0x00000000,
1722 0x01e, 0x00044457,
1723 0x01f, 0x00080000,
1724 0x000, 0x00030159,
1725};
1726
1727u32 Rtl8192CUAGCTAB_1T_HPArray[RTL8192CUAGCTAB_1T_HPArrayLength] = {
1728 0xc78, 0x7b000001,
1729 0xc78, 0x7b010001,
1730 0xc78, 0x7b020001,
1731 0xc78, 0x7b030001,
1732 0xc78, 0x7b040001,
1733 0xc78, 0x7b050001,
1734 0xc78, 0x7b060001,
1735 0xc78, 0x7b070001,
1736 0xc78, 0x7b080001,
1737 0xc78, 0x7a090001,
1738 0xc78, 0x790a0001,
1739 0xc78, 0x780b0001,
1740 0xc78, 0x770c0001,
1741 0xc78, 0x760d0001,
1742 0xc78, 0x750e0001,
1743 0xc78, 0x740f0001,
1744 0xc78, 0x73100001,
1745 0xc78, 0x72110001,
1746 0xc78, 0x71120001,
1747 0xc78, 0x70130001,
1748 0xc78, 0x6f140001,
1749 0xc78, 0x6e150001,
1750 0xc78, 0x6d160001,
1751 0xc78, 0x6c170001,
1752 0xc78, 0x6b180001,
1753 0xc78, 0x6a190001,
1754 0xc78, 0x691a0001,
1755 0xc78, 0x681b0001,
1756 0xc78, 0x671c0001,
1757 0xc78, 0x661d0001,
1758 0xc78, 0x651e0001,
1759 0xc78, 0x641f0001,
1760 0xc78, 0x63200001,
1761 0xc78, 0x62210001,
1762 0xc78, 0x61220001,
1763 0xc78, 0x60230001,
1764 0xc78, 0x46240001,
1765 0xc78, 0x45250001,
1766 0xc78, 0x44260001,
1767 0xc78, 0x43270001,
1768 0xc78, 0x42280001,
1769 0xc78, 0x41290001,
1770 0xc78, 0x402a0001,
1771 0xc78, 0x262b0001,
1772 0xc78, 0x252c0001,
1773 0xc78, 0x242d0001,
1774 0xc78, 0x232e0001,
1775 0xc78, 0x222f0001,
1776 0xc78, 0x21300001,
1777 0xc78, 0x20310001,
1778 0xc78, 0x06320001,
1779 0xc78, 0x05330001,
1780 0xc78, 0x04340001,
1781 0xc78, 0x03350001,
1782 0xc78, 0x02360001,
1783 0xc78, 0x01370001,
1784 0xc78, 0x00380001,
1785 0xc78, 0x00390001,
1786 0xc78, 0x003a0001,
1787 0xc78, 0x003b0001,
1788 0xc78, 0x003c0001,
1789 0xc78, 0x003d0001,
1790 0xc78, 0x003e0001,
1791 0xc78, 0x003f0001,
1792 0xc78, 0x7b400001,
1793 0xc78, 0x7b410001,
1794 0xc78, 0x7b420001,
1795 0xc78, 0x7b430001,
1796 0xc78, 0x7b440001,
1797 0xc78, 0x7b450001,
1798 0xc78, 0x7b460001,
1799 0xc78, 0x7b470001,
1800 0xc78, 0x7b480001,
1801 0xc78, 0x7a490001,
1802 0xc78, 0x794a0001,
1803 0xc78, 0x784b0001,
1804 0xc78, 0x774c0001,
1805 0xc78, 0x764d0001,
1806 0xc78, 0x754e0001,
1807 0xc78, 0x744f0001,
1808 0xc78, 0x73500001,
1809 0xc78, 0x72510001,
1810 0xc78, 0x71520001,
1811 0xc78, 0x70530001,
1812 0xc78, 0x6f540001,
1813 0xc78, 0x6e550001,
1814 0xc78, 0x6d560001,
1815 0xc78, 0x6c570001,
1816 0xc78, 0x6b580001,
1817 0xc78, 0x6a590001,
1818 0xc78, 0x695a0001,
1819 0xc78, 0x685b0001,
1820 0xc78, 0x675c0001,
1821 0xc78, 0x665d0001,
1822 0xc78, 0x655e0001,
1823 0xc78, 0x645f0001,
1824 0xc78, 0x63600001,
1825 0xc78, 0x62610001,
1826 0xc78, 0x61620001,
1827 0xc78, 0x60630001,
1828 0xc78, 0x46640001,
1829 0xc78, 0x45650001,
1830 0xc78, 0x44660001,
1831 0xc78, 0x43670001,
1832 0xc78, 0x42680001,
1833 0xc78, 0x41690001,
1834 0xc78, 0x406a0001,
1835 0xc78, 0x266b0001,
1836 0xc78, 0x256c0001,
1837 0xc78, 0x246d0001,
1838 0xc78, 0x236e0001,
1839 0xc78, 0x226f0001,
1840 0xc78, 0x21700001,
1841 0xc78, 0x20710001,
1842 0xc78, 0x06720001,
1843 0xc78, 0x05730001,
1844 0xc78, 0x04740001,
1845 0xc78, 0x03750001,
1846 0xc78, 0x02760001,
1847 0xc78, 0x01770001,
1848 0xc78, 0x00780001,
1849 0xc78, 0x00790001,
1850 0xc78, 0x007a0001,
1851 0xc78, 0x007b0001,
1852 0xc78, 0x007c0001,
1853 0xc78, 0x007d0001,
1854 0xc78, 0x007e0001,
1855 0xc78, 0x007f0001,
1856 0xc78, 0x3800001e,
1857 0xc78, 0x3801001e,
1858 0xc78, 0x3802001e,
1859 0xc78, 0x3803001e,
1860 0xc78, 0x3804001e,
1861 0xc78, 0x3805001e,
1862 0xc78, 0x3806001e,
1863 0xc78, 0x3807001e,
1864 0xc78, 0x3808001e,
1865 0xc78, 0x3c09001e,
1866 0xc78, 0x3e0a001e,
1867 0xc78, 0x400b001e,
1868 0xc78, 0x440c001e,
1869 0xc78, 0x480d001e,
1870 0xc78, 0x4c0e001e,
1871 0xc78, 0x500f001e,
1872 0xc78, 0x5210001e,
1873 0xc78, 0x5611001e,
1874 0xc78, 0x5a12001e,
1875 0xc78, 0x5e13001e,
1876 0xc78, 0x6014001e,
1877 0xc78, 0x6015001e,
1878 0xc78, 0x6016001e,
1879 0xc78, 0x6217001e,
1880 0xc78, 0x6218001e,
1881 0xc78, 0x6219001e,
1882 0xc78, 0x621a001e,
1883 0xc78, 0x621b001e,
1884 0xc78, 0x621c001e,
1885 0xc78, 0x621d001e,
1886 0xc78, 0x621e001e,
1887 0xc78, 0x621f001e,
1888};
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/table.h b/drivers/net/wireless/rtlwifi/rtl8192cu/table.h
new file mode 100644
index 000000000000..c3d5cd826cfa
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/table.h
@@ -0,0 +1,71 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_TABLE__H_
31#define __RTL92CU_TABLE__H_
32
33#include <linux/types.h>
34
35#define RTL8192CUPHY_REG_2TARRAY_LENGTH 374
36extern u32 RTL8192CUPHY_REG_2TARRAY[RTL8192CUPHY_REG_2TARRAY_LENGTH];
37#define RTL8192CUPHY_REG_1TARRAY_LENGTH 374
38extern u32 RTL8192CUPHY_REG_1TARRAY[RTL8192CUPHY_REG_1TARRAY_LENGTH];
39
40#define RTL8192CUPHY_REG_ARRAY_PGLENGTH 336
41extern u32 RTL8192CUPHY_REG_ARRAY_PG[RTL8192CUPHY_REG_ARRAY_PGLENGTH];
42
43#define RTL8192CURADIOA_2TARRAYLENGTH 282
44extern u32 RTL8192CURADIOA_2TARRAY[RTL8192CURADIOA_2TARRAYLENGTH];
45#define RTL8192CURADIOB_2TARRAYLENGTH 78
46extern u32 RTL8192CU_RADIOB_2TARRAY[RTL8192CURADIOB_2TARRAYLENGTH];
47#define RTL8192CURADIOA_1TARRAYLENGTH 282
48extern u32 RTL8192CU_RADIOA_1TARRAY[RTL8192CURADIOA_1TARRAYLENGTH];
49#define RTL8192CURADIOB_1TARRAYLENGTH 1
50extern u32 RTL8192CU_RADIOB_1TARRAY[RTL8192CURADIOB_1TARRAYLENGTH];
51
52#define RTL8192CUMAC_2T_ARRAYLENGTH 172
53extern u32 RTL8192CUMAC_2T_ARRAY[RTL8192CUMAC_2T_ARRAYLENGTH];
54
55#define RTL8192CUAGCTAB_2TARRAYLENGTH 320
56extern u32 RTL8192CUAGCTAB_2TARRAY[RTL8192CUAGCTAB_2TARRAYLENGTH];
57#define RTL8192CUAGCTAB_1TARRAYLENGTH 320
58extern u32 RTL8192CUAGCTAB_1TARRAY[RTL8192CUAGCTAB_1TARRAYLENGTH];
59
60#define RTL8192CUPHY_REG_1T_HPArrayLength 378
61extern u32 RTL8192CUPHY_REG_1T_HPArray[RTL8192CUPHY_REG_1T_HPArrayLength];
62
63#define RTL8192CUPHY_REG_Array_PG_HPLength 336
64extern u32 RTL8192CUPHY_REG_Array_PG_HP[RTL8192CUPHY_REG_Array_PG_HPLength];
65
66#define RTL8192CURadioA_1T_HPArrayLength 282
67extern u32 RTL8192CURadioA_1T_HPArray[RTL8192CURadioA_1T_HPArrayLength];
68#define RTL8192CUAGCTAB_1T_HPArrayLength 320
69extern u32 Rtl8192CUAGCTAB_1T_HPArray[RTL8192CUAGCTAB_1T_HPArrayLength];
70
71#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
new file mode 100644
index 000000000000..3a92ba3c4a1e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
@@ -0,0 +1,687 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../usb.h"
32#include "../ps.h"
33#include "../base.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "rf.h"
38#include "dm.h"
39#include "mac.h"
40#include "trx.h"
41
42static int _ConfigVerTOutEP(struct ieee80211_hw *hw)
43{
44 u8 ep_cfg, txqsele;
45 u8 ep_nums = 0;
46
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
49 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
50
51 rtlusb->out_queue_sel = 0;
52 ep_cfg = rtl_read_byte(rtlpriv, REG_TEST_SIE_OPTIONAL);
53 ep_cfg = (ep_cfg & USB_TEST_EP_MASK) >> USB_TEST_EP_SHIFT;
54 switch (ep_cfg) {
55 case 0: /* 2 bulk OUT, 1 bulk IN */
56 case 3:
57 rtlusb->out_queue_sel = TX_SELE_HQ | TX_SELE_LQ;
58 ep_nums = 2;
59 break;
60 case 1: /* 1 bulk IN/OUT => map all endpoint to Low queue */
61 case 2: /* 1 bulk IN, 1 bulk OUT => map all endpoint to High queue */
62 txqsele = rtl_read_byte(rtlpriv, REG_TEST_USB_TXQS);
63 if (txqsele & 0x0F) /* /map all endpoint to High queue */
64 rtlusb->out_queue_sel = TX_SELE_HQ;
65 else if (txqsele&0xF0) /* map all endpoint to Low queue */
66 rtlusb->out_queue_sel = TX_SELE_LQ;
67 ep_nums = 1;
68 break;
69 default:
70 break;
71 }
72 return (rtlusb->out_ep_nums == ep_nums) ? 0 : -EINVAL;
73}
74
75static int _ConfigVerNOutEP(struct ieee80211_hw *hw)
76{
77 u8 ep_cfg;
78 u8 ep_nums = 0;
79
80 struct rtl_priv *rtlpriv = rtl_priv(hw);
81 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
82 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
83
84 rtlusb->out_queue_sel = 0;
85 /* Normal and High queue */
86 ep_cfg = rtl_read_byte(rtlpriv, (REG_NORMAL_SIE_EP + 1));
87 if (ep_cfg & USB_NORMAL_SIE_EP_MASK) {
88 rtlusb->out_queue_sel |= TX_SELE_HQ;
89 ep_nums++;
90 }
91 if ((ep_cfg >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK) {
92 rtlusb->out_queue_sel |= TX_SELE_NQ;
93 ep_nums++;
94 }
95 /* Low queue */
96 ep_cfg = rtl_read_byte(rtlpriv, (REG_NORMAL_SIE_EP + 2));
97 if (ep_cfg & USB_NORMAL_SIE_EP_MASK) {
98 rtlusb->out_queue_sel |= TX_SELE_LQ;
99 ep_nums++;
100 }
101 return (rtlusb->out_ep_nums == ep_nums) ? 0 : -EINVAL;
102}
103
104static void _TwoOutEpMapping(struct ieee80211_hw *hw, bool bIsChipB,
105 bool bwificfg, struct rtl_ep_map *ep_map)
106{
107 struct rtl_priv *rtlpriv = rtl_priv(hw);
108
109 if (bwificfg) { /* for WMM */
110 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
111 ("USB Chip-B & WMM Setting.....\n"));
112 ep_map->ep_mapping[RTL_TXQ_BE] = 2;
113 ep_map->ep_mapping[RTL_TXQ_BK] = 3;
114 ep_map->ep_mapping[RTL_TXQ_VI] = 3;
115 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
116 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
117 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
118 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
119 } else { /* typical setting */
120 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
121 ("USB typical Setting.....\n"));
122 ep_map->ep_mapping[RTL_TXQ_BE] = 3;
123 ep_map->ep_mapping[RTL_TXQ_BK] = 3;
124 ep_map->ep_mapping[RTL_TXQ_VI] = 2;
125 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
126 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
127 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
128 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
129 }
130}
131
132static void _ThreeOutEpMapping(struct ieee80211_hw *hw, bool bwificfg,
133 struct rtl_ep_map *ep_map)
134{
135 struct rtl_priv *rtlpriv = rtl_priv(hw);
136 if (bwificfg) { /* for WMM */
137 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
138 ("USB 3EP Setting for WMM.....\n"));
139 ep_map->ep_mapping[RTL_TXQ_BE] = 5;
140 ep_map->ep_mapping[RTL_TXQ_BK] = 3;
141 ep_map->ep_mapping[RTL_TXQ_VI] = 3;
142 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
143 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
144 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
145 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
146 } else { /* typical setting */
147 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
148 ("USB 3EP Setting for typical.....\n"));
149 ep_map->ep_mapping[RTL_TXQ_BE] = 5;
150 ep_map->ep_mapping[RTL_TXQ_BK] = 5;
151 ep_map->ep_mapping[RTL_TXQ_VI] = 3;
152 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
153 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
154 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
155 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
156 }
157}
158
159static void _OneOutEpMapping(struct ieee80211_hw *hw, struct rtl_ep_map *ep_map)
160{
161 ep_map->ep_mapping[RTL_TXQ_BE] = 2;
162 ep_map->ep_mapping[RTL_TXQ_BK] = 2;
163 ep_map->ep_mapping[RTL_TXQ_VI] = 2;
164 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
165 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
166 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
167 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
168}
169static int _out_ep_mapping(struct ieee80211_hw *hw)
170{
171 int err = 0;
172 bool bIsChipN, bwificfg = false;
173 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
174 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
175 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
176 struct rtl_ep_map *ep_map = &(rtlusb->ep_map);
177
178 bIsChipN = IS_NORMAL_CHIP(rtlhal->version);
179 switch (rtlusb->out_ep_nums) {
180 case 2:
181 _TwoOutEpMapping(hw, bIsChipN, bwificfg, ep_map);
182 break;
183 case 3:
184 /* Test chip doesn't support three out EPs. */
185 if (!bIsChipN) {
186 err = -EINVAL;
187 goto err_out;
188 }
189 _ThreeOutEpMapping(hw, bIsChipN, ep_map);
190 break;
191 case 1:
192 _OneOutEpMapping(hw, ep_map);
193 break;
194 default:
195 err = -EINVAL;
196 break;
197 }
198err_out:
199 return err;
200
201}
202/* endpoint mapping */
203int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw)
204{
205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
206 int error = 0;
207 if (likely(IS_NORMAL_CHIP(rtlhal->version)))
208 error = _ConfigVerNOutEP(hw);
209 else
210 error = _ConfigVerTOutEP(hw);
211 if (error)
212 goto err_out;
213 error = _out_ep_mapping(hw);
214 if (error)
215 goto err_out;
216err_out:
217 return error;
218}
219
220u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index)
221{
222 u16 hw_queue_index;
223
224 if (unlikely(ieee80211_is_beacon(fc))) {
225 hw_queue_index = RTL_TXQ_BCN;
226 goto out;
227 }
228 if (ieee80211_is_mgmt(fc)) {
229 hw_queue_index = RTL_TXQ_MGT;
230 goto out;
231 }
232 switch (mac80211_queue_index) {
233 case 0:
234 hw_queue_index = RTL_TXQ_VO;
235 break;
236 case 1:
237 hw_queue_index = RTL_TXQ_VI;
238 break;
239 case 2:
240 hw_queue_index = RTL_TXQ_BE;
241 break;
242 case 3:
243 hw_queue_index = RTL_TXQ_BK;
244 break;
245 default:
246 hw_queue_index = RTL_TXQ_BE;
247 RT_ASSERT(false, ("QSLT_BE queue, skb_queue:%d\n",
248 mac80211_queue_index));
249 break;
250 }
251out:
252 return hw_queue_index;
253}
254
255static enum rtl_desc_qsel _rtl8192cu_mq_to_descq(struct ieee80211_hw *hw,
256 __le16 fc, u16 mac80211_queue_index)
257{
258 enum rtl_desc_qsel qsel;
259 struct rtl_priv *rtlpriv = rtl_priv(hw);
260
261 if (unlikely(ieee80211_is_beacon(fc))) {
262 qsel = QSLT_BEACON;
263 goto out;
264 }
265 if (ieee80211_is_mgmt(fc)) {
266 qsel = QSLT_MGNT;
267 goto out;
268 }
269 switch (mac80211_queue_index) {
270 case 0: /* VO */
271 qsel = QSLT_VO;
272 RT_TRACE(rtlpriv, COMP_USB, DBG_DMESG,
273 ("VO queue, set qsel = 0x%x\n", QSLT_VO));
274 break;
275 case 1: /* VI */
276 qsel = QSLT_VI;
277 RT_TRACE(rtlpriv, COMP_USB, DBG_DMESG,
278 ("VI queue, set qsel = 0x%x\n", QSLT_VI));
279 break;
280 case 3: /* BK */
281 qsel = QSLT_BK;
282 RT_TRACE(rtlpriv, COMP_USB, DBG_DMESG,
283 ("BK queue, set qsel = 0x%x\n", QSLT_BK));
284 break;
285 case 2: /* BE */
286 default:
287 qsel = QSLT_BE;
288 RT_TRACE(rtlpriv, COMP_USB, DBG_DMESG,
289 ("BE queue, set qsel = 0x%x\n", QSLT_BE));
290 break;
291 }
292out:
293 return qsel;
294}
295
296/* =============================================================== */
297
298/*----------------------------------------------------------------------
299 *
300 * Rx handler
301 *
302 *---------------------------------------------------------------------- */
303bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
304 struct rtl_stats *stats,
305 struct ieee80211_rx_status *rx_status,
306 u8 *p_desc, struct sk_buff *skb)
307{
308 struct rx_fwinfo_92c *p_drvinfo;
309 struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
310 u32 phystatus = GET_RX_DESC_PHY_STATUS(pdesc);
311
312 stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
313 stats->rx_drvinfo_size = (u8)GET_RX_DESC_DRVINFO_SIZE(pdesc) *
314 RX_DRV_INFO_SIZE_UNIT;
315 stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
316 stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
317 stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
318 stats->hwerror = (stats->crc | stats->icv);
319 stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
320 stats->rate = (u8) GET_RX_DESC_RX_MCS(pdesc);
321 stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
322 stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
323 stats->isampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
324 && (GET_RX_DESC_FAGGR(pdesc) == 1));
325 stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
326 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
327 rx_status->freq = hw->conf.channel->center_freq;
328 rx_status->band = hw->conf.channel->band;
329 if (GET_RX_DESC_CRC32(pdesc))
330 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
331 if (!GET_RX_DESC_SWDEC(pdesc))
332 rx_status->flag |= RX_FLAG_DECRYPTED;
333 if (GET_RX_DESC_BW(pdesc))
334 rx_status->flag |= RX_FLAG_40MHZ;
335 if (GET_RX_DESC_RX_HT(pdesc))
336 rx_status->flag |= RX_FLAG_HT;
337 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
338 if (stats->decrypted)
339 rx_status->flag |= RX_FLAG_DECRYPTED;
340 rx_status->rate_idx = _rtl92c_rate_mapping(hw,
341 (bool)GET_RX_DESC_RX_HT(pdesc),
342 (u8)GET_RX_DESC_RX_MCS(pdesc),
343 (bool)GET_RX_DESC_PAGGR(pdesc));
344 rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
345 if (phystatus == true) {
346 p_drvinfo = (struct rx_fwinfo_92c *)(pdesc + RTL_RX_DESC_SIZE);
347 rtl92c_translate_rx_signal_stuff(hw, skb, stats, pdesc,
348 p_drvinfo);
349 }
350 /*rx_status->qual = stats->signal; */
351 rx_status->signal = stats->rssi + 10;
352 /*rx_status->noise = -stats->noise; */
353 return true;
354}
355
356#define RTL_RX_DRV_INFO_UNIT 8
357
358static void _rtl_rx_process(struct ieee80211_hw *hw, struct sk_buff *skb)
359{
360 struct ieee80211_rx_status *rx_status =
361 (struct ieee80211_rx_status *)IEEE80211_SKB_RXCB(skb);
362 u32 skb_len, pkt_len, drvinfo_len;
363 struct rtl_priv *rtlpriv = rtl_priv(hw);
364 u8 *rxdesc;
365 struct rtl_stats stats = {
366 .signal = 0,
367 .noise = -98,
368 .rate = 0,
369 };
370 struct rx_fwinfo_92c *p_drvinfo;
371 bool bv;
372 __le16 fc;
373 struct ieee80211_hdr *hdr;
374
375 memset(rx_status, 0, sizeof(*rx_status));
376 rxdesc = skb->data;
377 skb_len = skb->len;
378 drvinfo_len = (GET_RX_DESC_DRVINFO_SIZE(rxdesc) * RTL_RX_DRV_INFO_UNIT);
379 pkt_len = GET_RX_DESC_PKT_LEN(rxdesc);
380 /* TODO: Error recovery. drop this skb or something. */
381 WARN_ON(skb_len < (pkt_len + RTL_RX_DESC_SIZE + drvinfo_len));
382 stats.length = (u16) GET_RX_DESC_PKT_LEN(rxdesc);
383 stats.rx_drvinfo_size = (u8)GET_RX_DESC_DRVINFO_SIZE(rxdesc) *
384 RX_DRV_INFO_SIZE_UNIT;
385 stats.rx_bufshift = (u8) (GET_RX_DESC_SHIFT(rxdesc) & 0x03);
386 stats.icv = (u16) GET_RX_DESC_ICV(rxdesc);
387 stats.crc = (u16) GET_RX_DESC_CRC32(rxdesc);
388 stats.hwerror = (stats.crc | stats.icv);
389 stats.decrypted = !GET_RX_DESC_SWDEC(rxdesc);
390 stats.rate = (u8) GET_RX_DESC_RX_MCS(rxdesc);
391 stats.shortpreamble = (u16) GET_RX_DESC_SPLCP(rxdesc);
392 stats.isampdu = (bool) ((GET_RX_DESC_PAGGR(rxdesc) == 1)
393 && (GET_RX_DESC_FAGGR(rxdesc) == 1));
394 stats.timestamp_low = GET_RX_DESC_TSFL(rxdesc);
395 stats.rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(rxdesc);
396 /* TODO: is center_freq changed when doing scan? */
397 /* TODO: Shall we add protection or just skip those two step? */
398 rx_status->freq = hw->conf.channel->center_freq;
399 rx_status->band = hw->conf.channel->band;
400 if (GET_RX_DESC_CRC32(rxdesc))
401 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
402 if (!GET_RX_DESC_SWDEC(rxdesc))
403 rx_status->flag |= RX_FLAG_DECRYPTED;
404 if (GET_RX_DESC_BW(rxdesc))
405 rx_status->flag |= RX_FLAG_40MHZ;
406 if (GET_RX_DESC_RX_HT(rxdesc))
407 rx_status->flag |= RX_FLAG_HT;
408 /* Data rate */
409 rx_status->rate_idx = _rtl92c_rate_mapping(hw,
410 (bool)GET_RX_DESC_RX_HT(rxdesc),
411 (u8)GET_RX_DESC_RX_MCS(rxdesc),
412 (bool)GET_RX_DESC_PAGGR(rxdesc)
413 );
414 /* There is a phy status after this rx descriptor. */
415 if (GET_RX_DESC_PHY_STATUS(rxdesc)) {
416 p_drvinfo = (struct rx_fwinfo_92c *)(rxdesc + RTL_RX_DESC_SIZE);
417 rtl92c_translate_rx_signal_stuff(hw, skb, &stats,
418 (struct rx_desc_92c *)rxdesc, p_drvinfo);
419 }
420 skb_pull(skb, (drvinfo_len + RTL_RX_DESC_SIZE));
421 hdr = (struct ieee80211_hdr *)(skb->data);
422 fc = hdr->frame_control;
423 bv = ieee80211_is_probe_resp(fc);
424 if (bv)
425 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
426 ("Got probe response frame.\n"));
427 if (ieee80211_is_beacon(fc))
428 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
429 ("Got beacon frame.\n"));
430 if (ieee80211_is_data(fc))
431 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Got data frame.\n"));
432 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
433 ("Fram: fc = 0x%X addr1 = 0x%02X:0x%02X:0x%02X:0x%02X:0x%02X:"
434 "0x%02X\n", fc, (u32)hdr->addr1[0], (u32)hdr->addr1[1],
435 (u32)hdr->addr1[2], (u32)hdr->addr1[3], (u32)hdr->addr1[4],
436 (u32)hdr->addr1[5]));
437 memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status));
438 ieee80211_rx_irqsafe(hw, skb);
439}
440
441void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb)
442{
443 _rtl_rx_process(hw, skb);
444}
445
446void rtl8192c_rx_segregate_hdl(
447 struct ieee80211_hw *hw,
448 struct sk_buff *skb,
449 struct sk_buff_head *skb_list)
450{
451}
452
453/*----------------------------------------------------------------------
454 *
455 * Tx handler
456 *
457 *---------------------------------------------------------------------- */
458void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb)
459{
460}
461
462int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb,
463 struct sk_buff *skb)
464{
465 return 0;
466}
467
468struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *hw,
469 struct sk_buff_head *list)
470{
471 return skb_dequeue(list);
472}
473
474/*======================================== trx ===============================*/
475
476static void _rtl_fill_usb_tx_desc(u8 *txdesc)
477{
478 SET_TX_DESC_OWN(txdesc, 1);
479 SET_TX_DESC_LAST_SEG(txdesc, 1);
480 SET_TX_DESC_FIRST_SEG(txdesc, 1);
481}
482/**
483 * For HW recovery information
484 */
485static void _rtl_tx_desc_checksum(u8 *txdesc)
486{
487 u16 *ptr = (u16 *)txdesc;
488 u16 checksum = 0;
489 u32 index;
490
491 /* Clear first */
492 SET_TX_DESC_TX_DESC_CHECKSUM(txdesc, 0);
493 for (index = 0; index < 16; index++)
494 checksum = checksum ^ (*(ptr + index));
495 SET_TX_DESC_TX_DESC_CHECKSUM(txdesc, checksum);
496}
497
498void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
499 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
500 struct ieee80211_tx_info *info, struct sk_buff *skb,
501 u8 queue_index,
502 struct rtl_tcb_desc *tcb_desc)
503{
504 struct rtl_priv *rtlpriv = rtl_priv(hw);
505 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
506 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
507 bool defaultadapter = true;
508 struct ieee80211_sta *sta = info->control.sta = info->control.sta;
509 u8 *qc = ieee80211_get_qos_ctl(hdr);
510 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
511 u16 seq_number;
512 __le16 fc = hdr->frame_control;
513 u8 rate_flag = info->control.rates[0].flags;
514 u16 pktlen = skb->len;
515 enum rtl_desc_qsel fw_qsel = _rtl8192cu_mq_to_descq(hw, fc,
516 skb_get_queue_mapping(skb));
517 u8 *txdesc;
518
519 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
520 rtl_get_tcb_desc(hw, info, sta, skb, tcb_desc);
521 txdesc = (u8 *)skb_push(skb, RTL_TX_HEADER_SIZE);
522 memset(txdesc, 0, RTL_TX_HEADER_SIZE);
523 SET_TX_DESC_PKT_SIZE(txdesc, pktlen);
524 SET_TX_DESC_LINIP(txdesc, 0);
525 SET_TX_DESC_PKT_OFFSET(txdesc, RTL_DUMMY_OFFSET);
526 SET_TX_DESC_OFFSET(txdesc, RTL_TX_HEADER_SIZE);
527 SET_TX_DESC_TX_RATE(txdesc, tcb_desc->hw_rate);
528 if (tcb_desc->use_shortgi || tcb_desc->use_shortpreamble)
529 SET_TX_DESC_DATA_SHORTGI(txdesc, 1);
530 if (mac->tids[tid].agg.agg_state == RTL_AGG_ON &&
531 info->flags & IEEE80211_TX_CTL_AMPDU) {
532 SET_TX_DESC_AGG_ENABLE(txdesc, 1);
533 SET_TX_DESC_MAX_AGG_NUM(txdesc, 0x14);
534 } else {
535 SET_TX_DESC_AGG_BREAK(txdesc, 1);
536 }
537 SET_TX_DESC_SEQ(txdesc, seq_number);
538 SET_TX_DESC_RTS_ENABLE(txdesc, ((tcb_desc->rts_enable &&
539 !tcb_desc->cts_enable) ? 1 : 0));
540 SET_TX_DESC_HW_RTS_ENABLE(txdesc, ((tcb_desc->rts_enable ||
541 tcb_desc->cts_enable) ? 1 : 0));
542 SET_TX_DESC_CTS2SELF(txdesc, ((tcb_desc->cts_enable) ? 1 : 0));
543 SET_TX_DESC_RTS_STBC(txdesc, ((tcb_desc->rts_stbc) ? 1 : 0));
544 SET_TX_DESC_RTS_RATE(txdesc, tcb_desc->rts_rate);
545 SET_TX_DESC_RTS_BW(txdesc, 0);
546 SET_TX_DESC_RTS_SC(txdesc, tcb_desc->rts_sc);
547 SET_TX_DESC_RTS_SHORT(txdesc,
548 ((tcb_desc->rts_rate <= DESC92C_RATE54M) ?
549 (tcb_desc->rts_use_shortpreamble ? 1 : 0)
550 : (tcb_desc->rts_use_shortgi ? 1 : 0)));
551 if (mac->bw_40) {
552 if (tcb_desc->packet_bw) {
553 SET_TX_DESC_DATA_BW(txdesc, 1);
554 SET_TX_DESC_DATA_SC(txdesc, 3);
555 } else {
556 SET_TX_DESC_DATA_BW(txdesc, 0);
557 if (rate_flag & IEEE80211_TX_RC_DUP_DATA)
558 SET_TX_DESC_DATA_SC(txdesc,
559 mac->cur_40_prime_sc);
560 }
561 } else {
562 SET_TX_DESC_DATA_BW(txdesc, 0);
563 SET_TX_DESC_DATA_SC(txdesc, 0);
564 }
565 rcu_read_lock();
566 sta = ieee80211_find_sta(mac->vif, mac->bssid);
567 if (sta) {
568 u8 ampdu_density = sta->ht_cap.ampdu_density;
569 SET_TX_DESC_AMPDU_DENSITY(txdesc, ampdu_density);
570 }
571 rcu_read_unlock();
572 if (info->control.hw_key) {
573 struct ieee80211_key_conf *keyconf = info->control.hw_key;
574 switch (keyconf->cipher) {
575 case WLAN_CIPHER_SUITE_WEP40:
576 case WLAN_CIPHER_SUITE_WEP104:
577 case WLAN_CIPHER_SUITE_TKIP:
578 SET_TX_DESC_SEC_TYPE(txdesc, 0x1);
579 break;
580 case WLAN_CIPHER_SUITE_CCMP:
581 SET_TX_DESC_SEC_TYPE(txdesc, 0x3);
582 break;
583 default:
584 SET_TX_DESC_SEC_TYPE(txdesc, 0x0);
585 break;
586 }
587 }
588 SET_TX_DESC_PKT_ID(txdesc, 0);
589 SET_TX_DESC_QUEUE_SEL(txdesc, fw_qsel);
590 SET_TX_DESC_DATA_RATE_FB_LIMIT(txdesc, 0x1F);
591 SET_TX_DESC_RTS_RATE_FB_LIMIT(txdesc, 0xF);
592 SET_TX_DESC_DISABLE_FB(txdesc, 0);
593 SET_TX_DESC_USE_RATE(txdesc, tcb_desc->use_driver_rate ? 1 : 0);
594 if (ieee80211_is_data_qos(fc)) {
595 if (mac->rdg_en) {
596 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
597 ("Enable RDG function.\n"));
598 SET_TX_DESC_RDG_ENABLE(txdesc, 1);
599 SET_TX_DESC_HTC(txdesc, 1);
600 }
601 }
602 if (rtlpriv->dm.useramask) {
603 SET_TX_DESC_RATE_ID(txdesc, tcb_desc->ratr_index);
604 SET_TX_DESC_MACID(txdesc, tcb_desc->mac_id);
605 } else {
606 SET_TX_DESC_RATE_ID(txdesc, 0xC + tcb_desc->ratr_index);
607 SET_TX_DESC_MACID(txdesc, tcb_desc->ratr_index);
608 }
609 if ((!ieee80211_is_data_qos(fc)) && ppsc->leisure_ps &&
610 ppsc->fwctrl_lps) {
611 SET_TX_DESC_HWSEQ_EN(txdesc, 1);
612 SET_TX_DESC_PKT_ID(txdesc, 8);
613 if (!defaultadapter)
614 SET_TX_DESC_QOS(txdesc, 1);
615 }
616 if (ieee80211_has_morefrags(fc))
617 SET_TX_DESC_MORE_FRAG(txdesc, 1);
618 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
619 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
620 SET_TX_DESC_BMC(txdesc, 1);
621 _rtl_fill_usb_tx_desc(txdesc);
622 _rtl_tx_desc_checksum(txdesc);
623 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, (" %s ==>\n", __func__));
624}
625
626void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 * pDesc,
627 u32 buffer_len, bool bIsPsPoll)
628{
629 /* Clear all status */
630 memset(pDesc, 0, RTL_TX_HEADER_SIZE);
631 SET_TX_DESC_FIRST_SEG(pDesc, 1); /* bFirstSeg; */
632 SET_TX_DESC_LAST_SEG(pDesc, 1); /* bLastSeg; */
633 SET_TX_DESC_OFFSET(pDesc, RTL_TX_HEADER_SIZE); /* Offset = 32 */
634 SET_TX_DESC_PKT_SIZE(pDesc, buffer_len); /* Buffer size + command hdr */
635 SET_TX_DESC_QUEUE_SEL(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
636 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error
637 * vlaue by Hw. */
638 if (bIsPsPoll) {
639 SET_TX_DESC_NAV_USE_HDR(pDesc, 1);
640 } else {
641 SET_TX_DESC_HWSEQ_EN(pDesc, 1); /* Hw set sequence number */
642 SET_TX_DESC_PKT_ID(pDesc, 0x100); /* set bit3 to 1. */
643 }
644 SET_TX_DESC_USE_RATE(pDesc, 1); /* use data rate which is set by Sw */
645 SET_TX_DESC_OWN(pDesc, 1);
646 SET_TX_DESC_TX_RATE(pDesc, DESC92C_RATE1M);
647 _rtl_tx_desc_checksum(pDesc);
648}
649
650void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw,
651 u8 *pdesc, bool firstseg,
652 bool lastseg, struct sk_buff *skb)
653{
654 struct rtl_priv *rtlpriv = rtl_priv(hw);
655 u8 fw_queue = QSLT_BEACON;
656 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
657 __le16 fc = hdr->frame_control;
658
659 memset((void *)pdesc, 0, RTL_TX_HEADER_SIZE);
660 if (firstseg)
661 SET_TX_DESC_OFFSET(pdesc, RTL_TX_HEADER_SIZE);
662 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
663 SET_TX_DESC_SEQ(pdesc, 0);
664 SET_TX_DESC_LINIP(pdesc, 0);
665 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
666 SET_TX_DESC_FIRST_SEG(pdesc, 1);
667 SET_TX_DESC_LAST_SEG(pdesc, 1);
668 SET_TX_DESC_RATE_ID(pdesc, 7);
669 SET_TX_DESC_MACID(pdesc, 0);
670 SET_TX_DESC_OWN(pdesc, 1);
671 SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
672 SET_TX_DESC_FIRST_SEG(pdesc, 1);
673 SET_TX_DESC_LAST_SEG(pdesc, 1);
674 SET_TX_DESC_OFFSET(pdesc, 0x20);
675 SET_TX_DESC_USE_RATE(pdesc, 1);
676 if (!ieee80211_is_data_qos(fc)) {
677 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
678 SET_TX_DESC_PKT_ID(pdesc, 8);
679 }
680 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, "H2C Tx Cmd Content\n",
681 pdesc, RTL_TX_DESC_SIZE);
682}
683
684bool rtl92cu_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
685{
686 return true;
687}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h
new file mode 100644
index 000000000000..53de5f66e242
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h
@@ -0,0 +1,433 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_TRX_H__
31#define __RTL92CU_TRX_H__
32
33#define RTL92C_USB_BULK_IN_NUM 1
34#define RTL92C_NUM_RX_URBS 8
35#define RTL92C_NUM_TX_URBS 32
36
37#define RTL92C_SIZE_MAX_RX_BUFFER 15360 /* 8192 */
38#define RX_DRV_INFO_SIZE_UNIT 8
39
40#define RTL_AGG_ON 1
41
42enum usb_rx_agg_mode {
43 USB_RX_AGG_DISABLE,
44 USB_RX_AGG_DMA,
45 USB_RX_AGG_USB,
46 USB_RX_AGG_DMA_USB
47};
48
49#define TX_SELE_HQ BIT(0) /* High Queue */
50#define TX_SELE_LQ BIT(1) /* Low Queue */
51#define TX_SELE_NQ BIT(2) /* Normal Queue */
52
53#define RTL_USB_TX_AGG_NUM_DESC 5
54
55#define RTL_USB_RX_AGG_PAGE_NUM 4
56#define RTL_USB_RX_AGG_PAGE_TIMEOUT 3
57
58#define RTL_USB_RX_AGG_BLOCK_NUM 5
59#define RTL_USB_RX_AGG_BLOCK_TIMEOUT 3
60
61/*======================== rx status =========================================*/
62
63struct rx_drv_info_92c {
64 /*
65 * Driver info contain PHY status and other variabel size info
66 * PHY Status content as below
67 */
68
69 /* DWORD 0 */
70 u8 gain_trsw[4];
71
72 /* DWORD 1 */
73 u8 pwdb_all;
74 u8 cfosho[4];
75
76 /* DWORD 2 */
77 u8 cfotail[4];
78
79 /* DWORD 3 */
80 s8 rxevm[2];
81 s8 rxsnr[4];
82
83 /* DWORD 4 */
84 u8 pdsnr[2];
85
86 /* DWORD 5 */
87 u8 csi_current[2];
88 u8 csi_target[2];
89
90 /* DWORD 6 */
91 u8 sigevm;
92 u8 max_ex_pwr;
93 u8 ex_intf_flag:1;
94 u8 sgi_en:1;
95 u8 rxsc:2;
96 u8 reserve:4;
97} __packed;
98
99/* Define a macro that takes a le32 word, converts it to host ordering,
100 * right shifts by a specified count, creates a mask of the specified
101 * bit count, and extracts that number of bits.
102 */
103
104#define SHIFT_AND_MASK_LE(__pdesc, __shift, __bits) \
105 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
106 BIT_LEN_MASK_32(__bits))
107
108/* Define a macro that clears a bit field in an le32 word and
109 * sets the specified value into that bit field. The resulting
110 * value remains in le32 ordering; however, it is properly converted
111 * to host ordering for the clear and set operations before conversion
112 * back to le32.
113 */
114
115#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
116 (*(__le32 *)(__pdesc) = \
117 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
118 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
119 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
120
121/* macros to read various fields in RX descriptor */
122
123/* DWORD 0 */
124#define GET_RX_DESC_PKT_LEN(__rxdesc) \
125 SHIFT_AND_MASK_LE((__rxdesc), 0, 14)
126#define GET_RX_DESC_CRC32(__rxdesc) \
127 SHIFT_AND_MASK_LE(__rxdesc, 14, 1)
128#define GET_RX_DESC_ICV(__rxdesc) \
129 SHIFT_AND_MASK_LE(__rxdesc, 15, 1)
130#define GET_RX_DESC_DRVINFO_SIZE(__rxdesc) \
131 SHIFT_AND_MASK_LE(__rxdesc, 16, 4)
132#define GET_RX_DESC_SECURITY(__rxdesc) \
133 SHIFT_AND_MASK_LE(__rxdesc, 20, 3)
134#define GET_RX_DESC_QOS(__rxdesc) \
135 SHIFT_AND_MASK_LE(__rxdesc, 23, 1)
136#define GET_RX_DESC_SHIFT(__rxdesc) \
137 SHIFT_AND_MASK_LE(__rxdesc, 24, 2)
138#define GET_RX_DESC_PHY_STATUS(__rxdesc) \
139 SHIFT_AND_MASK_LE(__rxdesc, 26, 1)
140#define GET_RX_DESC_SWDEC(__rxdesc) \
141 SHIFT_AND_MASK_LE(__rxdesc, 27, 1)
142#define GET_RX_DESC_LAST_SEG(__rxdesc) \
143 SHIFT_AND_MASK_LE(__rxdesc, 28, 1)
144#define GET_RX_DESC_FIRST_SEG(__rxdesc) \
145 SHIFT_AND_MASK_LE(__rxdesc, 29, 1)
146#define GET_RX_DESC_EOR(__rxdesc) \
147 SHIFT_AND_MASK_LE(__rxdesc, 30, 1)
148#define GET_RX_DESC_OWN(__rxdesc) \
149 SHIFT_AND_MASK_LE(__rxdesc, 31, 1)
150
151/* DWORD 1 */
152#define GET_RX_DESC_MACID(__rxdesc) \
153 SHIFT_AND_MASK_LE(__rxdesc+4, 0, 5)
154#define GET_RX_DESC_TID(__rxdesc) \
155 SHIFT_AND_MASK_LE(__rxdesc+4, 5, 4)
156#define GET_RX_DESC_PAGGR(__rxdesc) \
157 SHIFT_AND_MASK_LE(__rxdesc+4, 14, 1)
158#define GET_RX_DESC_FAGGR(__rxdesc) \
159 SHIFT_AND_MASK_LE(__rxdesc+4, 15, 1)
160#define GET_RX_DESC_A1_FIT(__rxdesc) \
161 SHIFT_AND_MASK_LE(__rxdesc+4, 16, 4)
162#define GET_RX_DESC_A2_FIT(__rxdesc) \
163 SHIFT_AND_MASK_LE(__rxdesc+4, 20, 4)
164#define GET_RX_DESC_PAM(__rxdesc) \
165 SHIFT_AND_MASK_LE(__rxdesc+4, 24, 1)
166#define GET_RX_DESC_PWR(__rxdesc) \
167 SHIFT_AND_MASK_LE(__rxdesc+4, 25, 1)
168#define GET_RX_DESC_MORE_DATA(__rxdesc) \
169 SHIFT_AND_MASK_LE(__rxdesc+4, 26, 1)
170#define GET_RX_DESC_MORE_FRAG(__rxdesc) \
171 SHIFT_AND_MASK_LE(__rxdesc+4, 27, 1)
172#define GET_RX_DESC_TYPE(__rxdesc) \
173 SHIFT_AND_MASK_LE(__rxdesc+4, 28, 2)
174#define GET_RX_DESC_MC(__rxdesc) \
175 SHIFT_AND_MASK_LE(__rxdesc+4, 30, 1)
176#define GET_RX_DESC_BC(__rxdesc) \
177 SHIFT_AND_MASK_LE(__rxdesc+4, 31, 1)
178
179/* DWORD 2 */
180#define GET_RX_DESC_SEQ(__rxdesc) \
181 SHIFT_AND_MASK_LE(__rxdesc+8, 0, 12)
182#define GET_RX_DESC_FRAG(__rxdesc) \
183 SHIFT_AND_MASK_LE(__rxdesc+8, 12, 4)
184#define GET_RX_DESC_USB_AGG_PKTNUM(__rxdesc) \
185 SHIFT_AND_MASK_LE(__rxdesc+8, 16, 8)
186#define GET_RX_DESC_NEXT_IND(__rxdesc) \
187 SHIFT_AND_MASK_LE(__rxdesc+8, 30, 1)
188
189/* DWORD 3 */
190#define GET_RX_DESC_RX_MCS(__rxdesc) \
191 SHIFT_AND_MASK_LE(__rxdesc+12, 0, 6)
192#define GET_RX_DESC_RX_HT(__rxdesc) \
193 SHIFT_AND_MASK_LE(__rxdesc+12, 6, 1)
194#define GET_RX_DESC_AMSDU(__rxdesc) \
195 SHIFT_AND_MASK_LE(__rxdesc+12, 7, 1)
196#define GET_RX_DESC_SPLCP(__rxdesc) \
197 SHIFT_AND_MASK_LE(__rxdesc+12, 8, 1)
198#define GET_RX_DESC_BW(__rxdesc) \
199 SHIFT_AND_MASK_LE(__rxdesc+12, 9, 1)
200#define GET_RX_DESC_HTC(__rxdesc) \
201 SHIFT_AND_MASK_LE(__rxdesc+12, 10, 1)
202#define GET_RX_DESC_TCP_CHK_RPT(__rxdesc) \
203 SHIFT_AND_MASK_LE(__rxdesc+12, 11, 1)
204#define GET_RX_DESC_IP_CHK_RPT(__rxdesc) \
205 SHIFT_AND_MASK_LE(__rxdesc+12, 12, 1)
206#define GET_RX_DESC_TCP_CHK_VALID(__rxdesc) \
207 SHIFT_AND_MASK_LE(__rxdesc+12, 13, 1)
208#define GET_RX_DESC_HWPC_ERR(__rxdesc) \
209 SHIFT_AND_MASK_LE(__rxdesc+12, 14, 1)
210#define GET_RX_DESC_HWPC_IND(__rxdesc) \
211 SHIFT_AND_MASK_LE(__rxdesc+12, 15, 1)
212#define GET_RX_DESC_IV0(__rxdesc) \
213 SHIFT_AND_MASK_LE(__rxdesc+12, 16, 16)
214
215/* DWORD 4 */
216#define GET_RX_DESC_IV1(__rxdesc) \
217 SHIFT_AND_MASK_LE(__rxdesc+16, 0, 32)
218
219/* DWORD 5 */
220#define GET_RX_DESC_TSFL(__rxdesc) \
221 SHIFT_AND_MASK_LE(__rxdesc+20, 0, 32)
222
223/*======================= tx desc ============================================*/
224
225/* macros to set various fields in TX descriptor */
226
227/* Dword 0 */
228#define SET_TX_DESC_PKT_SIZE(__txdesc, __value) \
229 SET_BITS_OFFSET_LE(__txdesc, 0, 16, __value)
230#define SET_TX_DESC_OFFSET(__txdesc, __value) \
231 SET_BITS_OFFSET_LE(__txdesc, 16, 8, __value)
232#define SET_TX_DESC_BMC(__txdesc, __value) \
233 SET_BITS_OFFSET_LE(__txdesc, 24, 1, __value)
234#define SET_TX_DESC_HTC(__txdesc, __value) \
235 SET_BITS_OFFSET_LE(__txdesc, 25, 1, __value)
236#define SET_TX_DESC_LAST_SEG(__txdesc, __value) \
237 SET_BITS_OFFSET_LE(__txdesc, 26, 1, __value)
238#define SET_TX_DESC_FIRST_SEG(__txdesc, __value) \
239 SET_BITS_OFFSET_LE(__txdesc, 27, 1, __value)
240#define SET_TX_DESC_LINIP(__txdesc, __value) \
241 SET_BITS_OFFSET_LE(__txdesc, 28, 1, __value)
242#define SET_TX_DESC_NO_ACM(__txdesc, __value) \
243 SET_BITS_OFFSET_LE(__txdesc, 29, 1, __value)
244#define SET_TX_DESC_GF(__txdesc, __value) \
245 SET_BITS_OFFSET_LE(__txdesc, 30, 1, __value)
246#define SET_TX_DESC_OWN(__txdesc, __value) \
247 SET_BITS_OFFSET_LE(__txdesc, 31, 1, __value)
248
249
250/* Dword 1 */
251#define SET_TX_DESC_MACID(__txdesc, __value) \
252 SET_BITS_OFFSET_LE(__txdesc+4, 0, 5, __value)
253#define SET_TX_DESC_AGG_ENABLE(__txdesc, __value) \
254 SET_BITS_OFFSET_LE(__txdesc+4, 5, 1, __value)
255#define SET_TX_DESC_AGG_BREAK(__txdesc, __value) \
256 SET_BITS_OFFSET_LE(__txdesc+4, 6, 1, __value)
257#define SET_TX_DESC_RDG_ENABLE(__txdesc, __value) \
258 SET_BITS_OFFSET_LE(__txdesc+4, 7, 1, __value)
259#define SET_TX_DESC_QUEUE_SEL(__txdesc, __value) \
260 SET_BITS_OFFSET_LE(__txdesc+4, 8, 5, __value)
261#define SET_TX_DESC_RDG_NAV_EXT(__txdesc, __value) \
262 SET_BITS_OFFSET_LE(__txdesc+4, 13, 1, __value)
263#define SET_TX_DESC_LSIG_TXOP_EN(__txdesc, __value) \
264 SET_BITS_OFFSET_LE(__txdesc+4, 14, 1, __value)
265#define SET_TX_DESC_PIFS(__txdesc, __value) \
266 SET_BITS_OFFSET_LE(__txdesc+4, 15, 1, __value)
267#define SET_TX_DESC_RATE_ID(__txdesc, __value) \
268 SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
269#define SET_TX_DESC_RA_BRSR_ID(__txdesc, __value) \
270 SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
271#define SET_TX_DESC_NAV_USE_HDR(__txdesc, __value) \
272 SET_BITS_OFFSET_LE(__txdesc+4, 20, 1, __value)
273#define SET_TX_DESC_EN_DESC_ID(__txdesc, __value) \
274 SET_BITS_OFFSET_LE(__txdesc+4, 21, 1, __value)
275#define SET_TX_DESC_SEC_TYPE(__txdesc, __value) \
276 SET_BITS_OFFSET_LE(__txdesc+4, 22, 2, __value)
277#define SET_TX_DESC_PKT_OFFSET(__txdesc, __value) \
278 SET_BITS_OFFSET_LE(__txdesc+4, 26, 5, __value)
279
280/* Dword 2 */
281#define SET_TX_DESC_RTS_RC(__txdesc, __value) \
282 SET_BITS_OFFSET_LE(__txdesc+8, 0, 6, __value)
283#define SET_TX_DESC_DATA_RC(__txdesc, __value) \
284 SET_BITS_OFFSET_LE(__txdesc+8, 6, 6, __value)
285#define SET_TX_DESC_BAR_RTY_TH(__txdesc, __value) \
286 SET_BITS_OFFSET_LE(__txdesc+8, 14, 2, __value)
287#define SET_TX_DESC_MORE_FRAG(__txdesc, __value) \
288 SET_BITS_OFFSET_LE(__txdesc+8, 17, 1, __value)
289#define SET_TX_DESC_RAW(__txdesc, __value) \
290 SET_BITS_OFFSET_LE(__txdesc+8, 18, 1, __value)
291#define SET_TX_DESC_CCX(__txdesc, __value) \
292 SET_BITS_OFFSET_LE(__txdesc+8, 19, 1, __value)
293#define SET_TX_DESC_AMPDU_DENSITY(__txdesc, __value) \
294 SET_BITS_OFFSET_LE(__txdesc+8, 20, 3, __value)
295#define SET_TX_DESC_ANTSEL_A(__txdesc, __value) \
296 SET_BITS_OFFSET_LE(__txdesc+8, 24, 1, __value)
297#define SET_TX_DESC_ANTSEL_B(__txdesc, __value) \
298 SET_BITS_OFFSET_LE(__txdesc+8, 25, 1, __value)
299#define SET_TX_DESC_TX_ANT_CCK(__txdesc, __value) \
300 SET_BITS_OFFSET_LE(__txdesc+8, 26, 2, __value)
301#define SET_TX_DESC_TX_ANTL(__txdesc, __value) \
302 SET_BITS_OFFSET_LE(__txdesc+8, 28, 2, __value)
303#define SET_TX_DESC_TX_ANT_HT(__txdesc, __value) \
304 SET_BITS_OFFSET_LE(__txdesc+8, 30, 2, __value)
305
306/* Dword 3 */
307#define SET_TX_DESC_NEXT_HEAP_PAGE(__txdesc, __value) \
308 SET_BITS_OFFSET_LE(__txdesc+12, 0, 8, __value)
309#define SET_TX_DESC_TAIL_PAGE(__txdesc, __value) \
310 SET_BITS_OFFSET_LE(__txdesc+12, 8, 8, __value)
311#define SET_TX_DESC_SEQ(__txdesc, __value) \
312 SET_BITS_OFFSET_LE(__txdesc+12, 16, 12, __value)
313#define SET_TX_DESC_PKT_ID(__txdesc, __value) \
314 SET_BITS_OFFSET_LE(__txdesc+12, 28, 4, __value)
315
316/* Dword 4 */
317#define SET_TX_DESC_RTS_RATE(__txdesc, __value) \
318 SET_BITS_OFFSET_LE(__txdesc+16, 0, 5, __value)
319#define SET_TX_DESC_AP_DCFE(__txdesc, __value) \
320 SET_BITS_OFFSET_LE(__txdesc+16, 5, 1, __value)
321#define SET_TX_DESC_QOS(__txdesc, __value) \
322 SET_BITS_OFFSET_LE(__txdesc+16, 6, 1, __value)
323#define SET_TX_DESC_HWSEQ_EN(__txdesc, __value) \
324 SET_BITS_OFFSET_LE(__txdesc+16, 7, 1, __value)
325#define SET_TX_DESC_USE_RATE(__txdesc, __value) \
326 SET_BITS_OFFSET_LE(__txdesc+16, 8, 1, __value)
327#define SET_TX_DESC_DISABLE_RTS_FB(__txdesc, __value) \
328 SET_BITS_OFFSET_LE(__txdesc+16, 9, 1, __value)
329#define SET_TX_DESC_DISABLE_FB(__txdesc, __value) \
330 SET_BITS_OFFSET_LE(__txdesc+16, 10, 1, __value)
331#define SET_TX_DESC_CTS2SELF(__txdesc, __value) \
332 SET_BITS_OFFSET_LE(__txdesc+16, 11, 1, __value)
333#define SET_TX_DESC_RTS_ENABLE(__txdesc, __value) \
334 SET_BITS_OFFSET_LE(__txdesc+16, 12, 1, __value)
335#define SET_TX_DESC_HW_RTS_ENABLE(__txdesc, __value) \
336 SET_BITS_OFFSET_LE(__txdesc+16, 13, 1, __value)
337#define SET_TX_DESC_WAIT_DCTS(__txdesc, __value) \
338 SET_BITS_OFFSET_LE(__txdesc+16, 18, 1, __value)
339#define SET_TX_DESC_CTS2AP_EN(__txdesc, __value) \
340 SET_BITS_OFFSET_LE(__txdesc+16, 19, 1, __value)
341#define SET_TX_DESC_DATA_SC(__txdesc, __value) \
342 SET_BITS_OFFSET_LE(__txdesc+16, 20, 2, __value)
343#define SET_TX_DESC_DATA_STBC(__txdesc, __value) \
344 SET_BITS_OFFSET_LE(__txdesc+16, 22, 2, __value)
345#define SET_TX_DESC_DATA_SHORT(__txdesc, __value) \
346 SET_BITS_OFFSET_LE(__txdesc+16, 24, 1, __value)
347#define SET_TX_DESC_DATA_BW(__txdesc, __value) \
348 SET_BITS_OFFSET_LE(__txdesc+16, 25, 1, __value)
349#define SET_TX_DESC_RTS_SHORT(__txdesc, __value) \
350 SET_BITS_OFFSET_LE(__txdesc+16, 26, 1, __value)
351#define SET_TX_DESC_RTS_BW(__txdesc, __value) \
352 SET_BITS_OFFSET_LE(__txdesc+16, 27, 1, __value)
353#define SET_TX_DESC_RTS_SC(__txdesc, __value) \
354 SET_BITS_OFFSET_LE(__txdesc+16, 28, 2, __value)
355#define SET_TX_DESC_RTS_STBC(__txdesc, __value) \
356 SET_BITS_OFFSET_LE(__txdesc+16, 30, 2, __value)
357
358/* Dword 5 */
359#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
360 SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
361#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
362 SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
363#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
364 SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
365#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__txdesc, __value) \
366 SET_BITS_OFFSET_LE(__txdesc+20, 8, 5, __value)
367#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__txdesc, __value) \
368 SET_BITS_OFFSET_LE(__txdesc+20, 13, 4, __value)
369#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__txdesc, __value) \
370 SET_BITS_OFFSET_LE(__txdesc+20, 17, 1, __value)
371#define SET_TX_DESC_DATA_RETRY_LIMIT(__txdesc, __value) \
372 SET_BITS_OFFSET_LE(__txdesc+20, 18, 6, __value)
373#define SET_TX_DESC_USB_TXAGG_NUM(__txdesc, __value) \
374 SET_BITS_OFFSET_LE(__txdesc+20, 24, 8, __value)
375
376/* Dword 6 */
377#define SET_TX_DESC_TXAGC_A(__txdesc, __value) \
378 SET_BITS_OFFSET_LE(__txdesc+24, 0, 5, __value)
379#define SET_TX_DESC_TXAGC_B(__txdesc, __value) \
380 SET_BITS_OFFSET_LE(__txdesc+24, 5, 5, __value)
381#define SET_TX_DESC_USB_MAX_LEN(__txdesc, __value) \
382 SET_BITS_OFFSET_LE(__txdesc+24, 10, 1, __value)
383#define SET_TX_DESC_MAX_AGG_NUM(__txdesc, __value) \
384 SET_BITS_OFFSET_LE(__txdesc+24, 11, 5, __value)
385#define SET_TX_DESC_MCSG1_MAX_LEN(__txdesc, __value) \
386 SET_BITS_OFFSET_LE(__txdesc+24, 16, 4, __value)
387#define SET_TX_DESC_MCSG2_MAX_LEN(__txdesc, __value) \
388 SET_BITS_OFFSET_LE(__txdesc+24, 20, 4, __value)
389#define SET_TX_DESC_MCSG3_MAX_LEN(__txdesc, __value) \
390 SET_BITS_OFFSET_LE(__txdesc+24, 24, 4, __value)
391#define SET_TX_DESC_MCSG7_MAX_LEN(__txdesc, __value) \
392 SET_BITS_OFFSET_LE(__txdesc+24, 28, 4, __value)
393
394/* Dword 7 */
395#define SET_TX_DESC_TX_DESC_CHECKSUM(__txdesc, __value) \
396 SET_BITS_OFFSET_LE(__txdesc+28, 0, 16, __value)
397#define SET_TX_DESC_MCSG4_MAX_LEN(__txdesc, __value) \
398 SET_BITS_OFFSET_LE(__txdesc+28, 16, 4, __value)
399#define SET_TX_DESC_MCSG5_MAX_LEN(__txdesc, __value) \
400 SET_BITS_OFFSET_LE(__txdesc+28, 20, 4, __value)
401#define SET_TX_DESC_MCSG6_MAX_LEN(__txdesc, __value) \
402 SET_BITS_OFFSET_LE(__txdesc+28, 24, 4, __value)
403#define SET_TX_DESC_MCSG15_MAX_LEN(__txdesc, __value) \
404 SET_BITS_OFFSET_LE(__txdesc+28, 28, 4, __value)
405
406
407int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw);
408u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index);
409bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
410 struct rtl_stats *stats,
411 struct ieee80211_rx_status *rx_status,
412 u8 *p_desc, struct sk_buff *skb);
413void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb);
414void rtl8192c_rx_segregate_hdl(struct ieee80211_hw *, struct sk_buff *,
415 struct sk_buff_head *);
416void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb);
417int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb,
418 struct sk_buff *skb);
419struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *,
420 struct sk_buff_head *);
421void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
422 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
423 struct ieee80211_tx_info *info, struct sk_buff *skb,
424 u8 queue_index,
425 struct rtl_tcb_desc *tcb_desc);
426void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 * pDesc,
427 u32 buffer_len, bool bIsPsPoll);
428void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw,
429 u8 *pdesc, bool b_firstseg,
430 bool b_lastseg, struct sk_buff *skb);
431bool rtl92cu_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb);
432
433#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-12 19:54:26 -0400