aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c201
1 files changed, 98 insertions, 103 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
index 1f07558debf2..8ab93a69f334 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
@@ -42,16 +42,15 @@ u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
42 struct rtl_priv *rtlpriv = rtl_priv(hw); 42 struct rtl_priv *rtlpriv = rtl_priv(hw);
43 u32 returnvalue, originalvalue, bitshift; 43 u32 returnvalue, originalvalue, bitshift;
44 44
45 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), " 45 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
46 "bitmask(%#x)\n", regaddr, 46 regaddr, bitmask);
47 bitmask));
48 originalvalue = rtl_read_dword(rtlpriv, regaddr); 47 originalvalue = rtl_read_dword(rtlpriv, regaddr);
49 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); 48 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
50 returnvalue = (originalvalue & bitmask) >> bitshift; 49 returnvalue = (originalvalue & bitmask) >> bitshift;
51 50
52 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x " 51 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
53 "Addr[0x%x]=0x%x\n", bitmask, 52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
54 regaddr, originalvalue)); 53 bitmask, regaddr, originalvalue);
55 54
56 return returnvalue; 55 return returnvalue;
57 56
@@ -64,9 +63,9 @@ void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
64 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 struct rtl_priv *rtlpriv = rtl_priv(hw);
65 u32 originalvalue, bitshift; 64 u32 originalvalue, bitshift;
66 65
67 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x)," 66 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
68 " data(%#x)\n", regaddr, bitmask, 67 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
69 data)); 68 regaddr, bitmask, data);
70 69
71 if (bitmask != MASKDWORD) { 70 if (bitmask != MASKDWORD) {
72 originalvalue = rtl_read_dword(rtlpriv, regaddr); 71 originalvalue = rtl_read_dword(rtlpriv, regaddr);
@@ -76,9 +75,9 @@ void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
76 75
77 rtl_write_dword(rtlpriv, regaddr, data); 76 rtl_write_dword(rtlpriv, regaddr, data);
78 77
79 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x)," 78 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
80 " data(%#x)\n", regaddr, bitmask, 79 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
81 data)); 80 regaddr, bitmask, data);
82 81
83} 82}
84EXPORT_SYMBOL(rtl92c_phy_set_bb_reg); 83EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
@@ -114,7 +113,7 @@ u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
114 offset &= 0x3f; 113 offset &= 0x3f;
115 newoffset = offset; 114 newoffset = offset;
116 if (RT_CANNOT_IO(hw)) { 115 if (RT_CANNOT_IO(hw)) {
117 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("return all one\n")); 116 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
118 return 0xFFFFFFFF; 117 return 0xFFFFFFFF;
119 } 118 }
120 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 119 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
@@ -144,9 +143,8 @@ u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
144 else 143 else
145 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback, 144 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
146 BLSSIREADBACKDATA); 145 BLSSIREADBACKDATA);
147 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n", 146 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
148 rfpath, pphyreg->rflssi_readback, 147 rfpath, pphyreg->rflssi_readback, retvalue);
149 retvalue));
150 return retvalue; 148 return retvalue;
151} 149}
152EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read); 150EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
@@ -162,16 +160,15 @@ void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
162 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 160 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
163 161
164 if (RT_CANNOT_IO(hw)) { 162 if (RT_CANNOT_IO(hw)) {
165 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("stop\n")); 163 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
166 return; 164 return;
167 } 165 }
168 offset &= 0x3f; 166 offset &= 0x3f;
169 newoffset = offset; 167 newoffset = offset;
170 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 168 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
171 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 169 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
172 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n", 170 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
173 rfpath, pphyreg->rf3wire_offset, 171 rfpath, pphyreg->rf3wire_offset, data_and_addr);
174 data_and_addr));
175} 172}
176EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write); 173EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
177 174
@@ -216,16 +213,16 @@ bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
216 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 213 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
217 bool rtstatus; 214 bool rtstatus;
218 215
219 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n")); 216 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
220 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw, 217 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
221 BASEBAND_CONFIG_PHY_REG); 218 BASEBAND_CONFIG_PHY_REG);
222 if (rtstatus != true) { 219 if (rtstatus != true) {
223 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!")); 220 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
224 return false; 221 return false;
225 } 222 }
226 if (rtlphy->rf_type == RF_1T2R) { 223 if (rtlphy->rf_type == RF_1T2R) {
227 _rtl92c_phy_bb_config_1t(hw); 224 _rtl92c_phy_bb_config_1t(hw);
228 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n")); 225 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
229 } 226 }
230 if (rtlefuse->autoload_failflag == false) { 227 if (rtlefuse->autoload_failflag == false) {
231 rtlphy->pwrgroup_cnt = 0; 228 rtlphy->pwrgroup_cnt = 0;
@@ -233,13 +230,13 @@ bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
233 BASEBAND_CONFIG_PHY_REG); 230 BASEBAND_CONFIG_PHY_REG);
234 } 231 }
235 if (rtstatus != true) { 232 if (rtstatus != true) {
236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!")); 233 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
237 return false; 234 return false;
238 } 235 }
239 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw, 236 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
240 BASEBAND_CONFIG_AGC_TAB); 237 BASEBAND_CONFIG_AGC_TAB);
241 if (rtstatus != true) { 238 if (rtstatus != true) {
242 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n")); 239 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
243 return false; 240 return false;
244 } 241 }
245 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 242 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
@@ -260,114 +257,114 @@ void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
260 if (regaddr == RTXAGC_A_RATE18_06) { 257 if (regaddr == RTXAGC_A_RATE18_06) {
261 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0] = data; 258 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0] = data;
262 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 259 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
263 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", 260 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
264 rtlphy->pwrgroup_cnt, 261 rtlphy->pwrgroup_cnt,
265 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0])); 262 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0]);
266 } 263 }
267 if (regaddr == RTXAGC_A_RATE54_24) { 264 if (regaddr == RTXAGC_A_RATE54_24) {
268 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1] = data; 265 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1] = data;
269 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 266 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
270 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", 267 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
271 rtlphy->pwrgroup_cnt, 268 rtlphy->pwrgroup_cnt,
272 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1])); 269 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1]);
273 } 270 }
274 if (regaddr == RTXAGC_A_CCK1_MCS32) { 271 if (regaddr == RTXAGC_A_CCK1_MCS32) {
275 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6] = data; 272 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6] = data;
276 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 273 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
277 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", 274 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
278 rtlphy->pwrgroup_cnt, 275 rtlphy->pwrgroup_cnt,
279 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6])); 276 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6]);
280 } 277 }
281 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { 278 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
282 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7] = data; 279 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7] = data;
283 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 280 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
284 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", 281 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
285 rtlphy->pwrgroup_cnt, 282 rtlphy->pwrgroup_cnt,
286 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7])); 283 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7]);
287 } 284 }
288 if (regaddr == RTXAGC_A_MCS03_MCS00) { 285 if (regaddr == RTXAGC_A_MCS03_MCS00) {
289 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2] = data; 286 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2] = data;
290 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 287 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
291 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", 288 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
292 rtlphy->pwrgroup_cnt, 289 rtlphy->pwrgroup_cnt,
293 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2])); 290 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2]);
294 } 291 }
295 if (regaddr == RTXAGC_A_MCS07_MCS04) { 292 if (regaddr == RTXAGC_A_MCS07_MCS04) {
296 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3] = data; 293 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3] = data;
297 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 294 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
298 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", 295 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
299 rtlphy->pwrgroup_cnt, 296 rtlphy->pwrgroup_cnt,
300 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3])); 297 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3]);
301 } 298 }
302 if (regaddr == RTXAGC_A_MCS11_MCS08) { 299 if (regaddr == RTXAGC_A_MCS11_MCS08) {
303 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4] = data; 300 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4] = data;
304 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 301 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
305 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", 302 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
306 rtlphy->pwrgroup_cnt, 303 rtlphy->pwrgroup_cnt,
307 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4])); 304 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4]);
308 } 305 }
309 if (regaddr == RTXAGC_A_MCS15_MCS12) { 306 if (regaddr == RTXAGC_A_MCS15_MCS12) {
310 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5] = data; 307 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5] = data;
311 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 308 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
312 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", 309 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
313 rtlphy->pwrgroup_cnt, 310 rtlphy->pwrgroup_cnt,
314 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5])); 311 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5]);
315 } 312 }
316 if (regaddr == RTXAGC_B_RATE18_06) { 313 if (regaddr == RTXAGC_B_RATE18_06) {
317 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8] = data; 314 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8] = data;
318 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 315 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
319 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", 316 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
320 rtlphy->pwrgroup_cnt, 317 rtlphy->pwrgroup_cnt,
321 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8])); 318 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8]);
322 } 319 }
323 if (regaddr == RTXAGC_B_RATE54_24) { 320 if (regaddr == RTXAGC_B_RATE54_24) {
324 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9] = data; 321 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9] = data;
325 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 322 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
326 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", 323 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
327 rtlphy->pwrgroup_cnt, 324 rtlphy->pwrgroup_cnt,
328 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9])); 325 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9]);
329 } 326 }
330 if (regaddr == RTXAGC_B_CCK1_55_MCS32) { 327 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
331 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14] = data; 328 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14] = data;
332 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 329 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
333 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", 330 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
334 rtlphy->pwrgroup_cnt, 331 rtlphy->pwrgroup_cnt,
335 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14])); 332 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14]);
336 } 333 }
337 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { 334 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
338 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15] = data; 335 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15] = data;
339 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 336 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
340 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", 337 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
341 rtlphy->pwrgroup_cnt, 338 rtlphy->pwrgroup_cnt,
342 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15])); 339 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15]);
343 } 340 }
344 if (regaddr == RTXAGC_B_MCS03_MCS00) { 341 if (regaddr == RTXAGC_B_MCS03_MCS00) {
345 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10] = data; 342 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10] = data;
346 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 343 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
347 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", 344 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
348 rtlphy->pwrgroup_cnt, 345 rtlphy->pwrgroup_cnt,
349 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10])); 346 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10]);
350 } 347 }
351 if (regaddr == RTXAGC_B_MCS07_MCS04) { 348 if (regaddr == RTXAGC_B_MCS07_MCS04) {
352 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11] = data; 349 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11] = data;
353 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 350 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
354 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", 351 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
355 rtlphy->pwrgroup_cnt, 352 rtlphy->pwrgroup_cnt,
356 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11])); 353 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11]);
357 } 354 }
358 if (regaddr == RTXAGC_B_MCS11_MCS08) { 355 if (regaddr == RTXAGC_B_MCS11_MCS08) {
359 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12] = data; 356 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12] = data;
360 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 357 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
361 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", 358 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
362 rtlphy->pwrgroup_cnt, 359 rtlphy->pwrgroup_cnt,
363 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12])); 360 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12]);
364 } 361 }
365 if (regaddr == RTXAGC_B_MCS15_MCS12) { 362 if (regaddr == RTXAGC_B_MCS15_MCS12) {
366 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13] = data; 363 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13] = data;
367 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 364 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
368 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", 365 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
369 rtlphy->pwrgroup_cnt, 366 rtlphy->pwrgroup_cnt,
370 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13])); 367 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13]);
371 368
372 rtlphy->pwrgroup_cnt++; 369 rtlphy->pwrgroup_cnt++;
373 } 370 }
@@ -389,12 +386,11 @@ void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
389 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 386 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
390 387
391 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 388 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
392 ("Default initial gain (c50=0x%x, " 389 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
393 "c58=0x%x, c60=0x%x, c68=0x%x\n", 390 rtlphy->default_initialgain[0],
394 rtlphy->default_initialgain[0], 391 rtlphy->default_initialgain[1],
395 rtlphy->default_initialgain[1], 392 rtlphy->default_initialgain[2],
396 rtlphy->default_initialgain[2], 393 rtlphy->default_initialgain[3]);
397 rtlphy->default_initialgain[3]));
398 394
399 rtlphy->framesync = (u8) rtl_get_bbreg(hw, 395 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
400 ROFDM0_RXDETECTOR3, MASKBYTE0); 396 ROFDM0_RXDETECTOR3, MASKBYTE0);
@@ -402,8 +398,8 @@ void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
402 ROFDM0_RXDETECTOR2, MASKDWORD); 398 ROFDM0_RXDETECTOR2, MASKDWORD);
403 399
404 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 400 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
405 ("Default framesync (0x%x) = 0x%x\n", 401 "Default framesync (0x%x) = 0x%x\n",
406 ROFDM0_RXDETECTOR3, rtlphy->framesync)); 402 ROFDM0_RXDETECTOR3, rtlphy->framesync);
407} 403}
408 404
409void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 405void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
@@ -615,8 +611,8 @@ bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
615 else 611 else
616 ofdmtxpwridx = 0; 612 ofdmtxpwridx = 0;
617 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE, 613 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
618 ("%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n", 614 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
619 power_indbm, ccktxpwridx, ofdmtxpwridx)); 615 power_indbm, ccktxpwridx, ofdmtxpwridx);
620 for (idx = 0; idx < 14; idx++) { 616 for (idx = 0; idx < 14; idx++) {
621 for (rf_path = 0; rf_path < 2; rf_path++) { 617 for (rf_path = 0; rf_path < 2; rf_path++) {
622 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx; 618 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
@@ -710,7 +706,7 @@ void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
710 break; 706 break;
711 default: 707 default:
712 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 708 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
713 ("Unknown Scan Backup operation.\n")); 709 "Unknown Scan Backup operation\n");
714 break; 710 break;
715 } 711 }
716 } 712 }
@@ -732,7 +728,7 @@ void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
732 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw); 728 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
733 } else { 729 } else {
734 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 730 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
735 ("FALSE driver sleep or unload\n")); 731 "FALSE driver sleep or unload\n");
736 rtlphy->set_bwmode_inprogress = false; 732 rtlphy->set_bwmode_inprogress = false;
737 rtlphy->current_chan_bw = tmp_bw; 733 rtlphy->current_chan_bw = tmp_bw;
738 } 734 }
@@ -747,7 +743,7 @@ void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
747 u32 delay; 743 u32 delay;
748 744
749 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 745 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
750 ("switch to channel%d\n", rtlphy->current_channel)); 746 "switch to channel%d\n", rtlphy->current_channel);
751 if (is_hal_stop(rtlhal)) 747 if (is_hal_stop(rtlhal))
752 return; 748 return;
753 do { 749 do {
@@ -765,7 +761,7 @@ void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
765 } 761 }
766 break; 762 break;
767 } while (true); 763 } while (true);
768 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n")); 764 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
769} 765}
770EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback); 766EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
771 767
@@ -787,12 +783,11 @@ u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
787 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 783 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
788 rtl92c_phy_sw_chnl_callback(hw); 784 rtl92c_phy_sw_chnl_callback(hw);
789 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 785 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
790 ("sw_chnl_inprogress false schdule workitem\n")); 786 "sw_chnl_inprogress false schdule workitem\n");
791 rtlphy->sw_chnl_inprogress = false; 787 rtlphy->sw_chnl_inprogress = false;
792 } else { 788 } else {
793 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 789 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
794 ("sw_chnl_inprogress false driver sleep or" 790 "sw_chnl_inprogress false driver sleep or unload\n");
795 " unload\n"));
796 rtlphy->sw_chnl_inprogress = false; 791 rtlphy->sw_chnl_inprogress = false;
797 } 792 }
798 return 1; 793 return 1;
@@ -916,7 +911,7 @@ bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
916 break; 911 break;
917 default: 912 default:
918 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 913 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
919 ("switch case not process\n")); 914 "switch case not processed\n");
920 break; 915 break;
921 } 916 }
922 917
@@ -1920,23 +1915,23 @@ bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1920 bool postprocessing = false; 1915 bool postprocessing = false;
1921 1916
1922 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1917 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1923 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n", 1918 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1924 iotype, rtlphy->set_io_inprogress)); 1919 iotype, rtlphy->set_io_inprogress);
1925 do { 1920 do {
1926 switch (iotype) { 1921 switch (iotype) {
1927 case IO_CMD_RESUME_DM_BY_SCAN: 1922 case IO_CMD_RESUME_DM_BY_SCAN:
1928 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1923 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1929 ("[IO CMD] Resume DM after scan.\n")); 1924 "[IO CMD] Resume DM after scan\n");
1930 postprocessing = true; 1925 postprocessing = true;
1931 break; 1926 break;
1932 case IO_CMD_PAUSE_DM_BY_SCAN: 1927 case IO_CMD_PAUSE_DM_BY_SCAN:
1933 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1928 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1934 ("[IO CMD] Pause DM before scan.\n")); 1929 "[IO CMD] Pause DM before scan\n");
1935 postprocessing = true; 1930 postprocessing = true;
1936 break; 1931 break;
1937 default: 1932 default:
1938 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1933 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1939 ("switch case not process\n")); 1934 "switch case not processed\n");
1940 break; 1935 break;
1941 } 1936 }
1942 } while (false); 1937 } while (false);
@@ -1947,7 +1942,7 @@ bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1947 return false; 1942 return false;
1948 } 1943 }
1949 rtl92c_phy_set_io(hw); 1944 rtl92c_phy_set_io(hw);
1950 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype)); 1945 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
1951 return true; 1946 return true;
1952} 1947}
1953EXPORT_SYMBOL(rtl92c_phy_set_io_cmd); 1948EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
@@ -1958,8 +1953,8 @@ void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1958 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1953 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1959 1954
1960 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1955 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1961 ("--->Cmd(%#x), set_io_inprogress(%d)\n", 1956 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1962 rtlphy->current_io_type, rtlphy->set_io_inprogress)); 1957 rtlphy->current_io_type, rtlphy->set_io_inprogress);
1963 switch (rtlphy->current_io_type) { 1958 switch (rtlphy->current_io_type) {
1964 case IO_CMD_RESUME_DM_BY_SCAN: 1959 case IO_CMD_RESUME_DM_BY_SCAN:
1965 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1; 1960 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
@@ -1973,12 +1968,12 @@ void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1973 break; 1968 break;
1974 default: 1969 default:
1975 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1970 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1976 ("switch case not process\n")); 1971 "switch case not processed\n");
1977 break; 1972 break;
1978 } 1973 }
1979 rtlphy->set_io_inprogress = false; 1974 rtlphy->set_io_inprogress = false;
1980 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1975 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
1981 ("<---(%#x)\n", rtlphy->current_io_type)); 1976 rtlphy->current_io_type);
1982} 1977}
1983EXPORT_SYMBOL(rtl92c_phy_set_io); 1978EXPORT_SYMBOL(rtl92c_phy_set_io);
1984 1979
@@ -2018,7 +2013,7 @@ void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
2018 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2013 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2019 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2014 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2020 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 2015 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
2021 ("Switch RF timeout !!!.\n")); 2016 "Switch RF timeout !!!\n");
2022 return; 2017 return;
2023 } 2018 }
2024 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2019 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 05:19:27 -0400