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path: root/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
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Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c815
1 files changed, 267 insertions, 548 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
index 9e32ac8a4425..77e61b19bf36 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
@@ -27,12 +27,13 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#include <linux/export.h>
31#include "../wifi.h" 30#include "../wifi.h"
32#include "../rtl8192ce/reg.h" 31#include "../rtl8192ce/reg.h"
33#include "../rtl8192ce/def.h" 32#include "../rtl8192ce/def.h"
34#include "dm_common.h" 33#include "dm_common.h"
34#include "fw_common.h"
35#include "phy_common.h" 35#include "phy_common.h"
36#include <linux/export.h>
36 37
37u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 38u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
38{ 39{
@@ -50,7 +51,6 @@ u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
50 bitmask, regaddr, originalvalue); 51 bitmask, regaddr, originalvalue);
51 52
52 return returnvalue; 53 return returnvalue;
53
54} 54}
55EXPORT_SYMBOL(rtl92c_phy_query_bb_reg); 55EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
56 56
@@ -75,7 +75,6 @@ void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
75 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 75 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
76 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 76 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
77 regaddr, bitmask, data); 77 regaddr, bitmask, data);
78
79} 78}
80EXPORT_SYMBOL(rtl92c_phy_set_bb_reg); 79EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
81 80
@@ -84,7 +83,6 @@ u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
84{ 83{
85 RT_ASSERT(false, "deprecated!\n"); 84 RT_ASSERT(false, "deprecated!\n");
86 return 0; 85 return 0;
87
88} 86}
89EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read); 87EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
90 88
@@ -129,10 +127,10 @@ u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
129 tmplong | BLSSIREADEDGE); 127 tmplong | BLSSIREADEDGE);
130 mdelay(1); 128 mdelay(1);
131 if (rfpath == RF90_PATH_A) 129 if (rfpath == RF90_PATH_A)
132 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 130 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
133 BIT(8)); 131 BIT(8));
134 else if (rfpath == RF90_PATH_B) 132 else if (rfpath == RF90_PATH_B)
135 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 133 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
136 BIT(8)); 134 BIT(8));
137 if (rfpi_enable) 135 if (rfpi_enable)
138 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 136 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
@@ -141,7 +139,8 @@ u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
141 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 139 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
142 BLSSIREADBACKDATA); 140 BLSSIREADBACKDATA);
143 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", 141 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
144 rfpath, pphyreg->rf_rb, retvalue); 142 rfpath, pphyreg->rf_rb,
143 retvalue);
145 return retvalue; 144 return retvalue;
146} 145}
147EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read); 146EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
@@ -165,7 +164,8 @@ void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
165 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 164 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
166 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 165 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
167 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 166 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
168 rfpath, pphyreg->rf3wire_offset, data_and_addr); 167 rfpath, pphyreg->rf3wire_offset,
168 data_and_addr);
169} 169}
170EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write); 170EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
171 171
@@ -174,7 +174,7 @@ u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
174 u32 i; 174 u32 i;
175 175
176 for (i = 0; i <= 31; i++) { 176 for (i = 0; i <= 31; i++) {
177 if ((bitmask >> i) & 0x1) 177 if (((bitmask >> i) & 0x1) == 1)
178 break; 178 break;
179 } 179 }
180 return i; 180 return i;
@@ -210,11 +210,10 @@ bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
210 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 210 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
211 bool rtstatus; 211 bool rtstatus;
212 212
213 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
214 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw, 213 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
215 BASEBAND_CONFIG_PHY_REG); 214 BASEBAND_CONFIG_PHY_REG);
216 if (!rtstatus) { 215 if (!rtstatus) {
217 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n"); 216 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
218 return false; 217 return false;
219 } 218 }
220 if (rtlphy->rf_type == RF_1T2R) { 219 if (rtlphy->rf_type == RF_1T2R) {
@@ -227,7 +226,7 @@ bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
227 BASEBAND_CONFIG_PHY_REG); 226 BASEBAND_CONFIG_PHY_REG);
228 } 227 }
229 if (!rtstatus) { 228 if (!rtstatus) {
230 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n"); 229 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
231 return false; 230 return false;
232 } 231 }
233 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw, 232 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
@@ -236,12 +235,12 @@ bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n"); 235 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
237 return false; 236 return false;
238 } 237 }
239 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 238 rtlphy->cck_high_power =
240 RFPGA0_XA_HSSIPARAMETER2, 239 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
241 0x200));
242 240
243 return true; 241 return true;
244} 242}
243
245EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile); 244EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
246 245
247void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw, 246void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
@@ -250,51 +249,153 @@ void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
250{ 249{
251 struct rtl_priv *rtlpriv = rtl_priv(hw); 250 struct rtl_priv *rtlpriv = rtl_priv(hw);
252 struct rtl_phy *rtlphy = &(rtlpriv->phy); 251 struct rtl_phy *rtlphy = &(rtlpriv->phy);
253 int index;
254
255 if (regaddr == RTXAGC_A_RATE18_06)
256 index = 0;
257 else if (regaddr == RTXAGC_A_RATE54_24)
258 index = 1;
259 else if (regaddr == RTXAGC_A_CCK1_MCS32)
260 index = 6;
261 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
262 index = 7;
263 else if (regaddr == RTXAGC_A_MCS03_MCS00)
264 index = 2;
265 else if (regaddr == RTXAGC_A_MCS07_MCS04)
266 index = 3;
267 else if (regaddr == RTXAGC_A_MCS11_MCS08)
268 index = 4;
269 else if (regaddr == RTXAGC_A_MCS15_MCS12)
270 index = 5;
271 else if (regaddr == RTXAGC_B_RATE18_06)
272 index = 8;
273 else if (regaddr == RTXAGC_B_RATE54_24)
274 index = 9;
275 else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
276 index = 14;
277 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
278 index = 15;
279 else if (regaddr == RTXAGC_B_MCS03_MCS00)
280 index = 10;
281 else if (regaddr == RTXAGC_B_MCS07_MCS04)
282 index = 11;
283 else if (regaddr == RTXAGC_B_MCS11_MCS08)
284 index = 12;
285 else if (regaddr == RTXAGC_B_MCS15_MCS12)
286 index = 13;
287 else
288 return;
289 252
290 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; 253 if (regaddr == RTXAGC_A_RATE18_06) {
291 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 254 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
292 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 255 data;
293 rtlphy->pwrgroup_cnt, index, 256 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
294 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); 257 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
258 rtlphy->pwrgroup_cnt,
259 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
260 pwrgroup_cnt][0]);
261 }
262 if (regaddr == RTXAGC_A_RATE54_24) {
263 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
264 data;
265 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
266 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
267 rtlphy->pwrgroup_cnt,
268 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
269 pwrgroup_cnt][1]);
270 }
271 if (regaddr == RTXAGC_A_CCK1_MCS32) {
272 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
273 data;
274 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
275 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
276 rtlphy->pwrgroup_cnt,
277 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
278 pwrgroup_cnt][6]);
279 }
280 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
281 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
282 data;
283 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
284 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
285 rtlphy->pwrgroup_cnt,
286 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
287 pwrgroup_cnt][7]);
288 }
289 if (regaddr == RTXAGC_A_MCS03_MCS00) {
290 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
291 data;
292 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
293 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
294 rtlphy->pwrgroup_cnt,
295 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
296 pwrgroup_cnt][2]);
297 }
298 if (regaddr == RTXAGC_A_MCS07_MCS04) {
299 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
300 data;
301 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
302 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
303 rtlphy->pwrgroup_cnt,
304 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
305 pwrgroup_cnt][3]);
306 }
307 if (regaddr == RTXAGC_A_MCS11_MCS08) {
308 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
309 data;
310 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
311 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
312 rtlphy->pwrgroup_cnt,
313 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
314 pwrgroup_cnt][4]);
315 }
316 if (regaddr == RTXAGC_A_MCS15_MCS12) {
317 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
318 data;
319 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
320 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
321 rtlphy->pwrgroup_cnt,
322 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
323 pwrgroup_cnt][5]);
324 }
325 if (regaddr == RTXAGC_B_RATE18_06) {
326 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
327 data;
328 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
329 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
330 rtlphy->pwrgroup_cnt,
331 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
332 pwrgroup_cnt][8]);
333 }
334 if (regaddr == RTXAGC_B_RATE54_24) {
335 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
336 data;
337 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
338 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
339 rtlphy->pwrgroup_cnt,
340 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
341 pwrgroup_cnt][9]);
342 }
343 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
344 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
345 data;
346 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
347 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
348 rtlphy->pwrgroup_cnt,
349 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
350 pwrgroup_cnt][14]);
351 }
352 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
353 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
354 data;
355 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
356 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
357 rtlphy->pwrgroup_cnt,
358 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
359 pwrgroup_cnt][15]);
360 }
361 if (regaddr == RTXAGC_B_MCS03_MCS00) {
362 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
363 data;
364 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
365 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
366 rtlphy->pwrgroup_cnt,
367 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
368 pwrgroup_cnt][10]);
369 }
370 if (regaddr == RTXAGC_B_MCS07_MCS04) {
371 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
372 data;
373 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
374 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
375 rtlphy->pwrgroup_cnt,
376 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
377 pwrgroup_cnt][11]);
378 }
379 if (regaddr == RTXAGC_B_MCS11_MCS08) {
380 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
381 data;
382 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
383 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
384 rtlphy->pwrgroup_cnt,
385 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
386 pwrgroup_cnt][12]);
387 }
388 if (regaddr == RTXAGC_B_MCS15_MCS12) {
389 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
390 data;
391 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
392 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
393 rtlphy->pwrgroup_cnt,
394 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
395 pwrgroup_cnt][13]);
295 396
296 if (index == 13)
297 rtlphy->pwrgroup_cnt++; 397 rtlphy->pwrgroup_cnt++;
398 }
298} 399}
299EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset); 400EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);
300 401
@@ -304,29 +405,29 @@ void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
304 struct rtl_phy *rtlphy = &(rtlpriv->phy); 405 struct rtl_phy *rtlphy = &(rtlpriv->phy);
305 406
306 rtlphy->default_initialgain[0] = 407 rtlphy->default_initialgain[0] =
307 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 408 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
308 rtlphy->default_initialgain[1] = 409 rtlphy->default_initialgain[1] =
309 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 410 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
310 rtlphy->default_initialgain[2] = 411 rtlphy->default_initialgain[2] =
311 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 412 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
312 rtlphy->default_initialgain[3] = 413 rtlphy->default_initialgain[3] =
313 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 414 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
314 415
315 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 416 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
316 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 417 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
317 rtlphy->default_initialgain[0], 418 rtlphy->default_initialgain[0],
318 rtlphy->default_initialgain[1], 419 rtlphy->default_initialgain[1],
319 rtlphy->default_initialgain[2], 420 rtlphy->default_initialgain[2],
320 rtlphy->default_initialgain[3]); 421 rtlphy->default_initialgain[3]);
321 422
322 rtlphy->framesync = (u8) rtl_get_bbreg(hw, 423 rtlphy->framesync = (u8)rtl_get_bbreg(hw,
323 ROFDM0_RXDETECTOR3, MASKBYTE0); 424 ROFDM0_RXDETECTOR3, MASKBYTE0);
324 rtlphy->framesync_c34 = rtl_get_bbreg(hw, 425 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
325 ROFDM0_RXDETECTOR2, MASKDWORD); 426 ROFDM0_RXDETECTOR2, MASKDWORD);
326 427
327 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 428 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
328 "Default framesync (0x%x) = 0x%x\n", 429 "Default framesync (0x%x) = 0x%x\n",
329 ROFDM0_RXDETECTOR3, rtlphy->framesync); 430 ROFDM0_RXDETECTOR3, rtlphy->framesync);
330} 431}
331 432
332void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 433void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
@@ -426,19 +527,17 @@ void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
426 long txpwr_dbm; 527 long txpwr_dbm;
427 528
428 txpwr_level = rtlphy->cur_cck_txpwridx; 529 txpwr_level = rtlphy->cur_cck_txpwridx;
429 txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw, 530 txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
430 WIRELESS_MODE_B, txpwr_level); 531 txpwr_level);
431 txpwr_level = rtlphy->cur_ofdm24g_txpwridx + 532 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
432 rtlefuse->legacy_ht_txpowerdiff; 533 rtlefuse->legacy_ht_txpowerdiff;
433 if (_rtl92c_phy_txpwr_idx_to_dbm(hw, 534 if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
434 WIRELESS_MODE_G,
435 txpwr_level) > txpwr_dbm) 535 txpwr_level) > txpwr_dbm)
436 txpwr_dbm = 536 txpwr_dbm =
437 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 537 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
438 txpwr_level); 538 txpwr_level);
439 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 539 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
440 if (_rtl92c_phy_txpwr_idx_to_dbm(hw, 540 if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
441 WIRELESS_MODE_N_24G,
442 txpwr_level) > txpwr_dbm) 541 txpwr_level) > txpwr_dbm)
443 txpwr_dbm = 542 txpwr_dbm =
444 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 543 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
@@ -480,21 +579,19 @@ static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
480 579
481 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 580 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
482 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 581 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
483
484} 582}
485 583
486void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 584void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
487{ 585{
488 struct rtl_priv *rtlpriv = rtl_priv(hw); 586 struct rtl_priv *rtlpriv = rtl_priv(hw);
489 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 587 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
490 u8 cckpowerlevel[2], ofdmpowerlevel[2]; 588 u8 cckpowerlevel[2], ofdmpowerlevel[2];
491 589
492 if (!rtlefuse->txpwr_fromeprom) 590 if (!rtlefuse->txpwr_fromeprom)
493 return; 591 return;
494 _rtl92c_get_txpower_index(hw, channel, 592 _rtl92c_get_txpower_index(hw, channel,
495 &cckpowerlevel[0], &ofdmpowerlevel[0]); 593 &cckpowerlevel[0], &ofdmpowerlevel[0]);
496 _rtl92c_ccxpower_index_check(hw, 594 _rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
497 channel, &cckpowerlevel[0],
498 &ofdmpowerlevel[0]); 595 &ofdmpowerlevel[0]);
499 rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); 596 rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
500 rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], 597 rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
@@ -509,11 +606,9 @@ bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
509 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 606 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
510 u8 idx; 607 u8 idx;
511 u8 rf_path; 608 u8 rf_path;
512 u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw, 609 u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_B,
513 WIRELESS_MODE_B,
514 power_indbm); 610 power_indbm);
515 u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw, 611 u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_N_24G,
516 WIRELESS_MODE_N_24G,
517 power_indbm); 612 power_indbm);
518 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0) 613 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
519 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff; 614 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
@@ -521,7 +616,7 @@ bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
521 ofdmtxpwridx = 0; 616 ofdmtxpwridx = 0;
522 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE, 617 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
523 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n", 618 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
524 power_indbm, ccktxpwridx, ofdmtxpwridx); 619 power_indbm, ccktxpwridx, ofdmtxpwridx);
525 for (idx = 0; idx < 14; idx++) { 620 for (idx = 0; idx < 14; idx++) {
526 for (rf_path = 0; rf_path < 2; rf_path++) { 621 for (rf_path = 0; rf_path < 2; rf_path++) {
527 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx; 622 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
@@ -536,7 +631,7 @@ bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
536} 631}
537EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm); 632EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
538 633
539u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw, 634u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
540 enum wireless_mode wirelessmode, 635 enum wireless_mode wirelessmode,
541 long power_indbm) 636 long power_indbm)
542{ 637{
@@ -557,7 +652,7 @@ u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
557 } 652 }
558 653
559 if ((power_indbm - offset) > 0) 654 if ((power_indbm - offset) > 0)
560 txpwridx = (u8) ((power_indbm - offset) * 2); 655 txpwridx = (u8)((power_indbm - offset) * 2);
561 else 656 else
562 txpwridx = 0; 657 txpwridx = 0;
563 658
@@ -566,7 +661,7 @@ u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
566 661
567 return txpwridx; 662 return txpwridx;
568} 663}
569EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_Idx); 664EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_idx);
570 665
571long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 666long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
572 enum wireless_mode wirelessmode, 667 enum wireless_mode wirelessmode,
@@ -607,7 +702,7 @@ void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
607 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw); 702 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
608 } else { 703 } else {
609 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 704 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
610 "FALSE driver sleep or unload\n"); 705 "false driver sleep or unload\n");
611 rtlphy->set_bwmode_inprogress = false; 706 rtlphy->set_bwmode_inprogress = false;
612 rtlphy->current_chan_bw = tmp_bw; 707 rtlphy->current_chan_bw = tmp_bw;
613 } 708 }
@@ -640,7 +735,7 @@ void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
640 } 735 }
641 break; 736 break;
642 } while (true); 737 } while (true);
643 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 738 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
644} 739}
645EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback); 740EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
646 741
@@ -655,14 +750,14 @@ u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
655 if (rtlphy->set_bwmode_inprogress) 750 if (rtlphy->set_bwmode_inprogress)
656 return 0; 751 return 0;
657 RT_ASSERT((rtlphy->current_channel <= 14), 752 RT_ASSERT((rtlphy->current_channel <= 14),
658 "WIRELESS_MODE_G but channel>14\n"); 753 "WIRELESS_MODE_G but channel>14");
659 rtlphy->sw_chnl_inprogress = true; 754 rtlphy->sw_chnl_inprogress = true;
660 rtlphy->sw_chnl_stage = 0; 755 rtlphy->sw_chnl_stage = 0;
661 rtlphy->sw_chnl_step = 0; 756 rtlphy->sw_chnl_step = 0;
662 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 757 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
663 rtl92c_phy_sw_chnl_callback(hw); 758 rtl92c_phy_sw_chnl_callback(hw);
664 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 759 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
665 "sw_chnl_inprogress false schedule workitem\n"); 760 "sw_chnl_inprogress false schdule workitem\n");
666 rtlphy->sw_chnl_inprogress = false; 761 rtlphy->sw_chnl_inprogress = false;
667 } else { 762 } else {
668 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 763 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
@@ -673,22 +768,22 @@ u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
673} 768}
674EXPORT_SYMBOL(rtl92c_phy_sw_chnl); 769EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
675 770
676static void _rtl92c_phy_sw_rf_setting(struct ieee80211_hw *hw, u8 channel) 771static void _rtl92c_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
677{ 772{
678 struct rtl_priv *rtlpriv = rtl_priv(hw); 773 struct rtl_priv *rtlpriv = rtl_priv(hw);
679 struct rtl_phy *rtlphy = &(rtlpriv->phy); 774 struct rtl_phy *rtlphy = &(rtlpriv->phy);
680 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 775 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
681 776 if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
682 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) { 777 if (channel == 6 &&
683 if (channel == 6 && rtlphy->current_chan_bw == 778 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
684 HT_CHANNEL_WIDTH_20) 779 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
685 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 780 MASKDWORD, 0x00255);
686 0x00255); 781 } else {
687 else{ 782 u32 backuprf0x1A =
688 u32 backupRF0x1A = (u32)rtl_get_rfreg(hw, RF90_PATH_A, 783 (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
689 RF_RX_G1, RFREG_OFFSET_MASK); 784 RFREG_OFFSET_MASK);
690 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 785 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
691 backupRF0x1A); 786 backuprf0x1A);
692 } 787 }
693 } 788 }
694} 789}
@@ -701,7 +796,7 @@ static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
701 struct swchnlcmd *pcmd; 796 struct swchnlcmd *pcmd;
702 797
703 if (cmdtable == NULL) { 798 if (cmdtable == NULL) {
704 RT_ASSERT(false, "cmdtable cannot be NULL\n"); 799 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
705 return false; 800 return false;
706 } 801 }
707 802
@@ -747,7 +842,7 @@ bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
747 rfdependcmdcnt = 0; 842 rfdependcmdcnt = 0;
748 843
749 RT_ASSERT((channel >= 1 && channel <= 14), 844 RT_ASSERT((channel >= 1 && channel <= 14),
750 "invalid channel for Zebra: %d\n", channel); 845 "illegal channel for Zebra: %d\n", channel);
751 846
752 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 847 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
753 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 848 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
@@ -768,6 +863,10 @@ bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
768 case 2: 863 case 2:
769 currentcmd = &postcommoncmd[*step]; 864 currentcmd = &postcommoncmd[*step];
770 break; 865 break;
866 default:
867 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
868 "Invalid 'stage' = %d, Check it!\n", *stage);
869 return true;
771 } 870 }
772 871
773 if (currentcmd->cmdid == CMDID_END) { 872 if (currentcmd->cmdid == CMDID_END) {
@@ -794,7 +893,7 @@ bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
794 break; 893 break;
795 case CMDID_WRITEPORT_UCHAR: 894 case CMDID_WRITEPORT_UCHAR:
796 rtl_write_byte(rtlpriv, currentcmd->para1, 895 rtl_write_byte(rtlpriv, currentcmd->para1,
797 (u8) currentcmd->para2); 896 (u8)currentcmd->para2);
798 break; 897 break;
799 case CMDID_RF_WRITEREG: 898 case CMDID_RF_WRITEREG:
800 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 899 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
@@ -806,12 +905,12 @@ bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
806 currentcmd->para1, 905 currentcmd->para1,
807 RFREG_OFFSET_MASK, 906 RFREG_OFFSET_MASK,
808 rtlphy->rfreg_chnlval[rfpath]); 907 rtlphy->rfreg_chnlval[rfpath]);
809 _rtl92c_phy_sw_rf_setting(hw, channel);
810 } 908 }
909 _rtl92c_phy_sw_rf_seting(hw, channel);
811 break; 910 break;
812 default: 911 default:
813 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 912 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
814 "switch case not processed\n"); 913 "switch case not process\n");
815 break; 914 break;
816 } 915 }
817 916
@@ -900,7 +999,7 @@ static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
900} 999}
901 1000
902static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, 1001static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
903 bool iqk_ok, long result[][8], 1002 bool b_iqk_ok, long result[][8],
904 u8 final_candidate, bool btxonly) 1003 u8 final_candidate, bool btxonly)
905{ 1004{
906 u32 oldval_0, x, tx0_a, reg; 1005 u32 oldval_0, x, tx0_a, reg;
@@ -908,7 +1007,7 @@ static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
908 1007
909 if (final_candidate == 0xFF) { 1008 if (final_candidate == 0xFF) {
910 return; 1009 return;
911 } else if (iqk_ok) { 1010 } else if (b_iqk_ok) {
912 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1011 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
913 MASKDWORD) >> 22) & 0x3FF; 1012 MASKDWORD) >> 22) & 0x3FF;
914 x = result[final_candidate][0]; 1013 x = result[final_candidate][0];
@@ -940,7 +1039,7 @@ static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
940} 1039}
941 1040
942static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw, 1041static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
943 bool iqk_ok, long result[][8], 1042 bool b_iqk_ok, long result[][8],
944 u8 final_candidate, bool btxonly) 1043 u8 final_candidate, bool btxonly)
945{ 1044{
946 u32 oldval_1, x, tx1_a, reg; 1045 u32 oldval_1, x, tx1_a, reg;
@@ -948,7 +1047,7 @@ static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
948 1047
949 if (final_candidate == 0xFF) { 1048 if (final_candidate == 0xFF) {
950 return; 1049 return;
951 } else if (iqk_ok) { 1050 } else if (b_iqk_ok) {
952 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 1051 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
953 MASKDWORD) >> 22) & 0x3FF; 1052 MASKDWORD) >> 22) & 0x3FF;
954 x = result[final_candidate][4]; 1053 x = result[final_candidate][4];
@@ -1017,7 +1116,7 @@ static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1017 u32 i; 1116 u32 i;
1018 1117
1019 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1118 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1020 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1119 rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
1021 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); 1120 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1022} 1121}
1023 1122
@@ -1043,14 +1142,14 @@ static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1043 u32 *macreg, u32 *macbackup) 1142 u32 *macreg, u32 *macbackup)
1044{ 1143{
1045 struct rtl_priv *rtlpriv = rtl_priv(hw); 1144 struct rtl_priv *rtlpriv = rtl_priv(hw);
1046 u32 i; 1145 u32 i = 0;
1047 1146
1048 rtl_write_byte(rtlpriv, macreg[0], 0x3F); 1147 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1049 1148
1050 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 1149 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1051 rtl_write_byte(rtlpriv, macreg[i], 1150 rtl_write_byte(rtlpriv, macreg[i],
1052 (u8) (macbackup[i] & (~BIT(3)))); 1151 (u8)(macbackup[i] & (~BIT(3))));
1053 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); 1152 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5))));
1054} 1153}
1055 1154
1056static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw) 1155static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
@@ -1126,7 +1225,6 @@ static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1126 } else { 1225 } else {
1127 return false; 1226 return false;
1128 } 1227 }
1129
1130} 1228}
1131 1229
1132static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, 1230static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
@@ -1142,51 +1240,37 @@ static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1142 0xe88, 0xe8c, 0xed0, 0xed4, 1240 0xe88, 0xe8c, 0xed0, 0xed4,
1143 0xed8, 0xedc, 0xee0, 0xeec 1241 0xed8, 0xedc, 0xee0, 0xeec
1144 }; 1242 };
1145
1146 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1243 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1147 0x522, 0x550, 0x551, 0x040 1244 0x522, 0x550, 0x551, 0x040
1148 }; 1245 };
1149
1150 u32 iqk_bb_reg_92C[9] = {
1151 0xc04, 0xc08, 0x874, 0xb68,
1152 0xb6c, 0x870, 0x860, 0x864,
1153 0x800
1154 };
1155
1156 const u32 retrycount = 2; 1246 const u32 retrycount = 2;
1247 u32 bbvalue;
1157 1248
1158 if (t == 0) { 1249 if (t == 0) {
1159 /* dummy read */ 1250 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1160 rtl_get_bbreg(hw, 0x800, MASKDWORD);
1161 1251
1162 _rtl92c_phy_save_adda_registers(hw, adda_reg, 1252 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1163 rtlphy->adda_backup, 16); 1253 rtlphy->adda_backup, 16);
1164 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg, 1254 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1165 rtlphy->iqk_mac_backup); 1255 rtlphy->iqk_mac_backup);
1166 _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg_92C,
1167 rtlphy->iqk_bb_backup, 9);
1168 } 1256 }
1169 _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t); 1257 _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1170 if (t == 0) { 1258 if (t == 0) {
1171 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1259 rtlphy->rfpi_enable =
1172 RFPGA0_XA_HSSIPARAMETER1, 1260 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
1173 BIT(8)); 1261 BIT(8));
1174 } 1262 }
1175 1263
1176 if (!rtlphy->rfpi_enable) 1264 if (!rtlphy->rfpi_enable)
1177 _rtl92c_phy_pi_mode_switch(hw, true); 1265 _rtl92c_phy_pi_mode_switch(hw, true);
1178 1266 if (t == 0) {
1179 rtl_set_bbreg(hw, 0x800, BIT(24), 0x0); 1267 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1180 1268 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1269 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1270 }
1181 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); 1271 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1182 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); 1272 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1183 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); 1273 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1184
1185 rtl_set_bbreg(hw, 0x870, BIT(10), 0x1);
1186 rtl_set_bbreg(hw, 0x870, BIT(26), 0x1);
1187 rtl_set_bbreg(hw, 0x860, BIT(10), 0x0);
1188 rtl_set_bbreg(hw, 0x864, BIT(10), 0x0);
1189
1190 if (is2t) { 1274 if (is2t) {
1191 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1275 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1192 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); 1276 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
@@ -1228,8 +1312,8 @@ static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1228 pathb_ok = _rtl92c_phy_path_b_iqk(hw); 1312 pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1229 if (pathb_ok == 0x03) { 1313 if (pathb_ok == 0x03) {
1230 result[t][4] = (rtl_get_bbreg(hw, 1314 result[t][4] = (rtl_get_bbreg(hw,
1231 0xeb4, 1315 0xeb4,
1232 MASKDWORD) & 1316 MASKDWORD) &
1233 0x3FF0000) >> 16; 1317 0x3FF0000) >> 16;
1234 result[t][5] = 1318 result[t][5] =
1235 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1319 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
@@ -1243,17 +1327,21 @@ static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1243 break; 1327 break;
1244 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1328 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1245 result[t][4] = (rtl_get_bbreg(hw, 1329 result[t][4] = (rtl_get_bbreg(hw,
1246 0xeb4, 1330 0xeb4,
1247 MASKDWORD) & 1331 MASKDWORD) &
1248 0x3FF0000) >> 16; 1332 0x3FF0000) >> 16;
1249 } 1333 }
1250 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1334 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1251 0x3FF0000) >> 16; 1335 0x3FF0000) >> 16;
1252 } 1336 }
1253 } 1337 }
1254 1338 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1339 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1340 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1255 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1341 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1256 1342 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1343 if (is2t)
1344 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1257 if (t != 0) { 1345 if (t != 0) {
1258 if (!rtlphy->rfpi_enable) 1346 if (!rtlphy->rfpi_enable)
1259 _rtl92c_phy_pi_mode_switch(hw, false); 1347 _rtl92c_phy_pi_mode_switch(hw, false);
@@ -1261,379 +1349,12 @@ static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1261 rtlphy->adda_backup, 16); 1349 rtlphy->adda_backup, 16);
1262 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg, 1350 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1263 rtlphy->iqk_mac_backup); 1351 rtlphy->iqk_mac_backup);
1264 _rtl92c_phy_reload_adda_registers(hw, iqk_bb_reg_92C,
1265 rtlphy->iqk_bb_backup, 9);
1266
1267 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1268 if (is2t)
1269 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1270
1271 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1272 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1273 } 1352 }
1274} 1353}
1275 1354
1276static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, 1355static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1277 char delta, bool is2t) 1356 char delta, bool is2t)
1278{ 1357{
1279#if 0 /* This routine is deliberately dummied out for later fixes */
1280 struct rtl_priv *rtlpriv = rtl_priv(hw);
1281 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1282 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1283
1284 u32 reg_d[PATH_NUM];
1285 u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
1286
1287 u32 bb_backup[APK_BB_REG_NUM];
1288 u32 bb_reg[APK_BB_REG_NUM] = {
1289 0x904, 0xc04, 0x800, 0xc08, 0x874
1290 };
1291 u32 bb_ap_mode[APK_BB_REG_NUM] = {
1292 0x00000020, 0x00a05430, 0x02040000,
1293 0x000800e4, 0x00204000
1294 };
1295 u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
1296 0x00000020, 0x00a05430, 0x02040000,
1297 0x000800e4, 0x22204000
1298 };
1299
1300 u32 afe_backup[APK_AFE_REG_NUM];
1301 u32 afe_reg[APK_AFE_REG_NUM] = {
1302 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
1303 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
1304 0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
1305 0xeec
1306 };
1307
1308 u32 mac_backup[IQK_MAC_REG_NUM];
1309 u32 mac_reg[IQK_MAC_REG_NUM] = {
1310 0x522, 0x550, 0x551, 0x040
1311 };
1312
1313 u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1314 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1315 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1316 };
1317
1318 u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1319 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
1320 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1321 };
1322
1323 u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1324 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1325 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1326 };
1327
1328 u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1329 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
1330 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1331 };
1332
1333 u32 afe_on_off[PATH_NUM] = {
1334 0x04db25a4, 0x0b1b25a4
1335 };
1336
1337 const u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
1338
1339 u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
1340
1341 u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
1342
1343 u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
1344
1345 const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
1346 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1347 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1348 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1349 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1350 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1351 };
1352
1353 const u32 apk_normal_setting_value_1[13] = {
1354 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1355 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1356 0x12680000, 0x00880000, 0x00880000
1357 };
1358
1359 const u32 apk_normal_setting_value_2[16] = {
1360 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1361 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1362 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1363 0x00050006
1364 };
1365
1366 u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
1367
1368 long bb_offset, delta_v, delta_offset;
1369
1370 if (!is2t)
1371 pathbound = 1;
1372
1373 return;
1374
1375 for (index = 0; index < PATH_NUM; index++) {
1376 apk_offset[index] = apk_normal_offset[index];
1377 apk_value[index] = apk_normal_value[index];
1378 afe_on_off[index] = 0x6fdb25a4;
1379 }
1380
1381 for (index = 0; index < APK_BB_REG_NUM; index++) {
1382 for (path = 0; path < pathbound; path++) {
1383 apk_rf_init_value[path][index] =
1384 apk_normal_rf_init_value[path][index];
1385 apk_rf_value_0[path][index] =
1386 apk_normal_rf_value_0[path][index];
1387 }
1388 bb_ap_mode[index] = bb_normal_ap_mode[index];
1389
1390 apkbound = 6;
1391 }
1392
1393 for (index = 0; index < APK_BB_REG_NUM; index++) {
1394 if (index == 0)
1395 continue;
1396 bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
1397 }
1398
1399 _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
1400
1401 _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
1402
1403 for (path = 0; path < pathbound; path++) {
1404 if (path == RF90_PATH_A) {
1405 offset = 0xb00;
1406 for (index = 0; index < 11; index++) {
1407 rtl_set_bbreg(hw, offset, MASKDWORD,
1408 apk_normal_setting_value_1
1409 [index]);
1410
1411 offset += 0x04;
1412 }
1413
1414 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1415
1416 offset = 0xb68;
1417 for (; index < 13; index++) {
1418 rtl_set_bbreg(hw, offset, MASKDWORD,
1419 apk_normal_setting_value_1
1420 [index]);
1421
1422 offset += 0x04;
1423 }
1424
1425 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1426
1427 offset = 0xb00;
1428 for (index = 0; index < 16; index++) {
1429 rtl_set_bbreg(hw, offset, MASKDWORD,
1430 apk_normal_setting_value_2
1431 [index]);
1432
1433 offset += 0x04;
1434 }
1435 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1436 } else if (path == RF90_PATH_B) {
1437 offset = 0xb70;
1438 for (index = 0; index < 10; index++) {
1439 rtl_set_bbreg(hw, offset, MASKDWORD,
1440 apk_normal_setting_value_1
1441 [index]);
1442
1443 offset += 0x04;
1444 }
1445 rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
1446 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1447
1448 offset = 0xb68;
1449 index = 11;
1450 for (; index < 13; index++) {
1451 rtl_set_bbreg(hw, offset, MASKDWORD,
1452 apk_normal_setting_value_1
1453 [index]);
1454
1455 offset += 0x04;
1456 }
1457
1458 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1459
1460 offset = 0xb60;
1461 for (index = 0; index < 16; index++) {
1462 rtl_set_bbreg(hw, offset, MASKDWORD,
1463 apk_normal_setting_value_2
1464 [index]);
1465
1466 offset += 0x04;
1467 }
1468 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1469 }
1470
1471 reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
1472 0xd, MASKDWORD);
1473
1474 for (index = 0; index < APK_AFE_REG_NUM; index++)
1475 rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
1476 afe_on_off[path]);
1477
1478 if (path == RF90_PATH_A) {
1479 for (index = 0; index < APK_BB_REG_NUM; index++) {
1480 if (index == 0)
1481 continue;
1482 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
1483 bb_ap_mode[index]);
1484 }
1485 }
1486
1487 _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
1488
1489 if (path == 0) {
1490 rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
1491 } else {
1492 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
1493 0x10000);
1494 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1495 0x1000f);
1496 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1497 0x20103);
1498 }
1499
1500 delta_offset = ((delta + 14) / 2);
1501 if (delta_offset < 0)
1502 delta_offset = 0;
1503 else if (delta_offset > 12)
1504 delta_offset = 12;
1505
1506 for (index = 0; index < APK_BB_REG_NUM; index++) {
1507 if (index != 1)
1508 continue;
1509
1510 tmpreg = apk_rf_init_value[path][index];
1511
1512 if (!rtlefuse->apk_thermalmeterignore) {
1513 bb_offset = (tmpreg & 0xF0000) >> 16;
1514
1515 if (!(tmpreg & BIT(15)))
1516 bb_offset = -bb_offset;
1517
1518 delta_v =
1519 apk_delta_mapping[index][delta_offset];
1520
1521 bb_offset += delta_v;
1522
1523 if (bb_offset < 0) {
1524 tmpreg = tmpreg & (~BIT(15));
1525 bb_offset = -bb_offset;
1526 } else {
1527 tmpreg = tmpreg | BIT(15);
1528 }
1529
1530 tmpreg =
1531 (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
1532 }
1533
1534 rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
1535 MASKDWORD, 0x8992e);
1536 rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
1537 MASKDWORD, apk_rf_value_0[path][index]);
1538 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1539 MASKDWORD, tmpreg);
1540
1541 i = 0;
1542 do {
1543 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
1544 rtl_set_bbreg(hw, apk_offset[path],
1545 MASKDWORD, apk_value[0]);
1546 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1547 ("PHY_APCalibrate() offset 0x%x "
1548 "value 0x%x\n",
1549 apk_offset[path],
1550 rtl_get_bbreg(hw, apk_offset[path],
1551 MASKDWORD)));
1552
1553 mdelay(3);
1554
1555 rtl_set_bbreg(hw, apk_offset[path],
1556 MASKDWORD, apk_value[1]);
1557 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1558 ("PHY_APCalibrate() offset 0x%x "
1559 "value 0x%x\n",
1560 apk_offset[path],
1561 rtl_get_bbreg(hw, apk_offset[path],
1562 MASKDWORD)));
1563
1564 mdelay(20);
1565
1566 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1567
1568 if (path == RF90_PATH_A)
1569 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1570 0x03E00000);
1571 else
1572 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1573 0xF8000000);
1574
1575 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1576 ("PHY_APCalibrate() offset "
1577 "0xbd8[25:21] %x\n", tmpreg));
1578
1579 i++;
1580
1581 } while (tmpreg > apkbound && i < 4);
1582
1583 apk_result[path][index] = tmpreg;
1584 }
1585 }
1586
1587 _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
1588
1589 for (index = 0; index < APK_BB_REG_NUM; index++) {
1590 if (index == 0)
1591 continue;
1592 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
1593 }
1594
1595 _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
1596
1597 for (path = 0; path < pathbound; path++) {
1598 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1599 MASKDWORD, reg_d[path]);
1600
1601 if (path == RF90_PATH_B) {
1602 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1603 0x1000f);
1604 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1605 0x20101);
1606 }
1607
1608 if (apk_result[path][1] > 6)
1609 apk_result[path][1] = 6;
1610 }
1611
1612 for (path = 0; path < pathbound; path++) {
1613 rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
1614 ((apk_result[path][1] << 15) |
1615 (apk_result[path][1] << 10) |
1616 (apk_result[path][1] << 5) |
1617 apk_result[path][1]));
1618
1619 if (path == RF90_PATH_A)
1620 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1621 ((apk_result[path][1] << 15) |
1622 (apk_result[path][1] << 10) |
1623 (0x00 << 5) | 0x05));
1624 else
1625 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1626 ((apk_result[path][1] << 15) |
1627 (apk_result[path][1] << 10) |
1628 (0x02 << 5) | 0x05));
1629
1630 rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
1631 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
1632 0x08));
1633
1634 }
1635 rtlphy->b_apk_done = true;
1636#endif
1637} 1358}
1638 1359
1639static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, 1360static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
@@ -1657,15 +1378,13 @@ static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1657 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2); 1378 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1658 else 1379 else
1659 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); 1380 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1660
1661 } 1381 }
1662
1663} 1382}
1664 1383
1665#undef IQK_ADDA_REG_NUM 1384#undef IQK_ADDA_REG_NUM
1666#undef IQK_DELAY_TIME 1385#undef IQK_DELAY_TIME
1667 1386
1668void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery) 1387void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1669{ 1388{
1670 struct rtl_priv *rtlpriv = rtl_priv(hw); 1389 struct rtl_priv *rtlpriv = rtl_priv(hw);
1671 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1390 struct rtl_phy *rtlphy = &(rtlpriv->phy);
@@ -1673,10 +1392,10 @@ void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1673 1392
1674 long result[4][8]; 1393 long result[4][8];
1675 u8 i, final_candidate; 1394 u8 i, final_candidate;
1676 bool patha_ok, pathb_ok; 1395 bool b_patha_ok, b_pathb_ok;
1677 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4, reg_tmp = 0; 1396 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1397 reg_ecc, reg_tmp = 0;
1678 bool is12simular, is13simular, is23simular; 1398 bool is12simular, is13simular, is23simular;
1679 bool start_conttx = false, singletone = false;
1680 u32 iqk_bb_reg[10] = { 1399 u32 iqk_bb_reg[10] = {
1681 ROFDM0_XARXIQIMBALANCE, 1400 ROFDM0_XARXIQIMBALANCE,
1682 ROFDM0_XBRXIQIMBALANCE, 1401 ROFDM0_XBRXIQIMBALANCE,
@@ -1690,14 +1409,12 @@ void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1690 ROFDM0_RXIQEXTANTA 1409 ROFDM0_RXIQEXTANTA
1691 }; 1410 };
1692 1411
1693 if (recovery) { 1412 if (b_recovery) {
1694 _rtl92c_phy_reload_adda_registers(hw, 1413 _rtl92c_phy_reload_adda_registers(hw,
1695 iqk_bb_reg, 1414 iqk_bb_reg,
1696 rtlphy->iqk_bb_backup, 10); 1415 rtlphy->iqk_bb_backup, 10);
1697 return; 1416 return;
1698 } 1417 }
1699 if (start_conttx || singletone)
1700 return;
1701 for (i = 0; i < 8; i++) { 1418 for (i = 0; i < 8; i++) {
1702 result[0][i] = 0; 1419 result[0][i] = 0;
1703 result[1][i] = 0; 1420 result[1][i] = 0;
@@ -1705,8 +1422,8 @@ void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1705 result[3][i] = 0; 1422 result[3][i] = 0;
1706 } 1423 }
1707 final_candidate = 0xff; 1424 final_candidate = 0xff;
1708 patha_ok = false; 1425 b_patha_ok = false;
1709 pathb_ok = false; 1426 b_pathb_ok = false;
1710 is12simular = false; 1427 is12simular = false;
1711 is23simular = false; 1428 is23simular = false;
1712 is13simular = false; 1429 is13simular = false;
@@ -1752,29 +1469,34 @@ void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1752 reg_e94 = result[i][0]; 1469 reg_e94 = result[i][0];
1753 reg_e9c = result[i][1]; 1470 reg_e9c = result[i][1];
1754 reg_ea4 = result[i][2]; 1471 reg_ea4 = result[i][2];
1472 reg_eac = result[i][3];
1755 reg_eb4 = result[i][4]; 1473 reg_eb4 = result[i][4];
1756 reg_ebc = result[i][5]; 1474 reg_ebc = result[i][5];
1757 reg_ec4 = result[i][6]; 1475 reg_ec4 = result[i][6];
1476 reg_ecc = result[i][7];
1758 } 1477 }
1759 if (final_candidate != 0xff) { 1478 if (final_candidate != 0xff) {
1760 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; 1479 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1761 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1]; 1480 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1762 reg_ea4 = result[final_candidate][2]; 1481 reg_ea4 = result[final_candidate][2];
1482 reg_eac = result[final_candidate][3];
1763 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4]; 1483 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1764 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5]; 1484 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1765 reg_ec4 = result[final_candidate][6]; 1485 reg_ec4 = result[final_candidate][6];
1766 patha_ok = pathb_ok = true; 1486 reg_ecc = result[final_candidate][7];
1487 b_patha_ok = true;
1488 b_pathb_ok = true;
1767 } else { 1489 } else {
1768 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; 1490 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1769 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; 1491 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1770 } 1492 }
1771 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ 1493 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1772 _rtl92c_phy_path_a_fill_iqk_matrix(hw, patha_ok, result, 1494 _rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1773 final_candidate, 1495 final_candidate,
1774 (reg_ea4 == 0)); 1496 (reg_ea4 == 0));
1775 if (IS_92C_SERIAL(rtlhal->version)) { 1497 if (IS_92C_SERIAL(rtlhal->version)) {
1776 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */ 1498 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1777 _rtl92c_phy_path_b_fill_iqk_matrix(hw, pathb_ok, 1499 _rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
1778 result, 1500 result,
1779 final_candidate, 1501 final_candidate,
1780 (reg_ec4 == 0)); 1502 (reg_ec4 == 0));
@@ -1788,10 +1510,7 @@ void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1788{ 1510{
1789 struct rtl_priv *rtlpriv = rtl_priv(hw); 1511 struct rtl_priv *rtlpriv = rtl_priv(hw);
1790 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1512 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1791 bool start_conttx = false, singletone = false;
1792 1513
1793 if (start_conttx || singletone)
1794 return;
1795 if (IS_92C_SERIAL(rtlhal->version)) 1514 if (IS_92C_SERIAL(rtlhal->version))
1796 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true); 1515 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1797 else 1516 else
@@ -1833,22 +1552,22 @@ bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1833 1552
1834 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1553 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1835 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 1554 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1836 iotype, rtlphy->set_io_inprogress); 1555 iotype, rtlphy->set_io_inprogress);
1837 do { 1556 do {
1838 switch (iotype) { 1557 switch (iotype) {
1839 case IO_CMD_RESUME_DM_BY_SCAN: 1558 case IO_CMD_RESUME_DM_BY_SCAN:
1840 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1559 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1841 "[IO CMD] Resume DM after scan\n"); 1560 "[IO CMD] Resume DM after scan.\n");
1842 postprocessing = true; 1561 postprocessing = true;
1843 break; 1562 break;
1844 case IO_CMD_PAUSE_DM_BY_SCAN: 1563 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1845 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1564 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1846 "[IO CMD] Pause DM before scan\n"); 1565 "[IO CMD] Pause DM before scan.\n");
1847 postprocessing = true; 1566 postprocessing = true;
1848 break; 1567 break;
1849 default: 1568 default:
1850 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1569 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1851 "switch case not processed\n"); 1570 "switch case not process\n");
1852 break; 1571 break;
1853 } 1572 }
1854 } while (false); 1573 } while (false);
@@ -1859,7 +1578,7 @@ bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1859 return false; 1578 return false;
1860 } 1579 }
1861 rtl92c_phy_set_io(hw); 1580 rtl92c_phy_set_io(hw);
1862 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); 1581 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1863 return true; 1582 return true;
1864} 1583}
1865EXPORT_SYMBOL(rtl92c_phy_set_io_cmd); 1584EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
@@ -1868,30 +1587,30 @@ void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1868{ 1587{
1869 struct rtl_priv *rtlpriv = rtl_priv(hw); 1588 struct rtl_priv *rtlpriv = rtl_priv(hw);
1870 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1589 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1871 struct dig_t dm_digtable = rtlpriv->dm_digtable; 1590 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1872 1591
1873 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1592 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1874 "--->Cmd(%#x), set_io_inprogress(%d)\n", 1593 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1875 rtlphy->current_io_type, rtlphy->set_io_inprogress); 1594 rtlphy->current_io_type, rtlphy->set_io_inprogress);
1876 switch (rtlphy->current_io_type) { 1595 switch (rtlphy->current_io_type) {
1877 case IO_CMD_RESUME_DM_BY_SCAN: 1596 case IO_CMD_RESUME_DM_BY_SCAN:
1878 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1; 1597 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1879 rtl92c_dm_write_dig(hw); 1598 rtl92c_dm_write_dig(hw);
1880 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); 1599 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1881 break; 1600 break;
1882 case IO_CMD_PAUSE_DM_BY_SCAN: 1601 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1883 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue; 1602 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1884 dm_digtable.cur_igvalue = 0x37; 1603 dm_digtable->cur_igvalue = 0x17;
1885 rtl92c_dm_write_dig(hw); 1604 rtl92c_dm_write_dig(hw);
1886 break; 1605 break;
1887 default: 1606 default:
1888 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1607 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1889 "switch case not processed\n"); 1608 "switch case not process\n");
1890 break; 1609 break;
1891 } 1610 }
1892 rtlphy->set_io_inprogress = false; 1611 rtlphy->set_io_inprogress = false;
1893 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", 1612 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1894 rtlphy->current_io_type); 1613 "(%#x)\n", rtlphy->current_io_type);
1895} 1614}
1896EXPORT_SYMBOL(rtl92c_phy_set_io); 1615EXPORT_SYMBOL(rtl92c_phy_set_io);
1897 1616
@@ -1931,7 +1650,7 @@ void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
1931 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 1650 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1932 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1651 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1933 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 1652 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1934 "Switch RF timeout !!!\n"); 1653 "Switch RF timeout !!!.\n");
1935 return; 1654 return;
1936 } 1655 }
1937 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1656 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 07:41:57 -0500