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path: root/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
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Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c2049
1 files changed, 2049 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
new file mode 100644
index 000000000000..3728abc4df59
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
@@ -0,0 +1,2049 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30/* Define macro to shorten lines */
31#define MCS_TXPWR mcs_txpwrlevel_origoffset
32
33static u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
34 enum radio_path rfpath, u32 offset);
35static void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
36 enum radio_path rfpath, u32 offset,
37 u32 data);
38static u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
39 enum radio_path rfpath, u32 offset);
40static void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
41 enum radio_path rfpath, u32 offset,
42 u32 data);
43static u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
44static bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
45static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
46static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
47 u8 configtype);
48static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
49 u8 configtype);
50static void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
51static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
52 u32 cmdtableidx, u32 cmdtablesz,
53 enum swchnlcmd_id cmdid, u32 para1,
54 u32 para2, u32 msdelay);
55static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
56 u8 channel, u8 *stage, u8 *step,
57 u32 *delay);
58static u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
59 enum wireless_mode wirelessmode,
60 long power_indbm);
61static bool _rtl92c_phy_config_rf_external_pa(struct ieee80211_hw *hw,
62 enum radio_path rfpath);
63static long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
64 enum wireless_mode wirelessmode,
65 u8 txpwridx);
66static void _rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
67
68u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
69{
70 struct rtl_priv *rtlpriv = rtl_priv(hw);
71 u32 returnvalue, originalvalue, bitshift;
72
73 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
74 "bitmask(%#x)\n", regaddr,
75 bitmask));
76 originalvalue = rtl_read_dword(rtlpriv, regaddr);
77 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
78 returnvalue = (originalvalue & bitmask) >> bitshift;
79
80 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
81 "Addr[0x%x]=0x%x\n", bitmask,
82 regaddr, originalvalue));
83
84 return returnvalue;
85
86}
87
88void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
89 u32 regaddr, u32 bitmask, u32 data)
90{
91 struct rtl_priv *rtlpriv = rtl_priv(hw);
92 u32 originalvalue, bitshift;
93
94 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
95 " data(%#x)\n", regaddr, bitmask,
96 data));
97
98 if (bitmask != MASKDWORD) {
99 originalvalue = rtl_read_dword(rtlpriv, regaddr);
100 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
101 data = ((originalvalue & (~bitmask)) | (data << bitshift));
102 }
103
104 rtl_write_dword(rtlpriv, regaddr, data);
105
106 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
107 " data(%#x)\n", regaddr, bitmask,
108 data));
109
110}
111
112static u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
113 enum radio_path rfpath, u32 offset)
114{
115 RT_ASSERT(false, ("deprecated!\n"));
116 return 0;
117}
118
119static void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
120 enum radio_path rfpath, u32 offset,
121 u32 data)
122{
123 RT_ASSERT(false, ("deprecated!\n"));
124}
125
126static u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
127 enum radio_path rfpath, u32 offset)
128{
129 struct rtl_priv *rtlpriv = rtl_priv(hw);
130 struct rtl_phy *rtlphy = &(rtlpriv->phy);
131 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
132 u32 newoffset;
133 u32 tmplong, tmplong2;
134 u8 rfpi_enable = 0;
135 u32 retvalue;
136
137 offset &= 0x3f;
138 newoffset = offset;
139 if (RT_CANNOT_IO(hw)) {
140 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("return all one\n"));
141 return 0xFFFFFFFF;
142 }
143 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
144 if (rfpath == RF90_PATH_A)
145 tmplong2 = tmplong;
146 else
147 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
148 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
149 (newoffset << 23) | BLSSIREADEDGE;
150 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
151 tmplong & (~BLSSIREADEDGE));
152 mdelay(1);
153 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
154 mdelay(1);
155 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
156 tmplong | BLSSIREADEDGE);
157 mdelay(1);
158 if (rfpath == RF90_PATH_A)
159 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
160 BIT(8));
161 else if (rfpath == RF90_PATH_B)
162 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
163 BIT(8));
164 if (rfpi_enable)
165 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
166 BLSSIREADBACKDATA);
167 else
168 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
169 BLSSIREADBACKDATA);
170 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
171 rfpath, pphyreg->rflssi_readback,
172 retvalue));
173 return retvalue;
174}
175
176static void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
177 enum radio_path rfpath, u32 offset,
178 u32 data)
179{
180 u32 data_and_addr;
181 u32 newoffset;
182 struct rtl_priv *rtlpriv = rtl_priv(hw);
183 struct rtl_phy *rtlphy = &(rtlpriv->phy);
184 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
185
186 if (RT_CANNOT_IO(hw)) {
187 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("stop\n"));
188 return;
189 }
190 offset &= 0x3f;
191 newoffset = offset;
192 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
193 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
194 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
195 rfpath, pphyreg->rf3wire_offset,
196 data_and_addr));
197}
198
199static u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
200{
201 u32 i;
202
203 for (i = 0; i <= 31; i++) {
204 if (((bitmask >> i) & 0x1) == 1)
205 break;
206 }
207 return i;
208}
209
210static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
211{
212 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
213 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
214 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
215 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
216 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
217 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
218 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
219 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
220 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
221 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
222}
223bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
224{
225 return rtl92c_phy_rf6052_config(hw);
226}
227
228static bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
229{
230 struct rtl_priv *rtlpriv = rtl_priv(hw);
231 struct rtl_phy *rtlphy = &(rtlpriv->phy);
232 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
233 bool rtstatus;
234
235 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
236 rtstatus = _rtl92c_phy_config_bb_with_headerfile(hw,
237 BASEBAND_CONFIG_PHY_REG);
238 if (rtstatus != true) {
239 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
240 return false;
241 }
242 if (rtlphy->rf_type == RF_1T2R) {
243 _rtl92c_phy_bb_config_1t(hw);
244 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
245 }
246 if (rtlefuse->autoload_failflag == false) {
247 rtlphy->pwrgroup_cnt = 0;
248 rtstatus = _rtl92c_phy_config_bb_with_pgheaderfile(hw,
249 BASEBAND_CONFIG_PHY_REG);
250 }
251 if (rtstatus != true) {
252 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
253 return false;
254 }
255 rtstatus = _rtl92c_phy_config_bb_with_headerfile(hw,
256 BASEBAND_CONFIG_AGC_TAB);
257 if (rtstatus != true) {
258 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
259 return false;
260 }
261 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
262 RFPGA0_XA_HSSIPARAMETER2,
263 0x200));
264 return true;
265}
266
267
268void rtl92c_phy_config_bb_external_pa(struct ieee80211_hw *hw)
269{
270}
271
272static void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
273 u32 regaddr, u32 bitmask,
274 u32 data)
275{
276 struct rtl_priv *rtlpriv = rtl_priv(hw);
277 struct rtl_phy *rtlphy = &(rtlpriv->phy);
278
279 if (regaddr == RTXAGC_A_RATE18_06) {
280 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0] = data;
281 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
282 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
283 rtlphy->pwrgroup_cnt,
284 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0]));
285 }
286 if (regaddr == RTXAGC_A_RATE54_24) {
287 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1] = data;
288 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
289 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
290 rtlphy->pwrgroup_cnt,
291 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1]));
292 }
293 if (regaddr == RTXAGC_A_CCK1_MCS32) {
294 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6] = data;
295 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
296 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
297 rtlphy->pwrgroup_cnt,
298 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6]));
299 }
300 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
301 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7] = data;
302 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
303 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
304 rtlphy->pwrgroup_cnt,
305 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7]));
306 }
307 if (regaddr == RTXAGC_A_MCS03_MCS00) {
308 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2] = data;
309 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
310 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
311 rtlphy->pwrgroup_cnt,
312 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2]));
313 }
314 if (regaddr == RTXAGC_A_MCS07_MCS04) {
315 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3] = data;
316 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
317 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
318 rtlphy->pwrgroup_cnt,
319 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3]));
320 }
321 if (regaddr == RTXAGC_A_MCS11_MCS08) {
322 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4] = data;
323 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
324 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
325 rtlphy->pwrgroup_cnt,
326 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4]));
327 }
328 if (regaddr == RTXAGC_A_MCS15_MCS12) {
329 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5] = data;
330 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
331 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
332 rtlphy->pwrgroup_cnt,
333 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5]));
334 }
335 if (regaddr == RTXAGC_B_RATE18_06) {
336 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8] = data;
337 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
338 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
339 rtlphy->pwrgroup_cnt,
340 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8]));
341 }
342 if (regaddr == RTXAGC_B_RATE54_24) {
343 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9] = data;
344
345 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
346 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
347 rtlphy->pwrgroup_cnt,
348 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9]));
349 }
350
351 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
352 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14] = data;
353
354 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
355 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
356 rtlphy->pwrgroup_cnt,
357 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14]));
358 }
359
360 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
361 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15] = data;
362
363 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
364 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
365 rtlphy->pwrgroup_cnt,
366 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15]));
367 }
368
369 if (regaddr == RTXAGC_B_MCS03_MCS00) {
370 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10] = data;
371
372 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
373 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
374 rtlphy->pwrgroup_cnt,
375 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10]));
376 }
377
378 if (regaddr == RTXAGC_B_MCS07_MCS04) {
379 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11] = data;
380
381 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
382 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
383 rtlphy->pwrgroup_cnt,
384 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11]));
385 }
386
387 if (regaddr == RTXAGC_B_MCS11_MCS08) {
388 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12] = data;
389
390 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
391 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
392 rtlphy->pwrgroup_cnt,
393 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12]));
394 }
395
396 if (regaddr == RTXAGC_B_MCS15_MCS12) {
397 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13] = data;
398
399 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
400 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
401 rtlphy->pwrgroup_cnt,
402 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13]));
403
404 rtlphy->pwrgroup_cnt++;
405 }
406}
407
408static bool _rtl92c_phy_config_rf_external_pa(struct ieee80211_hw *hw,
409 enum radio_path rfpath)
410{
411 return true;
412}
413
414void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
415{
416 struct rtl_priv *rtlpriv = rtl_priv(hw);
417 struct rtl_phy *rtlphy = &(rtlpriv->phy);
418
419 rtlphy->default_initialgain[0] =
420 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
421 rtlphy->default_initialgain[1] =
422 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
423 rtlphy->default_initialgain[2] =
424 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
425 rtlphy->default_initialgain[3] =
426 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
427
428 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
429 ("Default initial gain (c50=0x%x, "
430 "c58=0x%x, c60=0x%x, c68=0x%x\n",
431 rtlphy->default_initialgain[0],
432 rtlphy->default_initialgain[1],
433 rtlphy->default_initialgain[2],
434 rtlphy->default_initialgain[3]));
435
436 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
437 ROFDM0_RXDETECTOR3, MASKBYTE0);
438 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
439 ROFDM0_RXDETECTOR2, MASKDWORD);
440
441 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
442 ("Default framesync (0x%x) = 0x%x\n",
443 ROFDM0_RXDETECTOR3, rtlphy->framesync));
444}
445
446static void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
447{
448 struct rtl_priv *rtlpriv = rtl_priv(hw);
449 struct rtl_phy *rtlphy = &(rtlpriv->phy);
450
451 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
452 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
453 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
454 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
455
456 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
457 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
458 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
459 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
460
461 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
462 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
463
464 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
465 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
466
467 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
468 RFPGA0_XA_LSSIPARAMETER;
469 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
470 RFPGA0_XB_LSSIPARAMETER;
471
472 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
473 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
474 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
475 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
476
477 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
478 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
479 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
480 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
481
482 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
483 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
484
485 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
486 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
487
488 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
489 RFPGA0_XAB_SWITCHCONTROL;
490 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
491 RFPGA0_XAB_SWITCHCONTROL;
492 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
493 RFPGA0_XCD_SWITCHCONTROL;
494 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
495 RFPGA0_XCD_SWITCHCONTROL;
496
497 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
498 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
499 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
500 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
501
502 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
503 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
504 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
505 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
506
507 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
508 ROFDM0_XARXIQIMBALANCE;
509 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
510 ROFDM0_XBRXIQIMBALANCE;
511 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
512 ROFDM0_XCRXIQIMBANLANCE;
513 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
514 ROFDM0_XDRXIQIMBALANCE;
515
516 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
517 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
518 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
519 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
520
521 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
522 ROFDM0_XATXIQIMBALANCE;
523 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
524 ROFDM0_XBTXIQIMBALANCE;
525 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
526 ROFDM0_XCTXIQIMBALANCE;
527 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
528 ROFDM0_XDTXIQIMBALANCE;
529
530 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
531 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
532 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
533 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
534
535 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
536 RFPGA0_XA_LSSIREADBACK;
537 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
538 RFPGA0_XB_LSSIREADBACK;
539 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
540 RFPGA0_XC_LSSIREADBACK;
541 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
542 RFPGA0_XD_LSSIREADBACK;
543
544 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
545 TRANSCEIVEA_HSPI_READBACK;
546 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
547 TRANSCEIVEB_HSPI_READBACK;
548
549}
550
551void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
552{
553 struct rtl_priv *rtlpriv = rtl_priv(hw);
554 struct rtl_phy *rtlphy = &(rtlpriv->phy);
555 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
556 u8 txpwr_level;
557 long txpwr_dbm;
558
559 txpwr_level = rtlphy->cur_cck_txpwridx;
560 txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw,
561 WIRELESS_MODE_B, txpwr_level);
562 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
563 rtlefuse->legacy_ht_txpowerdiff;
564 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
565 WIRELESS_MODE_G,
566 txpwr_level) > txpwr_dbm)
567 txpwr_dbm =
568 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
569 txpwr_level);
570 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
571 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
572 WIRELESS_MODE_N_24G,
573 txpwr_level) > txpwr_dbm)
574 txpwr_dbm =
575 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
576 txpwr_level);
577 *powerlevel = txpwr_dbm;
578}
579
580static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
581 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
582{
583 struct rtl_priv *rtlpriv = rtl_priv(hw);
584 struct rtl_phy *rtlphy = &(rtlpriv->phy);
585 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
586 u8 index = (channel - 1);
587
588 cckpowerlevel[RF90_PATH_A] =
589 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
590 cckpowerlevel[RF90_PATH_B] =
591 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
592 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
593 ofdmpowerlevel[RF90_PATH_A] =
594 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
595 ofdmpowerlevel[RF90_PATH_B] =
596 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
597 } else if (get_rf_type(rtlphy) == RF_2T2R) {
598 ofdmpowerlevel[RF90_PATH_A] =
599 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
600 ofdmpowerlevel[RF90_PATH_B] =
601 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
602 }
603}
604
605static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
606 u8 channel, u8 *cckpowerlevel,
607 u8 *ofdmpowerlevel)
608{
609 struct rtl_priv *rtlpriv = rtl_priv(hw);
610 struct rtl_phy *rtlphy = &(rtlpriv->phy);
611
612 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
613 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
614}
615
616void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
617{
618 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
619 u8 cckpowerlevel[2], ofdmpowerlevel[2];
620
621 if (rtlefuse->txpwr_fromeprom == false)
622 return;
623 _rtl92c_get_txpower_index(hw, channel,
624 &cckpowerlevel[0], &ofdmpowerlevel[0]);
625 _rtl92c_ccxpower_index_check(hw,
626 channel, &cckpowerlevel[0],
627 &ofdmpowerlevel[0]);
628 rtl92c_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
629 rtl92c_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
630}
631
632bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
633{
634 struct rtl_priv *rtlpriv = rtl_priv(hw);
635 struct rtl_phy *rtlphy = &(rtlpriv->phy);
636 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
637 u8 idx;
638 u8 rf_path;
639
640 u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
641 WIRELESS_MODE_B,
642 power_indbm);
643 u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
644 WIRELESS_MODE_N_24G,
645 power_indbm);
646 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
647 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
648 else
649 ofdmtxpwridx = 0;
650 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
651 ("%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
652 power_indbm, ccktxpwridx, ofdmtxpwridx));
653 for (idx = 0; idx < 14; idx++) {
654 for (rf_path = 0; rf_path < 2; rf_path++) {
655 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
656 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
657 ofdmtxpwridx;
658 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
659 ofdmtxpwridx;
660 }
661 }
662 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
663 return true;
664}
665
666void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval)
667{
668}
669
670static u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
671 enum wireless_mode wirelessmode,
672 long power_indbm)
673{
674 u8 txpwridx;
675 long offset;
676
677 switch (wirelessmode) {
678 case WIRELESS_MODE_B:
679 offset = -7;
680 break;
681 case WIRELESS_MODE_G:
682 case WIRELESS_MODE_N_24G:
683 offset = -8;
684 break;
685 default:
686 offset = -8;
687 break;
688 }
689
690 if ((power_indbm - offset) > 0)
691 txpwridx = (u8) ((power_indbm - offset) * 2);
692 else
693 txpwridx = 0;
694
695 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
696 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
697
698 return txpwridx;
699}
700
701static long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
702 enum wireless_mode wirelessmode,
703 u8 txpwridx)
704{
705 long offset;
706 long pwrout_dbm;
707
708 switch (wirelessmode) {
709 case WIRELESS_MODE_B:
710 offset = -7;
711 break;
712 case WIRELESS_MODE_G:
713 case WIRELESS_MODE_N_24G:
714 offset = -8;
715 break;
716 default:
717 offset = -8;
718 break;
719 }
720 pwrout_dbm = txpwridx / 2 + offset;
721 return pwrout_dbm;
722}
723
724void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
725{
726 struct rtl_priv *rtlpriv = rtl_priv(hw);
727 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
728 enum io_type iotype;
729
730 if (!is_hal_stop(rtlhal)) {
731 switch (operation) {
732 case SCAN_OPT_BACKUP:
733 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
734 rtlpriv->cfg->ops->set_hw_reg(hw,
735 HW_VAR_IO_CMD,
736 (u8 *)&iotype);
737
738 break;
739 case SCAN_OPT_RESTORE:
740 iotype = IO_CMD_RESUME_DM_BY_SCAN;
741 rtlpriv->cfg->ops->set_hw_reg(hw,
742 HW_VAR_IO_CMD,
743 (u8 *)&iotype);
744 break;
745 default:
746 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
747 ("Unknown Scan Backup operation.\n"));
748 break;
749 }
750 }
751}
752
753void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
754 enum nl80211_channel_type ch_type)
755{
756 struct rtl_priv *rtlpriv = rtl_priv(hw);
757 struct rtl_phy *rtlphy = &(rtlpriv->phy);
758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
759 u8 tmp_bw = rtlphy->current_chan_bw;
760
761 if (rtlphy->set_bwmode_inprogress)
762 return;
763 rtlphy->set_bwmode_inprogress = true;
764 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
765 rtl92c_phy_set_bw_mode_callback(hw);
766 else {
767 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
768 ("FALSE driver sleep or unload\n"));
769 rtlphy->set_bwmode_inprogress = false;
770 rtlphy->current_chan_bw = tmp_bw;
771 }
772}
773
774void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
775{
776 struct rtl_priv *rtlpriv = rtl_priv(hw);
777 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
778 struct rtl_phy *rtlphy = &(rtlpriv->phy);
779 u32 delay;
780
781 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
782 ("switch to channel%d\n", rtlphy->current_channel));
783 if (is_hal_stop(rtlhal))
784 return;
785 do {
786 if (!rtlphy->sw_chnl_inprogress)
787 break;
788 if (!_rtl92c_phy_sw_chnl_step_by_step
789 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
790 &rtlphy->sw_chnl_step, &delay)) {
791 if (delay > 0)
792 mdelay(delay);
793 else
794 continue;
795 } else
796 rtlphy->sw_chnl_inprogress = false;
797 break;
798 } while (true);
799 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
800}
801
802u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
803{
804 struct rtl_priv *rtlpriv = rtl_priv(hw);
805 struct rtl_phy *rtlphy = &(rtlpriv->phy);
806 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
807
808 if (rtlphy->sw_chnl_inprogress)
809 return 0;
810 if (rtlphy->set_bwmode_inprogress)
811 return 0;
812 RT_ASSERT((rtlphy->current_channel <= 14),
813 ("WIRELESS_MODE_G but channel>14"));
814 rtlphy->sw_chnl_inprogress = true;
815 rtlphy->sw_chnl_stage = 0;
816 rtlphy->sw_chnl_step = 0;
817 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
818 rtl92c_phy_sw_chnl_callback(hw);
819 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
820 ("sw_chnl_inprogress false schdule workitem\n"));
821 rtlphy->sw_chnl_inprogress = false;
822 } else {
823 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
824 ("sw_chnl_inprogress false driver sleep or"
825 " unload\n"));
826 rtlphy->sw_chnl_inprogress = false;
827 }
828 return 1;
829}
830
831static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
832 u8 channel, u8 *stage, u8 *step,
833 u32 *delay)
834{
835 struct rtl_priv *rtlpriv = rtl_priv(hw);
836 struct rtl_phy *rtlphy = &(rtlpriv->phy);
837 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
838 u32 precommoncmdcnt;
839 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
840 u32 postcommoncmdcnt;
841 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
842 u32 rfdependcmdcnt;
843 struct swchnlcmd *currentcmd = NULL;
844 u8 rfpath;
845 u8 num_total_rfpath = rtlphy->num_total_rfpath;
846
847 precommoncmdcnt = 0;
848 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
849 MAX_PRECMD_CNT,
850 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
851 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
852 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
853
854 postcommoncmdcnt = 0;
855
856 _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
857 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
858
859 rfdependcmdcnt = 0;
860
861 RT_ASSERT((channel >= 1 && channel <= 14),
862 ("illegal channel for Zebra: %d\n", channel));
863
864 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
865 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
866 RF_CHNLBW, channel, 10);
867
868 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
869 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
870 0);
871
872 do {
873 switch (*stage) {
874 case 0:
875 currentcmd = &precommoncmd[*step];
876 break;
877 case 1:
878 currentcmd = &rfdependcmd[*step];
879 break;
880 case 2:
881 currentcmd = &postcommoncmd[*step];
882 break;
883 }
884
885 if (currentcmd->cmdid == CMDID_END) {
886 if ((*stage) == 2) {
887 return true;
888 } else {
889 (*stage)++;
890 (*step) = 0;
891 continue;
892 }
893 }
894
895 switch (currentcmd->cmdid) {
896 case CMDID_SET_TXPOWEROWER_LEVEL:
897 rtl92c_phy_set_txpower_level(hw, channel);
898 break;
899 case CMDID_WRITEPORT_ULONG:
900 rtl_write_dword(rtlpriv, currentcmd->para1,
901 currentcmd->para2);
902 break;
903 case CMDID_WRITEPORT_USHORT:
904 rtl_write_word(rtlpriv, currentcmd->para1,
905 (u16) currentcmd->para2);
906 break;
907 case CMDID_WRITEPORT_UCHAR:
908 rtl_write_byte(rtlpriv, currentcmd->para1,
909 (u8) currentcmd->para2);
910 break;
911 case CMDID_RF_WRITEREG:
912 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
913 rtlphy->rfreg_chnlval[rfpath] =
914 ((rtlphy->rfreg_chnlval[rfpath] &
915 0xfffffc00) | currentcmd->para2);
916
917 rtl_set_rfreg(hw, (enum radio_path)rfpath,
918 currentcmd->para1,
919 RFREG_OFFSET_MASK,
920 rtlphy->rfreg_chnlval[rfpath]);
921 }
922 break;
923 default:
924 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
925 ("switch case not process\n"));
926 break;
927 }
928
929 break;
930 } while (true);
931
932 (*delay) = currentcmd->msdelay;
933 (*step)++;
934 return false;
935}
936
937static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
938 u32 cmdtableidx, u32 cmdtablesz,
939 enum swchnlcmd_id cmdid,
940 u32 para1, u32 para2, u32 msdelay)
941{
942 struct swchnlcmd *pcmd;
943
944 if (cmdtable == NULL) {
945 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
946 return false;
947 }
948
949 if (cmdtableidx >= cmdtablesz)
950 return false;
951
952 pcmd = cmdtable + cmdtableidx;
953 pcmd->cmdid = cmdid;
954 pcmd->para1 = para1;
955 pcmd->para2 = para2;
956 pcmd->msdelay = msdelay;
957 return true;
958}
959
960bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
961{
962 return true;
963}
964
965static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
966{
967 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
968 u8 result = 0x00;
969
970 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
971 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
972 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
973 rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
974 config_pathb ? 0x28160202 : 0x28160502);
975
976 if (config_pathb) {
977 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
978 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
979 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
980 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
981 }
982
983 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
984 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
985 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
986
987 mdelay(IQK_DELAY_TIME);
988
989 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
990 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
991 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
992 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
993
994 if (!(reg_eac & BIT(28)) &&
995 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
996 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
997 result |= 0x01;
998 else
999 return result;
1000
1001 if (!(reg_eac & BIT(27)) &&
1002 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1003 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1004 result |= 0x02;
1005 return result;
1006}
1007
1008static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
1009{
1010 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1011 u8 result = 0x00;
1012
1013 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1014 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1015 mdelay(IQK_DELAY_TIME);
1016 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1017 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1018 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1019 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1020 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1021 if (!(reg_eac & BIT(31)) &&
1022 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1023 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1024 result |= 0x01;
1025 else
1026 return result;
1027
1028 if (!(reg_eac & BIT(30)) &&
1029 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1030 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1031 result |= 0x02;
1032 return result;
1033}
1034
1035static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1036 bool iqk_ok, long result[][8],
1037 u8 final_candidate, bool btxonly)
1038{
1039 u32 oldval_0, x, tx0_a, reg;
1040 long y, tx0_c;
1041
1042 if (final_candidate == 0xFF)
1043 return;
1044 else if (iqk_ok) {
1045 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1046 MASKDWORD) >> 22) & 0x3FF;
1047 x = result[final_candidate][0];
1048 if ((x & 0x00000200) != 0)
1049 x = x | 0xFFFFFC00;
1050 tx0_a = (x * oldval_0) >> 8;
1051 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1052 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1053 ((x * oldval_0 >> 7) & 0x1));
1054 y = result[final_candidate][1];
1055 if ((y & 0x00000200) != 0)
1056 y = y | 0xFFFFFC00;
1057 tx0_c = (y * oldval_0) >> 8;
1058 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1059 ((tx0_c & 0x3C0) >> 6));
1060 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1061 (tx0_c & 0x3F));
1062 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1063 ((y * oldval_0 >> 7) & 0x1));
1064 if (btxonly)
1065 return;
1066 reg = result[final_candidate][2];
1067 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1068 reg = result[final_candidate][3] & 0x3F;
1069 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1070 reg = (result[final_candidate][3] >> 6) & 0xF;
1071 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1072 }
1073}
1074
1075static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1076 bool iqk_ok, long result[][8],
1077 u8 final_candidate, bool btxonly)
1078{
1079 u32 oldval_1, x, tx1_a, reg;
1080 long y, tx1_c;
1081
1082 if (final_candidate == 0xFF)
1083 return;
1084 else if (iqk_ok) {
1085 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1086 MASKDWORD) >> 22) & 0x3FF;
1087 x = result[final_candidate][4];
1088 if ((x & 0x00000200) != 0)
1089 x = x | 0xFFFFFC00;
1090 tx1_a = (x * oldval_1) >> 8;
1091 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1092 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1093 ((x * oldval_1 >> 7) & 0x1));
1094 y = result[final_candidate][5];
1095 if ((y & 0x00000200) != 0)
1096 y = y | 0xFFFFFC00;
1097 tx1_c = (y * oldval_1) >> 8;
1098 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1099 ((tx1_c & 0x3C0) >> 6));
1100 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1101 (tx1_c & 0x3F));
1102 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1103 ((y * oldval_1 >> 7) & 0x1));
1104 if (btxonly)
1105 return;
1106 reg = result[final_candidate][6];
1107 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1108 reg = result[final_candidate][7] & 0x3F;
1109 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1110 reg = (result[final_candidate][7] >> 6) & 0xF;
1111 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1112 }
1113}
1114
1115static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1116 u32 *addareg, u32 *addabackup,
1117 u32 registernum)
1118{
1119 u32 i;
1120
1121 for (i = 0; i < registernum; i++)
1122 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1123}
1124
1125static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1126 u32 *macreg, u32 *macbackup)
1127{
1128 struct rtl_priv *rtlpriv = rtl_priv(hw);
1129 u32 i;
1130
1131 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1132 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1133 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1134}
1135
1136static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1137 u32 *addareg, u32 *addabackup,
1138 u32 regiesternum)
1139{
1140 u32 i;
1141
1142 for (i = 0; i < regiesternum; i++)
1143 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1144}
1145
1146static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1147 u32 *macreg, u32 *macbackup)
1148{
1149 struct rtl_priv *rtlpriv = rtl_priv(hw);
1150 u32 i;
1151
1152 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1153 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1154 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1155}
1156
1157static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1158 u32 *addareg, bool is_patha_on, bool is2t)
1159{
1160 u32 pathOn;
1161 u32 i;
1162
1163 pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1164 if (false == is2t) {
1165 pathOn = 0x0bdb25a0;
1166 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1167 } else {
1168 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1169 }
1170
1171 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1172 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1173}
1174
1175static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1176 u32 *macreg, u32 *macbackup)
1177{
1178 struct rtl_priv *rtlpriv = rtl_priv(hw);
1179 u32 i;
1180
1181 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1182
1183 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1184 rtl_write_byte(rtlpriv, macreg[i],
1185 (u8) (macbackup[i] & (~BIT(3))));
1186 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1187}
1188
1189static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1190{
1191 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1192 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1193 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1194}
1195
1196static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1197{
1198 u32 mode;
1199
1200 mode = pi_mode ? 0x01000100 : 0x01000000;
1201 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1202 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1203}
1204
1205static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1206 long result[][8], u8 c1, u8 c2)
1207{
1208 u32 i, j, diff, simularity_bitmap, bound;
1209 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1210
1211 u8 final_candidate[2] = { 0xFF, 0xFF };
1212 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1213
1214 if (is2t)
1215 bound = 8;
1216 else
1217 bound = 4;
1218
1219 simularity_bitmap = 0;
1220
1221 for (i = 0; i < bound; i++) {
1222 diff = (result[c1][i] > result[c2][i]) ?
1223 (result[c1][i] - result[c2][i]) :
1224 (result[c2][i] - result[c1][i]);
1225
1226 if (diff > MAX_TOLERANCE) {
1227 if ((i == 2 || i == 6) && !simularity_bitmap) {
1228 if (result[c1][i] + result[c1][i + 1] == 0)
1229 final_candidate[(i / 4)] = c2;
1230 else if (result[c2][i] + result[c2][i + 1] == 0)
1231 final_candidate[(i / 4)] = c1;
1232 else
1233 simularity_bitmap = simularity_bitmap |
1234 (1 << i);
1235 } else
1236 simularity_bitmap =
1237 simularity_bitmap | (1 << i);
1238 }
1239 }
1240
1241 if (simularity_bitmap == 0) {
1242 for (i = 0; i < (bound / 4); i++) {
1243 if (final_candidate[i] != 0xFF) {
1244 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1245 result[3][j] =
1246 result[final_candidate[i]][j];
1247 bresult = false;
1248 }
1249 }
1250 return bresult;
1251 } else if (!(simularity_bitmap & 0x0F)) {
1252 for (i = 0; i < 4; i++)
1253 result[3][i] = result[c1][i];
1254 return false;
1255 } else if (!(simularity_bitmap & 0xF0) && is2t) {
1256 for (i = 4; i < 8; i++)
1257 result[3][i] = result[c1][i];
1258 return false;
1259 } else {
1260 return false;
1261 }
1262
1263}
1264
1265static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1266 long result[][8], u8 t, bool is2t)
1267{
1268 struct rtl_priv *rtlpriv = rtl_priv(hw);
1269 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1270 u32 i;
1271 u8 patha_ok, pathb_ok;
1272 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1273 0x85c, 0xe6c, 0xe70, 0xe74,
1274 0xe78, 0xe7c, 0xe80, 0xe84,
1275 0xe88, 0xe8c, 0xed0, 0xed4,
1276 0xed8, 0xedc, 0xee0, 0xeec
1277 };
1278
1279 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1280 0x522, 0x550, 0x551, 0x040
1281 };
1282
1283 const u32 retrycount = 2;
1284
1285 u32 bbvalue;
1286
1287 if (t == 0) {
1288 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1289
1290 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1291 rtlphy->adda_backup, 16);
1292 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1293 rtlphy->iqk_mac_backup);
1294 }
1295 _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1296 if (t == 0) {
1297 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1298 RFPGA0_XA_HSSIPARAMETER1,
1299 BIT(8));
1300 }
1301 if (!rtlphy->rfpi_enable)
1302 _rtl92c_phy_pi_mode_switch(hw, true);
1303 if (t == 0) {
1304 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1305 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1306 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1307 }
1308 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1309 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1310 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1311 if (is2t) {
1312 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1313 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1314 }
1315 _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1316 rtlphy->iqk_mac_backup);
1317 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1318 if (is2t)
1319 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1320 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1321 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1322 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1323 for (i = 0; i < retrycount; i++) {
1324 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1325 if (patha_ok == 0x03) {
1326 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1327 0x3FF0000) >> 16;
1328 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1329 0x3FF0000) >> 16;
1330 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1331 0x3FF0000) >> 16;
1332 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1333 0x3FF0000) >> 16;
1334 break;
1335 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1336 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1337 MASKDWORD) & 0x3FF0000) >>
1338 16;
1339 result[t][1] =
1340 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1341
1342 }
1343
1344 if (is2t) {
1345 _rtl92c_phy_path_a_standby(hw);
1346 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1347 for (i = 0; i < retrycount; i++) {
1348 pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1349 if (pathb_ok == 0x03) {
1350 result[t][4] = (rtl_get_bbreg(hw,
1351 0xeb4,
1352 MASKDWORD) &
1353 0x3FF0000) >> 16;
1354 result[t][5] =
1355 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1356 0x3FF0000) >> 16;
1357 result[t][6] =
1358 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1359 0x3FF0000) >> 16;
1360 result[t][7] =
1361 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1362 0x3FF0000) >> 16;
1363 break;
1364 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1365 result[t][4] = (rtl_get_bbreg(hw,
1366 0xeb4,
1367 MASKDWORD) &
1368 0x3FF0000) >> 16;
1369 }
1370 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1371 0x3FF0000) >> 16;
1372 }
1373 }
1374 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1375 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1376 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1377 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1378 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1379 if (is2t)
1380 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1381 if (t != 0) {
1382 if (!rtlphy->rfpi_enable)
1383 _rtl92c_phy_pi_mode_switch(hw, false);
1384 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1385 rtlphy->adda_backup, 16);
1386 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1387 rtlphy->iqk_mac_backup);
1388 }
1389}
1390
1391static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1392 char delta, bool is2t)
1393{
1394 /* This routine is deliberately dummied out for later fixes */
1395#if 0
1396 struct rtl_priv *rtlpriv = rtl_priv(hw);
1397 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1398 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1399
1400 u32 reg_d[PATH_NUM];
1401 u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
1402
1403 u32 bb_backup[APK_BB_REG_NUM];
1404 u32 bb_reg[APK_BB_REG_NUM] = {
1405 0x904, 0xc04, 0x800, 0xc08, 0x874
1406 };
1407 u32 bb_ap_mode[APK_BB_REG_NUM] = {
1408 0x00000020, 0x00a05430, 0x02040000,
1409 0x000800e4, 0x00204000
1410 };
1411 u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
1412 0x00000020, 0x00a05430, 0x02040000,
1413 0x000800e4, 0x22204000
1414 };
1415
1416 u32 afe_backup[APK_AFE_REG_NUM];
1417 u32 afe_reg[APK_AFE_REG_NUM] = {
1418 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
1419 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
1420 0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
1421 0xeec
1422 };
1423
1424 u32 mac_backup[IQK_MAC_REG_NUM];
1425 u32 mac_reg[IQK_MAC_REG_NUM] = {
1426 0x522, 0x550, 0x551, 0x040
1427 };
1428
1429 u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1430 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1431 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1432 };
1433
1434 u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1435 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
1436 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1437 };
1438
1439 u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1440 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1441 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1442 };
1443
1444 u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1445 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
1446 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1447 };
1448
1449 u32 afe_on_off[PATH_NUM] = {
1450 0x04db25a4, 0x0b1b25a4
1451 };
1452
1453 u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
1454
1455 u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
1456
1457 u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
1458
1459 u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
1460
1461 const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
1462 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1463 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1464 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1465 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1466 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1467 };
1468
1469 const u32 apk_normal_setting_value_1[13] = {
1470 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1471 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1472 0x12680000, 0x00880000, 0x00880000
1473 };
1474
1475 const u32 apk_normal_setting_value_2[16] = {
1476 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1477 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1478 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1479 0x00050006
1480 };
1481
1482 const u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
1483
1484 long bb_offset, delta_v, delta_offset;
1485
1486 if (!is2t)
1487 pathbound = 1;
1488
1489 for (index = 0; index < PATH_NUM; index++) {
1490 apk_offset[index] = apk_normal_offset[index];
1491 apk_value[index] = apk_normal_value[index];
1492 afe_on_off[index] = 0x6fdb25a4;
1493 }
1494
1495 for (index = 0; index < APK_BB_REG_NUM; index++) {
1496 for (path = 0; path < pathbound; path++) {
1497 apk_rf_init_value[path][index] =
1498 apk_normal_rf_init_value[path][index];
1499 apk_rf_value_0[path][index] =
1500 apk_normal_rf_value_0[path][index];
1501 }
1502 bb_ap_mode[index] = bb_normal_ap_mode[index];
1503
1504 apkbound = 6;
1505 }
1506
1507 for (index = 0; index < APK_BB_REG_NUM; index++) {
1508 if (index == 0)
1509 continue;
1510 bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
1511 }
1512
1513 _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
1514
1515 _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
1516
1517 for (path = 0; path < pathbound; path++) {
1518 if (path == RF90_PATH_A) {
1519 offset = 0xb00;
1520 for (index = 0; index < 11; index++) {
1521 rtl_set_bbreg(hw, offset, MASKDWORD,
1522 apk_normal_setting_value_1
1523 [index]);
1524
1525 offset += 0x04;
1526 }
1527
1528 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1529
1530 offset = 0xb68;
1531 for (; index < 13; index++) {
1532 rtl_set_bbreg(hw, offset, MASKDWORD,
1533 apk_normal_setting_value_1
1534 [index]);
1535
1536 offset += 0x04;
1537 }
1538
1539 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1540
1541 offset = 0xb00;
1542 for (index = 0; index < 16; index++) {
1543 rtl_set_bbreg(hw, offset, MASKDWORD,
1544 apk_normal_setting_value_2
1545 [index]);
1546
1547 offset += 0x04;
1548 }
1549 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1550 } else if (path == RF90_PATH_B) {
1551 offset = 0xb70;
1552 for (index = 0; index < 10; index++) {
1553 rtl_set_bbreg(hw, offset, MASKDWORD,
1554 apk_normal_setting_value_1
1555 [index]);
1556
1557 offset += 0x04;
1558 }
1559 rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
1560 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1561
1562 offset = 0xb68;
1563 index = 11;
1564 for (; index < 13; index++) {
1565 rtl_set_bbreg(hw, offset, MASKDWORD,
1566 apk_normal_setting_value_1
1567 [index]);
1568
1569 offset += 0x04;
1570 }
1571
1572 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1573
1574 offset = 0xb60;
1575 for (index = 0; index < 16; index++) {
1576 rtl_set_bbreg(hw, offset, MASKDWORD,
1577 apk_normal_setting_value_2
1578 [index]);
1579
1580 offset += 0x04;
1581 }
1582 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1583 }
1584
1585 reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
1586 0xd, MASKDWORD);
1587
1588 for (index = 0; index < APK_AFE_REG_NUM; index++)
1589 rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
1590 afe_on_off[path]);
1591
1592 if (path == RF90_PATH_A) {
1593 for (index = 0; index < APK_BB_REG_NUM; index++) {
1594 if (index == 0)
1595 continue;
1596 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
1597 bb_ap_mode[index]);
1598 }
1599 }
1600
1601 _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
1602
1603 if (path == 0) {
1604 rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
1605 } else {
1606 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
1607 0x10000);
1608 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1609 0x1000f);
1610 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1611 0x20103);
1612 }
1613
1614 delta_offset = ((delta + 14) / 2);
1615 if (delta_offset < 0)
1616 delta_offset = 0;
1617 else if (delta_offset > 12)
1618 delta_offset = 12;
1619
1620 for (index = 0; index < APK_BB_REG_NUM; index++) {
1621 if (index != 1)
1622 continue;
1623
1624 tmpreg = apk_rf_init_value[path][index];
1625
1626 if (!rtlefuse->apk_thermalmeterignore) {
1627 bb_offset = (tmpreg & 0xF0000) >> 16;
1628
1629 if (!(tmpreg & BIT(15)))
1630 bb_offset = -bb_offset;
1631
1632 delta_v =
1633 apk_delta_mapping[index][delta_offset];
1634
1635 bb_offset += delta_v;
1636
1637 if (bb_offset < 0) {
1638 tmpreg = tmpreg & (~BIT(15));
1639 bb_offset = -bb_offset;
1640 } else {
1641 tmpreg = tmpreg | BIT(15);
1642 }
1643
1644 tmpreg =
1645 (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
1646 }
1647
1648 rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
1649 MASKDWORD, 0x8992e);
1650 rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
1651 MASKDWORD, apk_rf_value_0[path][index]);
1652 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1653 MASKDWORD, tmpreg);
1654
1655 i = 0;
1656 do {
1657 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
1658 rtl_set_bbreg(hw, apk_offset[path],
1659 MASKDWORD, apk_value[0]);
1660 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1661 ("PHY_APCalibrate() offset 0x%x "
1662 "value 0x%x\n",
1663 apk_offset[path],
1664 rtl_get_bbreg(hw, apk_offset[path],
1665 MASKDWORD)));
1666
1667 mdelay(3);
1668
1669 rtl_set_bbreg(hw, apk_offset[path],
1670 MASKDWORD, apk_value[1]);
1671 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1672 ("PHY_APCalibrate() offset 0x%x "
1673 "value 0x%x\n",
1674 apk_offset[path],
1675 rtl_get_bbreg(hw, apk_offset[path],
1676 MASKDWORD)));
1677
1678 mdelay(20);
1679
1680 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1681
1682 if (path == RF90_PATH_A)
1683 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1684 0x03E00000);
1685 else
1686 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1687 0xF8000000);
1688
1689 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1690 ("PHY_APCalibrate() offset "
1691 "0xbd8[25:21] %x\n", tmpreg));
1692
1693 i++;
1694
1695 } while (tmpreg > apkbound && i < 4);
1696
1697 apk_result[path][index] = tmpreg;
1698 }
1699 }
1700
1701 _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
1702
1703 for (index = 0; index < APK_BB_REG_NUM; index++) {
1704 if (index == 0)
1705 continue;
1706 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
1707 }
1708
1709 _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
1710
1711 for (path = 0; path < pathbound; path++) {
1712 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1713 MASKDWORD, reg_d[path]);
1714
1715 if (path == RF90_PATH_B) {
1716 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1717 0x1000f);
1718 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1719 0x20101);
1720 }
1721
1722 if (apk_result[path][1] > 6)
1723 apk_result[path][1] = 6;
1724 }
1725
1726 for (path = 0; path < pathbound; path++) {
1727 rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
1728 ((apk_result[path][1] << 15) |
1729 (apk_result[path][1] << 10) |
1730 (apk_result[path][1] << 5) |
1731 apk_result[path][1]));
1732
1733 if (path == RF90_PATH_A)
1734 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1735 ((apk_result[path][1] << 15) |
1736 (apk_result[path][1] << 10) |
1737 (0x00 << 5) | 0x05));
1738 else
1739 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1740 ((apk_result[path][1] << 15) |
1741 (apk_result[path][1] << 10) |
1742 (0x02 << 5) | 0x05));
1743
1744 rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
1745 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
1746 0x08));
1747
1748 }
1749
1750 rtlphy->apk_done = true;
1751#endif
1752}
1753
1754static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1755 bool bmain, bool is2t)
1756{
1757 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1758
1759 if (is_hal_stop(rtlhal)) {
1760 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1761 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1762 }
1763 if (is2t) {
1764 if (bmain)
1765 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1766 BIT(5) | BIT(6), 0x1);
1767 else
1768 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1769 BIT(5) | BIT(6), 0x2);
1770 } else {
1771 if (bmain)
1772 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1773 else
1774 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1775
1776 }
1777}
1778
1779#undef IQK_ADDA_REG_NUM
1780#undef IQK_DELAY_TIME
1781
1782void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1783{
1784 struct rtl_priv *rtlpriv = rtl_priv(hw);
1785 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1786 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1787
1788 long result[4][8];
1789 u8 i, final_candidate;
1790 bool patha_ok, pathb_ok;
1791 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1792 reg_ecc, reg_tmp = 0;
1793 bool is12simular, is13simular, is23simular;
1794 bool start_conttx = false, singletone = false;
1795 u32 iqk_bb_reg[10] = {
1796 ROFDM0_XARXIQIMBALANCE,
1797 ROFDM0_XBRXIQIMBALANCE,
1798 ROFDM0_ECCATHRESHOLD,
1799 ROFDM0_AGCRSSITABLE,
1800 ROFDM0_XATXIQIMBALANCE,
1801 ROFDM0_XBTXIQIMBALANCE,
1802 ROFDM0_XCTXIQIMBALANCE,
1803 ROFDM0_XCTXAFE,
1804 ROFDM0_XDTXAFE,
1805 ROFDM0_RXIQEXTANTA
1806 };
1807
1808 if (recovery) {
1809 _rtl92c_phy_reload_adda_registers(hw,
1810 iqk_bb_reg,
1811 rtlphy->iqk_bb_backup, 10);
1812 return;
1813 }
1814 if (start_conttx || singletone)
1815 return;
1816 for (i = 0; i < 8; i++) {
1817 result[0][i] = 0;
1818 result[1][i] = 0;
1819 result[2][i] = 0;
1820 result[3][i] = 0;
1821 }
1822 final_candidate = 0xff;
1823 patha_ok = false;
1824 pathb_ok = false;
1825 is12simular = false;
1826 is23simular = false;
1827 is13simular = false;
1828 for (i = 0; i < 3; i++) {
1829 if (IS_92C_SERIAL(rtlhal->version))
1830 _rtl92c_phy_iq_calibrate(hw, result, i, true);
1831 else
1832 _rtl92c_phy_iq_calibrate(hw, result, i, false);
1833 if (i == 1) {
1834 is12simular = _rtl92c_phy_simularity_compare(hw,
1835 result, 0,
1836 1);
1837 if (is12simular) {
1838 final_candidate = 0;
1839 break;
1840 }
1841 }
1842 if (i == 2) {
1843 is13simular = _rtl92c_phy_simularity_compare(hw,
1844 result, 0,
1845 2);
1846 if (is13simular) {
1847 final_candidate = 0;
1848 break;
1849 }
1850 is23simular = _rtl92c_phy_simularity_compare(hw,
1851 result, 1,
1852 2);
1853 if (is23simular)
1854 final_candidate = 1;
1855 else {
1856 for (i = 0; i < 8; i++)
1857 reg_tmp += result[3][i];
1858
1859 if (reg_tmp != 0)
1860 final_candidate = 3;
1861 else
1862 final_candidate = 0xFF;
1863 }
1864 }
1865 }
1866 for (i = 0; i < 4; i++) {
1867 reg_e94 = result[i][0];
1868 reg_e9c = result[i][1];
1869 reg_ea4 = result[i][2];
1870 reg_eac = result[i][3];
1871 reg_eb4 = result[i][4];
1872 reg_ebc = result[i][5];
1873 reg_ec4 = result[i][6];
1874 reg_ecc = result[i][7];
1875 }
1876 if (final_candidate != 0xff) {
1877 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1878 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1879 reg_ea4 = result[final_candidate][2];
1880 reg_eac = result[final_candidate][3];
1881 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1882 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1883 reg_ec4 = result[final_candidate][6];
1884 reg_ecc = result[final_candidate][7];
1885 patha_ok = pathb_ok = true;
1886 } else {
1887 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1888 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1889 }
1890 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1891 _rtl92c_phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
1892 final_candidate,
1893 (reg_ea4 == 0));
1894 if (IS_92C_SERIAL(rtlhal->version)) {
1895 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1896 _rtl92c_phy_path_b_fill_iqk_matrix(hw, pathb_ok,
1897 result,
1898 final_candidate,
1899 (reg_ec4 == 0));
1900 }
1901 _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1902 rtlphy->iqk_bb_backup, 10);
1903}
1904
1905void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1906{
1907 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1908 bool start_conttx = false, singletone = false;
1909
1910 if (start_conttx || singletone)
1911 return;
1912 if (IS_92C_SERIAL(rtlhal->version))
1913 _rtl92c_phy_lc_calibrate(hw, true);
1914 else
1915 _rtl92c_phy_lc_calibrate(hw, false);
1916}
1917
1918void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
1919{
1920 struct rtl_priv *rtlpriv = rtl_priv(hw);
1921 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1923
1924 if (rtlphy->apk_done)
1925 return;
1926 if (IS_92C_SERIAL(rtlhal->version))
1927 _rtl92c_phy_ap_calibrate(hw, delta, true);
1928 else
1929 _rtl92c_phy_ap_calibrate(hw, delta, false);
1930}
1931
1932void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1933{
1934 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1935
1936 if (IS_92C_SERIAL(rtlhal->version))
1937 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1938 else
1939 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1940}
1941
1942bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1943{
1944 struct rtl_priv *rtlpriv = rtl_priv(hw);
1945 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1946 bool postprocessing = false;
1947
1948 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1949 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1950 iotype, rtlphy->set_io_inprogress));
1951 do {
1952 switch (iotype) {
1953 case IO_CMD_RESUME_DM_BY_SCAN:
1954 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1955 ("[IO CMD] Resume DM after scan.\n"));
1956 postprocessing = true;
1957 break;
1958 case IO_CMD_PAUSE_DM_BY_SCAN:
1959 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1960 ("[IO CMD] Pause DM before scan.\n"));
1961 postprocessing = true;
1962 break;
1963 default:
1964 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1965 ("switch case not process\n"));
1966 break;
1967 }
1968 } while (false);
1969 if (postprocessing && !rtlphy->set_io_inprogress) {
1970 rtlphy->set_io_inprogress = true;
1971 rtlphy->current_io_type = iotype;
1972 } else {
1973 return false;
1974 }
1975 rtl92c_phy_set_io(hw);
1976 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
1977 return true;
1978}
1979
1980void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1981{
1982 struct rtl_priv *rtlpriv = rtl_priv(hw);
1983 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1984
1985 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1986 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
1987 rtlphy->current_io_type, rtlphy->set_io_inprogress));
1988 switch (rtlphy->current_io_type) {
1989 case IO_CMD_RESUME_DM_BY_SCAN:
1990 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1991 rtl92c_dm_write_dig(hw);
1992 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1993 break;
1994 case IO_CMD_PAUSE_DM_BY_SCAN:
1995 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
1996 dm_digtable.cur_igvalue = 0x17;
1997 rtl92c_dm_write_dig(hw);
1998 break;
1999 default:
2000 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2001 ("switch case not process\n"));
2002 break;
2003 }
2004 rtlphy->set_io_inprogress = false;
2005 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2006 ("<---(%#x)\n", rtlphy->current_io_type));
2007}
2008
2009void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
2010{
2011 struct rtl_priv *rtlpriv = rtl_priv(hw);
2012
2013 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2014 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2015 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2016 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2017 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2018 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2019}
2020
2021static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
2022{
2023 u32 u4b_tmp;
2024 u8 delay = 5;
2025 struct rtl_priv *rtlpriv = rtl_priv(hw);
2026
2027 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2028 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2029 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2030 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2031 while (u4b_tmp != 0 && delay > 0) {
2032 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
2033 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2034 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2035 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2036 delay--;
2037 }
2038 if (delay == 0) {
2039 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2040 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2041 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2042 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2043 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
2044 ("Switch RF timeout !!!.\n"));
2045 return;
2046 }
2047 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2048 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2049}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 18:31:57 -0400