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path: root/drivers/net/wireless/rtlwifi/pci.c
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-rw-r--r--drivers/net/wireless/rtlwifi/pci.c2071
1 files changed, 2071 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
new file mode 100644
index 000000000000..254b64ba4bf6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -0,0 +1,2071 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "core.h"
31#include "wifi.h"
32#include "pci.h"
33#include "base.h"
34#include "ps.h"
35#include "efuse.h"
36
37static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38 INTEL_VENDOR_ID,
39 ATI_VENDOR_ID,
40 AMD_VENDOR_ID,
41 SIS_VENDOR_ID
42};
43
44static const u8 ac_to_hwq[] = {
45 VO_QUEUE,
46 VI_QUEUE,
47 BE_QUEUE,
48 BK_QUEUE
49};
50
51static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
52 struct sk_buff *skb)
53{
54 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
55 __le16 fc = rtl_get_fc(skb);
56 u8 queue_index = skb_get_queue_mapping(skb);
57
58 if (unlikely(ieee80211_is_beacon(fc)))
59 return BEACON_QUEUE;
60 if (ieee80211_is_mgmt(fc))
61 return MGNT_QUEUE;
62 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
63 if (ieee80211_is_nullfunc(fc))
64 return HIGH_QUEUE;
65
66 return ac_to_hwq[queue_index];
67}
68
69/* Update PCI dependent default settings*/
70static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
71{
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
74 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
77 u8 init_aspm;
78
79 ppsc->reg_rfps_level = 0;
80 ppsc->support_aspm = 0;
81
82 /*Update PCI ASPM setting */
83 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
84 switch (rtlpci->const_pci_aspm) {
85 case 0:
86 /*No ASPM */
87 break;
88
89 case 1:
90 /*ASPM dynamically enabled/disable. */
91 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
92 break;
93
94 case 2:
95 /*ASPM with Clock Req dynamically enabled/disable. */
96 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
97 RT_RF_OFF_LEVL_CLK_REQ);
98 break;
99
100 case 3:
101 /*
102 * Always enable ASPM and Clock Req
103 * from initialization to halt.
104 * */
105 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
106 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
107 RT_RF_OFF_LEVL_CLK_REQ);
108 break;
109
110 case 4:
111 /*
112 * Always enable ASPM without Clock Req
113 * from initialization to halt.
114 * */
115 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
116 RT_RF_OFF_LEVL_CLK_REQ);
117 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
118 break;
119 }
120
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122
123 /*Update Radio OFF setting */
124 switch (rtlpci->const_hwsw_rfoff_d3) {
125 case 1:
126 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
128 break;
129
130 case 2:
131 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
132 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
134 break;
135
136 case 3:
137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
138 break;
139 }
140
141 /*Set HW definition to determine if it supports ASPM. */
142 switch (rtlpci->const_support_pciaspm) {
143 case 0:{
144 /*Not support ASPM. */
145 bool support_aspm = false;
146 ppsc->support_aspm = support_aspm;
147 break;
148 }
149 case 1:{
150 /*Support ASPM. */
151 bool support_aspm = true;
152 bool support_backdoor = true;
153 ppsc->support_aspm = support_aspm;
154
155 /*if (priv->oem_id == RT_CID_TOSHIBA &&
156 !priv->ndis_adapter.amd_l1_patch)
157 support_backdoor = false; */
158
159 ppsc->support_backdoor = support_backdoor;
160
161 break;
162 }
163 case 2:
164 /*ASPM value set by chipset. */
165 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
166 bool support_aspm = true;
167 ppsc->support_aspm = support_aspm;
168 }
169 break;
170 default:
171 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
172 ("switch case not process\n"));
173 break;
174 }
175
176 /* toshiba aspm issue, toshiba will set aspm selfly
177 * so we should not set aspm in driver */
178 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
179 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
180 init_aspm == 0x43)
181 ppsc->support_aspm = false;
182}
183
184static bool _rtl_pci_platform_switch_device_pci_aspm(
185 struct ieee80211_hw *hw,
186 u8 value)
187{
188 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
190
191 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
192 value |= 0x40;
193
194 pci_write_config_byte(rtlpci->pdev, 0x80, value);
195
196 return false;
197}
198
199/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
200static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
201{
202 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
203 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
204
205 pci_write_config_byte(rtlpci->pdev, 0x81, value);
206
207 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
208 udelay(100);
209
210 return true;
211}
212
213/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
214static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
215{
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
221 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
222 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
223 /*Retrieve original configuration settings. */
224 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
225 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
226 pcibridge_linkctrlreg;
227 u16 aspmlevel = 0;
228 u8 tmp_u1b = 0;
229
230 if (!ppsc->support_aspm)
231 return;
232
233 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
234 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
235 ("PCI(Bridge) UNKNOWN.\n"));
236
237 return;
238 }
239
240 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
241 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
242 _rtl_pci_switch_clk_req(hw, 0x0);
243 }
244
245 /*for promising device will in L0 state after an I/O. */
246 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
247
248 /*Set corresponding value. */
249 aspmlevel |= BIT(0) | BIT(1);
250 linkctrl_reg &= ~aspmlevel;
251 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
252
253 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
254 udelay(50);
255
256 /*4 Disable Pci Bridge ASPM */
257 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
258 pcicfg_addrport + (num4bytes << 2));
259 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
260
261 udelay(50);
262}
263
264/*
265 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
266 *power saving We should follow the sequence to enable
267 *RTL8192SE first then enable Pci Bridge ASPM
268 *or the system will show bluescreen.
269 */
270static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
271{
272 struct rtl_priv *rtlpriv = rtl_priv(hw);
273 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
274 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
275 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
276 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
277 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
278 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
279 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
280 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
281 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
282 u16 aspmlevel;
283 u8 u_pcibridge_aspmsetting;
284 u8 u_device_aspmsetting;
285
286 if (!ppsc->support_aspm)
287 return;
288
289 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
290 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
291 ("PCI(Bridge) UNKNOWN.\n"));
292 return;
293 }
294
295 /*4 Enable Pci Bridge ASPM */
296 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
297 pcicfg_addrport + (num4bytes << 2));
298
299 u_pcibridge_aspmsetting =
300 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
301 rtlpci->const_hostpci_aspm_setting;
302
303 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
304 u_pcibridge_aspmsetting &= ~BIT(0);
305
306 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
307
308 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
309 ("PlatformEnableASPM():PciBridge busnumber[%x], "
310 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
311 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
312 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
313 u_pcibridge_aspmsetting));
314
315 udelay(50);
316
317 /*Get ASPM level (with/without Clock Req) */
318 aspmlevel = rtlpci->const_devicepci_aspm_setting;
319 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
320
321 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
322 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
323
324 u_device_aspmsetting |= aspmlevel;
325
326 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
327
328 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
329 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
330 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
331 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
332 }
333 udelay(100);
334}
335
336static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
337{
338 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
339 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
340
341 bool status = false;
342 u8 offset_e0;
343 unsigned offset_e4;
344
345 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
346 pcicfg_addrport + 0xE0);
347 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
348
349 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
350 pcicfg_addrport + 0xE0);
351 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
352
353 if (offset_e0 == 0xA0) {
354 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
355 pcicfg_addrport + 0xE4);
356 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
357 if (offset_e4 & BIT(23))
358 status = true;
359 }
360
361 return status;
362}
363
364static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
365{
366 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
367 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
368 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
369 u8 linkctrl_reg;
370 u8 num4bbytes;
371
372 num4bbytes = (capabilityoffset + 0x10) / 4;
373
374 /*Read Link Control Register */
375 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
376 pcicfg_addrport + (num4bbytes << 2));
377 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
378
379 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
380}
381
382static void rtl_pci_parse_configuration(struct pci_dev *pdev,
383 struct ieee80211_hw *hw)
384{
385 struct rtl_priv *rtlpriv = rtl_priv(hw);
386 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
387
388 u8 tmp;
389 int pos;
390 u8 linkctrl_reg;
391
392 /*Link Control Register */
393 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
394 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
395 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
396
397 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
398 ("Link Control Register =%x\n",
399 pcipriv->ndis_adapter.linkctrl_reg));
400
401 pci_read_config_byte(pdev, 0x98, &tmp);
402 tmp |= BIT(4);
403 pci_write_config_byte(pdev, 0x98, tmp);
404
405 tmp = 0x17;
406 pci_write_config_byte(pdev, 0x70f, tmp);
407}
408
409static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
410{
411 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
412
413 _rtl_pci_update_default_setting(hw);
414
415 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
416 /*Always enable ASPM & Clock Req. */
417 rtl_pci_enable_aspm(hw);
418 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
419 }
420
421}
422
423static void _rtl_pci_io_handler_init(struct device *dev,
424 struct ieee80211_hw *hw)
425{
426 struct rtl_priv *rtlpriv = rtl_priv(hw);
427
428 rtlpriv->io.dev = dev;
429
430 rtlpriv->io.write8_async = pci_write8_async;
431 rtlpriv->io.write16_async = pci_write16_async;
432 rtlpriv->io.write32_async = pci_write32_async;
433
434 rtlpriv->io.read8_sync = pci_read8_sync;
435 rtlpriv->io.read16_sync = pci_read16_sync;
436 rtlpriv->io.read32_sync = pci_read32_sync;
437
438}
439
440static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
441{
442}
443
444static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
445 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
446{
447 struct rtl_priv *rtlpriv = rtl_priv(hw);
448 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
449 u8 additionlen = FCS_LEN;
450 struct sk_buff *next_skb;
451
452 /* here open is 4, wep/tkip is 8, aes is 12*/
453 if (info->control.hw_key)
454 additionlen += info->control.hw_key->icv_len;
455
456 /* The most skb num is 6 */
457 tcb_desc->empkt_num = 0;
458 spin_lock_bh(&rtlpriv->locks.waitq_lock);
459 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
460 struct ieee80211_tx_info *next_info;
461
462 next_info = IEEE80211_SKB_CB(next_skb);
463 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
464 tcb_desc->empkt_len[tcb_desc->empkt_num] =
465 next_skb->len + additionlen;
466 tcb_desc->empkt_num++;
467 } else {
468 break;
469 }
470
471 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
472 next_skb))
473 break;
474
475 if (tcb_desc->empkt_num >= 5)
476 break;
477 }
478 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
479
480 return true;
481}
482
483/* just for early mode now */
484static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
485{
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
488 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
489 struct sk_buff *skb = NULL;
490 struct ieee80211_tx_info *info = NULL;
491 int tid; /* should be int */
492
493 if (!rtlpriv->rtlhal.earlymode_enable)
494 return;
495
496 /* we juse use em for BE/BK/VI/VO */
497 for (tid = 7; tid >= 0; tid--) {
498 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
499 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
500 while (!mac->act_scanning &&
501 rtlpriv->psc.rfpwr_state == ERFON) {
502 struct rtl_tcb_desc tcb_desc;
503 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
504
505 spin_lock_bh(&rtlpriv->locks.waitq_lock);
506 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
507 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
508 skb = skb_dequeue(&mac->skb_waitq[tid]);
509 } else {
510 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
511 break;
512 }
513 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
514
515 /* Some macaddr can't do early mode. like
516 * multicast/broadcast/no_qos data */
517 info = IEEE80211_SKB_CB(skb);
518 if (info->flags & IEEE80211_TX_CTL_AMPDU)
519 _rtl_update_earlymode_info(hw, skb,
520 &tcb_desc, tid);
521
522 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
523 }
524 }
525}
526
527
528static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
529{
530 struct rtl_priv *rtlpriv = rtl_priv(hw);
531 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
532
533 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
534
535 while (skb_queue_len(&ring->queue)) {
536 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
537 struct sk_buff *skb;
538 struct ieee80211_tx_info *info;
539 __le16 fc;
540 u8 tid;
541
542 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
543 HW_DESC_OWN);
544
545 /*
546 *beacon packet will only use the first
547 *descriptor defautly,and the own may not
548 *be cleared by the hardware
549 */
550 if (own)
551 return;
552 ring->idx = (ring->idx + 1) % ring->entries;
553
554 skb = __skb_dequeue(&ring->queue);
555 pci_unmap_single(rtlpci->pdev,
556 rtlpriv->cfg->ops->
557 get_desc((u8 *) entry, true,
558 HW_DESC_TXBUFF_ADDR),
559 skb->len, PCI_DMA_TODEVICE);
560
561 /* remove early mode header */
562 if (rtlpriv->rtlhal.earlymode_enable)
563 skb_pull(skb, EM_HDR_LEN);
564
565 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
566 ("new ring->idx:%d, "
567 "free: skb_queue_len:%d, free: seq:%x\n",
568 ring->idx,
569 skb_queue_len(&ring->queue),
570 *(u16 *) (skb->data + 22)));
571
572 if (prio == TXCMD_QUEUE) {
573 dev_kfree_skb(skb);
574 goto tx_status_ok;
575
576 }
577
578 /* for sw LPS, just after NULL skb send out, we can
579 * sure AP kown we are sleeped, our we should not let
580 * rf to sleep*/
581 fc = rtl_get_fc(skb);
582 if (ieee80211_is_nullfunc(fc)) {
583 if (ieee80211_has_pm(fc)) {
584 rtlpriv->mac80211.offchan_deley = true;
585 rtlpriv->psc.state_inap = 1;
586 } else {
587 rtlpriv->psc.state_inap = 0;
588 }
589 }
590
591 /* update tid tx pkt num */
592 tid = rtl_get_tid(skb);
593 if (tid <= 7)
594 rtlpriv->link_info.tidtx_inperiod[tid]++;
595
596 info = IEEE80211_SKB_CB(skb);
597 ieee80211_tx_info_clear_status(info);
598
599 info->flags |= IEEE80211_TX_STAT_ACK;
600 /*info->status.rates[0].count = 1; */
601
602 ieee80211_tx_status_irqsafe(hw, skb);
603
604 if ((ring->entries - skb_queue_len(&ring->queue))
605 == 2) {
606
607 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
608 ("more desc left, wake"
609 "skb_queue@%d,ring->idx = %d,"
610 "skb_queue_len = 0x%d\n",
611 prio, ring->idx,
612 skb_queue_len(&ring->queue)));
613
614 ieee80211_wake_queue(hw,
615 skb_get_queue_mapping
616 (skb));
617 }
618tx_status_ok:
619 skb = NULL;
620 }
621
622 if (((rtlpriv->link_info.num_rx_inperiod +
623 rtlpriv->link_info.num_tx_inperiod) > 8) ||
624 (rtlpriv->link_info.num_rx_inperiod > 2)) {
625 rtl_lps_leave(hw);
626 }
627}
628
629static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
630{
631 struct rtl_priv *rtlpriv = rtl_priv(hw);
632 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
633 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
634
635 struct ieee80211_rx_status rx_status = { 0 };
636 unsigned int count = rtlpci->rxringcount;
637 u8 own;
638 u8 tmp_one;
639 u32 bufferaddress;
640 bool unicast = false;
641
642 struct rtl_stats stats = {
643 .signal = 0,
644 .noise = -98,
645 .rate = 0,
646 };
647
648 /*RX NORMAL PKT */
649 while (count--) {
650 /*rx descriptor */
651 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
652 rtlpci->rx_ring[rx_queue_idx].idx];
653 /*rx pkt */
654 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
655 rtlpci->rx_ring[rx_queue_idx].idx];
656
657 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
658 false, HW_DESC_OWN);
659
660 if (own) {
661 /*wait data to be filled by hardware */
662 return;
663 } else {
664 struct ieee80211_hdr *hdr;
665 __le16 fc;
666 struct sk_buff *new_skb = NULL;
667
668 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
669 &rx_status,
670 (u8 *) pdesc, skb);
671
672 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
673 if (unlikely(!new_skb)) {
674 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
675 DBG_DMESG,
676 ("can't alloc skb for rx\n"));
677 goto done;
678 }
679
680 pci_unmap_single(rtlpci->pdev,
681 *((dma_addr_t *) skb->cb),
682 rtlpci->rxbuffersize,
683 PCI_DMA_FROMDEVICE);
684
685 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
686 false,
687 HW_DESC_RXPKT_LEN));
688 skb_reserve(skb,
689 stats.rx_drvinfo_size + stats.rx_bufshift);
690
691 /*
692 *NOTICE This can not be use for mac80211,
693 *this is done in mac80211 code,
694 *if you done here sec DHCP will fail
695 *skb_trim(skb, skb->len - 4);
696 */
697
698 hdr = rtl_get_hdr(skb);
699 fc = rtl_get_fc(skb);
700
701 if (!stats.crc && !stats.hwerror) {
702 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
703 sizeof(rx_status));
704
705 if (is_broadcast_ether_addr(hdr->addr1)) {
706 ;/*TODO*/
707 } else if (is_multicast_ether_addr(hdr->addr1)) {
708 ;/*TODO*/
709 } else {
710 unicast = true;
711 rtlpriv->stats.rxbytesunicast +=
712 skb->len;
713 }
714
715 rtl_is_special_data(hw, skb, false);
716
717 if (ieee80211_is_data(fc)) {
718 rtlpriv->cfg->ops->led_control(hw,
719 LED_CTL_RX);
720
721 if (unicast)
722 rtlpriv->link_info.
723 num_rx_inperiod++;
724 }
725
726 /* for sw lps */
727 rtl_swlps_beacon(hw, (void *)skb->data,
728 skb->len);
729 rtl_recognize_peer(hw, (void *)skb->data,
730 skb->len);
731 if ((rtlpriv->mac80211.opmode ==
732 NL80211_IFTYPE_AP) &&
733 (rtlpriv->rtlhal.current_bandtype ==
734 BAND_ON_2_4G) &&
735 (ieee80211_is_beacon(fc) ||
736 ieee80211_is_probe_resp(fc))) {
737 dev_kfree_skb_any(skb);
738 } else {
739 if (unlikely(!rtl_action_proc(hw, skb,
740 false))) {
741 dev_kfree_skb_any(skb);
742 } else {
743 struct sk_buff *uskb = NULL;
744 u8 *pdata;
745 uskb = dev_alloc_skb(skb->len
746 + 128);
747 memcpy(IEEE80211_SKB_RXCB(uskb),
748 &rx_status,
749 sizeof(rx_status));
750 pdata = (u8 *)skb_put(uskb,
751 skb->len);
752 memcpy(pdata, skb->data,
753 skb->len);
754 dev_kfree_skb_any(skb);
755
756 ieee80211_rx_irqsafe(hw, uskb);
757 }
758 }
759 } else {
760 dev_kfree_skb_any(skb);
761 }
762
763 if (((rtlpriv->link_info.num_rx_inperiod +
764 rtlpriv->link_info.num_tx_inperiod) > 8) ||
765 (rtlpriv->link_info.num_rx_inperiod > 2)) {
766 rtl_lps_leave(hw);
767 }
768
769 skb = new_skb;
770
771 rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
772 rx_ring
773 [rx_queue_idx].
774 idx] = skb;
775 *((dma_addr_t *) skb->cb) =
776 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
777 rtlpci->rxbuffersize,
778 PCI_DMA_FROMDEVICE);
779
780 }
781done:
782 bufferaddress = (*((dma_addr_t *)skb->cb));
783 tmp_one = 1;
784 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
785 HW_DESC_RXBUFF_ADDR,
786 (u8 *)&bufferaddress);
787 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
788 (u8 *)&tmp_one);
789 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
790 HW_DESC_RXPKT_LEN,
791 (u8 *)&rtlpci->rxbuffersize);
792
793 if (rtlpci->rx_ring[rx_queue_idx].idx ==
794 rtlpci->rxringcount - 1)
795 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
796 HW_DESC_RXERO,
797 (u8 *)&tmp_one);
798
799 rtlpci->rx_ring[rx_queue_idx].idx =
800 (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
801 rtlpci->rxringcount;
802 }
803
804}
805
806static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
807{
808 struct ieee80211_hw *hw = dev_id;
809 struct rtl_priv *rtlpriv = rtl_priv(hw);
810 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
811 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
812 unsigned long flags;
813 u32 inta = 0;
814 u32 intb = 0;
815
816 if (rtlpci->irq_enabled == 0)
817 return IRQ_HANDLED;
818
819 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
820
821 /*read ISR: 4/8bytes */
822 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
823
824 /*Shared IRQ or HW disappared */
825 if (!inta || inta == 0xffff)
826 goto done;
827
828 /*<1> beacon related */
829 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
830 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
831 ("beacon ok interrupt!\n"));
832 }
833
834 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
835 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
836 ("beacon err interrupt!\n"));
837 }
838
839 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
840 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
841 ("beacon interrupt!\n"));
842 }
843
844 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
845 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
846 ("prepare beacon for interrupt!\n"));
847 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
848 }
849
850 /*<3> Tx related */
851 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
852 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
853
854 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
855 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
856 ("Manage ok interrupt!\n"));
857 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
858 }
859
860 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
861 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
862 ("HIGH_QUEUE ok interrupt!\n"));
863 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
864 }
865
866 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
867 rtlpriv->link_info.num_tx_inperiod++;
868
869 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
870 ("BK Tx OK interrupt!\n"));
871 _rtl_pci_tx_isr(hw, BK_QUEUE);
872 }
873
874 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
875 rtlpriv->link_info.num_tx_inperiod++;
876
877 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
878 ("BE TX OK interrupt!\n"));
879 _rtl_pci_tx_isr(hw, BE_QUEUE);
880 }
881
882 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
883 rtlpriv->link_info.num_tx_inperiod++;
884
885 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
886 ("VI TX OK interrupt!\n"));
887 _rtl_pci_tx_isr(hw, VI_QUEUE);
888 }
889
890 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
891 rtlpriv->link_info.num_tx_inperiod++;
892
893 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
894 ("Vo TX OK interrupt!\n"));
895 _rtl_pci_tx_isr(hw, VO_QUEUE);
896 }
897
898 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
899 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
900 rtlpriv->link_info.num_tx_inperiod++;
901
902 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
903 ("CMD TX OK interrupt!\n"));
904 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
905 }
906 }
907
908 /*<2> Rx related */
909 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
910 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
911 _rtl_pci_rx_interrupt(hw);
912 }
913
914 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
915 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
916 ("rx descriptor unavailable!\n"));
917 _rtl_pci_rx_interrupt(hw);
918 }
919
920 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
921 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
922 _rtl_pci_rx_interrupt(hw);
923 }
924
925 if (rtlpriv->rtlhal.earlymode_enable)
926 tasklet_schedule(&rtlpriv->works.irq_tasklet);
927
928 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
929 return IRQ_HANDLED;
930
931done:
932 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
933 return IRQ_HANDLED;
934}
935
936static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
937{
938 _rtl_pci_tx_chk_waitq(hw);
939}
940
941static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
942{
943 struct rtl_priv *rtlpriv = rtl_priv(hw);
944 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
945 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
946 struct rtl8192_tx_ring *ring = NULL;
947 struct ieee80211_hdr *hdr = NULL;
948 struct ieee80211_tx_info *info = NULL;
949 struct sk_buff *pskb = NULL;
950 struct rtl_tx_desc *pdesc = NULL;
951 struct rtl_tcb_desc tcb_desc;
952 u8 temp_one = 1;
953
954 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
955 ring = &rtlpci->tx_ring[BEACON_QUEUE];
956 pskb = __skb_dequeue(&ring->queue);
957 if (pskb)
958 kfree_skb(pskb);
959
960 /*NB: the beacon data buffer must be 32-bit aligned. */
961 pskb = ieee80211_beacon_get(hw, mac->vif);
962 if (pskb == NULL)
963 return;
964 hdr = rtl_get_hdr(pskb);
965 info = IEEE80211_SKB_CB(pskb);
966 pdesc = &ring->desc[0];
967 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
968 info, pskb, BEACON_QUEUE, &tcb_desc);
969
970 __skb_queue_tail(&ring->queue, pskb);
971
972 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
973 (u8 *)&temp_one);
974
975 return;
976}
977
978static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
979{
980 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
981 u8 i;
982
983 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
984 rtlpci->txringcount[i] = RT_TXDESC_NUM;
985
986 /*
987 *we just alloc 2 desc for beacon queue,
988 *because we just need first desc in hw beacon.
989 */
990 rtlpci->txringcount[BEACON_QUEUE] = 2;
991
992 /*
993 *BE queue need more descriptor for performance
994 *consideration or, No more tx desc will happen,
995 *and may cause mac80211 mem leakage.
996 */
997 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
998
999 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1000 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1001}
1002
1003static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1004 struct pci_dev *pdev)
1005{
1006 struct rtl_priv *rtlpriv = rtl_priv(hw);
1007 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1008 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1009 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1010
1011 rtlpci->up_first_time = true;
1012 rtlpci->being_init_adapter = false;
1013
1014 rtlhal->hw = hw;
1015 rtlpci->pdev = pdev;
1016
1017 /*Tx/Rx related var */
1018 _rtl_pci_init_trx_var(hw);
1019
1020 /*IBSS*/ mac->beacon_interval = 100;
1021
1022 /*AMPDU*/
1023 mac->min_space_cfg = 0;
1024 mac->max_mss_density = 0;
1025 /*set sane AMPDU defaults */
1026 mac->current_ampdu_density = 7;
1027 mac->current_ampdu_factor = 3;
1028
1029 /*QOS*/
1030 rtlpci->acm_method = eAcmWay2_SW;
1031
1032 /*task */
1033 tasklet_init(&rtlpriv->works.irq_tasklet,
1034 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1035 (unsigned long)hw);
1036 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1037 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1038 (unsigned long)hw);
1039}
1040
1041static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1042 unsigned int prio, unsigned int entries)
1043{
1044 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1045 struct rtl_priv *rtlpriv = rtl_priv(hw);
1046 struct rtl_tx_desc *ring;
1047 dma_addr_t dma;
1048 u32 nextdescaddress;
1049 int i;
1050
1051 ring = pci_alloc_consistent(rtlpci->pdev,
1052 sizeof(*ring) * entries, &dma);
1053
1054 if (!ring || (unsigned long)ring & 0xFF) {
1055 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1056 ("Cannot allocate TX ring (prio = %d)\n", prio));
1057 return -ENOMEM;
1058 }
1059
1060 memset(ring, 0, sizeof(*ring) * entries);
1061 rtlpci->tx_ring[prio].desc = ring;
1062 rtlpci->tx_ring[prio].dma = dma;
1063 rtlpci->tx_ring[prio].idx = 0;
1064 rtlpci->tx_ring[prio].entries = entries;
1065 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1066
1067 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1068 ("queue:%d, ring_addr:%p\n", prio, ring));
1069
1070 for (i = 0; i < entries; i++) {
1071 nextdescaddress = (u32) dma +
1072 ((i + 1) % entries) *
1073 sizeof(*ring);
1074
1075 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1076 true, HW_DESC_TX_NEXTDESC_ADDR,
1077 (u8 *)&nextdescaddress);
1078 }
1079
1080 return 0;
1081}
1082
1083static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1084{
1085 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1086 struct rtl_priv *rtlpriv = rtl_priv(hw);
1087 struct rtl_rx_desc *entry = NULL;
1088 int i, rx_queue_idx;
1089 u8 tmp_one = 1;
1090
1091 /*
1092 *rx_queue_idx 0:RX_MPDU_QUEUE
1093 *rx_queue_idx 1:RX_CMD_QUEUE
1094 */
1095 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1096 rx_queue_idx++) {
1097 rtlpci->rx_ring[rx_queue_idx].desc =
1098 pci_alloc_consistent(rtlpci->pdev,
1099 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1100 desc) * rtlpci->rxringcount,
1101 &rtlpci->rx_ring[rx_queue_idx].dma);
1102
1103 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1104 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1105 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1106 ("Cannot allocate RX ring\n"));
1107 return -ENOMEM;
1108 }
1109
1110 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1111 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1112 rtlpci->rxringcount);
1113
1114 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1115
1116 /* If amsdu_8k is disabled, set buffersize to 4096. This
1117 * change will reduce memory fragmentation.
1118 */
1119 if (rtlpci->rxbuffersize > 4096 &&
1120 rtlpriv->rtlhal.disable_amsdu_8k)
1121 rtlpci->rxbuffersize = 4096;
1122
1123 for (i = 0; i < rtlpci->rxringcount; i++) {
1124 struct sk_buff *skb =
1125 dev_alloc_skb(rtlpci->rxbuffersize);
1126 u32 bufferaddress;
1127 if (!skb)
1128 return 0;
1129 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1130
1131 /*skb->dev = dev; */
1132
1133 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1134
1135 /*
1136 *just set skb->cb to mapping addr
1137 *for pci_unmap_single use
1138 */
1139 *((dma_addr_t *) skb->cb) =
1140 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1141 rtlpci->rxbuffersize,
1142 PCI_DMA_FROMDEVICE);
1143
1144 bufferaddress = (*((dma_addr_t *)skb->cb));
1145 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1146 HW_DESC_RXBUFF_ADDR,
1147 (u8 *)&bufferaddress);
1148 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1149 HW_DESC_RXPKT_LEN,
1150 (u8 *)&rtlpci->
1151 rxbuffersize);
1152 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1153 HW_DESC_RXOWN,
1154 (u8 *)&tmp_one);
1155 }
1156
1157 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1158 HW_DESC_RXERO, (u8 *)&tmp_one);
1159 }
1160 return 0;
1161}
1162
1163static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1164 unsigned int prio)
1165{
1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1167 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1168 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1169
1170 while (skb_queue_len(&ring->queue)) {
1171 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1172 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1173
1174 pci_unmap_single(rtlpci->pdev,
1175 rtlpriv->cfg->
1176 ops->get_desc((u8 *) entry, true,
1177 HW_DESC_TXBUFF_ADDR),
1178 skb->len, PCI_DMA_TODEVICE);
1179 kfree_skb(skb);
1180 ring->idx = (ring->idx + 1) % ring->entries;
1181 }
1182
1183 pci_free_consistent(rtlpci->pdev,
1184 sizeof(*ring->desc) * ring->entries,
1185 ring->desc, ring->dma);
1186 ring->desc = NULL;
1187}
1188
1189static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1190{
1191 int i, rx_queue_idx;
1192
1193 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1194 /*rx_queue_idx 1:RX_CMD_QUEUE */
1195 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1196 rx_queue_idx++) {
1197 for (i = 0; i < rtlpci->rxringcount; i++) {
1198 struct sk_buff *skb =
1199 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1200 if (!skb)
1201 continue;
1202
1203 pci_unmap_single(rtlpci->pdev,
1204 *((dma_addr_t *) skb->cb),
1205 rtlpci->rxbuffersize,
1206 PCI_DMA_FROMDEVICE);
1207 kfree_skb(skb);
1208 }
1209
1210 pci_free_consistent(rtlpci->pdev,
1211 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1212 desc) * rtlpci->rxringcount,
1213 rtlpci->rx_ring[rx_queue_idx].desc,
1214 rtlpci->rx_ring[rx_queue_idx].dma);
1215 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1216 }
1217}
1218
1219static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1220{
1221 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1222 int ret;
1223 int i;
1224
1225 ret = _rtl_pci_init_rx_ring(hw);
1226 if (ret)
1227 return ret;
1228
1229 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1230 ret = _rtl_pci_init_tx_ring(hw, i,
1231 rtlpci->txringcount[i]);
1232 if (ret)
1233 goto err_free_rings;
1234 }
1235
1236 return 0;
1237
1238err_free_rings:
1239 _rtl_pci_free_rx_ring(rtlpci);
1240
1241 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1242 if (rtlpci->tx_ring[i].desc)
1243 _rtl_pci_free_tx_ring(hw, i);
1244
1245 return 1;
1246}
1247
1248static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1249{
1250 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1251 u32 i;
1252
1253 /*free rx rings */
1254 _rtl_pci_free_rx_ring(rtlpci);
1255
1256 /*free tx rings */
1257 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1258 _rtl_pci_free_tx_ring(hw, i);
1259
1260 return 0;
1261}
1262
1263int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1264{
1265 struct rtl_priv *rtlpriv = rtl_priv(hw);
1266 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1267 int i, rx_queue_idx;
1268 unsigned long flags;
1269 u8 tmp_one = 1;
1270
1271 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1272 /*rx_queue_idx 1:RX_CMD_QUEUE */
1273 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1274 rx_queue_idx++) {
1275 /*
1276 *force the rx_ring[RX_MPDU_QUEUE/
1277 *RX_CMD_QUEUE].idx to the first one
1278 */
1279 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1280 struct rtl_rx_desc *entry = NULL;
1281
1282 for (i = 0; i < rtlpci->rxringcount; i++) {
1283 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1284 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1285 false,
1286 HW_DESC_RXOWN,
1287 (u8 *)&tmp_one);
1288 }
1289 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1290 }
1291 }
1292
1293 /*
1294 *after reset, release previous pending packet,
1295 *and force the tx idx to the first one
1296 */
1297 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1298 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1299 if (rtlpci->tx_ring[i].desc) {
1300 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1301
1302 while (skb_queue_len(&ring->queue)) {
1303 struct rtl_tx_desc *entry =
1304 &ring->desc[ring->idx];
1305 struct sk_buff *skb =
1306 __skb_dequeue(&ring->queue);
1307
1308 pci_unmap_single(rtlpci->pdev,
1309 rtlpriv->cfg->ops->
1310 get_desc((u8 *)
1311 entry,
1312 true,
1313 HW_DESC_TXBUFF_ADDR),
1314 skb->len, PCI_DMA_TODEVICE);
1315 kfree_skb(skb);
1316 ring->idx = (ring->idx + 1) % ring->entries;
1317 }
1318 ring->idx = 0;
1319 }
1320 }
1321
1322 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1323
1324 return 0;
1325}
1326
1327static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1328 struct sk_buff *skb)
1329{
1330 struct rtl_priv *rtlpriv = rtl_priv(hw);
1331 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1332 struct ieee80211_sta *sta = info->control.sta;
1333 struct rtl_sta_info *sta_entry = NULL;
1334 u8 tid = rtl_get_tid(skb);
1335
1336 if (!sta)
1337 return false;
1338 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1339
1340 if (!rtlpriv->rtlhal.earlymode_enable)
1341 return false;
1342 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1343 return false;
1344 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1345 return false;
1346 if (tid > 7)
1347 return false;
1348
1349 /* maybe every tid should be checked */
1350 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1351 return false;
1352
1353 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1354 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1355 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1356
1357 return true;
1358}
1359
1360static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1361 struct rtl_tcb_desc *ptcb_desc)
1362{
1363 struct rtl_priv *rtlpriv = rtl_priv(hw);
1364 struct rtl_sta_info *sta_entry = NULL;
1365 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1366 struct ieee80211_sta *sta = info->control.sta;
1367 struct rtl8192_tx_ring *ring;
1368 struct rtl_tx_desc *pdesc;
1369 u8 idx;
1370 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1371 unsigned long flags;
1372 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1373 __le16 fc = rtl_get_fc(skb);
1374 u8 *pda_addr = hdr->addr1;
1375 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1376 /*ssn */
1377 u8 tid = 0;
1378 u16 seq_number = 0;
1379 u8 own;
1380 u8 temp_one = 1;
1381
1382 if (ieee80211_is_auth(fc)) {
1383 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1384 rtl_ips_nic_on(hw);
1385 }
1386
1387 if (rtlpriv->psc.sw_ps_enabled) {
1388 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1389 !ieee80211_has_pm(fc))
1390 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1391 }
1392
1393 rtl_action_proc(hw, skb, true);
1394
1395 if (is_multicast_ether_addr(pda_addr))
1396 rtlpriv->stats.txbytesmulticast += skb->len;
1397 else if (is_broadcast_ether_addr(pda_addr))
1398 rtlpriv->stats.txbytesbroadcast += skb->len;
1399 else
1400 rtlpriv->stats.txbytesunicast += skb->len;
1401
1402 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1403 ring = &rtlpci->tx_ring[hw_queue];
1404 if (hw_queue != BEACON_QUEUE)
1405 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1406 ring->entries;
1407 else
1408 idx = 0;
1409
1410 pdesc = &ring->desc[idx];
1411 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1412 true, HW_DESC_OWN);
1413
1414 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1415 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1416 ("No more TX desc@%d, ring->idx = %d,"
1417 "idx = %d, skb_queue_len = 0x%d\n",
1418 hw_queue, ring->idx, idx,
1419 skb_queue_len(&ring->queue)));
1420
1421 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1422 return skb->len;
1423 }
1424
1425 if (ieee80211_is_data_qos(fc)) {
1426 tid = rtl_get_tid(skb);
1427 if (sta) {
1428 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1429 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1430 IEEE80211_SCTL_SEQ) >> 4;
1431 seq_number += 1;
1432
1433 if (!ieee80211_has_morefrags(hdr->frame_control))
1434 sta_entry->tids[tid].seq_number = seq_number;
1435 }
1436 }
1437
1438 if (ieee80211_is_data(fc))
1439 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1440
1441 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1442 info, skb, hw_queue, ptcb_desc);
1443
1444 __skb_queue_tail(&ring->queue, skb);
1445
1446 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1447 HW_DESC_OWN, (u8 *)&temp_one);
1448
1449
1450 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1451 hw_queue != BEACON_QUEUE) {
1452
1453 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1454 ("less desc left, stop skb_queue@%d, "
1455 "ring->idx = %d,"
1456 "idx = %d, skb_queue_len = 0x%d\n",
1457 hw_queue, ring->idx, idx,
1458 skb_queue_len(&ring->queue)));
1459
1460 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1461 }
1462
1463 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1464
1465 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1466
1467 return 0;
1468}
1469
1470static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1471{
1472 struct rtl_priv *rtlpriv = rtl_priv(hw);
1473 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1474 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1475 u16 i = 0;
1476 int queue_id;
1477 struct rtl8192_tx_ring *ring;
1478
1479 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1480 u32 queue_len;
1481 ring = &pcipriv->dev.tx_ring[queue_id];
1482 queue_len = skb_queue_len(&ring->queue);
1483 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1484 queue_id == TXCMD_QUEUE) {
1485 queue_id--;
1486 continue;
1487 } else {
1488 msleep(20);
1489 i++;
1490 }
1491
1492 /* we just wait 1s for all queues */
1493 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1494 is_hal_stop(rtlhal) || i >= 200)
1495 return;
1496 }
1497}
1498
1499static void rtl_pci_deinit(struct ieee80211_hw *hw)
1500{
1501 struct rtl_priv *rtlpriv = rtl_priv(hw);
1502 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1503
1504 _rtl_pci_deinit_trx_ring(hw);
1505
1506 synchronize_irq(rtlpci->pdev->irq);
1507 tasklet_kill(&rtlpriv->works.irq_tasklet);
1508
1509 flush_workqueue(rtlpriv->works.rtl_wq);
1510 destroy_workqueue(rtlpriv->works.rtl_wq);
1511
1512}
1513
1514static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1515{
1516 struct rtl_priv *rtlpriv = rtl_priv(hw);
1517 int err;
1518
1519 _rtl_pci_init_struct(hw, pdev);
1520
1521 err = _rtl_pci_init_trx_ring(hw);
1522 if (err) {
1523 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1524 ("tx ring initialization failed"));
1525 return err;
1526 }
1527
1528 return 1;
1529}
1530
1531static int rtl_pci_start(struct ieee80211_hw *hw)
1532{
1533 struct rtl_priv *rtlpriv = rtl_priv(hw);
1534 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1535 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1536 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1537
1538 int err;
1539
1540 rtl_pci_reset_trx_ring(hw);
1541
1542 rtlpci->driver_is_goingto_unload = false;
1543 err = rtlpriv->cfg->ops->hw_init(hw);
1544 if (err) {
1545 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1546 ("Failed to config hardware!\n"));
1547 return err;
1548 }
1549
1550 rtlpriv->cfg->ops->enable_interrupt(hw);
1551 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1552
1553 rtl_init_rx_config(hw);
1554
1555 /*should after adapter start and interrupt enable. */
1556 set_hal_start(rtlhal);
1557
1558 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1559
1560 rtlpci->up_first_time = false;
1561
1562 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1563 return 0;
1564}
1565
1566static void rtl_pci_stop(struct ieee80211_hw *hw)
1567{
1568 struct rtl_priv *rtlpriv = rtl_priv(hw);
1569 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1570 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1571 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1572 unsigned long flags;
1573 u8 RFInProgressTimeOut = 0;
1574
1575 /*
1576 *should before disable interrrupt&adapter
1577 *and will do it immediately.
1578 */
1579 set_hal_stop(rtlhal);
1580
1581 rtlpriv->cfg->ops->disable_interrupt(hw);
1582
1583 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1584 while (ppsc->rfchange_inprogress) {
1585 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1586 if (RFInProgressTimeOut > 100) {
1587 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1588 break;
1589 }
1590 mdelay(1);
1591 RFInProgressTimeOut++;
1592 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1593 }
1594 ppsc->rfchange_inprogress = true;
1595 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1596
1597 rtlpci->driver_is_goingto_unload = true;
1598 rtlpriv->cfg->ops->hw_disable(hw);
1599 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1600
1601 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1602 ppsc->rfchange_inprogress = false;
1603 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1604
1605 rtl_pci_enable_aspm(hw);
1606}
1607
1608static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1609 struct ieee80211_hw *hw)
1610{
1611 struct rtl_priv *rtlpriv = rtl_priv(hw);
1612 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1613 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1614 struct pci_dev *bridge_pdev = pdev->bus->self;
1615 u16 venderid;
1616 u16 deviceid;
1617 u8 revisionid;
1618 u16 irqline;
1619 u8 tmp;
1620
1621 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1622 venderid = pdev->vendor;
1623 deviceid = pdev->device;
1624 pci_read_config_byte(pdev, 0x8, &revisionid);
1625 pci_read_config_word(pdev, 0x3C, &irqline);
1626
1627 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1628 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1629 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1630 * the correct driver is r8192e_pci, thus this routine should
1631 * return false.
1632 */
1633 if (deviceid == RTL_PCI_8192SE_DID &&
1634 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1635 return false;
1636
1637 if (deviceid == RTL_PCI_8192_DID ||
1638 deviceid == RTL_PCI_0044_DID ||
1639 deviceid == RTL_PCI_0047_DID ||
1640 deviceid == RTL_PCI_8192SE_DID ||
1641 deviceid == RTL_PCI_8174_DID ||
1642 deviceid == RTL_PCI_8173_DID ||
1643 deviceid == RTL_PCI_8172_DID ||
1644 deviceid == RTL_PCI_8171_DID) {
1645 switch (revisionid) {
1646 case RTL_PCI_REVISION_ID_8192PCIE:
1647 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1648 ("8192 PCI-E is found - "
1649 "vid/did=%x/%x\n", venderid, deviceid));
1650 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1651 break;
1652 case RTL_PCI_REVISION_ID_8192SE:
1653 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1654 ("8192SE is found - "
1655 "vid/did=%x/%x\n", venderid, deviceid));
1656 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1657 break;
1658 default:
1659 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1660 ("Err: Unknown device - "
1661 "vid/did=%x/%x\n", venderid, deviceid));
1662 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1663 break;
1664
1665 }
1666 } else if (deviceid == RTL_PCI_8192CET_DID ||
1667 deviceid == RTL_PCI_8192CE_DID ||
1668 deviceid == RTL_PCI_8191CE_DID ||
1669 deviceid == RTL_PCI_8188CE_DID) {
1670 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1671 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1672 ("8192C PCI-E is found - "
1673 "vid/did=%x/%x\n", venderid, deviceid));
1674 } else if (deviceid == RTL_PCI_8192DE_DID ||
1675 deviceid == RTL_PCI_8192DE_DID2) {
1676 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1677 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1678 ("8192D PCI-E is found - "
1679 "vid/did=%x/%x\n", venderid, deviceid));
1680 } else {
1681 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1682 ("Err: Unknown device -"
1683 " vid/did=%x/%x\n", venderid, deviceid));
1684
1685 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1686 }
1687
1688 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1689 if (revisionid == 0 || revisionid == 1) {
1690 if (revisionid == 0) {
1691 RT_TRACE(rtlpriv, COMP_INIT,
1692 DBG_LOUD, ("Find 92DE MAC0.\n"));
1693 rtlhal->interfaceindex = 0;
1694 } else if (revisionid == 1) {
1695 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1696 ("Find 92DE MAC1.\n"));
1697 rtlhal->interfaceindex = 1;
1698 }
1699 } else {
1700 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1701 ("Unknown device - "
1702 "VendorID/DeviceID=%x/%x, Revision=%x\n",
1703 venderid, deviceid, revisionid));
1704 rtlhal->interfaceindex = 0;
1705 }
1706 }
1707 /*find bus info */
1708 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1709 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1710 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1711
1712 /*find bridge info */
1713 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1714 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1715 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1716 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1717 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1718 ("Pci Bridge Vendor is found index: %d\n",
1719 tmp));
1720 break;
1721 }
1722 }
1723
1724 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1725 PCI_BRIDGE_VENDOR_UNKNOWN) {
1726 pcipriv->ndis_adapter.pcibridge_busnum =
1727 bridge_pdev->bus->number;
1728 pcipriv->ndis_adapter.pcibridge_devnum =
1729 PCI_SLOT(bridge_pdev->devfn);
1730 pcipriv->ndis_adapter.pcibridge_funcnum =
1731 PCI_FUNC(bridge_pdev->devfn);
1732 pcipriv->ndis_adapter.pcicfg_addrport =
1733 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1734 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1735 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
1736 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1737 pci_pcie_cap(bridge_pdev);
1738 pcipriv->ndis_adapter.num4bytes =
1739 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1740
1741 rtl_pci_get_linkcontrol_field(hw);
1742
1743 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1744 PCI_BRIDGE_VENDOR_AMD) {
1745 pcipriv->ndis_adapter.amd_l1_patch =
1746 rtl_pci_get_amd_l1_patch(hw);
1747 }
1748 }
1749
1750 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1751 ("pcidev busnumber:devnumber:funcnumber:"
1752 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1753 pcipriv->ndis_adapter.busnumber,
1754 pcipriv->ndis_adapter.devnumber,
1755 pcipriv->ndis_adapter.funcnumber,
1756 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1757
1758 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1759 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1760 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1761 pcipriv->ndis_adapter.pcibridge_busnum,
1762 pcipriv->ndis_adapter.pcibridge_devnum,
1763 pcipriv->ndis_adapter.pcibridge_funcnum,
1764 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1765 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1766 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1767 pcipriv->ndis_adapter.amd_l1_patch));
1768
1769 rtl_pci_parse_configuration(pdev, hw);
1770
1771 return true;
1772}
1773
1774int __devinit rtl_pci_probe(struct pci_dev *pdev,
1775 const struct pci_device_id *id)
1776{
1777 struct ieee80211_hw *hw = NULL;
1778
1779 struct rtl_priv *rtlpriv = NULL;
1780 struct rtl_pci_priv *pcipriv = NULL;
1781 struct rtl_pci *rtlpci;
1782 unsigned long pmem_start, pmem_len, pmem_flags;
1783 int err;
1784
1785 err = pci_enable_device(pdev);
1786 if (err) {
1787 RT_ASSERT(false,
1788 ("%s : Cannot enable new PCI device\n",
1789 pci_name(pdev)));
1790 return err;
1791 }
1792
1793 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1794 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1795 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1796 "for consistent allocations\n"));
1797 pci_disable_device(pdev);
1798 return -ENOMEM;
1799 }
1800 }
1801
1802 pci_set_master(pdev);
1803
1804 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1805 sizeof(struct rtl_priv), &rtl_ops);
1806 if (!hw) {
1807 RT_ASSERT(false,
1808 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1809 err = -ENOMEM;
1810 goto fail1;
1811 }
1812
1813 SET_IEEE80211_DEV(hw, &pdev->dev);
1814 pci_set_drvdata(pdev, hw);
1815
1816 rtlpriv = hw->priv;
1817 pcipriv = (void *)rtlpriv->priv;
1818 pcipriv->dev.pdev = pdev;
1819
1820 /* init cfg & intf_ops */
1821 rtlpriv->rtlhal.interface = INTF_PCI;
1822 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1823 rtlpriv->intf_ops = &rtl_pci_ops;
1824
1825 /*
1826 *init dbgp flags before all
1827 *other functions, because we will
1828 *use it in other funtions like
1829 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1830 *you can not use these macro
1831 *before this
1832 */
1833 rtl_dbgp_flag_init(hw);
1834
1835 /* MEM map */
1836 err = pci_request_regions(pdev, KBUILD_MODNAME);
1837 if (err) {
1838 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1839 return err;
1840 }
1841
1842 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1843 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1844 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1845
1846 /*shared mem start */
1847 rtlpriv->io.pci_mem_start =
1848 (unsigned long)pci_iomap(pdev,
1849 rtlpriv->cfg->bar_id, pmem_len);
1850 if (rtlpriv->io.pci_mem_start == 0) {
1851 RT_ASSERT(false, ("Can't map PCI mem\n"));
1852 goto fail2;
1853 }
1854
1855 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1856 ("mem mapped space: start: 0x%08lx len:%08lx "
1857 "flags:%08lx, after map:0x%08lx\n",
1858 pmem_start, pmem_len, pmem_flags,
1859 rtlpriv->io.pci_mem_start));
1860
1861 /* Disable Clk Request */
1862 pci_write_config_byte(pdev, 0x81, 0);
1863 /* leave D3 mode */
1864 pci_write_config_byte(pdev, 0x44, 0);
1865 pci_write_config_byte(pdev, 0x04, 0x06);
1866 pci_write_config_byte(pdev, 0x04, 0x07);
1867
1868 /* find adapter */
1869 if (!_rtl_pci_find_adapter(pdev, hw))
1870 goto fail3;
1871
1872 /* Init IO handler */
1873 _rtl_pci_io_handler_init(&pdev->dev, hw);
1874
1875 /*like read eeprom and so on */
1876 rtlpriv->cfg->ops->read_eeprom_info(hw);
1877
1878 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1879 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1880 ("Can't init_sw_vars.\n"));
1881 goto fail3;
1882 }
1883
1884 rtlpriv->cfg->ops->init_sw_leds(hw);
1885
1886 /*aspm */
1887 rtl_pci_init_aspm(hw);
1888
1889 /* Init mac80211 sw */
1890 err = rtl_init_core(hw);
1891 if (err) {
1892 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1893 ("Can't allocate sw for mac80211.\n"));
1894 goto fail3;
1895 }
1896
1897 /* Init PCI sw */
1898 err = !rtl_pci_init(hw, pdev);
1899 if (err) {
1900 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1901 ("Failed to init PCI.\n"));
1902 goto fail3;
1903 }
1904
1905 err = ieee80211_register_hw(hw);
1906 if (err) {
1907 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1908 ("Can't register mac80211 hw.\n"));
1909 goto fail3;
1910 } else {
1911 rtlpriv->mac80211.mac80211_registered = 1;
1912 }
1913
1914 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1915 if (err) {
1916 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1917 ("failed to create sysfs device attributes\n"));
1918 goto fail3;
1919 }
1920
1921 /*init rfkill */
1922 rtl_init_rfkill(hw);
1923
1924 rtlpci = rtl_pcidev(pcipriv);
1925 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1926 IRQF_SHARED, KBUILD_MODNAME, hw);
1927 if (err) {
1928 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1929 ("%s: failed to register IRQ handler\n",
1930 wiphy_name(hw->wiphy)));
1931 goto fail3;
1932 } else {
1933 rtlpci->irq_alloc = 1;
1934 }
1935
1936 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1937 return 0;
1938
1939fail3:
1940 pci_set_drvdata(pdev, NULL);
1941 rtl_deinit_core(hw);
1942 _rtl_pci_io_handler_release(hw);
1943 ieee80211_free_hw(hw);
1944
1945 if (rtlpriv->io.pci_mem_start != 0)
1946 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1947
1948fail2:
1949 pci_release_regions(pdev);
1950
1951fail1:
1952
1953 pci_disable_device(pdev);
1954
1955 return -ENODEV;
1956
1957}
1958EXPORT_SYMBOL(rtl_pci_probe);
1959
1960void rtl_pci_disconnect(struct pci_dev *pdev)
1961{
1962 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1963 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1964 struct rtl_priv *rtlpriv = rtl_priv(hw);
1965 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1966 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1967
1968 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1969
1970 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1971
1972 /*ieee80211_unregister_hw will call ops_stop */
1973 if (rtlmac->mac80211_registered == 1) {
1974 ieee80211_unregister_hw(hw);
1975 rtlmac->mac80211_registered = 0;
1976 } else {
1977 rtl_deinit_deferred_work(hw);
1978 rtlpriv->intf_ops->adapter_stop(hw);
1979 }
1980
1981 /*deinit rfkill */
1982 rtl_deinit_rfkill(hw);
1983
1984 rtl_pci_deinit(hw);
1985 rtl_deinit_core(hw);
1986 _rtl_pci_io_handler_release(hw);
1987 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1988
1989 if (rtlpci->irq_alloc) {
1990 free_irq(rtlpci->pdev->irq, hw);
1991 rtlpci->irq_alloc = 0;
1992 }
1993
1994 if (rtlpriv->io.pci_mem_start != 0) {
1995 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1996 pci_release_regions(pdev);
1997 }
1998
1999 pci_disable_device(pdev);
2000
2001 rtl_pci_disable_aspm(hw);
2002
2003 pci_set_drvdata(pdev, NULL);
2004
2005 ieee80211_free_hw(hw);
2006}
2007EXPORT_SYMBOL(rtl_pci_disconnect);
2008
2009/***************************************
2010kernel pci power state define:
2011PCI_D0 ((pci_power_t __force) 0)
2012PCI_D1 ((pci_power_t __force) 1)
2013PCI_D2 ((pci_power_t __force) 2)
2014PCI_D3hot ((pci_power_t __force) 3)
2015PCI_D3cold ((pci_power_t __force) 4)
2016PCI_UNKNOWN ((pci_power_t __force) 5)
2017
2018This function is called when system
2019goes into suspend state mac80211 will
2020call rtl_mac_stop() from the mac80211
2021suspend function first, So there is
2022no need to call hw_disable here.
2023****************************************/
2024int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2025{
2026 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2027 struct rtl_priv *rtlpriv = rtl_priv(hw);
2028
2029 rtlpriv->cfg->ops->hw_suspend(hw);
2030 rtl_deinit_rfkill(hw);
2031
2032 pci_save_state(pdev);
2033 pci_disable_device(pdev);
2034 pci_set_power_state(pdev, PCI_D3hot);
2035 return 0;
2036}
2037EXPORT_SYMBOL(rtl_pci_suspend);
2038
2039int rtl_pci_resume(struct pci_dev *pdev)
2040{
2041 int ret;
2042 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2043 struct rtl_priv *rtlpriv = rtl_priv(hw);
2044
2045 pci_set_power_state(pdev, PCI_D0);
2046 ret = pci_enable_device(pdev);
2047 if (ret) {
2048 RT_ASSERT(false, ("ERR: <======\n"));
2049 return ret;
2050 }
2051
2052 pci_restore_state(pdev);
2053
2054 rtlpriv->cfg->ops->hw_resume(hw);
2055 rtl_init_rfkill(hw);
2056 return 0;
2057}
2058EXPORT_SYMBOL(rtl_pci_resume);
2059
2060struct rtl_intf_ops rtl_pci_ops = {
2061 .read_efuse_byte = read_efuse_byte,
2062 .adapter_start = rtl_pci_start,
2063 .adapter_stop = rtl_pci_stop,
2064 .adapter_tx = rtl_pci_tx,
2065 .flush = rtl_pci_flush,
2066 .reset_trx_ring = rtl_pci_reset_trx_ring,
2067 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2068
2069 .disable_aspm = rtl_pci_disable_aspm,
2070 .enable_aspm = rtl_pci_enable_aspm,
2071};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-09 18:56:32 -0400