aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/rtl818x/rtl8187/dev.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/rtl818x/rtl8187/dev.c')
-rw-r--r--drivers/net/wireless/rtl818x/rtl8187/dev.c1604
1 files changed, 1604 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtl818x/rtl8187/dev.c b/drivers/net/wireless/rtl818x/rtl8187/dev.c
new file mode 100644
index 000000000000..1e0be14d10d4
--- /dev/null
+++ b/drivers/net/wireless/rtl818x/rtl8187/dev.c
@@ -0,0 +1,1604 @@
1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
10 * The driver was extended to the RTL8187B in 2008 by:
11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/init.h>
24#include <linux/usb.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/etherdevice.h>
28#include <linux/eeprom_93cx6.h>
29#include <net/mac80211.h>
30
31#include "rtl8187.h"
32#include "rtl8225.h"
33#ifdef CONFIG_RTL8187_LEDS
34#include "leds.h"
35#endif
36#include "rfkill.h"
37
38MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
39MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
40MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
41MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
42MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
43MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
44MODULE_LICENSE("GPL");
45
46static struct usb_device_id rtl8187_table[] __devinitdata = {
47 /* Asus */
48 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
49 /* Belkin */
50 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
51 /* Realtek */
52 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
53 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
54 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
55 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
56 /* Surecom */
57 {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
58 /* Logitech */
59 {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
60 /* Netgear */
61 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
62 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
63 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
64 /* HP */
65 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
66 /* Sitecom */
67 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
68 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
69 {USB_DEVICE(0x0df6, 0x0029), .driver_info = DEVICE_RTL8187B},
70 /* Sphairon Access Systems GmbH */
71 {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
72 /* Dick Smith Electronics */
73 {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
74 /* Abocom */
75 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
76 /* Qcom */
77 {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
78 /* AirLive */
79 {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
80 /* Linksys */
81 {USB_DEVICE(0x1737, 0x0073), .driver_info = DEVICE_RTL8187B},
82 {}
83};
84
85MODULE_DEVICE_TABLE(usb, rtl8187_table);
86
87static const struct ieee80211_rate rtl818x_rates[] = {
88 { .bitrate = 10, .hw_value = 0, },
89 { .bitrate = 20, .hw_value = 1, },
90 { .bitrate = 55, .hw_value = 2, },
91 { .bitrate = 110, .hw_value = 3, },
92 { .bitrate = 60, .hw_value = 4, },
93 { .bitrate = 90, .hw_value = 5, },
94 { .bitrate = 120, .hw_value = 6, },
95 { .bitrate = 180, .hw_value = 7, },
96 { .bitrate = 240, .hw_value = 8, },
97 { .bitrate = 360, .hw_value = 9, },
98 { .bitrate = 480, .hw_value = 10, },
99 { .bitrate = 540, .hw_value = 11, },
100};
101
102static const struct ieee80211_channel rtl818x_channels[] = {
103 { .center_freq = 2412 },
104 { .center_freq = 2417 },
105 { .center_freq = 2422 },
106 { .center_freq = 2427 },
107 { .center_freq = 2432 },
108 { .center_freq = 2437 },
109 { .center_freq = 2442 },
110 { .center_freq = 2447 },
111 { .center_freq = 2452 },
112 { .center_freq = 2457 },
113 { .center_freq = 2462 },
114 { .center_freq = 2467 },
115 { .center_freq = 2472 },
116 { .center_freq = 2484 },
117};
118
119static void rtl8187_iowrite_async_cb(struct urb *urb)
120{
121 kfree(urb->context);
122}
123
124static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
125 void *data, u16 len)
126{
127 struct usb_ctrlrequest *dr;
128 struct urb *urb;
129 struct rtl8187_async_write_data {
130 u8 data[4];
131 struct usb_ctrlrequest dr;
132 } *buf;
133 int rc;
134
135 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
136 if (!buf)
137 return;
138
139 urb = usb_alloc_urb(0, GFP_ATOMIC);
140 if (!urb) {
141 kfree(buf);
142 return;
143 }
144
145 dr = &buf->dr;
146
147 dr->bRequestType = RTL8187_REQT_WRITE;
148 dr->bRequest = RTL8187_REQ_SET_REG;
149 dr->wValue = addr;
150 dr->wIndex = 0;
151 dr->wLength = cpu_to_le16(len);
152
153 memcpy(buf, data, len);
154
155 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
156 (unsigned char *)dr, buf, len,
157 rtl8187_iowrite_async_cb, buf);
158 usb_anchor_urb(urb, &priv->anchored);
159 rc = usb_submit_urb(urb, GFP_ATOMIC);
160 if (rc < 0) {
161 kfree(buf);
162 usb_unanchor_urb(urb);
163 }
164 usb_free_urb(urb);
165}
166
167static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
168 __le32 *addr, u32 val)
169{
170 __le32 buf = cpu_to_le32(val);
171
172 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
173 &buf, sizeof(buf));
174}
175
176void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
177{
178 struct rtl8187_priv *priv = dev->priv;
179
180 data <<= 8;
181 data |= addr | 0x80;
182
183 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
184 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
185 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
186 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
187}
188
189static void rtl8187_tx_cb(struct urb *urb)
190{
191 struct sk_buff *skb = (struct sk_buff *)urb->context;
192 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
193 struct ieee80211_hw *hw = info->rate_driver_data[0];
194 struct rtl8187_priv *priv = hw->priv;
195
196 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
197 sizeof(struct rtl8187_tx_hdr));
198 ieee80211_tx_info_clear_status(info);
199
200 if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
201 if (priv->is_rtl8187b) {
202 skb_queue_tail(&priv->b_tx_status.queue, skb);
203
204 /* queue is "full", discard last items */
205 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
206 struct sk_buff *old_skb;
207
208 dev_dbg(&priv->udev->dev,
209 "transmit status queue full\n");
210
211 old_skb = skb_dequeue(&priv->b_tx_status.queue);
212 ieee80211_tx_status_irqsafe(hw, old_skb);
213 }
214 return;
215 } else {
216 info->flags |= IEEE80211_TX_STAT_ACK;
217 }
218 }
219 if (priv->is_rtl8187b)
220 ieee80211_tx_status_irqsafe(hw, skb);
221 else {
222 /* Retry information for the RTI8187 is only available by
223 * reading a register in the device. We are in interrupt mode
224 * here, thus queue the skb and finish on a work queue. */
225 skb_queue_tail(&priv->b_tx_status.queue, skb);
226 ieee80211_queue_delayed_work(hw, &priv->work, 0);
227 }
228}
229
230static void rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
231{
232 struct rtl8187_priv *priv = dev->priv;
233 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
234 unsigned int ep;
235 void *buf;
236 struct urb *urb;
237 __le16 rts_dur = 0;
238 u32 flags;
239 int rc;
240
241 urb = usb_alloc_urb(0, GFP_ATOMIC);
242 if (!urb) {
243 kfree_skb(skb);
244 return;
245 }
246
247 flags = skb->len;
248 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
249
250 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
251 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
252 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
253 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
254 flags |= RTL818X_TX_DESC_FLAG_RTS;
255 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
256 rts_dur = ieee80211_rts_duration(dev, priv->vif,
257 skb->len, info);
258 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
259 flags |= RTL818X_TX_DESC_FLAG_CTS;
260 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
261 }
262
263 if (!priv->is_rtl8187b) {
264 struct rtl8187_tx_hdr *hdr =
265 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
266 hdr->flags = cpu_to_le32(flags);
267 hdr->len = 0;
268 hdr->rts_duration = rts_dur;
269 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
270 buf = hdr;
271
272 ep = 2;
273 } else {
274 /* fc needs to be calculated before skb_push() */
275 unsigned int epmap[4] = { 6, 7, 5, 4 };
276 struct ieee80211_hdr *tx_hdr =
277 (struct ieee80211_hdr *)(skb->data);
278 u16 fc = le16_to_cpu(tx_hdr->frame_control);
279
280 struct rtl8187b_tx_hdr *hdr =
281 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
282 struct ieee80211_rate *txrate =
283 ieee80211_get_tx_rate(dev, info);
284 memset(hdr, 0, sizeof(*hdr));
285 hdr->flags = cpu_to_le32(flags);
286 hdr->rts_duration = rts_dur;
287 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
288 hdr->tx_duration =
289 ieee80211_generic_frame_duration(dev, priv->vif,
290 skb->len, txrate);
291 buf = hdr;
292
293 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
294 ep = 12;
295 else
296 ep = epmap[skb_get_queue_mapping(skb)];
297 }
298
299 info->rate_driver_data[0] = dev;
300 info->rate_driver_data[1] = urb;
301
302 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
303 buf, skb->len, rtl8187_tx_cb, skb);
304 urb->transfer_flags |= URB_ZERO_PACKET;
305 usb_anchor_urb(urb, &priv->anchored);
306 rc = usb_submit_urb(urb, GFP_ATOMIC);
307 if (rc < 0) {
308 usb_unanchor_urb(urb);
309 kfree_skb(skb);
310 }
311 usb_free_urb(urb);
312}
313
314static void rtl8187_rx_cb(struct urb *urb)
315{
316 struct sk_buff *skb = (struct sk_buff *)urb->context;
317 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
318 struct ieee80211_hw *dev = info->dev;
319 struct rtl8187_priv *priv = dev->priv;
320 struct ieee80211_rx_status rx_status = { 0 };
321 int rate, signal;
322 u32 flags;
323 unsigned long f;
324
325 spin_lock_irqsave(&priv->rx_queue.lock, f);
326 __skb_unlink(skb, &priv->rx_queue);
327 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
328 skb_put(skb, urb->actual_length);
329
330 if (unlikely(urb->status)) {
331 dev_kfree_skb_irq(skb);
332 return;
333 }
334
335 if (!priv->is_rtl8187b) {
336 struct rtl8187_rx_hdr *hdr =
337 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
338 flags = le32_to_cpu(hdr->flags);
339 /* As with the RTL8187B below, the AGC is used to calculate
340 * signal strength. In this case, the scaling
341 * constants are derived from the output of p54usb.
342 */
343 signal = -4 - ((27 * hdr->agc) >> 6);
344 rx_status.antenna = (hdr->signal >> 7) & 1;
345 rx_status.mactime = le64_to_cpu(hdr->mac_time);
346 } else {
347 struct rtl8187b_rx_hdr *hdr =
348 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
349 /* The Realtek datasheet for the RTL8187B shows that the RX
350 * header contains the following quantities: signal quality,
351 * RSSI, AGC, the received power in dB, and the measured SNR.
352 * In testing, none of these quantities show qualitative
353 * agreement with AP signal strength, except for the AGC,
354 * which is inversely proportional to the strength of the
355 * signal. In the following, the signal strength
356 * is derived from the AGC. The arbitrary scaling constants
357 * are chosen to make the results close to the values obtained
358 * for a BCM4312 using b43 as the driver. The noise is ignored
359 * for now.
360 */
361 flags = le32_to_cpu(hdr->flags);
362 signal = 14 - hdr->agc / 2;
363 rx_status.antenna = (hdr->rssi >> 7) & 1;
364 rx_status.mactime = le64_to_cpu(hdr->mac_time);
365 }
366
367 rx_status.signal = signal;
368 priv->signal = signal;
369 rate = (flags >> 20) & 0xF;
370 skb_trim(skb, flags & 0x0FFF);
371 rx_status.rate_idx = rate;
372 rx_status.freq = dev->conf.channel->center_freq;
373 rx_status.band = dev->conf.channel->band;
374 rx_status.flag |= RX_FLAG_MACTIME_MPDU;
375 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
376 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
377 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
378 ieee80211_rx_irqsafe(dev, skb);
379
380 skb = dev_alloc_skb(RTL8187_MAX_RX);
381 if (unlikely(!skb)) {
382 /* TODO check rx queue length and refill *somewhere* */
383 return;
384 }
385
386 info = (struct rtl8187_rx_info *)skb->cb;
387 info->urb = urb;
388 info->dev = dev;
389 urb->transfer_buffer = skb_tail_pointer(skb);
390 urb->context = skb;
391 skb_queue_tail(&priv->rx_queue, skb);
392
393 usb_anchor_urb(urb, &priv->anchored);
394 if (usb_submit_urb(urb, GFP_ATOMIC)) {
395 usb_unanchor_urb(urb);
396 skb_unlink(skb, &priv->rx_queue);
397 dev_kfree_skb_irq(skb);
398 }
399}
400
401static int rtl8187_init_urbs(struct ieee80211_hw *dev)
402{
403 struct rtl8187_priv *priv = dev->priv;
404 struct urb *entry = NULL;
405 struct sk_buff *skb;
406 struct rtl8187_rx_info *info;
407 int ret = 0;
408
409 while (skb_queue_len(&priv->rx_queue) < 16) {
410 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
411 if (!skb) {
412 ret = -ENOMEM;
413 goto err;
414 }
415 entry = usb_alloc_urb(0, GFP_KERNEL);
416 if (!entry) {
417 ret = -ENOMEM;
418 goto err;
419 }
420 usb_fill_bulk_urb(entry, priv->udev,
421 usb_rcvbulkpipe(priv->udev,
422 priv->is_rtl8187b ? 3 : 1),
423 skb_tail_pointer(skb),
424 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
425 info = (struct rtl8187_rx_info *)skb->cb;
426 info->urb = entry;
427 info->dev = dev;
428 skb_queue_tail(&priv->rx_queue, skb);
429 usb_anchor_urb(entry, &priv->anchored);
430 ret = usb_submit_urb(entry, GFP_KERNEL);
431 if (ret) {
432 skb_unlink(skb, &priv->rx_queue);
433 usb_unanchor_urb(entry);
434 goto err;
435 }
436 usb_free_urb(entry);
437 }
438 return ret;
439
440err:
441 usb_free_urb(entry);
442 kfree_skb(skb);
443 usb_kill_anchored_urbs(&priv->anchored);
444 return ret;
445}
446
447static void rtl8187b_status_cb(struct urb *urb)
448{
449 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
450 struct rtl8187_priv *priv = hw->priv;
451 u64 val;
452 unsigned int cmd_type;
453
454 if (unlikely(urb->status))
455 return;
456
457 /*
458 * Read from status buffer:
459 *
460 * bits [30:31] = cmd type:
461 * - 0 indicates tx beacon interrupt
462 * - 1 indicates tx close descriptor
463 *
464 * In the case of tx beacon interrupt:
465 * [0:9] = Last Beacon CW
466 * [10:29] = reserved
467 * [30:31] = 00b
468 * [32:63] = Last Beacon TSF
469 *
470 * If it's tx close descriptor:
471 * [0:7] = Packet Retry Count
472 * [8:14] = RTS Retry Count
473 * [15] = TOK
474 * [16:27] = Sequence No
475 * [28] = LS
476 * [29] = FS
477 * [30:31] = 01b
478 * [32:47] = unused (reserved?)
479 * [48:63] = MAC Used Time
480 */
481 val = le64_to_cpu(priv->b_tx_status.buf);
482
483 cmd_type = (val >> 30) & 0x3;
484 if (cmd_type == 1) {
485 unsigned int pkt_rc, seq_no;
486 bool tok;
487 struct sk_buff *skb;
488 struct ieee80211_hdr *ieee80211hdr;
489 unsigned long flags;
490
491 pkt_rc = val & 0xFF;
492 tok = val & (1 << 15);
493 seq_no = (val >> 16) & 0xFFF;
494
495 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
496 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
497 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
498
499 /*
500 * While testing, it was discovered that the seq_no
501 * doesn't actually contains the sequence number.
502 * Instead of returning just the 12 bits of sequence
503 * number, hardware is returning entire sequence control
504 * (fragment number plus sequence number) in a 12 bit
505 * only field overflowing after some time. As a
506 * workaround, just consider the lower bits, and expect
507 * it's unlikely we wrongly ack some sent data
508 */
509 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
510 & 0xFFF) == seq_no)
511 break;
512 }
513 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
514 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
515
516 __skb_unlink(skb, &priv->b_tx_status.queue);
517 if (tok)
518 info->flags |= IEEE80211_TX_STAT_ACK;
519 info->status.rates[0].count = pkt_rc + 1;
520
521 ieee80211_tx_status_irqsafe(hw, skb);
522 }
523 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
524 }
525
526 usb_anchor_urb(urb, &priv->anchored);
527 if (usb_submit_urb(urb, GFP_ATOMIC))
528 usb_unanchor_urb(urb);
529}
530
531static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
532{
533 struct rtl8187_priv *priv = dev->priv;
534 struct urb *entry;
535 int ret = 0;
536
537 entry = usb_alloc_urb(0, GFP_KERNEL);
538 if (!entry)
539 return -ENOMEM;
540
541 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
542 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
543 rtl8187b_status_cb, dev);
544
545 usb_anchor_urb(entry, &priv->anchored);
546 ret = usb_submit_urb(entry, GFP_KERNEL);
547 if (ret)
548 usb_unanchor_urb(entry);
549 usb_free_urb(entry);
550
551 return ret;
552}
553
554static void rtl8187_set_anaparam(struct rtl8187_priv *priv, bool rfon)
555{
556 u32 anaparam, anaparam2;
557 u8 anaparam3, reg;
558
559 if (!priv->is_rtl8187b) {
560 if (rfon) {
561 anaparam = RTL8187_RTL8225_ANAPARAM_ON;
562 anaparam2 = RTL8187_RTL8225_ANAPARAM2_ON;
563 } else {
564 anaparam = RTL8187_RTL8225_ANAPARAM_OFF;
565 anaparam2 = RTL8187_RTL8225_ANAPARAM2_OFF;
566 }
567 } else {
568 if (rfon) {
569 anaparam = RTL8187B_RTL8225_ANAPARAM_ON;
570 anaparam2 = RTL8187B_RTL8225_ANAPARAM2_ON;
571 anaparam3 = RTL8187B_RTL8225_ANAPARAM3_ON;
572 } else {
573 anaparam = RTL8187B_RTL8225_ANAPARAM_OFF;
574 anaparam2 = RTL8187B_RTL8225_ANAPARAM2_OFF;
575 anaparam3 = RTL8187B_RTL8225_ANAPARAM3_OFF;
576 }
577 }
578
579 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
580 RTL818X_EEPROM_CMD_CONFIG);
581 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
582 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
583 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
584 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
585 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
586 if (priv->is_rtl8187b)
587 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3, anaparam3);
588 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
589 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
590 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
591 RTL818X_EEPROM_CMD_NORMAL);
592}
593
594static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
595{
596 struct rtl8187_priv *priv = dev->priv;
597 u8 reg;
598 int i;
599
600 reg = rtl818x_ioread8(priv, &priv->map->CMD);
601 reg &= (1 << 1);
602 reg |= RTL818X_CMD_RESET;
603 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
604
605 i = 10;
606 do {
607 msleep(2);
608 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
609 RTL818X_CMD_RESET))
610 break;
611 } while (--i);
612
613 if (!i) {
614 wiphy_err(dev->wiphy, "Reset timeout!\n");
615 return -ETIMEDOUT;
616 }
617
618 /* reload registers from eeprom */
619 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
620
621 i = 10;
622 do {
623 msleep(4);
624 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
625 RTL818X_EEPROM_CMD_CONFIG))
626 break;
627 } while (--i);
628
629 if (!i) {
630 wiphy_err(dev->wiphy, "eeprom reset timeout!\n");
631 return -ETIMEDOUT;
632 }
633
634 return 0;
635}
636
637static int rtl8187_init_hw(struct ieee80211_hw *dev)
638{
639 struct rtl8187_priv *priv = dev->priv;
640 u8 reg;
641 int res;
642
643 /* reset */
644 rtl8187_set_anaparam(priv, true);
645
646 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
647
648 msleep(200);
649 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
650 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
651 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
652 msleep(200);
653
654 res = rtl8187_cmd_reset(dev);
655 if (res)
656 return res;
657
658 rtl8187_set_anaparam(priv, true);
659
660 /* setup card */
661 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
662 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
663
664 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
665 rtl818x_iowrite8(priv, &priv->map->GPIO0, 1);
666 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
667
668 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
669
670 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
671 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
672 reg &= 0x3F;
673 reg |= 0x80;
674 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
675
676 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
677
678 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
679 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
680 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
681
682 // TODO: set RESP_RATE and BRSR properly
683 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
684 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
685
686 /* host_usb_init */
687 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
688 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
689 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
690 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
691 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
692 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0x20);
693 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
694 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
695 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
696 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
697 msleep(100);
698
699 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
700 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
701 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
702 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
703 RTL818X_EEPROM_CMD_CONFIG);
704 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
705 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
706 RTL818X_EEPROM_CMD_NORMAL);
707 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
708 msleep(100);
709
710 priv->rf->init(dev);
711
712 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
713 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
714 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
715 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
716 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
717 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
718 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
719
720 return 0;
721}
722
723static const u8 rtl8187b_reg_table[][3] = {
724 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
725 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
726 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
727 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
728
729 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
730 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
731 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1},
732 {0xF2, 0x02, 1}, {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1},
733 {0xF6, 0x06, 1}, {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
734
735 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
736 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
737 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
738 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
739 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
740 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
741 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2},
742
743 {0x5B, 0x40, 0}, {0x84, 0x88, 0}, {0x85, 0x24, 0}, {0x88, 0x54, 0},
744 {0x8B, 0xB8, 0}, {0x8C, 0x07, 0}, {0x8D, 0x00, 0}, {0x94, 0x1B, 0},
745 {0x95, 0x12, 0}, {0x96, 0x00, 0}, {0x97, 0x06, 0}, {0x9D, 0x1A, 0},
746 {0x9F, 0x10, 0}, {0xB4, 0x22, 0}, {0xBE, 0x80, 0}, {0xDB, 0x00, 0},
747 {0xEE, 0x00, 0}, {0x4C, 0x00, 2},
748
749 {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, {0x8E, 0x08, 0},
750 {0x8F, 0x00, 0}
751};
752
753static int rtl8187b_init_hw(struct ieee80211_hw *dev)
754{
755 struct rtl8187_priv *priv = dev->priv;
756 int res, i;
757 u8 reg;
758
759 rtl8187_set_anaparam(priv, true);
760
761 /* Reset PLL sequence on 8187B. Realtek note: reduces power
762 * consumption about 30 mA */
763 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
764 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
765 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
766 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
767
768 res = rtl8187_cmd_reset(dev);
769 if (res)
770 return res;
771
772 rtl8187_set_anaparam(priv, true);
773
774 /* BRSR (Basic Rate Set Register) on 8187B looks to be the same as
775 * RESP_RATE on 8187L in Realtek sources: each bit should be each
776 * one of the 12 rates, all are enabled */
777 rtl818x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF);
778
779 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
780 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
781 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
782
783 /* Auto Rate Fallback Register (ARFR): 1M-54M setting */
784 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
785 rtl818x_iowrite8_idx(priv, (u8 *)0xFFE2, 0x00, 1);
786
787 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
788
789 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
790 RTL818X_EEPROM_CMD_CONFIG);
791 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
792 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
793 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
794 RTL818X_EEPROM_CMD_NORMAL);
795
796 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
797 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
798 rtl818x_iowrite8_idx(priv,
799 (u8 *)(uintptr_t)
800 (rtl8187b_reg_table[i][0] | 0xFF00),
801 rtl8187b_reg_table[i][1],
802 rtl8187b_reg_table[i][2]);
803 }
804
805 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
806 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
807
808 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
809 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
810 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
811
812 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
813
814 /* RFSW_CTRL register */
815 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
816
817 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
818 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
819 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
820 msleep(100);
821
822 priv->rf->init(dev);
823
824 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
825 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
826 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
827
828 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
829 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
830 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
831 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
832 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
833 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
834 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
835
836 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
837 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
838 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
839 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
840 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
841 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
842 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
843 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
844 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
845 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
846 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
847 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
848 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
849
850 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
851
852 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
853
854 priv->slot_time = 0x9;
855 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
856 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
857 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
858 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
859 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
860
861 /* ENEDCA flag must always be set, transmit issues? */
862 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
863
864 return 0;
865}
866
867static void rtl8187_work(struct work_struct *work)
868{
869 /* The RTL8187 returns the retry count through register 0xFFFA. In
870 * addition, it appears to be a cumulative retry count, not the
871 * value for the current TX packet. When multiple TX entries are
872 * waiting in the queue, the retry count will be the total for all.
873 * The "error" may matter for purposes of rate setting, but there is
874 * no other choice with this hardware.
875 */
876 struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
877 work.work);
878 struct ieee80211_tx_info *info;
879 struct ieee80211_hw *dev = priv->dev;
880 static u16 retry;
881 u16 tmp;
882 u16 avg_retry;
883 int length;
884
885 mutex_lock(&priv->conf_mutex);
886 tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
887 length = skb_queue_len(&priv->b_tx_status.queue);
888 if (unlikely(!length))
889 length = 1;
890 if (unlikely(tmp < retry))
891 tmp = retry;
892 avg_retry = (tmp - retry) / length;
893 while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
894 struct sk_buff *old_skb;
895
896 old_skb = skb_dequeue(&priv->b_tx_status.queue);
897 info = IEEE80211_SKB_CB(old_skb);
898 info->status.rates[0].count = avg_retry + 1;
899 if (info->status.rates[0].count > RETRY_COUNT)
900 info->flags &= ~IEEE80211_TX_STAT_ACK;
901 ieee80211_tx_status_irqsafe(dev, old_skb);
902 }
903 retry = tmp;
904 mutex_unlock(&priv->conf_mutex);
905}
906
907static int rtl8187_start(struct ieee80211_hw *dev)
908{
909 struct rtl8187_priv *priv = dev->priv;
910 u32 reg;
911 int ret;
912
913 mutex_lock(&priv->conf_mutex);
914
915 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
916 rtl8187b_init_hw(dev);
917 if (ret)
918 goto rtl8187_start_exit;
919
920 init_usb_anchor(&priv->anchored);
921 priv->dev = dev;
922
923 if (priv->is_rtl8187b) {
924 reg = RTL818X_RX_CONF_MGMT |
925 RTL818X_RX_CONF_DATA |
926 RTL818X_RX_CONF_BROADCAST |
927 RTL818X_RX_CONF_NICMAC |
928 RTL818X_RX_CONF_BSSID |
929 (7 << 13 /* RX FIFO threshold NONE */) |
930 (7 << 10 /* MAX RX DMA */) |
931 RTL818X_RX_CONF_RX_AUTORESETPHY |
932 RTL818X_RX_CONF_ONLYERLPKT |
933 RTL818X_RX_CONF_MULTICAST;
934 priv->rx_conf = reg;
935 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
936
937 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
938 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
939 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
940 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
941 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
942
943 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
944 RTL818X_TX_CONF_HW_SEQNUM |
945 RTL818X_TX_CONF_DISREQQSIZE |
946 (RETRY_COUNT << 8 /* short retry limit */) |
947 (RETRY_COUNT << 0 /* long retry limit */) |
948 (7 << 21 /* MAX TX DMA */));
949 rtl8187_init_urbs(dev);
950 rtl8187b_init_status_urb(dev);
951 goto rtl8187_start_exit;
952 }
953
954 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
955
956 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
957 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
958
959 rtl8187_init_urbs(dev);
960
961 reg = RTL818X_RX_CONF_ONLYERLPKT |
962 RTL818X_RX_CONF_RX_AUTORESETPHY |
963 RTL818X_RX_CONF_BSSID |
964 RTL818X_RX_CONF_MGMT |
965 RTL818X_RX_CONF_DATA |
966 (7 << 13 /* RX FIFO threshold NONE */) |
967 (7 << 10 /* MAX RX DMA */) |
968 RTL818X_RX_CONF_BROADCAST |
969 RTL818X_RX_CONF_NICMAC;
970
971 priv->rx_conf = reg;
972 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
973
974 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
975 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
976 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
977 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
978
979 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
980 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
981 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
982 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
983 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
984
985 reg = RTL818X_TX_CONF_CW_MIN |
986 (7 << 21 /* MAX TX DMA */) |
987 RTL818X_TX_CONF_NO_ICV;
988 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
989
990 reg = rtl818x_ioread8(priv, &priv->map->CMD);
991 reg |= RTL818X_CMD_TX_ENABLE;
992 reg |= RTL818X_CMD_RX_ENABLE;
993 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
994 INIT_DELAYED_WORK(&priv->work, rtl8187_work);
995
996rtl8187_start_exit:
997 mutex_unlock(&priv->conf_mutex);
998 return ret;
999}
1000
1001static void rtl8187_stop(struct ieee80211_hw *dev)
1002{
1003 struct rtl8187_priv *priv = dev->priv;
1004 struct sk_buff *skb;
1005 u32 reg;
1006
1007 mutex_lock(&priv->conf_mutex);
1008 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
1009
1010 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1011 reg &= ~RTL818X_CMD_TX_ENABLE;
1012 reg &= ~RTL818X_CMD_RX_ENABLE;
1013 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1014
1015 priv->rf->stop(dev);
1016 rtl8187_set_anaparam(priv, false);
1017
1018 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1019 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1020 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1021 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1022
1023 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
1024 dev_kfree_skb_any(skb);
1025
1026 usb_kill_anchored_urbs(&priv->anchored);
1027 mutex_unlock(&priv->conf_mutex);
1028
1029 if (!priv->is_rtl8187b)
1030 cancel_delayed_work_sync(&priv->work);
1031}
1032
1033static int rtl8187_add_interface(struct ieee80211_hw *dev,
1034 struct ieee80211_vif *vif)
1035{
1036 struct rtl8187_priv *priv = dev->priv;
1037 int i;
1038 int ret = -EOPNOTSUPP;
1039
1040 mutex_lock(&priv->conf_mutex);
1041 if (priv->vif)
1042 goto exit;
1043
1044 switch (vif->type) {
1045 case NL80211_IFTYPE_STATION:
1046 break;
1047 default:
1048 goto exit;
1049 }
1050
1051 ret = 0;
1052 priv->vif = vif;
1053
1054 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1055 for (i = 0; i < ETH_ALEN; i++)
1056 rtl818x_iowrite8(priv, &priv->map->MAC[i],
1057 ((u8 *)vif->addr)[i]);
1058 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1059
1060exit:
1061 mutex_unlock(&priv->conf_mutex);
1062 return ret;
1063}
1064
1065static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1066 struct ieee80211_vif *vif)
1067{
1068 struct rtl8187_priv *priv = dev->priv;
1069 mutex_lock(&priv->conf_mutex);
1070 priv->vif = NULL;
1071 mutex_unlock(&priv->conf_mutex);
1072}
1073
1074static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
1075{
1076 struct rtl8187_priv *priv = dev->priv;
1077 struct ieee80211_conf *conf = &dev->conf;
1078 u32 reg;
1079
1080 mutex_lock(&priv->conf_mutex);
1081 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1082 /* Enable TX loopback on MAC level to avoid TX during channel
1083 * changes, as this has be seen to causes problems and the
1084 * card will stop work until next reset
1085 */
1086 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1087 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
1088 priv->rf->set_chan(dev, conf);
1089 msleep(10);
1090 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1091
1092 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1093 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1094 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1095 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
1096 mutex_unlock(&priv->conf_mutex);
1097 return 0;
1098}
1099
1100/*
1101 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1102 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1103 */
1104static __le32 *rtl8187b_ac_addr[4] = {
1105 (__le32 *) 0xFFF0, /* AC_VO */
1106 (__le32 *) 0xFFF4, /* AC_VI */
1107 (__le32 *) 0xFFFC, /* AC_BK */
1108 (__le32 *) 0xFFF8, /* AC_BE */
1109};
1110
1111#define SIFS_TIME 0xa
1112
1113static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1114 bool use_short_preamble)
1115{
1116 if (priv->is_rtl8187b) {
1117 u8 difs, eifs;
1118 u16 ack_timeout;
1119 int queue;
1120
1121 if (use_short_slot) {
1122 priv->slot_time = 0x9;
1123 difs = 0x1c;
1124 eifs = 0x53;
1125 } else {
1126 priv->slot_time = 0x14;
1127 difs = 0x32;
1128 eifs = 0x5b;
1129 }
1130 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1131 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1132 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1133
1134 /*
1135 * BRSR+1 on 8187B is in fact EIFS register
1136 * Value in units of 4 us
1137 */
1138 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1139
1140 /*
1141 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1142 * register. In units of 4 us like eifs register
1143 * ack_timeout = ack duration + plcp + difs + preamble
1144 */
1145 ack_timeout = 112 + 48 + difs;
1146 if (use_short_preamble)
1147 ack_timeout += 72;
1148 else
1149 ack_timeout += 144;
1150 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1151 DIV_ROUND_UP(ack_timeout, 4));
1152
1153 for (queue = 0; queue < 4; queue++)
1154 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1155 priv->aifsn[queue] * priv->slot_time +
1156 SIFS_TIME);
1157 } else {
1158 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1159 if (use_short_slot) {
1160 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1161 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1162 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
1163 } else {
1164 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1165 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1166 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
1167 }
1168 }
1169}
1170
1171static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1172 struct ieee80211_vif *vif,
1173 struct ieee80211_bss_conf *info,
1174 u32 changed)
1175{
1176 struct rtl8187_priv *priv = dev->priv;
1177 int i;
1178 u8 reg;
1179
1180 if (changed & BSS_CHANGED_BSSID) {
1181 mutex_lock(&priv->conf_mutex);
1182 for (i = 0; i < ETH_ALEN; i++)
1183 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1184 info->bssid[i]);
1185
1186 if (priv->is_rtl8187b)
1187 reg = RTL818X_MSR_ENEDCA;
1188 else
1189 reg = 0;
1190
1191 if (is_valid_ether_addr(info->bssid))
1192 reg |= RTL818X_MSR_INFRA;
1193 else
1194 reg |= RTL818X_MSR_NO_LINK;
1195
1196 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1197
1198 mutex_unlock(&priv->conf_mutex);
1199 }
1200
1201 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1202 rtl8187_conf_erp(priv, info->use_short_slot,
1203 info->use_short_preamble);
1204}
1205
1206static u64 rtl8187_prepare_multicast(struct ieee80211_hw *dev,
1207 struct netdev_hw_addr_list *mc_list)
1208{
1209 return netdev_hw_addr_list_count(mc_list);
1210}
1211
1212static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1213 unsigned int changed_flags,
1214 unsigned int *total_flags,
1215 u64 multicast)
1216{
1217 struct rtl8187_priv *priv = dev->priv;
1218
1219 if (changed_flags & FIF_FCSFAIL)
1220 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1221 if (changed_flags & FIF_CONTROL)
1222 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1223 if (changed_flags & FIF_OTHER_BSS)
1224 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1225 if (*total_flags & FIF_ALLMULTI || multicast > 0)
1226 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1227 else
1228 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1229
1230 *total_flags = 0;
1231
1232 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1233 *total_flags |= FIF_FCSFAIL;
1234 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1235 *total_flags |= FIF_CONTROL;
1236 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1237 *total_flags |= FIF_OTHER_BSS;
1238 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1239 *total_flags |= FIF_ALLMULTI;
1240
1241 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1242}
1243
1244static int rtl8187_conf_tx(struct ieee80211_hw *dev, u16 queue,
1245 const struct ieee80211_tx_queue_params *params)
1246{
1247 struct rtl8187_priv *priv = dev->priv;
1248 u8 cw_min, cw_max;
1249
1250 if (queue > 3)
1251 return -EINVAL;
1252
1253 cw_min = fls(params->cw_min);
1254 cw_max = fls(params->cw_max);
1255
1256 if (priv->is_rtl8187b) {
1257 priv->aifsn[queue] = params->aifs;
1258
1259 /*
1260 * This is the structure of AC_*_PARAM registers in 8187B:
1261 * - TXOP limit field, bit offset = 16
1262 * - ECWmax, bit offset = 12
1263 * - ECWmin, bit offset = 8
1264 * - AIFS, bit offset = 0
1265 */
1266 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1267 (params->txop << 16) | (cw_max << 12) |
1268 (cw_min << 8) | (params->aifs *
1269 priv->slot_time + SIFS_TIME));
1270 } else {
1271 if (queue != 0)
1272 return -EINVAL;
1273
1274 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1275 cw_min | (cw_max << 4));
1276 }
1277 return 0;
1278}
1279
1280static u64 rtl8187_get_tsf(struct ieee80211_hw *dev)
1281{
1282 struct rtl8187_priv *priv = dev->priv;
1283
1284 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
1285 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
1286}
1287
1288static const struct ieee80211_ops rtl8187_ops = {
1289 .tx = rtl8187_tx,
1290 .start = rtl8187_start,
1291 .stop = rtl8187_stop,
1292 .add_interface = rtl8187_add_interface,
1293 .remove_interface = rtl8187_remove_interface,
1294 .config = rtl8187_config,
1295 .bss_info_changed = rtl8187_bss_info_changed,
1296 .prepare_multicast = rtl8187_prepare_multicast,
1297 .configure_filter = rtl8187_configure_filter,
1298 .conf_tx = rtl8187_conf_tx,
1299 .rfkill_poll = rtl8187_rfkill_poll,
1300 .get_tsf = rtl8187_get_tsf,
1301};
1302
1303static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1304{
1305 struct ieee80211_hw *dev = eeprom->data;
1306 struct rtl8187_priv *priv = dev->priv;
1307 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1308
1309 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1310 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1311 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1312 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1313}
1314
1315static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1316{
1317 struct ieee80211_hw *dev = eeprom->data;
1318 struct rtl8187_priv *priv = dev->priv;
1319 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1320
1321 if (eeprom->reg_data_in)
1322 reg |= RTL818X_EEPROM_CMD_WRITE;
1323 if (eeprom->reg_data_out)
1324 reg |= RTL818X_EEPROM_CMD_READ;
1325 if (eeprom->reg_data_clock)
1326 reg |= RTL818X_EEPROM_CMD_CK;
1327 if (eeprom->reg_chip_select)
1328 reg |= RTL818X_EEPROM_CMD_CS;
1329
1330 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1331 udelay(10);
1332}
1333
1334static int __devinit rtl8187_probe(struct usb_interface *intf,
1335 const struct usb_device_id *id)
1336{
1337 struct usb_device *udev = interface_to_usbdev(intf);
1338 struct ieee80211_hw *dev;
1339 struct rtl8187_priv *priv;
1340 struct eeprom_93cx6 eeprom;
1341 struct ieee80211_channel *channel;
1342 const char *chip_name;
1343 u16 txpwr, reg;
1344 u16 product_id = le16_to_cpu(udev->descriptor.idProduct);
1345 int err, i;
1346 u8 mac_addr[ETH_ALEN];
1347
1348 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1349 if (!dev) {
1350 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1351 return -ENOMEM;
1352 }
1353
1354 priv = dev->priv;
1355 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
1356
1357 /* allocate "DMA aware" buffer for register accesses */
1358 priv->io_dmabuf = kmalloc(sizeof(*priv->io_dmabuf), GFP_KERNEL);
1359 if (!priv->io_dmabuf) {
1360 err = -ENOMEM;
1361 goto err_free_dev;
1362 }
1363 mutex_init(&priv->io_mutex);
1364
1365 SET_IEEE80211_DEV(dev, &intf->dev);
1366 usb_set_intfdata(intf, dev);
1367 priv->udev = udev;
1368
1369 usb_get_dev(udev);
1370
1371 skb_queue_head_init(&priv->rx_queue);
1372
1373 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1374 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1375
1376 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1377 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1378 priv->map = (struct rtl818x_csr *)0xFF00;
1379
1380 priv->band.band = IEEE80211_BAND_2GHZ;
1381 priv->band.channels = priv->channels;
1382 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1383 priv->band.bitrates = priv->rates;
1384 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1385 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1386
1387
1388 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1389 IEEE80211_HW_SIGNAL_DBM |
1390 IEEE80211_HW_RX_INCLUDES_FCS;
1391 /* Initialize rate-control variables */
1392 dev->max_rates = 1;
1393 dev->max_rate_tries = RETRY_COUNT;
1394
1395 eeprom.data = dev;
1396 eeprom.register_read = rtl8187_eeprom_register_read;
1397 eeprom.register_write = rtl8187_eeprom_register_write;
1398 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1399 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1400 else
1401 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1402
1403 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1404 udelay(10);
1405
1406 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1407 (__le16 __force *)mac_addr, 3);
1408 if (!is_valid_ether_addr(mac_addr)) {
1409 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1410 "generated MAC address\n");
1411 random_ether_addr(mac_addr);
1412 }
1413 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1414
1415 channel = priv->channels;
1416 for (i = 0; i < 3; i++) {
1417 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1418 &txpwr);
1419 (*channel++).hw_value = txpwr & 0xFF;
1420 (*channel++).hw_value = txpwr >> 8;
1421 }
1422 for (i = 0; i < 2; i++) {
1423 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1424 &txpwr);
1425 (*channel++).hw_value = txpwr & 0xFF;
1426 (*channel++).hw_value = txpwr >> 8;
1427 }
1428
1429 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1430 &priv->txpwr_base);
1431
1432 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1433 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
1434 /* 0 means asic B-cut, we should use SW 3 wire
1435 * bit-by-bit banging for radio. 1 means we can use
1436 * USB specific request to write radio registers */
1437 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
1438 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
1439 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1440
1441 if (!priv->is_rtl8187b) {
1442 u32 reg32;
1443 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1444 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1445 switch (reg32) {
1446 case RTL818X_TX_CONF_R8187vD_B:
1447 /* Some RTL8187B devices have a USB ID of 0x8187
1448 * detect them here */
1449 chip_name = "RTL8187BvB(early)";
1450 priv->is_rtl8187b = 1;
1451 priv->hw_rev = RTL8187BvB;
1452 break;
1453 case RTL818X_TX_CONF_R8187vD:
1454 chip_name = "RTL8187vD";
1455 break;
1456 default:
1457 chip_name = "RTL8187vB (default)";
1458 }
1459 } else {
1460 /*
1461 * Force USB request to write radio registers for 8187B, Realtek
1462 * only uses it in their sources
1463 */
1464 /*if (priv->asic_rev == 0) {
1465 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1466 "requests to write to radio registers\n");
1467 priv->asic_rev = 1;
1468 }*/
1469 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1470 case RTL818X_R8187B_B:
1471 chip_name = "RTL8187BvB";
1472 priv->hw_rev = RTL8187BvB;
1473 break;
1474 case RTL818X_R8187B_D:
1475 chip_name = "RTL8187BvD";
1476 priv->hw_rev = RTL8187BvD;
1477 break;
1478 case RTL818X_R8187B_E:
1479 chip_name = "RTL8187BvE";
1480 priv->hw_rev = RTL8187BvE;
1481 break;
1482 default:
1483 chip_name = "RTL8187BvB (default)";
1484 priv->hw_rev = RTL8187BvB;
1485 }
1486 }
1487
1488 if (!priv->is_rtl8187b) {
1489 for (i = 0; i < 2; i++) {
1490 eeprom_93cx6_read(&eeprom,
1491 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1492 &txpwr);
1493 (*channel++).hw_value = txpwr & 0xFF;
1494 (*channel++).hw_value = txpwr >> 8;
1495 }
1496 } else {
1497 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1498 &txpwr);
1499 (*channel++).hw_value = txpwr & 0xFF;
1500
1501 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1502 (*channel++).hw_value = txpwr & 0xFF;
1503
1504 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1505 (*channel++).hw_value = txpwr & 0xFF;
1506 (*channel++).hw_value = txpwr >> 8;
1507 }
1508 /* Handle the differing rfkill GPIO bit in different models */
1509 priv->rfkill_mask = RFKILL_MASK_8187_89_97;
1510 if (product_id == 0x8197 || product_id == 0x8198) {
1511 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_SELECT_GPIO, &reg);
1512 if (reg & 0xFF00)
1513 priv->rfkill_mask = RFKILL_MASK_8198;
1514 }
1515
1516 /*
1517 * XXX: Once this driver supports anything that requires
1518 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1519 */
1520 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1521
1522 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1523 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1524 " info!\n");
1525
1526 priv->rf = rtl8187_detect_rf(dev);
1527 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1528 sizeof(struct rtl8187_tx_hdr) :
1529 sizeof(struct rtl8187b_tx_hdr);
1530 if (!priv->is_rtl8187b)
1531 dev->queues = 1;
1532 else
1533 dev->queues = 4;
1534
1535 err = ieee80211_register_hw(dev);
1536 if (err) {
1537 printk(KERN_ERR "rtl8187: Cannot register device\n");
1538 goto err_free_dmabuf;
1539 }
1540 mutex_init(&priv->conf_mutex);
1541 skb_queue_head_init(&priv->b_tx_status.queue);
1542
1543 wiphy_info(dev->wiphy, "hwaddr %pM, %s V%d + %s, rfkill mask %d\n",
1544 mac_addr, chip_name, priv->asic_rev, priv->rf->name,
1545 priv->rfkill_mask);
1546
1547#ifdef CONFIG_RTL8187_LEDS
1548 eeprom_93cx6_read(&eeprom, 0x3F, &reg);
1549 reg &= 0xFF;
1550 rtl8187_leds_init(dev, reg);
1551#endif
1552 rtl8187_rfkill_init(dev);
1553
1554 return 0;
1555
1556 err_free_dmabuf:
1557 kfree(priv->io_dmabuf);
1558 err_free_dev:
1559 ieee80211_free_hw(dev);
1560 usb_set_intfdata(intf, NULL);
1561 usb_put_dev(udev);
1562 return err;
1563}
1564
1565static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1566{
1567 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1568 struct rtl8187_priv *priv;
1569
1570 if (!dev)
1571 return;
1572
1573#ifdef CONFIG_RTL8187_LEDS
1574 rtl8187_leds_exit(dev);
1575#endif
1576 rtl8187_rfkill_exit(dev);
1577 ieee80211_unregister_hw(dev);
1578
1579 priv = dev->priv;
1580 usb_reset_device(priv->udev);
1581 usb_put_dev(interface_to_usbdev(intf));
1582 kfree(priv->io_dmabuf);
1583 ieee80211_free_hw(dev);
1584}
1585
1586static struct usb_driver rtl8187_driver = {
1587 .name = KBUILD_MODNAME,
1588 .id_table = rtl8187_table,
1589 .probe = rtl8187_probe,
1590 .disconnect = __devexit_p(rtl8187_disconnect),
1591};
1592
1593static int __init rtl8187_init(void)
1594{
1595 return usb_register(&rtl8187_driver);
1596}
1597
1598static void __exit rtl8187_exit(void)
1599{
1600 usb_deregister(&rtl8187_driver);
1601}
1602
1603module_init(rtl8187_init);
1604module_exit(rtl8187_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 11:15:20 -0400