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-rw-r--r--drivers/net/wireless/rt2x00/Kconfig109
-rw-r--r--drivers/net/wireless/rt2x00/Makefile3
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c42
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.h5
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c79
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.h5
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c213
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.h4
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h1852
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c2325
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.h150
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c1288
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.h159
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c2582
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.h1834
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h127
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00config.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00crypto.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00debug.c9
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00debug.h2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dev.c42
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dump.h2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00firmware.c3
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00ht.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00leds.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00leds.h6
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00lib.h20
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00link.c90
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00mac.c52
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c13
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.h27
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.c103
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h8
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00reg.h2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00soc.c160
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00soc.h42
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c7
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.h21
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c117
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.h13
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c77
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.h6
42 files changed, 6893 insertions, 4714 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index ed1f997e3521..5239e082cd0f 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -1,6 +1,6 @@
1menuconfig RT2X00 1menuconfig RT2X00
2 tristate "Ralink driver support" 2 tristate "Ralink driver support"
3 depends on MAC80211 && WLAN_80211 3 depends on MAC80211
4 ---help--- 4 ---help---
5 This will enable the support for the Ralink drivers, 5 This will enable the support for the Ralink drivers,
6 developed in the rt2x00 project <http://rt2x00.serialmonkey.com>. 6 developed in the rt2x00 project <http://rt2x00.serialmonkey.com>.
@@ -53,6 +53,62 @@ config RT61PCI
53 53
54 When compiled as a module, this driver will be called rt61pci. 54 When compiled as a module, this driver will be called rt61pci.
55 55
56config RT2800PCI_PCI
57 boolean
58 depends on PCI
59 default y
60
61config RT2800PCI_SOC
62 boolean
63 depends on RALINK_RT288X || RALINK_RT305X
64 default y
65
66config RT2800PCI
67 tristate "Ralink rt28xx/rt30xx/rt35xx (PCI/PCIe/PCMCIA) support (EXPERIMENTAL)"
68 depends on (RT2800PCI_PCI || RT2800PCI_SOC) && EXPERIMENTAL
69 select RT2800_LIB
70 select RT2X00_LIB_PCI if RT2800PCI_PCI
71 select RT2X00_LIB_SOC if RT2800PCI_SOC
72 select RT2X00_LIB_HT
73 select RT2X00_LIB_FIRMWARE
74 select RT2X00_LIB_CRYPTO
75 select CRC_CCITT
76 select EEPROM_93CX6
77 ---help---
78 This adds support for rt2800/rt3000/rt3500 wireless chipset family.
79 Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890 & RT3052
80
81 This driver is non-functional at the moment and is intended for
82 developers.
83
84 When compiled as a module, this driver will be called "rt2800pci.ko".
85
86if RT2800PCI
87
88config RT2800PCI_RT30XX
89 bool "rt2800pci - Include support for rt30xx (PCI/PCIe/PCMCIA) devices"
90 default n
91 ---help---
92 This adds support for rt30xx wireless chipset family to the
93 rt2800pci driver.
94 Supported chips: RT3090, RT3091 & RT3092
95
96 Support for these devices is non-functional at the moment and is
97 intended for testers and developers.
98
99config RT2800PCI_RT35XX
100 bool "rt2800pci - Include support for rt35xx (PCI/PCIe/PCMCIA) devices"
101 default n
102 ---help---
103 This adds support for rt35xx wireless chipset family to the
104 rt2800pci driver.
105 Supported chips: RT3060, RT3062, RT3562, RT3592
106
107 Support for these devices is non-functional at the moment and is
108 intended for testers and developers.
109
110endif
111
56config RT2500USB 112config RT2500USB
57 tristate "Ralink rt2500 (USB) support" 113 tristate "Ralink rt2500 (USB) support"
58 depends on USB 114 depends on USB
@@ -78,8 +134,9 @@ config RT73USB
78 When compiled as a module, this driver will be called rt73usb. 134 When compiled as a module, this driver will be called rt73usb.
79 135
80config RT2800USB 136config RT2800USB
81 tristate "Ralink rt2800 (USB) support" 137 tristate "Ralink rt2800 (USB) support (EXPERIMENTAL)"
82 depends on USB && EXPERIMENTAL 138 depends on USB && EXPERIMENTAL
139 select RT2800_LIB
83 select RT2X00_LIB_USB 140 select RT2X00_LIB_USB
84 select RT2X00_LIB_HT 141 select RT2X00_LIB_HT
85 select RT2X00_LIB_FIRMWARE 142 select RT2X00_LIB_FIRMWARE
@@ -89,12 +146,60 @@ config RT2800USB
89 This adds experimental support for rt2800 wireless chipset family. 146 This adds experimental support for rt2800 wireless chipset family.
90 Supported chips: RT2770, RT2870 & RT3070. 147 Supported chips: RT2770, RT2870 & RT3070.
91 148
149 Known issues:
150 - support for RT2870 chips doesn't work with 802.11n APs yet
151 - support for RT3070 chips is non-functional at the moment
152
92 When compiled as a module, this driver will be called "rt2800usb.ko". 153 When compiled as a module, this driver will be called "rt2800usb.ko".
93 154
155if RT2800USB
156
157config RT2800USB_RT30XX
158 bool "rt2800usb - Include support for rt30xx (USB) devices"
159 default n
160 ---help---
161 This adds support for rt30xx wireless chipset family to the
162 rt2800usb driver.
163 Supported chips: RT3070, RT3071 & RT3072
164
165 Support for these devices is non-functional at the moment and is
166 intended for testers and developers.
167
168config RT2800USB_RT35XX
169 bool "rt2800usb - Include support for rt35xx (USB) devices"
170 default n
171 ---help---
172 This adds support for rt35xx wireless chipset family to the
173 rt2800usb driver.
174 Supported chips: RT3572
175
176 Support for these devices is non-functional at the moment and is
177 intended for testers and developers.
178
179config RT2800USB_UNKNOWN
180 bool "rt2800usb - Include support for unknown (USB) devices"
181 default n
182 ---help---
183 This adds support for rt2800 family devices that are known to
184 have a rt2800 family chipset, but for which the exact chipset
185 is unknown.
186
187 Support status for these devices is unknown, and enabling these
188 devices may or may not work.
189
190endif
191
192config RT2800_LIB
193 tristate
194
94config RT2X00_LIB_PCI 195config RT2X00_LIB_PCI
95 tristate 196 tristate
96 select RT2X00_LIB 197 select RT2X00_LIB
97 198
199config RT2X00_LIB_SOC
200 tristate
201 select RT2X00_LIB
202
98config RT2X00_LIB_USB 203config RT2X00_LIB_USB
99 tristate 204 tristate
100 select RT2X00_LIB 205 select RT2X00_LIB
diff --git a/drivers/net/wireless/rt2x00/Makefile b/drivers/net/wireless/rt2x00/Makefile
index 13043ea97667..971339858297 100644
--- a/drivers/net/wireless/rt2x00/Makefile
+++ b/drivers/net/wireless/rt2x00/Makefile
@@ -11,10 +11,13 @@ rt2x00lib-$(CONFIG_RT2X00_LIB_HT) += rt2x00ht.o
11 11
12obj-$(CONFIG_RT2X00_LIB) += rt2x00lib.o 12obj-$(CONFIG_RT2X00_LIB) += rt2x00lib.o
13obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o 13obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o
14obj-$(CONFIG_RT2X00_LIB_SOC) += rt2x00soc.o
14obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00usb.o 15obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00usb.o
16obj-$(CONFIG_RT2800_LIB) += rt2800lib.o
15obj-$(CONFIG_RT2400PCI) += rt2400pci.o 17obj-$(CONFIG_RT2400PCI) += rt2400pci.o
16obj-$(CONFIG_RT2500PCI) += rt2500pci.o 18obj-$(CONFIG_RT2500PCI) += rt2500pci.o
17obj-$(CONFIG_RT61PCI) += rt61pci.o 19obj-$(CONFIG_RT61PCI) += rt61pci.o
20obj-$(CONFIG_RT2800PCI) += rt2800pci.o
18obj-$(CONFIG_RT2500USB) += rt2500usb.o 21obj-$(CONFIG_RT2500USB) += rt2500usb.o
19obj-$(CONFIG_RT73USB) += rt73usb.o 22obj-$(CONFIG_RT73USB) += rt73usb.o
20obj-$(CONFIG_RT2800USB) += rt2800usb.o 23obj-$(CONFIG_RT2800USB) += rt2800usb.o
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 798f625e38f7..5f5204b82891 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -31,6 +31,7 @@
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/pci.h> 32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h> 33#include <linux/eeprom_93cx6.h>
34#include <linux/slab.h>
34 35
35#include "rt2x00.h" 36#include "rt2x00.h"
36#include "rt2x00pci.h" 37#include "rt2x00pci.h"
@@ -451,7 +452,7 @@ static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
451 /* 452 /*
452 * RF2420 chipset don't need any additional actions. 453 * RF2420 chipset don't need any additional actions.
453 */ 454 */
454 if (rt2x00_rf(&rt2x00dev->chip, RF2420)) 455 if (rt2x00_rf(rt2x00dev, RF2420))
455 return; 456 return;
456 457
457 /* 458 /*
@@ -1340,10 +1341,10 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1340 */ 1341 */
1341 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1342 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1342 rt2x00pci_register_read(rt2x00dev, CSR0, &reg); 1343 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1343 rt2x00_set_chip_rf(rt2x00dev, value, reg); 1344 rt2x00_set_chip(rt2x00dev, RT2460, value,
1345 rt2x00_get_field32(reg, CSR0_REVISION));
1344 1346
1345 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) && 1347 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1346 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1347 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 1348 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1348 return -ENODEV; 1349 return -ENODEV;
1349 } 1350 }
@@ -1431,7 +1432,6 @@ static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1431 IEEE80211_HW_SIGNAL_DBM | 1432 IEEE80211_HW_SIGNAL_DBM |
1432 IEEE80211_HW_SUPPORTS_PS | 1433 IEEE80211_HW_SUPPORTS_PS |
1433 IEEE80211_HW_PS_NULLFUNC_STACK; 1434 IEEE80211_HW_PS_NULLFUNC_STACK;
1434 rt2x00dev->hw->extra_tx_headroom = 0;
1435 1435
1436 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 1436 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1437 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1437 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
@@ -1562,7 +1562,6 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1562 .get_stats = rt2x00mac_get_stats, 1562 .get_stats = rt2x00mac_get_stats,
1563 .bss_info_changed = rt2x00mac_bss_info_changed, 1563 .bss_info_changed = rt2x00mac_bss_info_changed,
1564 .conf_tx = rt2400pci_conf_tx, 1564 .conf_tx = rt2400pci_conf_tx,
1565 .get_tx_stats = rt2x00mac_get_tx_stats,
1566 .get_tsf = rt2400pci_get_tsf, 1565 .get_tsf = rt2400pci_get_tsf,
1567 .tx_last_beacon = rt2400pci_tx_last_beacon, 1566 .tx_last_beacon = rt2400pci_tx_last_beacon,
1568 .rfkill_poll = rt2x00mac_rfkill_poll, 1567 .rfkill_poll = rt2x00mac_rfkill_poll,
@@ -1622,27 +1621,28 @@ static const struct data_queue_desc rt2400pci_queue_atim = {
1622}; 1621};
1623 1622
1624static const struct rt2x00_ops rt2400pci_ops = { 1623static const struct rt2x00_ops rt2400pci_ops = {
1625 .name = KBUILD_MODNAME, 1624 .name = KBUILD_MODNAME,
1626 .max_sta_intf = 1, 1625 .max_sta_intf = 1,
1627 .max_ap_intf = 1, 1626 .max_ap_intf = 1,
1628 .eeprom_size = EEPROM_SIZE, 1627 .eeprom_size = EEPROM_SIZE,
1629 .rf_size = RF_SIZE, 1628 .rf_size = RF_SIZE,
1630 .tx_queues = NUM_TX_QUEUES, 1629 .tx_queues = NUM_TX_QUEUES,
1631 .rx = &rt2400pci_queue_rx, 1630 .extra_tx_headroom = 0,
1632 .tx = &rt2400pci_queue_tx, 1631 .rx = &rt2400pci_queue_rx,
1633 .bcn = &rt2400pci_queue_bcn, 1632 .tx = &rt2400pci_queue_tx,
1634 .atim = &rt2400pci_queue_atim, 1633 .bcn = &rt2400pci_queue_bcn,
1635 .lib = &rt2400pci_rt2x00_ops, 1634 .atim = &rt2400pci_queue_atim,
1636 .hw = &rt2400pci_mac80211_ops, 1635 .lib = &rt2400pci_rt2x00_ops,
1636 .hw = &rt2400pci_mac80211_ops,
1637#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1637#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1638 .debugfs = &rt2400pci_rt2x00debug, 1638 .debugfs = &rt2400pci_rt2x00debug,
1639#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1639#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1640}; 1640};
1641 1641
1642/* 1642/*
1643 * RT2400pci module information. 1643 * RT2400pci module information.
1644 */ 1644 */
1645static struct pci_device_id rt2400pci_device_table[] = { 1645static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
1646 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) }, 1646 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1647 { 0, } 1647 { 0, }
1648}; 1648};
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.h b/drivers/net/wireless/rt2x00/rt2400pci.h
index ccd644104ad1..c048b18f4133 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.h
+++ b/drivers/net/wireless/rt2x00/rt2400pci.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -35,7 +35,7 @@
35 35
36/* 36/*
37 * Signal information. 37 * Signal information.
38 * Defaul offset is required for RSSI <-> dBm conversion. 38 * Default offset is required for RSSI <-> dBm conversion.
39 */ 39 */
40#define DEFAULT_RSSI_OFFSET 100 40#define DEFAULT_RSSI_OFFSET 100
41 41
@@ -65,6 +65,7 @@
65 * CSR0: ASIC revision number. 65 * CSR0: ASIC revision number.
66 */ 66 */
67#define CSR0 0x0000 67#define CSR0 0x0000
68#define CSR0_REVISION FIELD32(0x0000ffff)
68 69
69/* 70/*
70 * CSR1: System control register. 71 * CSR1: System control register.
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index 2e872ac69826..2a73f593aab0 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -31,6 +31,7 @@
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/pci.h> 32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h> 33#include <linux/eeprom_93cx6.h>
34#include <linux/slab.h>
34 35
35#include "rt2x00.h" 36#include "rt2x00.h"
36#include "rt2x00pci.h" 37#include "rt2x00pci.h"
@@ -440,8 +441,7 @@ static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
440 /* 441 /*
441 * RT2525E and RT5222 need to flip TX I/Q 442 * RT2525E and RT5222 need to flip TX I/Q
442 */ 443 */
443 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) || 444 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
444 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
445 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1); 445 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
446 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1); 446 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
447 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1); 447 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
@@ -449,7 +449,7 @@ static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
449 /* 449 /*
450 * RT2525E does not need RX I/Q Flip. 450 * RT2525E does not need RX I/Q Flip.
451 */ 451 */
452 if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) 452 if (rt2x00_rf(rt2x00dev, RF2525E))
453 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0); 453 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
454 } else { 454 } else {
455 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0); 455 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
@@ -475,14 +475,14 @@ static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
475 * Switch on tuning bits. 475 * Switch on tuning bits.
476 * For RT2523 devices we do not need to update the R1 register. 476 * For RT2523 devices we do not need to update the R1 register.
477 */ 477 */
478 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) 478 if (!rt2x00_rf(rt2x00dev, RF2523))
479 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); 479 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
480 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); 480 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
481 481
482 /* 482 /*
483 * For RT2525 we should first set the channel to half band higher. 483 * For RT2525 we should first set the channel to half band higher.
484 */ 484 */
485 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) { 485 if (rt2x00_rf(rt2x00dev, RF2525)) {
486 static const u32 vals[] = { 486 static const u32 vals[] = {
487 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a, 487 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
488 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a, 488 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
@@ -516,7 +516,7 @@ static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
516 * Switch off tuning bits. 516 * Switch off tuning bits.
517 * For RT2523 devices we do not need to update the R1 register. 517 * For RT2523 devices we do not need to update the R1 register.
518 */ 518 */
519 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) { 519 if (!rt2x00_rf(rt2x00dev, RF2523)) {
520 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); 520 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
521 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); 521 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
522 } 522 }
@@ -640,7 +640,7 @@ static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
640 * up to version C the link tuning should halt after 20 640 * up to version C the link tuning should halt after 20
641 * seconds while being associated. 641 * seconds while being associated.
642 */ 642 */
643 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D && 643 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
644 rt2x00dev->intf_associated && count > 20) 644 rt2x00dev->intf_associated && count > 20)
645 return; 645 return;
646 646
@@ -650,7 +650,7 @@ static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
650 * should go straight to dynamic CCA tuning when they 650 * should go straight to dynamic CCA tuning when they
651 * are not associated. 651 * are not associated.
652 */ 652 */
653 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D || 653 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
654 !rt2x00dev->intf_associated) 654 !rt2x00dev->intf_associated)
655 goto dynamic_cca_tune; 655 goto dynamic_cca_tune;
656 656
@@ -1504,14 +1504,15 @@ static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1504 */ 1504 */
1505 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1505 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1506 rt2x00pci_register_read(rt2x00dev, CSR0, &reg); 1506 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1507 rt2x00_set_chip_rf(rt2x00dev, value, reg); 1507 rt2x00_set_chip(rt2x00dev, RT2560, value,
1508 1508 rt2x00_get_field32(reg, CSR0_REVISION));
1509 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) && 1509
1510 !rt2x00_rf(&rt2x00dev->chip, RF2523) && 1510 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1511 !rt2x00_rf(&rt2x00dev->chip, RF2524) && 1511 !rt2x00_rf(rt2x00dev, RF2523) &&
1512 !rt2x00_rf(&rt2x00dev->chip, RF2525) && 1512 !rt2x00_rf(rt2x00dev, RF2524) &&
1513 !rt2x00_rf(&rt2x00dev->chip, RF2525E) && 1513 !rt2x00_rf(rt2x00dev, RF2525) &&
1514 !rt2x00_rf(&rt2x00dev->chip, RF5222)) { 1514 !rt2x00_rf(rt2x00dev, RF2525E) &&
1515 !rt2x00_rf(rt2x00dev, RF5222)) {
1515 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 1516 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1516 return -ENODEV; 1517 return -ENODEV;
1517 } 1518 }
@@ -1732,8 +1733,6 @@ static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1732 IEEE80211_HW_SUPPORTS_PS | 1733 IEEE80211_HW_SUPPORTS_PS |
1733 IEEE80211_HW_PS_NULLFUNC_STACK; 1734 IEEE80211_HW_PS_NULLFUNC_STACK;
1734 1735
1735 rt2x00dev->hw->extra_tx_headroom = 0;
1736
1737 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 1736 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1738 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1737 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1739 rt2x00_eeprom_addr(rt2x00dev, 1738 rt2x00_eeprom_addr(rt2x00dev,
@@ -1745,22 +1744,22 @@ static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1745 spec->supported_bands = SUPPORT_BAND_2GHZ; 1744 spec->supported_bands = SUPPORT_BAND_2GHZ;
1746 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 1745 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1747 1746
1748 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) { 1747 if (rt2x00_rf(rt2x00dev, RF2522)) {
1749 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522); 1748 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1750 spec->channels = rf_vals_bg_2522; 1749 spec->channels = rf_vals_bg_2522;
1751 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) { 1750 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1752 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523); 1751 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1753 spec->channels = rf_vals_bg_2523; 1752 spec->channels = rf_vals_bg_2523;
1754 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) { 1753 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1755 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524); 1754 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1756 spec->channels = rf_vals_bg_2524; 1755 spec->channels = rf_vals_bg_2524;
1757 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) { 1756 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1758 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525); 1757 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1759 spec->channels = rf_vals_bg_2525; 1758 spec->channels = rf_vals_bg_2525;
1760 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) { 1759 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1761 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e); 1760 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1762 spec->channels = rf_vals_bg_2525e; 1761 spec->channels = rf_vals_bg_2525e;
1763 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) { 1762 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1764 spec->supported_bands |= SUPPORT_BAND_5GHZ; 1763 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1765 spec->num_channels = ARRAY_SIZE(rf_vals_5222); 1764 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1766 spec->channels = rf_vals_5222; 1765 spec->channels = rf_vals_5222;
@@ -1861,7 +1860,6 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1861 .get_stats = rt2x00mac_get_stats, 1860 .get_stats = rt2x00mac_get_stats,
1862 .bss_info_changed = rt2x00mac_bss_info_changed, 1861 .bss_info_changed = rt2x00mac_bss_info_changed,
1863 .conf_tx = rt2x00mac_conf_tx, 1862 .conf_tx = rt2x00mac_conf_tx,
1864 .get_tx_stats = rt2x00mac_get_tx_stats,
1865 .get_tsf = rt2500pci_get_tsf, 1863 .get_tsf = rt2500pci_get_tsf,
1866 .tx_last_beacon = rt2500pci_tx_last_beacon, 1864 .tx_last_beacon = rt2500pci_tx_last_beacon,
1867 .rfkill_poll = rt2x00mac_rfkill_poll, 1865 .rfkill_poll = rt2x00mac_rfkill_poll,
@@ -1921,27 +1919,28 @@ static const struct data_queue_desc rt2500pci_queue_atim = {
1921}; 1919};
1922 1920
1923static const struct rt2x00_ops rt2500pci_ops = { 1921static const struct rt2x00_ops rt2500pci_ops = {
1924 .name = KBUILD_MODNAME, 1922 .name = KBUILD_MODNAME,
1925 .max_sta_intf = 1, 1923 .max_sta_intf = 1,
1926 .max_ap_intf = 1, 1924 .max_ap_intf = 1,
1927 .eeprom_size = EEPROM_SIZE, 1925 .eeprom_size = EEPROM_SIZE,
1928 .rf_size = RF_SIZE, 1926 .rf_size = RF_SIZE,
1929 .tx_queues = NUM_TX_QUEUES, 1927 .tx_queues = NUM_TX_QUEUES,
1930 .rx = &rt2500pci_queue_rx, 1928 .extra_tx_headroom = 0,
1931 .tx = &rt2500pci_queue_tx, 1929 .rx = &rt2500pci_queue_rx,
1932 .bcn = &rt2500pci_queue_bcn, 1930 .tx = &rt2500pci_queue_tx,
1933 .atim = &rt2500pci_queue_atim, 1931 .bcn = &rt2500pci_queue_bcn,
1934 .lib = &rt2500pci_rt2x00_ops, 1932 .atim = &rt2500pci_queue_atim,
1935 .hw = &rt2500pci_mac80211_ops, 1933 .lib = &rt2500pci_rt2x00_ops,
1934 .hw = &rt2500pci_mac80211_ops,
1936#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1935#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1937 .debugfs = &rt2500pci_rt2x00debug, 1936 .debugfs = &rt2500pci_rt2x00debug,
1938#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1937#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1939}; 1938};
1940 1939
1941/* 1940/*
1942 * RT2500pci module information. 1941 * RT2500pci module information.
1943 */ 1942 */
1944static struct pci_device_id rt2500pci_device_table[] = { 1943static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
1945 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) }, 1944 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1946 { 0, } 1945 { 0, }
1947}; 1946};
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.h b/drivers/net/wireless/rt2x00/rt2500pci.h
index 54d37957883c..d708031361ac 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.h
+++ b/drivers/net/wireless/rt2x00/rt2500pci.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -46,7 +46,7 @@
46 46
47/* 47/*
48 * Signal information. 48 * Signal information.
49 * Defaul offset is required for RSSI <-> dBm conversion. 49 * Default offset is required for RSSI <-> dBm conversion.
50 */ 50 */
51#define DEFAULT_RSSI_OFFSET 121 51#define DEFAULT_RSSI_OFFSET 121
52 52
@@ -76,6 +76,7 @@
76 * CSR0: ASIC revision number. 76 * CSR0: ASIC revision number.
77 */ 77 */
78#define CSR0 0x0000 78#define CSR0 0x0000
79#define CSR0_REVISION FIELD32(0x0000ffff)
79 80
80/* 81/*
81 * CSR1: System control register. 82 * CSR1: System control register.
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index 22dd6d9e2981..8ebb705fe106 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -29,6 +29,7 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/slab.h>
32#include <linux/usb.h> 33#include <linux/usb.h>
33 34
34#include "rt2x00.h" 35#include "rt2x00.h"
@@ -368,7 +369,7 @@ static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
368 369
369 /* 370 /*
370 * The encryption key doesn't fit within the CSR cache, 371 * The encryption key doesn't fit within the CSR cache,
371 * this means we should allocate it seperately and use 372 * this means we should allocate it separately and use
372 * rt2x00usb_vendor_request() to send the key to the hardware. 373 * rt2x00usb_vendor_request() to send the key to the hardware.
373 */ 374 */
374 reg = KEY_ENTRY(key->hw_key_idx); 375 reg = KEY_ENTRY(key->hw_key_idx);
@@ -382,7 +383,7 @@ static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
382 /* 383 /*
383 * The driver does not support the IV/EIV generation 384 * The driver does not support the IV/EIV generation
384 * in hardware. However it demands the data to be provided 385 * in hardware. However it demands the data to be provided
385 * both seperately as well as inside the frame. 386 * both separately as well as inside the frame.
386 * We already provided the CONFIG_CRYPTO_COPY_IV to rt2x00lib 387 * We already provided the CONFIG_CRYPTO_COPY_IV to rt2x00lib
387 * to ensure rt2x00lib will not strip the data from the 388 * to ensure rt2x00lib will not strip the data from the
388 * frame after the copy, now we must tell mac80211 389 * frame after the copy, now we must tell mac80211
@@ -565,8 +566,7 @@ static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev,
565 /* 566 /*
566 * RT2525E and RT5222 need to flip TX I/Q 567 * RT2525E and RT5222 need to flip TX I/Q
567 */ 568 */
568 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) || 569 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
569 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
570 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1); 570 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
571 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1); 571 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1);
572 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1); 572 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1);
@@ -574,7 +574,7 @@ static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev,
574 /* 574 /*
575 * RT2525E does not need RX I/Q Flip. 575 * RT2525E does not need RX I/Q Flip.
576 */ 576 */
577 if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) 577 if (rt2x00_rf(rt2x00dev, RF2525E))
578 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0); 578 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
579 } else { 579 } else {
580 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0); 580 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0);
@@ -598,7 +598,7 @@ static void rt2500usb_config_channel(struct rt2x00_dev *rt2x00dev,
598 /* 598 /*
599 * For RT2525E we should first set the channel to half band higher. 599 * For RT2525E we should first set the channel to half band higher.
600 */ 600 */
601 if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) { 601 if (rt2x00_rf(rt2x00dev, RF2525E)) {
602 static const u32 vals[] = { 602 static const u32 vals[] = {
603 0x000008aa, 0x000008ae, 0x000008ae, 0x000008b2, 603 0x000008aa, 0x000008ae, 0x000008ae, 0x000008b2,
604 0x000008b2, 0x000008b6, 0x000008b6, 0x000008ba, 604 0x000008b2, 0x000008b6, 0x000008b6, 0x000008ba,
@@ -716,139 +716,6 @@ static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
716} 716}
717 717
718/* 718/*
719 * NOTE: This function is directly ported from legacy driver, but
720 * despite it being declared it was never called. Although link tuning
721 * sounds like a good idea, and usually works well for the other drivers,
722 * it does _not_ work with rt2500usb. Enabling this function will result
723 * in TX capabilities only until association kicks in. Immediately
724 * after the successful association all TX frames will be kept in the
725 * hardware queue and never transmitted.
726 */
727#if 0
728static void rt2500usb_link_tuner(struct rt2x00_dev *rt2x00dev)
729{
730 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
731 u16 bbp_thresh;
732 u16 vgc_bound;
733 u16 sens;
734 u16 r24;
735 u16 r25;
736 u16 r61;
737 u16 r17_sens;
738 u8 r17;
739 u8 up_bound;
740 u8 low_bound;
741
742 /*
743 * Read current r17 value, as well as the sensitivity values
744 * for the r17 register.
745 */
746 rt2500usb_bbp_read(rt2x00dev, 17, &r17);
747 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &r17_sens);
748
749 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &vgc_bound);
750 up_bound = rt2x00_get_field16(vgc_bound, EEPROM_BBPTUNE_VGCUPPER);
751 low_bound = rt2x00_get_field16(vgc_bound, EEPROM_BBPTUNE_VGCLOWER);
752
753 /*
754 * If we are not associated, we should go straight to the
755 * dynamic CCA tuning.
756 */
757 if (!rt2x00dev->intf_associated)
758 goto dynamic_cca_tune;
759
760 /*
761 * Determine the BBP tuning threshold and correctly
762 * set BBP 24, 25 and 61.
763 */
764 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE, &bbp_thresh);
765 bbp_thresh = rt2x00_get_field16(bbp_thresh, EEPROM_BBPTUNE_THRESHOLD);
766
767 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &r24);
768 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &r25);
769 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &r61);
770
771 if ((rssi + bbp_thresh) > 0) {
772 r24 = rt2x00_get_field16(r24, EEPROM_BBPTUNE_R24_HIGH);
773 r25 = rt2x00_get_field16(r25, EEPROM_BBPTUNE_R25_HIGH);
774 r61 = rt2x00_get_field16(r61, EEPROM_BBPTUNE_R61_HIGH);
775 } else {
776 r24 = rt2x00_get_field16(r24, EEPROM_BBPTUNE_R24_LOW);
777 r25 = rt2x00_get_field16(r25, EEPROM_BBPTUNE_R25_LOW);
778 r61 = rt2x00_get_field16(r61, EEPROM_BBPTUNE_R61_LOW);
779 }
780
781 rt2500usb_bbp_write(rt2x00dev, 24, r24);
782 rt2500usb_bbp_write(rt2x00dev, 25, r25);
783 rt2500usb_bbp_write(rt2x00dev, 61, r61);
784
785 /*
786 * A too low RSSI will cause too much false CCA which will
787 * then corrupt the R17 tuning. To remidy this the tuning should
788 * be stopped (While making sure the R17 value will not exceed limits)
789 */
790 if (rssi >= -40) {
791 if (r17 != 0x60)
792 rt2500usb_bbp_write(rt2x00dev, 17, 0x60);
793 return;
794 }
795
796 /*
797 * Special big-R17 for short distance
798 */
799 if (rssi >= -58) {
800 sens = rt2x00_get_field16(r17_sens, EEPROM_BBPTUNE_R17_LOW);
801 if (r17 != sens)
802 rt2500usb_bbp_write(rt2x00dev, 17, sens);
803 return;
804 }
805
806 /*
807 * Special mid-R17 for middle distance
808 */
809 if (rssi >= -74) {
810 sens = rt2x00_get_field16(r17_sens, EEPROM_BBPTUNE_R17_HIGH);
811 if (r17 != sens)
812 rt2500usb_bbp_write(rt2x00dev, 17, sens);
813 return;
814 }
815
816 /*
817 * Leave short or middle distance condition, restore r17
818 * to the dynamic tuning range.
819 */
820 low_bound = 0x32;
821 if (rssi < -77)
822 up_bound -= (-77 - rssi);
823
824 if (up_bound < low_bound)
825 up_bound = low_bound;
826
827 if (r17 > up_bound) {
828 rt2500usb_bbp_write(rt2x00dev, 17, up_bound);
829 rt2x00dev->link.vgc_level = up_bound;
830 return;
831 }
832
833dynamic_cca_tune:
834
835 /*
836 * R17 is inside the dynamic tuning range,
837 * start tuning the link based on the false cca counter.
838 */
839 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
840 rt2500usb_bbp_write(rt2x00dev, 17, ++r17);
841 rt2x00dev->link.vgc_level = r17;
842 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
843 rt2500usb_bbp_write(rt2x00dev, 17, --r17);
844 rt2x00dev->link.vgc_level = r17;
845 }
846}
847#else
848#define rt2500usb_link_tuner NULL
849#endif
850
851/*
852 * Initialization functions. 719 * Initialization functions.
853 */ 720 */
854static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev) 721static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
@@ -926,7 +793,7 @@ static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
926 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1); 793 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1);
927 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg); 794 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
928 795
929 if (rt2x00_rev(&rt2x00dev->chip) >= RT2570_VERSION_C) { 796 if (rt2x00_rev(rt2x00dev) >= RT2570_VERSION_C) {
930 rt2500usb_register_read(rt2x00dev, PHY_CSR2, &reg); 797 rt2500usb_register_read(rt2x00dev, PHY_CSR2, &reg);
931 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 0); 798 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 0);
932 } else { 799 } else {
@@ -1543,19 +1410,17 @@ static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1543 rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1410 rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1544 rt2x00_set_chip(rt2x00dev, RT2570, value, reg); 1411 rt2x00_set_chip(rt2x00dev, RT2570, value, reg);
1545 1412
1546 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x000ffff0, 0) || 1413 if (((reg & 0xfff0) != 0) || ((reg & 0x0000000f) == 0)) {
1547 rt2x00_check_rev(&rt2x00dev->chip, 0x0000000f, 0)) {
1548
1549 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 1414 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1550 return -ENODEV; 1415 return -ENODEV;
1551 } 1416 }
1552 1417
1553 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) && 1418 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1554 !rt2x00_rf(&rt2x00dev->chip, RF2523) && 1419 !rt2x00_rf(rt2x00dev, RF2523) &&
1555 !rt2x00_rf(&rt2x00dev->chip, RF2524) && 1420 !rt2x00_rf(rt2x00dev, RF2524) &&
1556 !rt2x00_rf(&rt2x00dev->chip, RF2525) && 1421 !rt2x00_rf(rt2x00dev, RF2525) &&
1557 !rt2x00_rf(&rt2x00dev->chip, RF2525E) && 1422 !rt2x00_rf(rt2x00dev, RF2525E) &&
1558 !rt2x00_rf(&rt2x00dev->chip, RF5222)) { 1423 !rt2x00_rf(rt2x00dev, RF5222)) {
1559 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 1424 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1560 return -ENODEV; 1425 return -ENODEV;
1561 } 1426 }
@@ -1779,6 +1644,11 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1779 unsigned int i; 1644 unsigned int i;
1780 1645
1781 /* 1646 /*
1647 * Disable powersaving as default.
1648 */
1649 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1650
1651 /*
1782 * Initialize all hw fields. 1652 * Initialize all hw fields.
1783 */ 1653 */
1784 rt2x00dev->hw->flags = 1654 rt2x00dev->hw->flags =
@@ -1788,8 +1658,6 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1788 IEEE80211_HW_SUPPORTS_PS | 1658 IEEE80211_HW_SUPPORTS_PS |
1789 IEEE80211_HW_PS_NULLFUNC_STACK; 1659 IEEE80211_HW_PS_NULLFUNC_STACK;
1790 1660
1791 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1792
1793 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 1661 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1794 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1662 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1795 rt2x00_eeprom_addr(rt2x00dev, 1663 rt2x00_eeprom_addr(rt2x00dev,
@@ -1801,22 +1669,22 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1801 spec->supported_bands = SUPPORT_BAND_2GHZ; 1669 spec->supported_bands = SUPPORT_BAND_2GHZ;
1802 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 1670 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1803 1671
1804 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) { 1672 if (rt2x00_rf(rt2x00dev, RF2522)) {
1805 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522); 1673 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1806 spec->channels = rf_vals_bg_2522; 1674 spec->channels = rf_vals_bg_2522;
1807 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) { 1675 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1808 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523); 1676 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1809 spec->channels = rf_vals_bg_2523; 1677 spec->channels = rf_vals_bg_2523;
1810 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) { 1678 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1811 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524); 1679 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1812 spec->channels = rf_vals_bg_2524; 1680 spec->channels = rf_vals_bg_2524;
1813 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) { 1681 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1814 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525); 1682 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1815 spec->channels = rf_vals_bg_2525; 1683 spec->channels = rf_vals_bg_2525;
1816 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) { 1684 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1817 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e); 1685 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1818 spec->channels = rf_vals_bg_2525e; 1686 spec->channels = rf_vals_bg_2525e;
1819 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) { 1687 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1820 spec->supported_bands |= SUPPORT_BAND_5GHZ; 1688 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1821 spec->num_channels = ARRAY_SIZE(rf_vals_5222); 1689 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1822 spec->channels = rf_vals_5222; 1690 spec->channels = rf_vals_5222;
@@ -1897,7 +1765,6 @@ static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1897 .get_stats = rt2x00mac_get_stats, 1765 .get_stats = rt2x00mac_get_stats,
1898 .bss_info_changed = rt2x00mac_bss_info_changed, 1766 .bss_info_changed = rt2x00mac_bss_info_changed,
1899 .conf_tx = rt2x00mac_conf_tx, 1767 .conf_tx = rt2x00mac_conf_tx,
1900 .get_tx_stats = rt2x00mac_get_tx_stats,
1901 .rfkill_poll = rt2x00mac_rfkill_poll, 1768 .rfkill_poll = rt2x00mac_rfkill_poll,
1902}; 1769};
1903 1770
@@ -1910,7 +1777,6 @@ static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
1910 .rfkill_poll = rt2500usb_rfkill_poll, 1777 .rfkill_poll = rt2500usb_rfkill_poll,
1911 .link_stats = rt2500usb_link_stats, 1778 .link_stats = rt2500usb_link_stats,
1912 .reset_tuner = rt2500usb_reset_tuner, 1779 .reset_tuner = rt2500usb_reset_tuner,
1913 .link_tuner = rt2500usb_link_tuner,
1914 .write_tx_desc = rt2500usb_write_tx_desc, 1780 .write_tx_desc = rt2500usb_write_tx_desc,
1915 .write_tx_data = rt2x00usb_write_tx_data, 1781 .write_tx_data = rt2x00usb_write_tx_data,
1916 .write_beacon = rt2500usb_write_beacon, 1782 .write_beacon = rt2500usb_write_beacon,
@@ -1956,20 +1822,21 @@ static const struct data_queue_desc rt2500usb_queue_atim = {
1956}; 1822};
1957 1823
1958static const struct rt2x00_ops rt2500usb_ops = { 1824static const struct rt2x00_ops rt2500usb_ops = {
1959 .name = KBUILD_MODNAME, 1825 .name = KBUILD_MODNAME,
1960 .max_sta_intf = 1, 1826 .max_sta_intf = 1,
1961 .max_ap_intf = 1, 1827 .max_ap_intf = 1,
1962 .eeprom_size = EEPROM_SIZE, 1828 .eeprom_size = EEPROM_SIZE,
1963 .rf_size = RF_SIZE, 1829 .rf_size = RF_SIZE,
1964 .tx_queues = NUM_TX_QUEUES, 1830 .tx_queues = NUM_TX_QUEUES,
1965 .rx = &rt2500usb_queue_rx, 1831 .extra_tx_headroom = TXD_DESC_SIZE,
1966 .tx = &rt2500usb_queue_tx, 1832 .rx = &rt2500usb_queue_rx,
1967 .bcn = &rt2500usb_queue_bcn, 1833 .tx = &rt2500usb_queue_tx,
1968 .atim = &rt2500usb_queue_atim, 1834 .bcn = &rt2500usb_queue_bcn,
1969 .lib = &rt2500usb_rt2x00_ops, 1835 .atim = &rt2500usb_queue_atim,
1970 .hw = &rt2500usb_mac80211_ops, 1836 .lib = &rt2500usb_rt2x00_ops,
1837 .hw = &rt2500usb_mac80211_ops,
1971#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1838#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1972 .debugfs = &rt2500usb_rt2x00debug, 1839 .debugfs = &rt2500usb_rt2x00debug,
1973#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1840#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1974}; 1841};
1975 1842
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.h b/drivers/net/wireless/rt2x00/rt2500usb.h
index b01edca42583..b493306a7eed 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.h
+++ b/drivers/net/wireless/rt2x00/rt2500usb.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -46,7 +46,7 @@
46 46
47/* 47/*
48 * Signal information. 48 * Signal information.
49 * Defaul offset is required for RSSI <-> dBm conversion. 49 * Default offset is required for RSSI <-> dBm conversion.
50 */ 50 */
51#define DEFAULT_RSSI_OFFSET 120 51#define DEFAULT_RSSI_OFFSET 120
52 52
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
new file mode 100644
index 000000000000..74c0433dba37
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -0,0 +1,1852 @@
1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800
30 Abstract: Data structures and registers for the rt2800 modules.
31 Supported chipsets: RT2800E, RT2800ED & RT2800U.
32 */
33
34#ifndef RT2800_H
35#define RT2800_H
36
37/*
38 * RF chip defines.
39 *
40 * RF2820 2.4G 2T3R
41 * RF2850 2.4G/5G 2T3R
42 * RF2720 2.4G 1T2R
43 * RF2750 2.4G/5G 1T2R
44 * RF3020 2.4G 1T1R
45 * RF2020 2.4G B/G
46 * RF3021 2.4G 1T2R
47 * RF3022 2.4G 2T2R
48 * RF3052 2.4G 2T2R
49 */
50#define RF2820 0x0001
51#define RF2850 0x0002
52#define RF2720 0x0003
53#define RF2750 0x0004
54#define RF3020 0x0005
55#define RF2020 0x0006
56#define RF3021 0x0007
57#define RF3022 0x0008
58#define RF3052 0x0009
59
60/*
61 * Chipset version.
62 */
63#define RT2860C_VERSION 0x0100
64#define RT2860D_VERSION 0x0101
65#define RT2880E_VERSION 0x0200
66#define RT2883_VERSION 0x0300
67#define RT3070_VERSION 0x0200
68
69/*
70 * Signal information.
71 * Default offset is required for RSSI <-> dBm conversion.
72 */
73#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
74
75/*
76 * Register layout information.
77 */
78#define CSR_REG_BASE 0x1000
79#define CSR_REG_SIZE 0x0800
80#define EEPROM_BASE 0x0000
81#define EEPROM_SIZE 0x0110
82#define BBP_BASE 0x0000
83#define BBP_SIZE 0x0080
84#define RF_BASE 0x0004
85#define RF_SIZE 0x0010
86
87/*
88 * Number of TX queues.
89 */
90#define NUM_TX_QUEUES 4
91
92/*
93 * USB registers.
94 */
95
96/*
97 * INT_SOURCE_CSR: Interrupt source register.
98 * Write one to clear corresponding bit.
99 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
100 */
101#define INT_SOURCE_CSR 0x0200
102#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
103#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
104#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
105#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
106#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
107#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
108#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
109#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
110#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
111#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
112#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
113#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
114#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
115#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
116#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
117#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
118#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
119#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
120
121/*
122 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
123 */
124#define INT_MASK_CSR 0x0204
125#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
126#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
127#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
128#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
129#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
130#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
131#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
132#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
133#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
134#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
135#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
136#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
137#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
138#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
139#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
140#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
141#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
142#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
143
144/*
145 * WPDMA_GLO_CFG
146 */
147#define WPDMA_GLO_CFG 0x0208
148#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
149#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
150#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
151#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
152#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
153#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
154#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
155#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
156#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
157
158/*
159 * WPDMA_RST_IDX
160 */
161#define WPDMA_RST_IDX 0x020c
162#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
163#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
164#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
165#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
166#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
167#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
168#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
169
170/*
171 * DELAY_INT_CFG
172 */
173#define DELAY_INT_CFG 0x0210
174#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
175#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
176#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
177#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
178#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
179#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
180
181/*
182 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
183 * AIFSN0: AC_BE
184 * AIFSN1: AC_BK
185 * AIFSN2: AC_VI
186 * AIFSN3: AC_VO
187 */
188#define WMM_AIFSN_CFG 0x0214
189#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
190#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
191#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
192#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
193
194/*
195 * WMM_CWMIN_CSR: CWmin for each EDCA AC
196 * CWMIN0: AC_BE
197 * CWMIN1: AC_BK
198 * CWMIN2: AC_VI
199 * CWMIN3: AC_VO
200 */
201#define WMM_CWMIN_CFG 0x0218
202#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
203#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
204#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
205#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
206
207/*
208 * WMM_CWMAX_CSR: CWmax for each EDCA AC
209 * CWMAX0: AC_BE
210 * CWMAX1: AC_BK
211 * CWMAX2: AC_VI
212 * CWMAX3: AC_VO
213 */
214#define WMM_CWMAX_CFG 0x021c
215#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
216#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
217#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
218#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
219
220/*
221 * AC_TXOP0: AC_BK/AC_BE TXOP register
222 * AC0TXOP: AC_BK in unit of 32us
223 * AC1TXOP: AC_BE in unit of 32us
224 */
225#define WMM_TXOP0_CFG 0x0220
226#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
227#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
228
229/*
230 * AC_TXOP1: AC_VO/AC_VI TXOP register
231 * AC2TXOP: AC_VI in unit of 32us
232 * AC3TXOP: AC_VO in unit of 32us
233 */
234#define WMM_TXOP1_CFG 0x0224
235#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
236#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
237
238/*
239 * GPIO_CTRL_CFG:
240 */
241#define GPIO_CTRL_CFG 0x0228
242#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
243#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
244#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
245#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
246#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
247#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
248#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
249#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
250#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
251
252/*
253 * MCU_CMD_CFG
254 */
255#define MCU_CMD_CFG 0x022c
256
257/*
258 * AC_BK register offsets
259 */
260#define TX_BASE_PTR0 0x0230
261#define TX_MAX_CNT0 0x0234
262#define TX_CTX_IDX0 0x0238
263#define TX_DTX_IDX0 0x023c
264
265/*
266 * AC_BE register offsets
267 */
268#define TX_BASE_PTR1 0x0240
269#define TX_MAX_CNT1 0x0244
270#define TX_CTX_IDX1 0x0248
271#define TX_DTX_IDX1 0x024c
272
273/*
274 * AC_VI register offsets
275 */
276#define TX_BASE_PTR2 0x0250
277#define TX_MAX_CNT2 0x0254
278#define TX_CTX_IDX2 0x0258
279#define TX_DTX_IDX2 0x025c
280
281/*
282 * AC_VO register offsets
283 */
284#define TX_BASE_PTR3 0x0260
285#define TX_MAX_CNT3 0x0264
286#define TX_CTX_IDX3 0x0268
287#define TX_DTX_IDX3 0x026c
288
289/*
290 * HCCA register offsets
291 */
292#define TX_BASE_PTR4 0x0270
293#define TX_MAX_CNT4 0x0274
294#define TX_CTX_IDX4 0x0278
295#define TX_DTX_IDX4 0x027c
296
297/*
298 * MGMT register offsets
299 */
300#define TX_BASE_PTR5 0x0280
301#define TX_MAX_CNT5 0x0284
302#define TX_CTX_IDX5 0x0288
303#define TX_DTX_IDX5 0x028c
304
305/*
306 * RX register offsets
307 */
308#define RX_BASE_PTR 0x0290
309#define RX_MAX_CNT 0x0294
310#define RX_CRX_IDX 0x0298
311#define RX_DRX_IDX 0x029c
312
313/*
314 * PBF_SYS_CTRL
315 * HOST_RAM_WRITE: enable Host program ram write selection
316 */
317#define PBF_SYS_CTRL 0x0400
318#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
319#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
320
321/*
322 * HOST-MCU shared memory
323 */
324#define HOST_CMD_CSR 0x0404
325#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
326
327/*
328 * PBF registers
329 * Most are for debug. Driver doesn't touch PBF register.
330 */
331#define PBF_CFG 0x0408
332#define PBF_MAX_PCNT 0x040c
333#define PBF_CTRL 0x0410
334#define PBF_INT_STA 0x0414
335#define PBF_INT_ENA 0x0418
336
337/*
338 * BCN_OFFSET0:
339 */
340#define BCN_OFFSET0 0x042c
341#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
342#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
343#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
344#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
345
346/*
347 * BCN_OFFSET1:
348 */
349#define BCN_OFFSET1 0x0430
350#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
351#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
352#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
353#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
354
355/*
356 * PBF registers
357 * Most are for debug. Driver doesn't touch PBF register.
358 */
359#define TXRXQ_PCNT 0x0438
360#define PBF_DBG 0x043c
361
362/*
363 * RF registers
364 */
365#define RF_CSR_CFG 0x0500
366#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
367#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
368#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
369#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
370
371/*
372 * EFUSE_CSR: RT30x0 EEPROM
373 */
374#define EFUSE_CTRL 0x0580
375#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
376#define EFUSE_CTRL_MODE FIELD32(0x000000c0)
377#define EFUSE_CTRL_KICK FIELD32(0x40000000)
378#define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
379
380/*
381 * EFUSE_DATA0
382 */
383#define EFUSE_DATA0 0x0590
384
385/*
386 * EFUSE_DATA1
387 */
388#define EFUSE_DATA1 0x0594
389
390/*
391 * EFUSE_DATA2
392 */
393#define EFUSE_DATA2 0x0598
394
395/*
396 * EFUSE_DATA3
397 */
398#define EFUSE_DATA3 0x059c
399
400/*
401 * MAC Control/Status Registers(CSR).
402 * Some values are set in TU, whereas 1 TU == 1024 us.
403 */
404
405/*
406 * MAC_CSR0: ASIC revision number.
407 * ASIC_REV: 0
408 * ASIC_VER: 2860 or 2870
409 */
410#define MAC_CSR0 0x1000
411#define MAC_CSR0_REVISION FIELD32(0x0000ffff)
412#define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
413
414/*
415 * MAC_SYS_CTRL:
416 */
417#define MAC_SYS_CTRL 0x1004
418#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
419#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
420#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
421#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
422#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
423#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
424#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
425#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
426
427/*
428 * MAC_ADDR_DW0: STA MAC register 0
429 */
430#define MAC_ADDR_DW0 0x1008
431#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
432#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
433#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
434#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
435
436/*
437 * MAC_ADDR_DW1: STA MAC register 1
438 * UNICAST_TO_ME_MASK:
439 * Used to mask off bits from byte 5 of the MAC address
440 * to determine the UNICAST_TO_ME bit for RX frames.
441 * The full mask is complemented by BSS_ID_MASK:
442 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
443 */
444#define MAC_ADDR_DW1 0x100c
445#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
446#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
447#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
448
449/*
450 * MAC_BSSID_DW0: BSSID register 0
451 */
452#define MAC_BSSID_DW0 0x1010
453#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
454#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
455#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
456#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
457
458/*
459 * MAC_BSSID_DW1: BSSID register 1
460 * BSS_ID_MASK:
461 * 0: 1-BSSID mode (BSS index = 0)
462 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
463 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
464 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
465 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
466 * BSSID. This will make sure that those bits will be ignored
467 * when determining the MY_BSS of RX frames.
468 */
469#define MAC_BSSID_DW1 0x1014
470#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
471#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
472#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
473#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
474
475/*
476 * MAX_LEN_CFG: Maximum frame length register.
477 * MAX_MPDU: rt2860b max 16k bytes
478 * MAX_PSDU: Maximum PSDU length
479 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
480 */
481#define MAX_LEN_CFG 0x1018
482#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
483#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
484#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
485#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
486
487/*
488 * BBP_CSR_CFG: BBP serial control register
489 * VALUE: Register value to program into BBP
490 * REG_NUM: Selected BBP register
491 * READ_CONTROL: 0 write BBP, 1 read BBP
492 * BUSY: ASIC is busy executing BBP commands
493 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
494 * BBP_RW_MODE: 0 serial, 1 paralell
495 */
496#define BBP_CSR_CFG 0x101c
497#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
498#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
499#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
500#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
501#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
502#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
503
504/*
505 * RF_CSR_CFG0: RF control register
506 * REGID_AND_VALUE: Register value to program into RF
507 * BITWIDTH: Selected RF register
508 * STANDBYMODE: 0 high when standby, 1 low when standby
509 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
510 * BUSY: ASIC is busy executing RF commands
511 */
512#define RF_CSR_CFG0 0x1020
513#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
514#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
515#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
516#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
517#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
518#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
519
520/*
521 * RF_CSR_CFG1: RF control register
522 * REGID_AND_VALUE: Register value to program into RF
523 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
524 * 0: 3 system clock cycle (37.5usec)
525 * 1: 5 system clock cycle (62.5usec)
526 */
527#define RF_CSR_CFG1 0x1024
528#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
529#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
530
531/*
532 * RF_CSR_CFG2: RF control register
533 * VALUE: Register value to program into RF
534 */
535#define RF_CSR_CFG2 0x1028
536#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
537
538/*
539 * LED_CFG: LED control
540 * color LED's:
541 * 0: off
542 * 1: blinking upon TX2
543 * 2: periodic slow blinking
544 * 3: always on
545 * LED polarity:
546 * 0: active low
547 * 1: active high
548 */
549#define LED_CFG 0x102c
550#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
551#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
552#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
553#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
554#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
555#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
556#define LED_CFG_LED_POLAR FIELD32(0x40000000)
557
558/*
559 * XIFS_TIME_CFG: MAC timing
560 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
561 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
562 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
563 * when MAC doesn't reference BBP signal BBRXEND
564 * EIFS: unit 1us
565 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
566 *
567 */
568#define XIFS_TIME_CFG 0x1100
569#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
570#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
571#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
572#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
573#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
574
575/*
576 * BKOFF_SLOT_CFG:
577 */
578#define BKOFF_SLOT_CFG 0x1104
579#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
580#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
581
582/*
583 * NAV_TIME_CFG:
584 */
585#define NAV_TIME_CFG 0x1108
586#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
587#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
588#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
589#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
590
591/*
592 * CH_TIME_CFG: count as channel busy
593 */
594#define CH_TIME_CFG 0x110c
595
596/*
597 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
598 */
599#define PBF_LIFE_TIMER 0x1110
600
601/*
602 * BCN_TIME_CFG:
603 * BEACON_INTERVAL: in unit of 1/16 TU
604 * TSF_TICKING: Enable TSF auto counting
605 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
606 * BEACON_GEN: Enable beacon generator
607 */
608#define BCN_TIME_CFG 0x1114
609#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
610#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
611#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
612#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
613#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
614#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
615
616/*
617 * TBTT_SYNC_CFG:
618 */
619#define TBTT_SYNC_CFG 0x1118
620
621/*
622 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
623 */
624#define TSF_TIMER_DW0 0x111c
625#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
626
627/*
628 * TSF_TIMER_DW1: Local msb TSF timer, read-only
629 */
630#define TSF_TIMER_DW1 0x1120
631#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
632
633/*
634 * TBTT_TIMER: TImer remains till next TBTT, read-only
635 */
636#define TBTT_TIMER 0x1124
637
638/*
639 * INT_TIMER_CFG:
640 */
641#define INT_TIMER_CFG 0x1128
642
643/*
644 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
645 */
646#define INT_TIMER_EN 0x112c
647
648/*
649 * CH_IDLE_STA: channel idle time
650 */
651#define CH_IDLE_STA 0x1130
652
653/*
654 * CH_BUSY_STA: channel busy time
655 */
656#define CH_BUSY_STA 0x1134
657
658/*
659 * MAC_STATUS_CFG:
660 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
661 * if 1 or higher one of the 2 registers is busy.
662 */
663#define MAC_STATUS_CFG 0x1200
664#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
665
666/*
667 * PWR_PIN_CFG:
668 */
669#define PWR_PIN_CFG 0x1204
670
671/*
672 * AUTOWAKEUP_CFG: Manual power control / status register
673 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
674 * AUTOWAKE: 0:sleep, 1:awake
675 */
676#define AUTOWAKEUP_CFG 0x1208
677#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
678#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
679#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
680
681/*
682 * EDCA_AC0_CFG:
683 */
684#define EDCA_AC0_CFG 0x1300
685#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
686#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
687#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
688#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
689
690/*
691 * EDCA_AC1_CFG:
692 */
693#define EDCA_AC1_CFG 0x1304
694#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
695#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
696#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
697#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
698
699/*
700 * EDCA_AC2_CFG:
701 */
702#define EDCA_AC2_CFG 0x1308
703#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
704#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
705#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
706#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
707
708/*
709 * EDCA_AC3_CFG:
710 */
711#define EDCA_AC3_CFG 0x130c
712#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
713#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
714#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
715#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
716
717/*
718 * EDCA_TID_AC_MAP:
719 */
720#define EDCA_TID_AC_MAP 0x1310
721
722/*
723 * TX_PWR_CFG_0:
724 */
725#define TX_PWR_CFG_0 0x1314
726#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
727#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
728#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
729#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
730#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
731#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
732#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
733#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
734
735/*
736 * TX_PWR_CFG_1:
737 */
738#define TX_PWR_CFG_1 0x1318
739#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
740#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
741#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
742#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
743#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
744#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
745#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
746#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
747
748/*
749 * TX_PWR_CFG_2:
750 */
751#define TX_PWR_CFG_2 0x131c
752#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
753#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
754#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
755#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
756#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
757#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
758#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
759#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
760
761/*
762 * TX_PWR_CFG_3:
763 */
764#define TX_PWR_CFG_3 0x1320
765#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
766#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
767#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
768#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
769#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
770#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
771#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
772#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
773
774/*
775 * TX_PWR_CFG_4:
776 */
777#define TX_PWR_CFG_4 0x1324
778#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
779#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
780#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
781#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
782
783/*
784 * TX_PIN_CFG:
785 */
786#define TX_PIN_CFG 0x1328
787#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
788#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
789#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
790#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
791#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
792#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
793#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
794#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
795#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
796#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
797#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
798#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
799#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
800#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
801#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
802#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
803#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
804#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
805#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
806#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
807
808/*
809 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
810 */
811#define TX_BAND_CFG 0x132c
812#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
813#define TX_BAND_CFG_A FIELD32(0x00000002)
814#define TX_BAND_CFG_BG FIELD32(0x00000004)
815
816/*
817 * TX_SW_CFG0:
818 */
819#define TX_SW_CFG0 0x1330
820
821/*
822 * TX_SW_CFG1:
823 */
824#define TX_SW_CFG1 0x1334
825
826/*
827 * TX_SW_CFG2:
828 */
829#define TX_SW_CFG2 0x1338
830
831/*
832 * TXOP_THRES_CFG:
833 */
834#define TXOP_THRES_CFG 0x133c
835
836/*
837 * TXOP_CTRL_CFG:
838 */
839#define TXOP_CTRL_CFG 0x1340
840
841/*
842 * TX_RTS_CFG:
843 * RTS_THRES: unit:byte
844 * RTS_FBK_EN: enable rts rate fallback
845 */
846#define TX_RTS_CFG 0x1344
847#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
848#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
849#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
850
851/*
852 * TX_TIMEOUT_CFG:
853 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
854 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
855 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
856 * it is recommended that:
857 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
858 */
859#define TX_TIMEOUT_CFG 0x1348
860#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
861#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
862#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
863
864/*
865 * TX_RTY_CFG:
866 * SHORT_RTY_LIMIT: short retry limit
867 * LONG_RTY_LIMIT: long retry limit
868 * LONG_RTY_THRE: Long retry threshoold
869 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
870 * 0:expired by retry limit, 1: expired by mpdu life timer
871 * AGG_RTY_MODE: Aggregate MPDU retry mode
872 * 0:expired by retry limit, 1: expired by mpdu life timer
873 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
874 */
875#define TX_RTY_CFG 0x134c
876#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
877#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
878#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
879#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
880#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
881#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
882
883/*
884 * TX_LINK_CFG:
885 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
886 * MFB_ENABLE: TX apply remote MFB 1:enable
887 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
888 * 0: not apply remote remote unsolicit (MFS=7)
889 * TX_MRQ_EN: MCS request TX enable
890 * TX_RDG_EN: RDG TX enable
891 * TX_CF_ACK_EN: Piggyback CF-ACK enable
892 * REMOTE_MFB: remote MCS feedback
893 * REMOTE_MFS: remote MCS feedback sequence number
894 */
895#define TX_LINK_CFG 0x1350
896#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
897#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
898#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
899#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
900#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
901#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
902#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
903#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
904
905/*
906 * HT_FBK_CFG0:
907 */
908#define HT_FBK_CFG0 0x1354
909#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
910#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
911#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
912#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
913#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
914#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
915#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
916#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
917
918/*
919 * HT_FBK_CFG1:
920 */
921#define HT_FBK_CFG1 0x1358
922#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
923#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
924#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
925#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
926#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
927#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
928#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
929#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
930
931/*
932 * LG_FBK_CFG0:
933 */
934#define LG_FBK_CFG0 0x135c
935#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
936#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
937#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
938#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
939#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
940#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
941#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
942#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
943
944/*
945 * LG_FBK_CFG1:
946 */
947#define LG_FBK_CFG1 0x1360
948#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
949#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
950#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
951#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
952
953/*
954 * CCK_PROT_CFG: CCK Protection
955 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
956 * PROTECT_CTRL: Protection control frame type for CCK TX
957 * 0:none, 1:RTS/CTS, 2:CTS-to-self
958 * PROTECT_NAV: TXOP protection type for CCK TX
959 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
960 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
961 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
962 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
963 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
964 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
965 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
966 * RTS_TH_EN: RTS threshold enable on CCK TX
967 */
968#define CCK_PROT_CFG 0x1364
969#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
970#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
971#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
972#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
973#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
974#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
975#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
976#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
977#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
978#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
979
980/*
981 * OFDM_PROT_CFG: OFDM Protection
982 */
983#define OFDM_PROT_CFG 0x1368
984#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
985#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
986#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
987#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
988#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
989#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
990#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
991#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
992#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
993#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
994
995/*
996 * MM20_PROT_CFG: MM20 Protection
997 */
998#define MM20_PROT_CFG 0x136c
999#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1000#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1001#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1002#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1003#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1004#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1005#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1006#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1007#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1008#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1009
1010/*
1011 * MM40_PROT_CFG: MM40 Protection
1012 */
1013#define MM40_PROT_CFG 0x1370
1014#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1015#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1016#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1017#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1018#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1019#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1020#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1021#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1022#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1023#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1024
1025/*
1026 * GF20_PROT_CFG: GF20 Protection
1027 */
1028#define GF20_PROT_CFG 0x1374
1029#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1030#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1031#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1032#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1033#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1034#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1035#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1036#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1037#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1038#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1039
1040/*
1041 * GF40_PROT_CFG: GF40 Protection
1042 */
1043#define GF40_PROT_CFG 0x1378
1044#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1045#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1046#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1047#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1048#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1049#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1050#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1051#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1052#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1053#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1054
1055/*
1056 * EXP_CTS_TIME:
1057 */
1058#define EXP_CTS_TIME 0x137c
1059
1060/*
1061 * EXP_ACK_TIME:
1062 */
1063#define EXP_ACK_TIME 0x1380
1064
1065/*
1066 * RX_FILTER_CFG: RX configuration register.
1067 */
1068#define RX_FILTER_CFG 0x1400
1069#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1070#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1071#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1072#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1073#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1074#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1075#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1076#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1077#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1078#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1079#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1080#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1081#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1082#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1083#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1084#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1085#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1086
1087/*
1088 * AUTO_RSP_CFG:
1089 * AUTORESPONDER: 0: disable, 1: enable
1090 * BAC_ACK_POLICY: 0:long, 1:short preamble
1091 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1092 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1093 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1094 * DUAL_CTS_EN: Power bit value in control frame
1095 * ACK_CTS_PSM_BIT:Power bit value in control frame
1096 */
1097#define AUTO_RSP_CFG 0x1404
1098#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1099#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1100#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1101#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1102#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1103#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1104#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1105
1106/*
1107 * LEGACY_BASIC_RATE:
1108 */
1109#define LEGACY_BASIC_RATE 0x1408
1110
1111/*
1112 * HT_BASIC_RATE:
1113 */
1114#define HT_BASIC_RATE 0x140c
1115
1116/*
1117 * HT_CTRL_CFG:
1118 */
1119#define HT_CTRL_CFG 0x1410
1120
1121/*
1122 * SIFS_COST_CFG:
1123 */
1124#define SIFS_COST_CFG 0x1414
1125
1126/*
1127 * RX_PARSER_CFG:
1128 * Set NAV for all received frames
1129 */
1130#define RX_PARSER_CFG 0x1418
1131
1132/*
1133 * TX_SEC_CNT0:
1134 */
1135#define TX_SEC_CNT0 0x1500
1136
1137/*
1138 * RX_SEC_CNT0:
1139 */
1140#define RX_SEC_CNT0 0x1504
1141
1142/*
1143 * CCMP_FC_MUTE:
1144 */
1145#define CCMP_FC_MUTE 0x1508
1146
1147/*
1148 * TXOP_HLDR_ADDR0:
1149 */
1150#define TXOP_HLDR_ADDR0 0x1600
1151
1152/*
1153 * TXOP_HLDR_ADDR1:
1154 */
1155#define TXOP_HLDR_ADDR1 0x1604
1156
1157/*
1158 * TXOP_HLDR_ET:
1159 */
1160#define TXOP_HLDR_ET 0x1608
1161
1162/*
1163 * QOS_CFPOLL_RA_DW0:
1164 */
1165#define QOS_CFPOLL_RA_DW0 0x160c
1166
1167/*
1168 * QOS_CFPOLL_RA_DW1:
1169 */
1170#define QOS_CFPOLL_RA_DW1 0x1610
1171
1172/*
1173 * QOS_CFPOLL_QC:
1174 */
1175#define QOS_CFPOLL_QC 0x1614
1176
1177/*
1178 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1179 */
1180#define RX_STA_CNT0 0x1700
1181#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1182#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1183
1184/*
1185 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1186 */
1187#define RX_STA_CNT1 0x1704
1188#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1189#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1190
1191/*
1192 * RX_STA_CNT2:
1193 */
1194#define RX_STA_CNT2 0x1708
1195#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1196#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1197
1198/*
1199 * TX_STA_CNT0: TX Beacon count
1200 */
1201#define TX_STA_CNT0 0x170c
1202#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1203#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1204
1205/*
1206 * TX_STA_CNT1: TX tx count
1207 */
1208#define TX_STA_CNT1 0x1710
1209#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1210#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1211
1212/*
1213 * TX_STA_CNT2: TX tx count
1214 */
1215#define TX_STA_CNT2 0x1714
1216#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1217#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1218
1219/*
1220 * TX_STA_FIFO: TX Result for specific PID status fifo register
1221 */
1222#define TX_STA_FIFO 0x1718
1223#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1224#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1225#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1226#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1227#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1228#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1229#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1230#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1231#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1232
1233/*
1234 * TX_AGG_CNT: Debug counter
1235 */
1236#define TX_AGG_CNT 0x171c
1237#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1238#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1239
1240/*
1241 * TX_AGG_CNT0:
1242 */
1243#define TX_AGG_CNT0 0x1720
1244#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1245#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1246
1247/*
1248 * TX_AGG_CNT1:
1249 */
1250#define TX_AGG_CNT1 0x1724
1251#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1252#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1253
1254/*
1255 * TX_AGG_CNT2:
1256 */
1257#define TX_AGG_CNT2 0x1728
1258#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1259#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1260
1261/*
1262 * TX_AGG_CNT3:
1263 */
1264#define TX_AGG_CNT3 0x172c
1265#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1266#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1267
1268/*
1269 * TX_AGG_CNT4:
1270 */
1271#define TX_AGG_CNT4 0x1730
1272#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1273#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1274
1275/*
1276 * TX_AGG_CNT5:
1277 */
1278#define TX_AGG_CNT5 0x1734
1279#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1280#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1281
1282/*
1283 * TX_AGG_CNT6:
1284 */
1285#define TX_AGG_CNT6 0x1738
1286#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1287#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1288
1289/*
1290 * TX_AGG_CNT7:
1291 */
1292#define TX_AGG_CNT7 0x173c
1293#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1294#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1295
1296/*
1297 * MPDU_DENSITY_CNT:
1298 * TX_ZERO_DEL: TX zero length delimiter count
1299 * RX_ZERO_DEL: RX zero length delimiter count
1300 */
1301#define MPDU_DENSITY_CNT 0x1740
1302#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1303#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1304
1305/*
1306 * Security key table memory.
1307 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1308 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1309 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1310 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1311 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1312 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1313 */
1314#define MAC_WCID_BASE 0x1800
1315#define PAIRWISE_KEY_TABLE_BASE 0x4000
1316#define MAC_IVEIV_TABLE_BASE 0x6000
1317#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1318#define SHARED_KEY_TABLE_BASE 0x6c00
1319#define SHARED_KEY_MODE_BASE 0x7000
1320
1321#define MAC_WCID_ENTRY(__idx) \
1322 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1323#define PAIRWISE_KEY_ENTRY(__idx) \
1324 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1325#define MAC_IVEIV_ENTRY(__idx) \
1326 ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) )
1327#define MAC_WCID_ATTR_ENTRY(__idx) \
1328 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1329#define SHARED_KEY_ENTRY(__idx) \
1330 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1331#define SHARED_KEY_MODE_ENTRY(__idx) \
1332 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1333
1334struct mac_wcid_entry {
1335 u8 mac[6];
1336 u8 reserved[2];
1337} __attribute__ ((packed));
1338
1339struct hw_key_entry {
1340 u8 key[16];
1341 u8 tx_mic[8];
1342 u8 rx_mic[8];
1343} __attribute__ ((packed));
1344
1345struct mac_iveiv_entry {
1346 u8 iv[8];
1347} __attribute__ ((packed));
1348
1349/*
1350 * MAC_WCID_ATTRIBUTE:
1351 */
1352#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1353#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1354#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1355#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1356
1357/*
1358 * SHARED_KEY_MODE:
1359 */
1360#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1361#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1362#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1363#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1364#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1365#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1366#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1367#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1368
1369/*
1370 * HOST-MCU communication
1371 */
1372
1373/*
1374 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1375 */
1376#define H2M_MAILBOX_CSR 0x7010
1377#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1378#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1379#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1380#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1381
1382/*
1383 * H2M_MAILBOX_CID:
1384 */
1385#define H2M_MAILBOX_CID 0x7014
1386#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1387#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1388#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1389#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1390
1391/*
1392 * H2M_MAILBOX_STATUS:
1393 */
1394#define H2M_MAILBOX_STATUS 0x701c
1395
1396/*
1397 * H2M_INT_SRC:
1398 */
1399#define H2M_INT_SRC 0x7024
1400
1401/*
1402 * H2M_BBP_AGENT:
1403 */
1404#define H2M_BBP_AGENT 0x7028
1405
1406/*
1407 * MCU_LEDCS: LED control for MCU Mailbox.
1408 */
1409#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1410#define MCU_LEDCS_POLARITY FIELD8(0x01)
1411
1412/*
1413 * HW_CS_CTS_BASE:
1414 * Carrier-sense CTS frame base address.
1415 * It's where mac stores carrier-sense frame for carrier-sense function.
1416 */
1417#define HW_CS_CTS_BASE 0x7700
1418
1419/*
1420 * HW_DFS_CTS_BASE:
1421 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1422 */
1423#define HW_DFS_CTS_BASE 0x7780
1424
1425/*
1426 * TXRX control registers - base address 0x3000
1427 */
1428
1429/*
1430 * TXRX_CSR1:
1431 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1432 */
1433#define TXRX_CSR1 0x77d0
1434
1435/*
1436 * HW_DEBUG_SETTING_BASE:
1437 * since NULL frame won't be that long (256 byte)
1438 * We steal 16 tail bytes to save debugging settings
1439 */
1440#define HW_DEBUG_SETTING_BASE 0x77f0
1441#define HW_DEBUG_SETTING_BASE2 0x7770
1442
1443/*
1444 * HW_BEACON_BASE
1445 * In order to support maximum 8 MBSS and its maximum length
1446 * is 512 bytes for each beacon
1447 * Three section discontinue memory segments will be used.
1448 * 1. The original region for BCN 0~3
1449 * 2. Extract memory from FCE table for BCN 4~5
1450 * 3. Extract memory from Pair-wise key table for BCN 6~7
1451 * It occupied those memory of wcid 238~253 for BCN 6
1452 * and wcid 222~237 for BCN 7
1453 *
1454 * IMPORTANT NOTE: Not sure why legacy driver does this,
1455 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1456 */
1457#define HW_BEACON_BASE0 0x7800
1458#define HW_BEACON_BASE1 0x7a00
1459#define HW_BEACON_BASE2 0x7c00
1460#define HW_BEACON_BASE3 0x7e00
1461#define HW_BEACON_BASE4 0x7200
1462#define HW_BEACON_BASE5 0x7400
1463#define HW_BEACON_BASE6 0x5dc0
1464#define HW_BEACON_BASE7 0x5bc0
1465
1466#define HW_BEACON_OFFSET(__index) \
1467 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1468 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1469 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1470
1471/*
1472 * BBP registers.
1473 * The wordsize of the BBP is 8 bits.
1474 */
1475
1476/*
1477 * BBP 1: TX Antenna
1478 */
1479#define BBP1_TX_POWER FIELD8(0x07)
1480#define BBP1_TX_ANTENNA FIELD8(0x18)
1481
1482/*
1483 * BBP 3: RX Antenna
1484 */
1485#define BBP3_RX_ANTENNA FIELD8(0x18)
1486#define BBP3_HT40_PLUS FIELD8(0x20)
1487
1488/*
1489 * BBP 4: Bandwidth
1490 */
1491#define BBP4_TX_BF FIELD8(0x01)
1492#define BBP4_BANDWIDTH FIELD8(0x18)
1493
1494/*
1495 * RFCSR registers
1496 * The wordsize of the RFCSR is 8 bits.
1497 */
1498
1499/*
1500 * RFCSR 6:
1501 */
1502#define RFCSR6_R FIELD8(0x03)
1503
1504/*
1505 * RFCSR 7:
1506 */
1507#define RFCSR7_RF_TUNING FIELD8(0x01)
1508
1509/*
1510 * RFCSR 12:
1511 */
1512#define RFCSR12_TX_POWER FIELD8(0x1f)
1513
1514/*
1515 * RFCSR 22:
1516 */
1517#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1518
1519/*
1520 * RFCSR 23:
1521 */
1522#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1523
1524/*
1525 * RFCSR 30:
1526 */
1527#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1528
1529/*
1530 * RF registers
1531 */
1532
1533/*
1534 * RF 2
1535 */
1536#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1537#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1538#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1539
1540/*
1541 * RF 3
1542 */
1543#define RF3_TXPOWER_G FIELD32(0x00003e00)
1544#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1545#define RF3_TXPOWER_A FIELD32(0x00003c00)
1546
1547/*
1548 * RF 4
1549 */
1550#define RF4_TXPOWER_G FIELD32(0x000007c0)
1551#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1552#define RF4_TXPOWER_A FIELD32(0x00000780)
1553#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1554#define RF4_HT40 FIELD32(0x00200000)
1555
1556/*
1557 * EEPROM content.
1558 * The wordsize of the EEPROM is 16 bits.
1559 */
1560
1561/*
1562 * EEPROM Version
1563 */
1564#define EEPROM_VERSION 0x0001
1565#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1566#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1567
1568/*
1569 * HW MAC address.
1570 */
1571#define EEPROM_MAC_ADDR_0 0x0002
1572#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1573#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1574#define EEPROM_MAC_ADDR_1 0x0003
1575#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1576#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1577#define EEPROM_MAC_ADDR_2 0x0004
1578#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1579#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1580
1581/*
1582 * EEPROM ANTENNA config
1583 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1584 * TXPATH: 1: 1T, 2: 2T
1585 */
1586#define EEPROM_ANTENNA 0x001a
1587#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1588#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1589#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1590
1591/*
1592 * EEPROM NIC config
1593 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1594 */
1595#define EEPROM_NIC 0x001b
1596#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1597#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1598#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1599#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1600#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1601#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1602#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1603#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1604#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1605#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1606
1607/*
1608 * EEPROM frequency
1609 */
1610#define EEPROM_FREQ 0x001d
1611#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1612#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1613#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1614
1615/*
1616 * EEPROM LED
1617 * POLARITY_RDY_G: Polarity RDY_G setting.
1618 * POLARITY_RDY_A: Polarity RDY_A setting.
1619 * POLARITY_ACT: Polarity ACT setting.
1620 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1621 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1622 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1623 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1624 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1625 * LED_MODE: Led mode.
1626 */
1627#define EEPROM_LED1 0x001e
1628#define EEPROM_LED2 0x001f
1629#define EEPROM_LED3 0x0020
1630#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1631#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1632#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1633#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1634#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1635#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1636#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1637#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1638#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1639
1640/*
1641 * EEPROM LNA
1642 */
1643#define EEPROM_LNA 0x0022
1644#define EEPROM_LNA_BG FIELD16(0x00ff)
1645#define EEPROM_LNA_A0 FIELD16(0xff00)
1646
1647/*
1648 * EEPROM RSSI BG offset
1649 */
1650#define EEPROM_RSSI_BG 0x0023
1651#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1652#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1653
1654/*
1655 * EEPROM RSSI BG2 offset
1656 */
1657#define EEPROM_RSSI_BG2 0x0024
1658#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1659#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1660
1661/*
1662 * EEPROM RSSI A offset
1663 */
1664#define EEPROM_RSSI_A 0x0025
1665#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1666#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1667
1668/*
1669 * EEPROM RSSI A2 offset
1670 */
1671#define EEPROM_RSSI_A2 0x0026
1672#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1673#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1674
1675/*
1676 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1677 * This is delta in 40MHZ.
1678 * VALUE: Tx Power dalta value (MAX=4)
1679 * TYPE: 1: Plus the delta value, 0: minus the delta value
1680 * TXPOWER: Enable:
1681 */
1682#define EEPROM_TXPOWER_DELTA 0x0028
1683#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1684#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1685#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1686
1687/*
1688 * EEPROM TXPOWER 802.11BG
1689 */
1690#define EEPROM_TXPOWER_BG1 0x0029
1691#define EEPROM_TXPOWER_BG2 0x0030
1692#define EEPROM_TXPOWER_BG_SIZE 7
1693#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1694#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1695
1696/*
1697 * EEPROM TXPOWER 802.11A
1698 */
1699#define EEPROM_TXPOWER_A1 0x003c
1700#define EEPROM_TXPOWER_A2 0x0053
1701#define EEPROM_TXPOWER_A_SIZE 6
1702#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1703#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1704
1705/*
1706 * EEPROM TXpower byrate: 20MHZ power
1707 */
1708#define EEPROM_TXPOWER_BYRATE 0x006f
1709
1710/*
1711 * EEPROM BBP.
1712 */
1713#define EEPROM_BBP_START 0x0078
1714#define EEPROM_BBP_SIZE 16
1715#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1716#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1717
1718/*
1719 * MCU mailbox commands.
1720 */
1721#define MCU_SLEEP 0x30
1722#define MCU_WAKEUP 0x31
1723#define MCU_RADIO_OFF 0x35
1724#define MCU_CURRENT 0x36
1725#define MCU_LED 0x50
1726#define MCU_LED_STRENGTH 0x51
1727#define MCU_LED_1 0x52
1728#define MCU_LED_2 0x53
1729#define MCU_LED_3 0x54
1730#define MCU_RADAR 0x60
1731#define MCU_BOOT_SIGNAL 0x72
1732#define MCU_BBP_SIGNAL 0x80
1733#define MCU_POWER_SAVE 0x83
1734
1735/*
1736 * MCU mailbox tokens
1737 */
1738#define TOKEN_WAKUP 3
1739
1740/*
1741 * DMA descriptor defines.
1742 */
1743#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1744#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1745
1746/*
1747 * TX WI structure
1748 */
1749
1750/*
1751 * Word0
1752 * FRAG: 1 To inform TKIP engine this is a fragment.
1753 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1754 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1755 * BW: Channel bandwidth 20MHz or 40 MHz
1756 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1757 */
1758#define TXWI_W0_FRAG FIELD32(0x00000001)
1759#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1760#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1761#define TXWI_W0_TS FIELD32(0x00000008)
1762#define TXWI_W0_AMPDU FIELD32(0x00000010)
1763#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1764#define TXWI_W0_TX_OP FIELD32(0x00000300)
1765#define TXWI_W0_MCS FIELD32(0x007f0000)
1766#define TXWI_W0_BW FIELD32(0x00800000)
1767#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1768#define TXWI_W0_STBC FIELD32(0x06000000)
1769#define TXWI_W0_IFS FIELD32(0x08000000)
1770#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1771
1772/*
1773 * Word1
1774 */
1775#define TXWI_W1_ACK FIELD32(0x00000001)
1776#define TXWI_W1_NSEQ FIELD32(0x00000002)
1777#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1778#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1779#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1780#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1781
1782/*
1783 * Word2
1784 */
1785#define TXWI_W2_IV FIELD32(0xffffffff)
1786
1787/*
1788 * Word3
1789 */
1790#define TXWI_W3_EIV FIELD32(0xffffffff)
1791
1792/*
1793 * RX WI structure
1794 */
1795
1796/*
1797 * Word0
1798 */
1799#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1800#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1801#define RXWI_W0_BSSID FIELD32(0x00001c00)
1802#define RXWI_W0_UDF FIELD32(0x0000e000)
1803#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1804#define RXWI_W0_TID FIELD32(0xf0000000)
1805
1806/*
1807 * Word1
1808 */
1809#define RXWI_W1_FRAG FIELD32(0x0000000f)
1810#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1811#define RXWI_W1_MCS FIELD32(0x007f0000)
1812#define RXWI_W1_BW FIELD32(0x00800000)
1813#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1814#define RXWI_W1_STBC FIELD32(0x06000000)
1815#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1816
1817/*
1818 * Word2
1819 */
1820#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1821#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1822#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1823
1824/*
1825 * Word3
1826 */
1827#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1828#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1829
1830/*
1831 * Macros for converting txpower from EEPROM to mac80211 value
1832 * and from mac80211 value to register value.
1833 */
1834#define MIN_G_TXPOWER 0
1835#define MIN_A_TXPOWER -7
1836#define MAX_G_TXPOWER 31
1837#define MAX_A_TXPOWER 15
1838#define DEFAULT_TXPOWER 5
1839
1840#define TXPOWER_G_FROM_DEV(__txpower) \
1841 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1842
1843#define TXPOWER_G_TO_DEV(__txpower) \
1844 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1845
1846#define TXPOWER_A_FROM_DEV(__txpower) \
1847 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1848
1849#define TXPOWER_A_TO_DEV(__txpower) \
1850 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1851
1852#endif /* RT2800_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
new file mode 100644
index 000000000000..c015ce9fdd09
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -0,0 +1,2325 @@
1/*
2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
4
5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/slab.h>
39
40#include "rt2x00.h"
41#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
42#include "rt2x00usb.h"
43#endif
44#if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
45#include "rt2x00pci.h"
46#endif
47#include "rt2800lib.h"
48#include "rt2800.h"
49#include "rt2800usb.h"
50
51MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
52MODULE_DESCRIPTION("rt2800 library");
53MODULE_LICENSE("GPL");
54
55/*
56 * Register access.
57 * All access to the CSR registers will go through the methods
58 * rt2800_register_read and rt2800_register_write.
59 * BBP and RF register require indirect register access,
60 * and use the CSR registers BBPCSR and RFCSR to achieve this.
61 * These indirect registers work with busy bits,
62 * and we will try maximal REGISTER_BUSY_COUNT times to access
63 * the register while taking a REGISTER_BUSY_DELAY us delay
64 * between each attampt. When the busy bit is still set at that time,
65 * the access attempt is considered to have failed,
66 * and we will print an error.
67 * The _lock versions must be used if you already hold the csr_mutex
68 */
69#define WAIT_FOR_BBP(__dev, __reg) \
70 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
71#define WAIT_FOR_RFCSR(__dev, __reg) \
72 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
73#define WAIT_FOR_RF(__dev, __reg) \
74 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
75#define WAIT_FOR_MCU(__dev, __reg) \
76 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
77 H2M_MAILBOX_CSR_OWNER, (__reg))
78
79static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
80 const unsigned int word, const u8 value)
81{
82 u32 reg;
83
84 mutex_lock(&rt2x00dev->csr_mutex);
85
86 /*
87 * Wait until the BBP becomes available, afterwards we
88 * can safely write the new data into the register.
89 */
90 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
91 reg = 0;
92 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
93 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
94 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
95 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
96 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
97 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
98
99 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
100 }
101
102 mutex_unlock(&rt2x00dev->csr_mutex);
103}
104
105static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
106 const unsigned int word, u8 *value)
107{
108 u32 reg;
109
110 mutex_lock(&rt2x00dev->csr_mutex);
111
112 /*
113 * Wait until the BBP becomes available, afterwards we
114 * can safely write the read request into the register.
115 * After the data has been written, we wait until hardware
116 * returns the correct value, if at any time the register
117 * doesn't become available in time, reg will be 0xffffffff
118 * which means we return 0xff to the caller.
119 */
120 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
121 reg = 0;
122 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
123 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
124 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
125 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
126 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
127
128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
129
130 WAIT_FOR_BBP(rt2x00dev, &reg);
131 }
132
133 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
134
135 mutex_unlock(&rt2x00dev->csr_mutex);
136}
137
138static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
139 const unsigned int word, const u8 value)
140{
141 u32 reg;
142
143 mutex_lock(&rt2x00dev->csr_mutex);
144
145 /*
146 * Wait until the RFCSR becomes available, afterwards we
147 * can safely write the new data into the register.
148 */
149 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
150 reg = 0;
151 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
152 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
153 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
154 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
155
156 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
157 }
158
159 mutex_unlock(&rt2x00dev->csr_mutex);
160}
161
162static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
163 const unsigned int word, u8 *value)
164{
165 u32 reg;
166
167 mutex_lock(&rt2x00dev->csr_mutex);
168
169 /*
170 * Wait until the RFCSR becomes available, afterwards we
171 * can safely write the read request into the register.
172 * After the data has been written, we wait until hardware
173 * returns the correct value, if at any time the register
174 * doesn't become available in time, reg will be 0xffffffff
175 * which means we return 0xff to the caller.
176 */
177 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
178 reg = 0;
179 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
180 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
181 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
182
183 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
184
185 WAIT_FOR_RFCSR(rt2x00dev, &reg);
186 }
187
188 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
189
190 mutex_unlock(&rt2x00dev->csr_mutex);
191}
192
193static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, const u32 value)
195{
196 u32 reg;
197
198 mutex_lock(&rt2x00dev->csr_mutex);
199
200 /*
201 * Wait until the RF becomes available, afterwards we
202 * can safely write the new data into the register.
203 */
204 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
205 reg = 0;
206 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
207 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
208 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
209 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
210
211 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
212 rt2x00_rf_write(rt2x00dev, word, value);
213 }
214
215 mutex_unlock(&rt2x00dev->csr_mutex);
216}
217
218void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
219 const u8 command, const u8 token,
220 const u8 arg0, const u8 arg1)
221{
222 u32 reg;
223
224 /*
225 * SOC devices don't support MCU requests.
226 */
227 if (rt2x00_is_soc(rt2x00dev))
228 return;
229
230 mutex_lock(&rt2x00dev->csr_mutex);
231
232 /*
233 * Wait until the MCU becomes available, afterwards we
234 * can safely write the new data into the register.
235 */
236 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
237 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
238 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
239 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
240 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
241 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
242
243 reg = 0;
244 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
245 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
246 }
247
248 mutex_unlock(&rt2x00dev->csr_mutex);
249}
250EXPORT_SYMBOL_GPL(rt2800_mcu_request);
251
252int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
253{
254 unsigned int i;
255 u32 reg;
256
257 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
258 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
259 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
260 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
261 return 0;
262
263 msleep(1);
264 }
265
266 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
267 return -EACCES;
268}
269EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
270
271#ifdef CONFIG_RT2X00_LIB_DEBUGFS
272const struct rt2x00debug rt2800_rt2x00debug = {
273 .owner = THIS_MODULE,
274 .csr = {
275 .read = rt2800_register_read,
276 .write = rt2800_register_write,
277 .flags = RT2X00DEBUGFS_OFFSET,
278 .word_base = CSR_REG_BASE,
279 .word_size = sizeof(u32),
280 .word_count = CSR_REG_SIZE / sizeof(u32),
281 },
282 .eeprom = {
283 .read = rt2x00_eeprom_read,
284 .write = rt2x00_eeprom_write,
285 .word_base = EEPROM_BASE,
286 .word_size = sizeof(u16),
287 .word_count = EEPROM_SIZE / sizeof(u16),
288 },
289 .bbp = {
290 .read = rt2800_bbp_read,
291 .write = rt2800_bbp_write,
292 .word_base = BBP_BASE,
293 .word_size = sizeof(u8),
294 .word_count = BBP_SIZE / sizeof(u8),
295 },
296 .rf = {
297 .read = rt2x00_rf_read,
298 .write = rt2800_rf_write,
299 .word_base = RF_BASE,
300 .word_size = sizeof(u32),
301 .word_count = RF_SIZE / sizeof(u32),
302 },
303};
304EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
305#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
306
307int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
308{
309 u32 reg;
310
311 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
312 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
313}
314EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
315
316#ifdef CONFIG_RT2X00_LIB_LEDS
317static void rt2800_brightness_set(struct led_classdev *led_cdev,
318 enum led_brightness brightness)
319{
320 struct rt2x00_led *led =
321 container_of(led_cdev, struct rt2x00_led, led_dev);
322 unsigned int enabled = brightness != LED_OFF;
323 unsigned int bg_mode =
324 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
325 unsigned int polarity =
326 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
327 EEPROM_FREQ_LED_POLARITY);
328 unsigned int ledmode =
329 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
330 EEPROM_FREQ_LED_MODE);
331
332 if (led->type == LED_TYPE_RADIO) {
333 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
334 enabled ? 0x20 : 0);
335 } else if (led->type == LED_TYPE_ASSOC) {
336 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
337 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
338 } else if (led->type == LED_TYPE_QUALITY) {
339 /*
340 * The brightness is divided into 6 levels (0 - 5),
341 * The specs tell us the following levels:
342 * 0, 1 ,3, 7, 15, 31
343 * to determine the level in a simple way we can simply
344 * work with bitshifting:
345 * (1 << level) - 1
346 */
347 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
348 (1 << brightness / (LED_FULL / 6)) - 1,
349 polarity);
350 }
351}
352
353static int rt2800_blink_set(struct led_classdev *led_cdev,
354 unsigned long *delay_on, unsigned long *delay_off)
355{
356 struct rt2x00_led *led =
357 container_of(led_cdev, struct rt2x00_led, led_dev);
358 u32 reg;
359
360 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
361 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
362 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
363 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
364 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
365 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
366 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
367 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
368 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
369
370 return 0;
371}
372
373static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
374 struct rt2x00_led *led, enum led_type type)
375{
376 led->rt2x00dev = rt2x00dev;
377 led->type = type;
378 led->led_dev.brightness_set = rt2800_brightness_set;
379 led->led_dev.blink_set = rt2800_blink_set;
380 led->flags = LED_INITIALIZED;
381}
382#endif /* CONFIG_RT2X00_LIB_LEDS */
383
384/*
385 * Configuration handlers.
386 */
387static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
388 struct rt2x00lib_crypto *crypto,
389 struct ieee80211_key_conf *key)
390{
391 struct mac_wcid_entry wcid_entry;
392 struct mac_iveiv_entry iveiv_entry;
393 u32 offset;
394 u32 reg;
395
396 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
397
398 rt2800_register_read(rt2x00dev, offset, &reg);
399 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
400 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
401 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
402 (crypto->cmd == SET_KEY) * crypto->cipher);
403 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
404 (crypto->cmd == SET_KEY) * crypto->bssidx);
405 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
406 rt2800_register_write(rt2x00dev, offset, reg);
407
408 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
409
410 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
411 if ((crypto->cipher == CIPHER_TKIP) ||
412 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
413 (crypto->cipher == CIPHER_AES))
414 iveiv_entry.iv[3] |= 0x20;
415 iveiv_entry.iv[3] |= key->keyidx << 6;
416 rt2800_register_multiwrite(rt2x00dev, offset,
417 &iveiv_entry, sizeof(iveiv_entry));
418
419 offset = MAC_WCID_ENTRY(key->hw_key_idx);
420
421 memset(&wcid_entry, 0, sizeof(wcid_entry));
422 if (crypto->cmd == SET_KEY)
423 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
424 rt2800_register_multiwrite(rt2x00dev, offset,
425 &wcid_entry, sizeof(wcid_entry));
426}
427
428int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
429 struct rt2x00lib_crypto *crypto,
430 struct ieee80211_key_conf *key)
431{
432 struct hw_key_entry key_entry;
433 struct rt2x00_field32 field;
434 u32 offset;
435 u32 reg;
436
437 if (crypto->cmd == SET_KEY) {
438 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
439
440 memcpy(key_entry.key, crypto->key,
441 sizeof(key_entry.key));
442 memcpy(key_entry.tx_mic, crypto->tx_mic,
443 sizeof(key_entry.tx_mic));
444 memcpy(key_entry.rx_mic, crypto->rx_mic,
445 sizeof(key_entry.rx_mic));
446
447 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
448 rt2800_register_multiwrite(rt2x00dev, offset,
449 &key_entry, sizeof(key_entry));
450 }
451
452 /*
453 * The cipher types are stored over multiple registers
454 * starting with SHARED_KEY_MODE_BASE each word will have
455 * 32 bits and contains the cipher types for 2 bssidx each.
456 * Using the correct defines correctly will cause overhead,
457 * so just calculate the correct offset.
458 */
459 field.bit_offset = 4 * (key->hw_key_idx % 8);
460 field.bit_mask = 0x7 << field.bit_offset;
461
462 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
463
464 rt2800_register_read(rt2x00dev, offset, &reg);
465 rt2x00_set_field32(&reg, field,
466 (crypto->cmd == SET_KEY) * crypto->cipher);
467 rt2800_register_write(rt2x00dev, offset, reg);
468
469 /*
470 * Update WCID information
471 */
472 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
473
474 return 0;
475}
476EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
477
478int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
479 struct rt2x00lib_crypto *crypto,
480 struct ieee80211_key_conf *key)
481{
482 struct hw_key_entry key_entry;
483 u32 offset;
484
485 if (crypto->cmd == SET_KEY) {
486 /*
487 * 1 pairwise key is possible per AID, this means that the AID
488 * equals our hw_key_idx. Make sure the WCID starts _after_ the
489 * last possible shared key entry.
490 */
491 if (crypto->aid > (256 - 32))
492 return -ENOSPC;
493
494 key->hw_key_idx = 32 + crypto->aid;
495
496 memcpy(key_entry.key, crypto->key,
497 sizeof(key_entry.key));
498 memcpy(key_entry.tx_mic, crypto->tx_mic,
499 sizeof(key_entry.tx_mic));
500 memcpy(key_entry.rx_mic, crypto->rx_mic,
501 sizeof(key_entry.rx_mic));
502
503 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
504 rt2800_register_multiwrite(rt2x00dev, offset,
505 &key_entry, sizeof(key_entry));
506 }
507
508 /*
509 * Update WCID information
510 */
511 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
512
513 return 0;
514}
515EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
516
517void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
518 const unsigned int filter_flags)
519{
520 u32 reg;
521
522 /*
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
527 */
528 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
529 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
530 !(filter_flags & FIF_FCSFAIL));
531 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
532 !(filter_flags & FIF_PLCPFAIL));
533 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
534 !(filter_flags & FIF_PROMISC_IN_BSS));
535 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
536 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
537 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
538 !(filter_flags & FIF_ALLMULTI));
539 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
540 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
541 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
542 !(filter_flags & FIF_CONTROL));
543 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
544 !(filter_flags & FIF_CONTROL));
545 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
546 !(filter_flags & FIF_CONTROL));
547 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
548 !(filter_flags & FIF_CONTROL));
549 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
550 !(filter_flags & FIF_CONTROL));
551 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
552 !(filter_flags & FIF_PSPOLL));
553 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
554 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
555 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
556 !(filter_flags & FIF_CONTROL));
557 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
558}
559EXPORT_SYMBOL_GPL(rt2800_config_filter);
560
561void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
562 struct rt2x00intf_conf *conf, const unsigned int flags)
563{
564 unsigned int beacon_base;
565 u32 reg;
566
567 if (flags & CONFIG_UPDATE_TYPE) {
568 /*
569 * Clear current synchronisation setup.
570 * For the Beacon base registers we only need to clear
571 * the first byte since that byte contains the VALID and OWNER
572 * bits which (when set to 0) will invalidate the entire beacon.
573 */
574 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
575 rt2800_register_write(rt2x00dev, beacon_base, 0);
576
577 /*
578 * Enable synchronisation.
579 */
580 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
581 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
582 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
583 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
584 (conf->sync == TSF_SYNC_BEACON));
585 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
586 }
587
588 if (flags & CONFIG_UPDATE_MAC) {
589 reg = le32_to_cpu(conf->mac[1]);
590 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
591 conf->mac[1] = cpu_to_le32(reg);
592
593 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
594 conf->mac, sizeof(conf->mac));
595 }
596
597 if (flags & CONFIG_UPDATE_BSSID) {
598 reg = le32_to_cpu(conf->bssid[1]);
599 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
600 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
601 conf->bssid[1] = cpu_to_le32(reg);
602
603 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
604 conf->bssid, sizeof(conf->bssid));
605 }
606}
607EXPORT_SYMBOL_GPL(rt2800_config_intf);
608
609void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
610{
611 u32 reg;
612
613 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
614 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
615 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
616
617 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
618 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
619 !!erp->short_preamble);
620 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
621 !!erp->short_preamble);
622 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
623
624 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
625 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
626 erp->cts_protection ? 2 : 0);
627 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
628
629 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
630 erp->basic_rates);
631 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
632
633 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
634 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
635 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
636 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
637
638 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
639 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
640 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
641 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
642 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
643 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
644 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
645
646 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
647 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
648 erp->beacon_int * 16);
649 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
650}
651EXPORT_SYMBOL_GPL(rt2800_config_erp);
652
653void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
654{
655 u8 r1;
656 u8 r3;
657
658 rt2800_bbp_read(rt2x00dev, 1, &r1);
659 rt2800_bbp_read(rt2x00dev, 3, &r3);
660
661 /*
662 * Configure the TX antenna.
663 */
664 switch ((int)ant->tx) {
665 case 1:
666 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
667 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
668 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
669 break;
670 case 2:
671 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
672 break;
673 case 3:
674 /* Do nothing */
675 break;
676 }
677
678 /*
679 * Configure the RX antenna.
680 */
681 switch ((int)ant->rx) {
682 case 1:
683 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
684 break;
685 case 2:
686 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
687 break;
688 case 3:
689 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
690 break;
691 }
692
693 rt2800_bbp_write(rt2x00dev, 3, r3);
694 rt2800_bbp_write(rt2x00dev, 1, r1);
695}
696EXPORT_SYMBOL_GPL(rt2800_config_ant);
697
698static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
699 struct rt2x00lib_conf *libconf)
700{
701 u16 eeprom;
702 short lna_gain;
703
704 if (libconf->rf.channel <= 14) {
705 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
706 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
707 } else if (libconf->rf.channel <= 64) {
708 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
709 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
710 } else if (libconf->rf.channel <= 128) {
711 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
712 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
713 } else {
714 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
715 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
716 }
717
718 rt2x00dev->lna_gain = lna_gain;
719}
720
721static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
722 struct ieee80211_conf *conf,
723 struct rf_channel *rf,
724 struct channel_info *info)
725{
726 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
727
728 if (rt2x00dev->default_ant.tx == 1)
729 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
730
731 if (rt2x00dev->default_ant.rx == 1) {
732 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
733 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
734 } else if (rt2x00dev->default_ant.rx == 2)
735 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
736
737 if (rf->channel > 14) {
738 /*
739 * When TX power is below 0, we should increase it by 7 to
740 * make it a positive value (Minumum value is -7).
741 * However this means that values between 0 and 7 have
742 * double meaning, and we should set a 7DBm boost flag.
743 */
744 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
745 (info->tx_power1 >= 0));
746
747 if (info->tx_power1 < 0)
748 info->tx_power1 += 7;
749
750 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
751 TXPOWER_A_TO_DEV(info->tx_power1));
752
753 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
754 (info->tx_power2 >= 0));
755
756 if (info->tx_power2 < 0)
757 info->tx_power2 += 7;
758
759 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
760 TXPOWER_A_TO_DEV(info->tx_power2));
761 } else {
762 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
763 TXPOWER_G_TO_DEV(info->tx_power1));
764 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
765 TXPOWER_G_TO_DEV(info->tx_power2));
766 }
767
768 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
769
770 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
771 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
772 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
773 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
774
775 udelay(200);
776
777 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
778 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
779 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
780 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
781
782 udelay(200);
783
784 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
785 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
786 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
787 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
788}
789
790static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
791 struct ieee80211_conf *conf,
792 struct rf_channel *rf,
793 struct channel_info *info)
794{
795 u8 rfcsr;
796
797 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
798 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
799
800 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
801 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
802 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
803
804 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
805 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
806 TXPOWER_G_TO_DEV(info->tx_power1));
807 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
808
809 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
810 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
811 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
812
813 rt2800_rfcsr_write(rt2x00dev, 24,
814 rt2x00dev->calibration[conf_is_ht40(conf)]);
815
816 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
817 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
818 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
819}
820
821static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
822 struct ieee80211_conf *conf,
823 struct rf_channel *rf,
824 struct channel_info *info)
825{
826 u32 reg;
827 unsigned int tx_pin;
828 u8 bbp;
829
830 if ((rt2x00_rt(rt2x00dev, RT3070) ||
831 rt2x00_rt(rt2x00dev, RT3090)) &&
832 (rt2x00_rf(rt2x00dev, RF2020) ||
833 rt2x00_rf(rt2x00dev, RF3020) ||
834 rt2x00_rf(rt2x00dev, RF3021) ||
835 rt2x00_rf(rt2x00dev, RF3022)))
836 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
837 else
838 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
839
840 /*
841 * Change BBP settings
842 */
843 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
844 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
845 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
846 rt2800_bbp_write(rt2x00dev, 86, 0);
847
848 if (rf->channel <= 14) {
849 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
850 rt2800_bbp_write(rt2x00dev, 82, 0x62);
851 rt2800_bbp_write(rt2x00dev, 75, 0x46);
852 } else {
853 rt2800_bbp_write(rt2x00dev, 82, 0x84);
854 rt2800_bbp_write(rt2x00dev, 75, 0x50);
855 }
856 } else {
857 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
858
859 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
860 rt2800_bbp_write(rt2x00dev, 75, 0x46);
861 else
862 rt2800_bbp_write(rt2x00dev, 75, 0x50);
863 }
864
865 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
866 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
867 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
868 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
869 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
870
871 tx_pin = 0;
872
873 /* Turn on unused PA or LNA when not using 1T or 1R */
874 if (rt2x00dev->default_ant.tx != 1) {
875 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
876 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
877 }
878
879 /* Turn on unused PA or LNA when not using 1T or 1R */
880 if (rt2x00dev->default_ant.rx != 1) {
881 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
882 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
883 }
884
885 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
886 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
887 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
888 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
889 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
890 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
891
892 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
893
894 rt2800_bbp_read(rt2x00dev, 4, &bbp);
895 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
896 rt2800_bbp_write(rt2x00dev, 4, bbp);
897
898 rt2800_bbp_read(rt2x00dev, 3, &bbp);
899 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
900 rt2800_bbp_write(rt2x00dev, 3, bbp);
901
902 if (rt2x00_rt(rt2x00dev, RT2860) &&
903 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
904 if (conf_is_ht40(conf)) {
905 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
906 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
907 rt2800_bbp_write(rt2x00dev, 73, 0x16);
908 } else {
909 rt2800_bbp_write(rt2x00dev, 69, 0x16);
910 rt2800_bbp_write(rt2x00dev, 70, 0x08);
911 rt2800_bbp_write(rt2x00dev, 73, 0x11);
912 }
913 }
914
915 msleep(1);
916}
917
918static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
919 const int txpower)
920{
921 u32 reg;
922 u32 value = TXPOWER_G_TO_DEV(txpower);
923 u8 r1;
924
925 rt2800_bbp_read(rt2x00dev, 1, &r1);
926 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
927 rt2800_bbp_write(rt2x00dev, 1, r1);
928
929 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
931 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
932 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
933 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
938 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
939
940 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
941 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
942 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
943 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
944 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
945 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
946 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
947 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
948 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
949 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
950
951 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
952 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
953 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
954 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
955 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
956 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
957 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
958 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
959 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
960 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
961
962 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
963 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
964 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
965 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
966 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
967 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
968 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
969 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
970 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
971 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
972
973 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
974 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
975 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
976 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
977 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
978 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
979}
980
981static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
982 struct rt2x00lib_conf *libconf)
983{
984 u32 reg;
985
986 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
987 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
988 libconf->conf->short_frame_max_tx_count);
989 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
990 libconf->conf->long_frame_max_tx_count);
991 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
992 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
993 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
994 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
995 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
996}
997
998static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
999 struct rt2x00lib_conf *libconf)
1000{
1001 enum dev_state state =
1002 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1003 STATE_SLEEP : STATE_AWAKE;
1004 u32 reg;
1005
1006 if (state == STATE_SLEEP) {
1007 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1008
1009 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1010 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1011 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1012 libconf->conf->listen_interval - 1);
1013 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1014 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1015
1016 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1017 } else {
1018 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1019
1020 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1021 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1022 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1023 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1024 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1025 }
1026}
1027
1028void rt2800_config(struct rt2x00_dev *rt2x00dev,
1029 struct rt2x00lib_conf *libconf,
1030 const unsigned int flags)
1031{
1032 /* Always recalculate LNA gain before changing configuration */
1033 rt2800_config_lna_gain(rt2x00dev, libconf);
1034
1035 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1036 rt2800_config_channel(rt2x00dev, libconf->conf,
1037 &libconf->rf, &libconf->channel);
1038 if (flags & IEEE80211_CONF_CHANGE_POWER)
1039 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1040 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1041 rt2800_config_retry_limit(rt2x00dev, libconf);
1042 if (flags & IEEE80211_CONF_CHANGE_PS)
1043 rt2800_config_ps(rt2x00dev, libconf);
1044}
1045EXPORT_SYMBOL_GPL(rt2800_config);
1046
1047/*
1048 * Link tuning
1049 */
1050void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1051{
1052 u32 reg;
1053
1054 /*
1055 * Update FCS error count from register.
1056 */
1057 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1058 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1059}
1060EXPORT_SYMBOL_GPL(rt2800_link_stats);
1061
1062static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1063{
1064 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1065 if (rt2x00_is_usb(rt2x00dev) &&
1066 rt2x00_rt(rt2x00dev, RT3070) &&
1067 (rt2x00_rev(rt2x00dev) == RT3070_VERSION))
1068 return 0x1c + (2 * rt2x00dev->lna_gain);
1069 else
1070 return 0x2e + rt2x00dev->lna_gain;
1071 }
1072
1073 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1074 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1075 else
1076 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1077}
1078
1079static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1080 struct link_qual *qual, u8 vgc_level)
1081{
1082 if (qual->vgc_level != vgc_level) {
1083 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1084 qual->vgc_level = vgc_level;
1085 qual->vgc_level_reg = vgc_level;
1086 }
1087}
1088
1089void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1090{
1091 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1092}
1093EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1094
1095void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1096 const u32 count)
1097{
1098 if (rt2x00_rt(rt2x00dev, RT2860) &&
1099 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION))
1100 return;
1101
1102 /*
1103 * When RSSI is better then -80 increase VGC level with 0x10
1104 */
1105 rt2800_set_vgc(rt2x00dev, qual,
1106 rt2800_get_default_vgc(rt2x00dev) +
1107 ((qual->rssi > -80) * 0x10));
1108}
1109EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1110
1111/*
1112 * Initialization functions.
1113 */
1114int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1115{
1116 u32 reg;
1117 unsigned int i;
1118
1119 if (rt2x00_is_usb(rt2x00dev)) {
1120 /*
1121 * Wait until BBP and RF are ready.
1122 */
1123 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1124 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1125 if (reg && reg != ~0)
1126 break;
1127 msleep(1);
1128 }
1129
1130 if (i == REGISTER_BUSY_COUNT) {
1131 ERROR(rt2x00dev, "Unstable hardware.\n");
1132 return -EBUSY;
1133 }
1134
1135 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1136 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1137 reg & ~0x00002000);
1138 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
1139 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1140
1141 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1142 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1143 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1144 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1145
1146 if (rt2x00_is_usb(rt2x00dev)) {
1147 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1148#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1149 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1150 USB_MODE_RESET, REGISTER_TIMEOUT);
1151#endif
1152 }
1153
1154 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1155
1156 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1157 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1158 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1159 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1160 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1161 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1162
1163 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1164 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1165 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1166 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1167 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1168 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1169
1170 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1171 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1172
1173 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1174
1175 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1176 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1177 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1178 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1179 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1180 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1181 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1182 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1183
1184 if (rt2x00_is_usb(rt2x00dev) &&
1185 rt2x00_rt(rt2x00dev, RT3070) &&
1186 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1187 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1188 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1189 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1190 } else {
1191 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1192 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1193 }
1194
1195 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1196 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1197 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1198 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1199 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1200 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1201 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1202 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1203 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1204 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1205
1206 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1207 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1208 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1209 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1210
1211 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1212 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1213 if ((rt2x00_rt(rt2x00dev, RT2872) &&
1214 (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION)) ||
1215 rt2x00_rt(rt2x00dev, RT2880) ||
1216 rt2x00_rt(rt2x00dev, RT2883) ||
1217 rt2x00_rt(rt2x00dev, RT2890) ||
1218 rt2x00_rt(rt2x00dev, RT3052) ||
1219 (rt2x00_rt(rt2x00dev, RT3070) &&
1220 (rt2x00_rev(rt2x00dev) < RT3070_VERSION)))
1221 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1222 else
1223 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1224 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1225 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1226 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1227
1228 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1229
1230 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1231 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1232 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1233 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1234 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1235 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1236 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1237
1238 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1239 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1240 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1241 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1242 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1243 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1244 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1245 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1246 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1247 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1248 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1249
1250 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1251 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1252 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1253 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1254 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1255 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1256 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1257 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1258 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1259 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1260 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1261
1262 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1263 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1264 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1265 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1266 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1267 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1268 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1269 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1270 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1271 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1272 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1273
1274 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1275 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1276 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1277 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1278 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1279 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1280 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1281 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1282 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1283 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1284 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1285
1286 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1287 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1288 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1289 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1290 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1291 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1292 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1293 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1294 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1295 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1296 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1297
1298 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1299 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1300 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1301 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1302 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1303 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1304 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1305 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1306 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1307 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1308 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1309
1310 if (rt2x00_is_usb(rt2x00dev)) {
1311 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1312
1313 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1314 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1315 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1316 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1317 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1318 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1319 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1320 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1321 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1322 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1323 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1324 }
1325
1326 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1327 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1328
1329 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1330 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1331 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1332 IEEE80211_MAX_RTS_THRESHOLD);
1333 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1334 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1335
1336 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1337 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1338
1339 /*
1340 * ASIC will keep garbage value after boot, clear encryption keys.
1341 */
1342 for (i = 0; i < 4; i++)
1343 rt2800_register_write(rt2x00dev,
1344 SHARED_KEY_MODE_ENTRY(i), 0);
1345
1346 for (i = 0; i < 256; i++) {
1347 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1348 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1349 wcid, sizeof(wcid));
1350
1351 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1352 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1353 }
1354
1355 /*
1356 * Clear all beacons
1357 * For the Beacon base registers we only need to clear
1358 * the first byte since that byte contains the VALID and OWNER
1359 * bits which (when set to 0) will invalidate the entire beacon.
1360 */
1361 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1362 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1363 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1364 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1365 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1366 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1367 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1368 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1369
1370 if (rt2x00_is_usb(rt2x00dev)) {
1371 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1372 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1373 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1374 }
1375
1376 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1377 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1378 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1379 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1380 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1381 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1382 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1383 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1384 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1385 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1386
1387 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1388 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1389 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1390 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1391 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1392 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1393 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1394 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1395 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1396 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1397
1398 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1399 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1400 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1401 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1402 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1403 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1404 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1405 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1406 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1407 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1408
1409 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1410 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1411 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1412 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1413 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1414 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1415
1416 /*
1417 * We must clear the error counters.
1418 * These registers are cleared on read,
1419 * so we may pass a useless variable to store the value.
1420 */
1421 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1422 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1423 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1424 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1425 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1426 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1427
1428 return 0;
1429}
1430EXPORT_SYMBOL_GPL(rt2800_init_registers);
1431
1432static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1433{
1434 unsigned int i;
1435 u32 reg;
1436
1437 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1438 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1439 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1440 return 0;
1441
1442 udelay(REGISTER_BUSY_DELAY);
1443 }
1444
1445 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1446 return -EACCES;
1447}
1448
1449static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1450{
1451 unsigned int i;
1452 u8 value;
1453
1454 /*
1455 * BBP was enabled after firmware was loaded,
1456 * but we need to reactivate it now.
1457 */
1458 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1459 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1460 msleep(1);
1461
1462 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1463 rt2800_bbp_read(rt2x00dev, 0, &value);
1464 if ((value != 0xff) && (value != 0x00))
1465 return 0;
1466 udelay(REGISTER_BUSY_DELAY);
1467 }
1468
1469 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1470 return -EACCES;
1471}
1472
1473int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1474{
1475 unsigned int i;
1476 u16 eeprom;
1477 u8 reg_id;
1478 u8 value;
1479
1480 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1481 rt2800_wait_bbp_ready(rt2x00dev)))
1482 return -EACCES;
1483
1484 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1485 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1486 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1487 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1488 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1489 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1490 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1491 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1492 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1493 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1494 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1495 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1496 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1497 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1498
1499 if (rt2x00_rt(rt2x00dev, RT2860) &&
1500 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
1501 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1502 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1503 }
1504
1505 if (rt2x00_rt(rt2x00dev, RT2860) &&
1506 (rt2x00_rev(rt2x00dev) > RT2860D_VERSION))
1507 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1508
1509 if (rt2x00_is_usb(rt2x00dev) &&
1510 rt2x00_rt(rt2x00dev, RT3070) &&
1511 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1512 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1513 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1514 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1515 }
1516
1517 if (rt2x00_rt(rt2x00dev, RT3052)) {
1518 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1519 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1520 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1521 }
1522
1523 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1524 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1525
1526 if (eeprom != 0xffff && eeprom != 0x0000) {
1527 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1528 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1529 rt2800_bbp_write(rt2x00dev, reg_id, value);
1530 }
1531 }
1532
1533 return 0;
1534}
1535EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1536
1537static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1538 bool bw40, u8 rfcsr24, u8 filter_target)
1539{
1540 unsigned int i;
1541 u8 bbp;
1542 u8 rfcsr;
1543 u8 passband;
1544 u8 stopband;
1545 u8 overtuned = 0;
1546
1547 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1548
1549 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1550 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1551 rt2800_bbp_write(rt2x00dev, 4, bbp);
1552
1553 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1554 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1555 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1556
1557 /*
1558 * Set power & frequency of passband test tone
1559 */
1560 rt2800_bbp_write(rt2x00dev, 24, 0);
1561
1562 for (i = 0; i < 100; i++) {
1563 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1564 msleep(1);
1565
1566 rt2800_bbp_read(rt2x00dev, 55, &passband);
1567 if (passband)
1568 break;
1569 }
1570
1571 /*
1572 * Set power & frequency of stopband test tone
1573 */
1574 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1575
1576 for (i = 0; i < 100; i++) {
1577 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1578 msleep(1);
1579
1580 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1581
1582 if ((passband - stopband) <= filter_target) {
1583 rfcsr24++;
1584 overtuned += ((passband - stopband) == filter_target);
1585 } else
1586 break;
1587
1588 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1589 }
1590
1591 rfcsr24 -= !!overtuned;
1592
1593 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1594 return rfcsr24;
1595}
1596
1597int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1598{
1599 u8 rfcsr;
1600 u8 bbp;
1601
1602 if (rt2x00_is_usb(rt2x00dev) &&
1603 rt2x00_rt(rt2x00dev, RT3070) &&
1604 (rt2x00_rev(rt2x00dev) != RT3070_VERSION))
1605 return 0;
1606
1607 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1608 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1609 !rt2x00_rf(rt2x00dev, RF3021) &&
1610 !rt2x00_rf(rt2x00dev, RF3022))
1611 return 0;
1612 }
1613
1614 /*
1615 * Init RF calibration.
1616 */
1617 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1618 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1619 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1620 msleep(1);
1621 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1622 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1623
1624 if (rt2x00_is_usb(rt2x00dev)) {
1625 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1626 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1627 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1628 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1629 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1630 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1631 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1632 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1633 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1634 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1635 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1636 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1637 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1638 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1639 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1640 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1641 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1642 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1643 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1644 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1645 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1646 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1647 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1648 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1649 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1650 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1651 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1652 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1653 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1654 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1655 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1656 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1657 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1658 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1659 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1660 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1661 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1662 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1663 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1664 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1665 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1666 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1667 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1668 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1669 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1670 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1671 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1672 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1673 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1674 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1675 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1676 }
1677
1678 /*
1679 * Set RX Filter calibration for 20MHz and 40MHz
1680 */
1681 rt2x00dev->calibration[0] =
1682 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1683 rt2x00dev->calibration[1] =
1684 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1685
1686 /*
1687 * Set back to initial state
1688 */
1689 rt2800_bbp_write(rt2x00dev, 24, 0);
1690
1691 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1692 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1693 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1694
1695 /*
1696 * set BBP back to BW20
1697 */
1698 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1699 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1700 rt2800_bbp_write(rt2x00dev, 4, bbp);
1701
1702 return 0;
1703}
1704EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1705
1706int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1707{
1708 u32 reg;
1709
1710 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1711
1712 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1713}
1714EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1715
1716static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1717{
1718 u32 reg;
1719
1720 mutex_lock(&rt2x00dev->csr_mutex);
1721
1722 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1723 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1724 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1725 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1726 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1727
1728 /* Wait until the EEPROM has been loaded */
1729 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1730
1731 /* Apparently the data is read from end to start */
1732 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1733 (u32 *)&rt2x00dev->eeprom[i]);
1734 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1735 (u32 *)&rt2x00dev->eeprom[i + 2]);
1736 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1737 (u32 *)&rt2x00dev->eeprom[i + 4]);
1738 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1739 (u32 *)&rt2x00dev->eeprom[i + 6]);
1740
1741 mutex_unlock(&rt2x00dev->csr_mutex);
1742}
1743
1744void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1745{
1746 unsigned int i;
1747
1748 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1749 rt2800_efuse_read(rt2x00dev, i);
1750}
1751EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1752
1753int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1754{
1755 u16 word;
1756 u8 *mac;
1757 u8 default_lna_gain;
1758
1759 /*
1760 * Start validation of the data that has been read.
1761 */
1762 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1763 if (!is_valid_ether_addr(mac)) {
1764 random_ether_addr(mac);
1765 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1766 }
1767
1768 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1769 if (word == 0xffff) {
1770 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1771 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1772 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1773 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1774 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1775 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1776 rt2x00_rt(rt2x00dev, RT2870) ||
1777 rt2x00_rt(rt2x00dev, RT2872) ||
1778 rt2x00_rt(rt2x00dev, RT2880) ||
1779 (rt2x00_rt(rt2x00dev, RT2883) &&
1780 (rt2x00_rev(rt2x00dev) < RT2883_VERSION))) {
1781 /*
1782 * There is a max of 2 RX streams for RT28x0 series
1783 */
1784 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1785 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1786 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1787 }
1788
1789 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1790 if (word == 0xffff) {
1791 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1792 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1793 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1794 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1795 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1796 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1797 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1798 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1799 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1800 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1801 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1802 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1803 }
1804
1805 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1806 if ((word & 0x00ff) == 0x00ff) {
1807 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1808 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1809 LED_MODE_TXRX_ACTIVITY);
1810 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1811 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1812 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1813 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1814 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1815 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1816 }
1817
1818 /*
1819 * During the LNA validation we are going to use
1820 * lna0 as correct value. Note that EEPROM_LNA
1821 * is never validated.
1822 */
1823 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1824 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1825
1826 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1827 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1828 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1829 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1830 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1831 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1832
1833 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1834 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1835 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1836 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1837 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1838 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1839 default_lna_gain);
1840 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1841
1842 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1843 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1844 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1845 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1846 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1847 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1848
1849 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1850 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1851 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1852 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1853 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1854 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1855 default_lna_gain);
1856 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1857
1858 return 0;
1859}
1860EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1861
1862int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1863{
1864 u32 reg;
1865 u16 value;
1866 u16 eeprom;
1867
1868 /*
1869 * Read EEPROM word for configuration.
1870 */
1871 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1872
1873 /*
1874 * Identify RF chipset.
1875 */
1876 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1877 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1878
1879 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1880 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1881
1882 if (!rt2x00_rt(rt2x00dev, RT2860) &&
1883 !rt2x00_rt(rt2x00dev, RT2870) &&
1884 !rt2x00_rt(rt2x00dev, RT2872) &&
1885 !rt2x00_rt(rt2x00dev, RT2880) &&
1886 !rt2x00_rt(rt2x00dev, RT2883) &&
1887 !rt2x00_rt(rt2x00dev, RT2890) &&
1888 !rt2x00_rt(rt2x00dev, RT3052) &&
1889 !rt2x00_rt(rt2x00dev, RT3070) &&
1890 !rt2x00_rt(rt2x00dev, RT3071) &&
1891 !rt2x00_rt(rt2x00dev, RT3090) &&
1892 !rt2x00_rt(rt2x00dev, RT3390) &&
1893 !rt2x00_rt(rt2x00dev, RT3572)) {
1894 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1895 return -ENODEV;
1896 }
1897
1898 if (!rt2x00_rf(rt2x00dev, RF2820) &&
1899 !rt2x00_rf(rt2x00dev, RF2850) &&
1900 !rt2x00_rf(rt2x00dev, RF2720) &&
1901 !rt2x00_rf(rt2x00dev, RF2750) &&
1902 !rt2x00_rf(rt2x00dev, RF3020) &&
1903 !rt2x00_rf(rt2x00dev, RF2020) &&
1904 !rt2x00_rf(rt2x00dev, RF3021) &&
1905 !rt2x00_rf(rt2x00dev, RF3022) &&
1906 !rt2x00_rf(rt2x00dev, RF3052)) {
1907 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1908 return -ENODEV;
1909 }
1910
1911 /*
1912 * Identify default antenna configuration.
1913 */
1914 rt2x00dev->default_ant.tx =
1915 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1916 rt2x00dev->default_ant.rx =
1917 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1918
1919 /*
1920 * Read frequency offset and RF programming sequence.
1921 */
1922 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1923 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1924
1925 /*
1926 * Read external LNA informations.
1927 */
1928 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1929
1930 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1931 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1932 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1933 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1934
1935 /*
1936 * Detect if this device has an hardware controlled radio.
1937 */
1938 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1939 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1940
1941 /*
1942 * Store led settings, for correct led behaviour.
1943 */
1944#ifdef CONFIG_RT2X00_LIB_LEDS
1945 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1946 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1947 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1948
1949 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1950#endif /* CONFIG_RT2X00_LIB_LEDS */
1951
1952 return 0;
1953}
1954EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1955
1956/*
1957 * RF value list for rt28x0
1958 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1959 */
1960static const struct rf_channel rf_vals[] = {
1961 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1962 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1963 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1964 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1965 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1966 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1967 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1968 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1969 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1970 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1971 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1972 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1973 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1974 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1975
1976 /* 802.11 UNI / HyperLan 2 */
1977 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1978 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1979 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1980 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1981 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1982 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1983 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1984 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1985 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1986 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1987 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1988 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1989
1990 /* 802.11 HyperLan 2 */
1991 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1992 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1993 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1994 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1995 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1996 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1997 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1998 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1999 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2000 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2001 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2002 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2003 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2004 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2005 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2006 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2007
2008 /* 802.11 UNII */
2009 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2010 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2011 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2012 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2013 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2014 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2015 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2016 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2017 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2018 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2019 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2020
2021 /* 802.11 Japan */
2022 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2023 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2024 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2025 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2026 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2027 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2028 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2029};
2030
2031/*
2032 * RF value list for rt3070
2033 * Supports: 2.4 GHz
2034 */
2035static const struct rf_channel rf_vals_302x[] = {
2036 {1, 241, 2, 2 },
2037 {2, 241, 2, 7 },
2038 {3, 242, 2, 2 },
2039 {4, 242, 2, 7 },
2040 {5, 243, 2, 2 },
2041 {6, 243, 2, 7 },
2042 {7, 244, 2, 2 },
2043 {8, 244, 2, 7 },
2044 {9, 245, 2, 2 },
2045 {10, 245, 2, 7 },
2046 {11, 246, 2, 2 },
2047 {12, 246, 2, 7 },
2048 {13, 247, 2, 2 },
2049 {14, 248, 2, 4 },
2050};
2051
2052int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2053{
2054 struct hw_mode_spec *spec = &rt2x00dev->spec;
2055 struct channel_info *info;
2056 char *tx_power1;
2057 char *tx_power2;
2058 unsigned int i;
2059 u16 eeprom;
2060
2061 /*
2062 * Disable powersaving as default on PCI devices.
2063 */
2064 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2065 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2066
2067 /*
2068 * Initialize all hw fields.
2069 */
2070 rt2x00dev->hw->flags =
2071 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2072 IEEE80211_HW_SIGNAL_DBM |
2073 IEEE80211_HW_SUPPORTS_PS |
2074 IEEE80211_HW_PS_NULLFUNC_STACK;
2075
2076 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2077 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2078 rt2x00_eeprom_addr(rt2x00dev,
2079 EEPROM_MAC_ADDR_0));
2080
2081 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2082
2083 /*
2084 * Initialize hw_mode information.
2085 */
2086 spec->supported_bands = SUPPORT_BAND_2GHZ;
2087 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2088
2089 if (rt2x00_rf(rt2x00dev, RF2820) ||
2090 rt2x00_rf(rt2x00dev, RF2720) ||
2091 rt2x00_rf(rt2x00dev, RF3052)) {
2092 spec->num_channels = 14;
2093 spec->channels = rf_vals;
2094 } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2095 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2096 spec->num_channels = ARRAY_SIZE(rf_vals);
2097 spec->channels = rf_vals;
2098 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2099 rt2x00_rf(rt2x00dev, RF2020) ||
2100 rt2x00_rf(rt2x00dev, RF3021) ||
2101 rt2x00_rf(rt2x00dev, RF3022)) {
2102 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2103 spec->channels = rf_vals_302x;
2104 }
2105
2106 /*
2107 * Initialize HT information.
2108 */
2109 if (!rt2x00_rf(rt2x00dev, RF2020))
2110 spec->ht.ht_supported = true;
2111 else
2112 spec->ht.ht_supported = false;
2113
2114 spec->ht.cap =
2115 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2116 IEEE80211_HT_CAP_GRN_FLD |
2117 IEEE80211_HT_CAP_SGI_20 |
2118 IEEE80211_HT_CAP_SGI_40 |
2119 IEEE80211_HT_CAP_TX_STBC |
2120 IEEE80211_HT_CAP_RX_STBC;
2121 spec->ht.ampdu_factor = 3;
2122 spec->ht.ampdu_density = 4;
2123 spec->ht.mcs.tx_params =
2124 IEEE80211_HT_MCS_TX_DEFINED |
2125 IEEE80211_HT_MCS_TX_RX_DIFF |
2126 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2127 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2128
2129 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2130 case 3:
2131 spec->ht.mcs.rx_mask[2] = 0xff;
2132 case 2:
2133 spec->ht.mcs.rx_mask[1] = 0xff;
2134 case 1:
2135 spec->ht.mcs.rx_mask[0] = 0xff;
2136 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2137 break;
2138 }
2139
2140 /*
2141 * Create channel information array
2142 */
2143 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2144 if (!info)
2145 return -ENOMEM;
2146
2147 spec->channels_info = info;
2148
2149 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2150 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2151
2152 for (i = 0; i < 14; i++) {
2153 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2154 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2155 }
2156
2157 if (spec->num_channels > 14) {
2158 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2159 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2160
2161 for (i = 14; i < spec->num_channels; i++) {
2162 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2163 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2164 }
2165 }
2166
2167 return 0;
2168}
2169EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2170
2171/*
2172 * IEEE80211 stack callback functions.
2173 */
2174static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2175 u32 *iv32, u16 *iv16)
2176{
2177 struct rt2x00_dev *rt2x00dev = hw->priv;
2178 struct mac_iveiv_entry iveiv_entry;
2179 u32 offset;
2180
2181 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2182 rt2800_register_multiread(rt2x00dev, offset,
2183 &iveiv_entry, sizeof(iveiv_entry));
2184
2185 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2186 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2187}
2188
2189static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2190{
2191 struct rt2x00_dev *rt2x00dev = hw->priv;
2192 u32 reg;
2193 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2194
2195 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2196 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2197 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2198
2199 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2200 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2201 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2202
2203 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2204 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2205 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2206
2207 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2208 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2209 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2210
2211 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2212 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2213 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2214
2215 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2216 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2217 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2218
2219 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2220 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2221 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2222
2223 return 0;
2224}
2225
2226static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2227 const struct ieee80211_tx_queue_params *params)
2228{
2229 struct rt2x00_dev *rt2x00dev = hw->priv;
2230 struct data_queue *queue;
2231 struct rt2x00_field32 field;
2232 int retval;
2233 u32 reg;
2234 u32 offset;
2235
2236 /*
2237 * First pass the configuration through rt2x00lib, that will
2238 * update the queue settings and validate the input. After that
2239 * we are free to update the registers based on the value
2240 * in the queue parameter.
2241 */
2242 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2243 if (retval)
2244 return retval;
2245
2246 /*
2247 * We only need to perform additional register initialization
2248 * for WMM queues/
2249 */
2250 if (queue_idx >= 4)
2251 return 0;
2252
2253 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2254
2255 /* Update WMM TXOP register */
2256 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2257 field.bit_offset = (queue_idx & 1) * 16;
2258 field.bit_mask = 0xffff << field.bit_offset;
2259
2260 rt2800_register_read(rt2x00dev, offset, &reg);
2261 rt2x00_set_field32(&reg, field, queue->txop);
2262 rt2800_register_write(rt2x00dev, offset, reg);
2263
2264 /* Update WMM registers */
2265 field.bit_offset = queue_idx * 4;
2266 field.bit_mask = 0xf << field.bit_offset;
2267
2268 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2269 rt2x00_set_field32(&reg, field, queue->aifs);
2270 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2271
2272 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2273 rt2x00_set_field32(&reg, field, queue->cw_min);
2274 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2275
2276 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2277 rt2x00_set_field32(&reg, field, queue->cw_max);
2278 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2279
2280 /* Update EDCA registers */
2281 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2282
2283 rt2800_register_read(rt2x00dev, offset, &reg);
2284 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2285 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2286 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2287 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2288 rt2800_register_write(rt2x00dev, offset, reg);
2289
2290 return 0;
2291}
2292
2293static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2294{
2295 struct rt2x00_dev *rt2x00dev = hw->priv;
2296 u64 tsf;
2297 u32 reg;
2298
2299 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2300 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2301 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2302 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2303
2304 return tsf;
2305}
2306
2307const struct ieee80211_ops rt2800_mac80211_ops = {
2308 .tx = rt2x00mac_tx,
2309 .start = rt2x00mac_start,
2310 .stop = rt2x00mac_stop,
2311 .add_interface = rt2x00mac_add_interface,
2312 .remove_interface = rt2x00mac_remove_interface,
2313 .config = rt2x00mac_config,
2314 .configure_filter = rt2x00mac_configure_filter,
2315 .set_tim = rt2x00mac_set_tim,
2316 .set_key = rt2x00mac_set_key,
2317 .get_stats = rt2x00mac_get_stats,
2318 .get_tkip_seq = rt2800_get_tkip_seq,
2319 .set_rts_threshold = rt2800_set_rts_threshold,
2320 .bss_info_changed = rt2x00mac_bss_info_changed,
2321 .conf_tx = rt2800_conf_tx,
2322 .get_tsf = rt2800_get_tsf,
2323 .rfkill_poll = rt2x00mac_rfkill_poll,
2324};
2325EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
new file mode 100644
index 000000000000..ebabeae62d1b
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -0,0 +1,150 @@
1/*
2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the
16 Free Software Foundation, Inc.,
17 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#ifndef RT2800LIB_H
21#define RT2800LIB_H
22
23struct rt2800_ops {
24 void (*register_read)(struct rt2x00_dev *rt2x00dev,
25 const unsigned int offset, u32 *value);
26 void (*register_read_lock)(struct rt2x00_dev *rt2x00dev,
27 const unsigned int offset, u32 *value);
28 void (*register_write)(struct rt2x00_dev *rt2x00dev,
29 const unsigned int offset, u32 value);
30 void (*register_write_lock)(struct rt2x00_dev *rt2x00dev,
31 const unsigned int offset, u32 value);
32
33 void (*register_multiread)(struct rt2x00_dev *rt2x00dev,
34 const unsigned int offset,
35 void *value, const u32 length);
36 void (*register_multiwrite)(struct rt2x00_dev *rt2x00dev,
37 const unsigned int offset,
38 const void *value, const u32 length);
39
40 int (*regbusy_read)(struct rt2x00_dev *rt2x00dev,
41 const unsigned int offset,
42 const struct rt2x00_field32 field, u32 *reg);
43};
44
45static inline void rt2800_register_read(struct rt2x00_dev *rt2x00dev,
46 const unsigned int offset,
47 u32 *value)
48{
49 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
50
51 rt2800ops->register_read(rt2x00dev, offset, value);
52}
53
54static inline void rt2800_register_read_lock(struct rt2x00_dev *rt2x00dev,
55 const unsigned int offset,
56 u32 *value)
57{
58 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
59
60 rt2800ops->register_read_lock(rt2x00dev, offset, value);
61}
62
63static inline void rt2800_register_write(struct rt2x00_dev *rt2x00dev,
64 const unsigned int offset,
65 u32 value)
66{
67 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
68
69 rt2800ops->register_write(rt2x00dev, offset, value);
70}
71
72static inline void rt2800_register_write_lock(struct rt2x00_dev *rt2x00dev,
73 const unsigned int offset,
74 u32 value)
75{
76 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
77
78 rt2800ops->register_write_lock(rt2x00dev, offset, value);
79}
80
81static inline void rt2800_register_multiread(struct rt2x00_dev *rt2x00dev,
82 const unsigned int offset,
83 void *value, const u32 length)
84{
85 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
86
87 rt2800ops->register_multiread(rt2x00dev, offset, value, length);
88}
89
90static inline void rt2800_register_multiwrite(struct rt2x00_dev *rt2x00dev,
91 const unsigned int offset,
92 const void *value,
93 const u32 length)
94{
95 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
96
97 rt2800ops->register_multiwrite(rt2x00dev, offset, value, length);
98}
99
100static inline int rt2800_regbusy_read(struct rt2x00_dev *rt2x00dev,
101 const unsigned int offset,
102 const struct rt2x00_field32 field,
103 u32 *reg)
104{
105 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
106
107 return rt2800ops->regbusy_read(rt2x00dev, offset, field, reg);
108}
109
110void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
111 const u8 command, const u8 token,
112 const u8 arg0, const u8 arg1);
113
114extern const struct rt2x00debug rt2800_rt2x00debug;
115
116int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev);
117int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
118 struct rt2x00lib_crypto *crypto,
119 struct ieee80211_key_conf *key);
120int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
121 struct rt2x00lib_crypto *crypto,
122 struct ieee80211_key_conf *key);
123void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
124 const unsigned int filter_flags);
125void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
126 struct rt2x00intf_conf *conf, const unsigned int flags);
127void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp);
128void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant);
129void rt2800_config(struct rt2x00_dev *rt2x00dev,
130 struct rt2x00lib_conf *libconf,
131 const unsigned int flags);
132void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
133void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
134void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
135 const u32 count);
136
137int rt2800_init_registers(struct rt2x00_dev *rt2x00dev);
138int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev);
139int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev);
140int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev);
141
142int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev);
143void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev);
144int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev);
145int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev);
146int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev);
147
148extern const struct ieee80211_ops rt2800_mac80211_ops;
149
150#endif /* RT2800LIB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
new file mode 100644
index 000000000000..91cce2d0f6db
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -0,0 +1,1288 @@
1/*
2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34#include <linux/crc-ccitt.h>
35#include <linux/delay.h>
36#include <linux/etherdevice.h>
37#include <linux/init.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/pci.h>
41#include <linux/platform_device.h>
42#include <linux/eeprom_93cx6.h>
43
44#include "rt2x00.h"
45#include "rt2x00pci.h"
46#include "rt2x00soc.h"
47#include "rt2800lib.h"
48#include "rt2800.h"
49#include "rt2800pci.h"
50
51/*
52 * Allow hardware encryption to be disabled.
53 */
54static int modparam_nohwcrypt = 1;
55module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57
58static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
59{
60 unsigned int i;
61 u32 reg;
62
63 for (i = 0; i < 200; i++) {
64 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
65
66 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
67 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
68 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
69 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
70 break;
71
72 udelay(REGISTER_BUSY_DELAY);
73 }
74
75 if (i == 200)
76 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
77
78 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
79 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
80}
81
82#ifdef CONFIG_RT2800PCI_SOC
83static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
84{
85 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
86
87 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
88}
89#else
90static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
91{
92}
93#endif /* CONFIG_RT2800PCI_SOC */
94
95#ifdef CONFIG_RT2800PCI_PCI
96static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
97{
98 struct rt2x00_dev *rt2x00dev = eeprom->data;
99 u32 reg;
100
101 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
102
103 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
104 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
105 eeprom->reg_data_clock =
106 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
107 eeprom->reg_chip_select =
108 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
109}
110
111static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
112{
113 struct rt2x00_dev *rt2x00dev = eeprom->data;
114 u32 reg = 0;
115
116 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
117 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
118 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
119 !!eeprom->reg_data_clock);
120 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
121 !!eeprom->reg_chip_select);
122
123 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
124}
125
126static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
127{
128 struct eeprom_93cx6 eeprom;
129 u32 reg;
130
131 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
132
133 eeprom.data = rt2x00dev;
134 eeprom.register_read = rt2800pci_eepromregister_read;
135 eeprom.register_write = rt2800pci_eepromregister_write;
136 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
137 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
138 eeprom.reg_data_in = 0;
139 eeprom.reg_data_out = 0;
140 eeprom.reg_data_clock = 0;
141 eeprom.reg_chip_select = 0;
142
143 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
144 EEPROM_SIZE / sizeof(u16));
145}
146
147static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
148{
149 return rt2800_efuse_detect(rt2x00dev);
150}
151
152static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
153{
154 rt2800_read_eeprom_efuse(rt2x00dev);
155}
156#else
157static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
158{
159}
160
161static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
162{
163 return 0;
164}
165
166static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
167{
168}
169#endif /* CONFIG_RT2800PCI_PCI */
170
171/*
172 * Firmware functions
173 */
174static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
175{
176 return FIRMWARE_RT2860;
177}
178
179static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
180 const u8 *data, const size_t len)
181{
182 u16 fw_crc;
183 u16 crc;
184
185 /*
186 * Only support 8kb firmware files.
187 */
188 if (len != 8192)
189 return FW_BAD_LENGTH;
190
191 /*
192 * The last 2 bytes in the firmware array are the crc checksum itself,
193 * this means that we should never pass those 2 bytes to the crc
194 * algorithm.
195 */
196 fw_crc = (data[len - 2] << 8 | data[len - 1]);
197
198 /*
199 * Use the crc ccitt algorithm.
200 * This will return the same value as the legacy driver which
201 * used bit ordering reversion on the both the firmware bytes
202 * before input input as well as on the final output.
203 * Obviously using crc ccitt directly is much more efficient.
204 */
205 crc = crc_ccitt(~0, data, len - 2);
206
207 /*
208 * There is a small difference between the crc-itu-t + bitrev and
209 * the crc-ccitt crc calculation. In the latter method the 2 bytes
210 * will be swapped, use swab16 to convert the crc to the correct
211 * value.
212 */
213 crc = swab16(crc);
214
215 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
216}
217
218static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
219 const u8 *data, const size_t len)
220{
221 unsigned int i;
222 u32 reg;
223
224 /*
225 * Wait for stable hardware.
226 */
227 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
228 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
229 if (reg && reg != ~0)
230 break;
231 msleep(1);
232 }
233
234 if (i == REGISTER_BUSY_COUNT) {
235 ERROR(rt2x00dev, "Unstable hardware.\n");
236 return -EBUSY;
237 }
238
239 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
240 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
241
242 /*
243 * Disable DMA, will be reenabled later when enabling
244 * the radio.
245 */
246 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
247 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
248 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
249 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
250 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
251 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
252 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
253
254 /*
255 * enable Host program ram write selection
256 */
257 reg = 0;
258 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
259 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
260
261 /*
262 * Write firmware to device.
263 */
264 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
265 data, len);
266
267 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
268 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
269
270 /*
271 * Wait for device to stabilize.
272 */
273 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
274 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
275 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
276 break;
277 msleep(1);
278 }
279
280 if (i == REGISTER_BUSY_COUNT) {
281 ERROR(rt2x00dev, "PBF system register not ready.\n");
282 return -EBUSY;
283 }
284
285 /*
286 * Disable interrupts
287 */
288 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
289
290 /*
291 * Initialize BBP R/W access agent
292 */
293 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
294 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
295
296 return 0;
297}
298
299/*
300 * Initialization functions.
301 */
302static bool rt2800pci_get_entry_state(struct queue_entry *entry)
303{
304 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
305 u32 word;
306
307 if (entry->queue->qid == QID_RX) {
308 rt2x00_desc_read(entry_priv->desc, 1, &word);
309
310 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
311 } else {
312 rt2x00_desc_read(entry_priv->desc, 1, &word);
313
314 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
315 }
316}
317
318static void rt2800pci_clear_entry(struct queue_entry *entry)
319{
320 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
321 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
322 u32 word;
323
324 if (entry->queue->qid == QID_RX) {
325 rt2x00_desc_read(entry_priv->desc, 0, &word);
326 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
327 rt2x00_desc_write(entry_priv->desc, 0, word);
328
329 rt2x00_desc_read(entry_priv->desc, 1, &word);
330 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
331 rt2x00_desc_write(entry_priv->desc, 1, word);
332 } else {
333 rt2x00_desc_read(entry_priv->desc, 1, &word);
334 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
335 rt2x00_desc_write(entry_priv->desc, 1, word);
336 }
337}
338
339static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
340{
341 struct queue_entry_priv_pci *entry_priv;
342 u32 reg;
343
344 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
345 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
346 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
347 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
348 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
349 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
350 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
351 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
352 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
353
354 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
355 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
356
357 /*
358 * Initialize registers.
359 */
360 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
361 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
362 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
363 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
364 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
365
366 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
367 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
368 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
369 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
370 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
371
372 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
373 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
374 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
375 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
376 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
377
378 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
379 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
380 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
381 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
382 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
383
384 entry_priv = rt2x00dev->rx->entries[0].priv_data;
385 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
386 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
387 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
388 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
389
390 /*
391 * Enable global DMA configuration
392 */
393 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
394 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
395 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
396 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
397 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
398
399 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
400
401 return 0;
402}
403
404/*
405 * Device state switch handlers.
406 */
407static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
408 enum dev_state state)
409{
410 u32 reg;
411
412 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
413 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
414 (state == STATE_RADIO_RX_ON) ||
415 (state == STATE_RADIO_RX_ON_LINK));
416 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
417}
418
419static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
420 enum dev_state state)
421{
422 int mask = (state == STATE_RADIO_IRQ_ON);
423 u32 reg;
424
425 /*
426 * When interrupts are being enabled, the interrupt registers
427 * should clear the register to assure a clean state.
428 */
429 if (state == STATE_RADIO_IRQ_ON) {
430 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
431 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
432 }
433
434 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
435 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
436 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
437 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
438 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
439 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
440 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
441 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
442 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
443 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
444 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
445 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
446 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
447 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
448 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
449 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
450 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
451 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
452 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
453 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
454}
455
456static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
457{
458 u32 reg;
459 u16 word;
460
461 /*
462 * Initialize all registers.
463 */
464 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
465 rt2800pci_init_queues(rt2x00dev) ||
466 rt2800_init_registers(rt2x00dev) ||
467 rt2800_wait_wpdma_ready(rt2x00dev) ||
468 rt2800_init_bbp(rt2x00dev) ||
469 rt2800_init_rfcsr(rt2x00dev)))
470 return -EIO;
471
472 /*
473 * Send signal to firmware during boot time.
474 */
475 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
476
477 /*
478 * Enable RX.
479 */
480 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
481 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
482 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
483 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
484
485 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
486 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
487 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
488 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
489 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
490 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
491
492 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
493 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
494 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
495 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
496
497 /*
498 * Initialize LED control
499 */
500 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
501 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
502 word & 0xff, (word >> 8) & 0xff);
503
504 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
505 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
506 word & 0xff, (word >> 8) & 0xff);
507
508 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
509 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
510 word & 0xff, (word >> 8) & 0xff);
511
512 return 0;
513}
514
515static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
516{
517 u32 reg;
518
519 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
520 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
521 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
522 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
523 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
524 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
525 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
526
527 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
528 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
529 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
530
531 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
532
533 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
534 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
535 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
536 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
537 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
538 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
539 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
540 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
541 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
542
543 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
544 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
545
546 /* Wait for DMA, ignore error */
547 rt2800_wait_wpdma_ready(rt2x00dev);
548}
549
550static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
551 enum dev_state state)
552{
553 /*
554 * Always put the device to sleep (even when we intend to wakeup!)
555 * if the device is booting and wasn't asleep it will return
556 * failure when attempting to wakeup.
557 */
558 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
559
560 if (state == STATE_AWAKE) {
561 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
562 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
563 }
564
565 return 0;
566}
567
568static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
569 enum dev_state state)
570{
571 int retval = 0;
572
573 switch (state) {
574 case STATE_RADIO_ON:
575 /*
576 * Before the radio can be enabled, the device first has
577 * to be woken up. After that it needs a bit of time
578 * to be fully awake and then the radio can be enabled.
579 */
580 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
581 msleep(1);
582 retval = rt2800pci_enable_radio(rt2x00dev);
583 break;
584 case STATE_RADIO_OFF:
585 /*
586 * After the radio has been disabled, the device should
587 * be put to sleep for powersaving.
588 */
589 rt2800pci_disable_radio(rt2x00dev);
590 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
591 break;
592 case STATE_RADIO_RX_ON:
593 case STATE_RADIO_RX_ON_LINK:
594 case STATE_RADIO_RX_OFF:
595 case STATE_RADIO_RX_OFF_LINK:
596 rt2800pci_toggle_rx(rt2x00dev, state);
597 break;
598 case STATE_RADIO_IRQ_ON:
599 case STATE_RADIO_IRQ_OFF:
600 rt2800pci_toggle_irq(rt2x00dev, state);
601 break;
602 case STATE_DEEP_SLEEP:
603 case STATE_SLEEP:
604 case STATE_STANDBY:
605 case STATE_AWAKE:
606 retval = rt2800pci_set_state(rt2x00dev, state);
607 break;
608 default:
609 retval = -ENOTSUPP;
610 break;
611 }
612
613 if (unlikely(retval))
614 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
615 state, retval);
616
617 return retval;
618}
619
620/*
621 * TX descriptor initialization
622 */
623static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
624 struct sk_buff *skb,
625 struct txentry_desc *txdesc)
626{
627 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
628 __le32 *txd = skbdesc->desc;
629 __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom);
630 u32 word;
631
632 /*
633 * Initialize TX Info descriptor
634 */
635 rt2x00_desc_read(txwi, 0, &word);
636 rt2x00_set_field32(&word, TXWI_W0_FRAG,
637 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
638 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
639 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
640 rt2x00_set_field32(&word, TXWI_W0_TS,
641 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
642 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
643 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
644 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
645 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
646 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
647 rt2x00_set_field32(&word, TXWI_W0_BW,
648 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
649 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
650 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
651 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
652 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
653 rt2x00_desc_write(txwi, 0, word);
654
655 rt2x00_desc_read(txwi, 1, &word);
656 rt2x00_set_field32(&word, TXWI_W1_ACK,
657 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
658 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
659 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
660 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
661 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
662 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
663 txdesc->key_idx : 0xff);
664 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
665 skb->len - txdesc->l2pad);
666 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
667 skbdesc->entry->queue->qid + 1);
668 rt2x00_desc_write(txwi, 1, word);
669
670 /*
671 * Always write 0 to IV/EIV fields, hardware will insert the IV
672 * from the IVEIV register when TXD_W3_WIV is set to 0.
673 * When TXD_W3_WIV is set to 1 it will use the IV data
674 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
675 * crypto entry in the registers should be used to encrypt the frame.
676 */
677 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
678 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
679
680 /*
681 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
682 * must contains a TXWI structure + 802.11 header + padding + 802.11
683 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
684 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
685 * data. It means that LAST_SEC0 is always 0.
686 */
687
688 /*
689 * Initialize TX descriptor
690 */
691 rt2x00_desc_read(txd, 0, &word);
692 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
693 rt2x00_desc_write(txd, 0, word);
694
695 rt2x00_desc_read(txd, 1, &word);
696 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
697 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
698 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
699 rt2x00_set_field32(&word, TXD_W1_BURST,
700 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
701 rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
702 rt2x00dev->ops->extra_tx_headroom);
703 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
704 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
705 rt2x00_desc_write(txd, 1, word);
706
707 rt2x00_desc_read(txd, 2, &word);
708 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
709 skbdesc->skb_dma + rt2x00dev->ops->extra_tx_headroom);
710 rt2x00_desc_write(txd, 2, word);
711
712 rt2x00_desc_read(txd, 3, &word);
713 rt2x00_set_field32(&word, TXD_W3_WIV,
714 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
715 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
716 rt2x00_desc_write(txd, 3, word);
717}
718
719/*
720 * TX data initialization
721 */
722static void rt2800pci_write_beacon(struct queue_entry *entry)
723{
724 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
725 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
726 unsigned int beacon_base;
727 u32 reg;
728
729 /*
730 * Disable beaconing while we are reloading the beacon data,
731 * otherwise we might be sending out invalid data.
732 */
733 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
734 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
735 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
736
737 /*
738 * Write entire beacon with descriptor to register.
739 */
740 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
741 rt2800_register_multiwrite(rt2x00dev,
742 beacon_base,
743 skbdesc->desc, skbdesc->desc_len);
744 rt2800_register_multiwrite(rt2x00dev,
745 beacon_base + skbdesc->desc_len,
746 entry->skb->data, entry->skb->len);
747
748 /*
749 * Clean up beacon skb.
750 */
751 dev_kfree_skb_any(entry->skb);
752 entry->skb = NULL;
753}
754
755static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
756 const enum data_queue_qid queue_idx)
757{
758 struct data_queue *queue;
759 unsigned int idx, qidx = 0;
760 u32 reg;
761
762 if (queue_idx == QID_BEACON) {
763 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
764 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
765 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
766 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
767 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
768 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
769 }
770 return;
771 }
772
773 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
774 return;
775
776 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
777 idx = queue->index[Q_INDEX];
778
779 if (queue_idx == QID_MGMT)
780 qidx = 5;
781 else
782 qidx = queue_idx;
783
784 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
785}
786
787static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
788 const enum data_queue_qid qid)
789{
790 u32 reg;
791
792 if (qid == QID_BEACON) {
793 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
794 return;
795 }
796
797 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
798 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
799 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
800 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
801 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
802 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
803}
804
805/*
806 * RX control handlers
807 */
808static void rt2800pci_fill_rxdone(struct queue_entry *entry,
809 struct rxdone_entry_desc *rxdesc)
810{
811 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
812 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
813 __le32 *rxd = entry_priv->desc;
814 __le32 *rxwi = (__le32 *)entry->skb->data;
815 u32 rxd3;
816 u32 rxwi0;
817 u32 rxwi1;
818 u32 rxwi2;
819 u32 rxwi3;
820
821 rt2x00_desc_read(rxd, 3, &rxd3);
822 rt2x00_desc_read(rxwi, 0, &rxwi0);
823 rt2x00_desc_read(rxwi, 1, &rxwi1);
824 rt2x00_desc_read(rxwi, 2, &rxwi2);
825 rt2x00_desc_read(rxwi, 3, &rxwi3);
826
827 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
828 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
829
830 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
831 /*
832 * Unfortunately we don't know the cipher type used during
833 * decryption. This prevents us from correct providing
834 * correct statistics through debugfs.
835 */
836 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
837 rxdesc->cipher_status =
838 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
839 }
840
841 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
842 /*
843 * Hardware has stripped IV/EIV data from 802.11 frame during
844 * decryption. Unfortunately the descriptor doesn't contain
845 * any fields with the EIV/IV data either, so they can't
846 * be restored by rt2x00lib.
847 */
848 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
849
850 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
851 rxdesc->flags |= RX_FLAG_DECRYPTED;
852 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
853 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
854 }
855
856 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
857 rxdesc->dev_flags |= RXDONE_MY_BSS;
858
859 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
860 rxdesc->dev_flags |= RXDONE_L2PAD;
861
862 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
863 rxdesc->flags |= RX_FLAG_SHORT_GI;
864
865 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
866 rxdesc->flags |= RX_FLAG_40MHZ;
867
868 /*
869 * Detect RX rate, always use MCS as signal type.
870 */
871 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
872 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
873 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
874
875 /*
876 * Mask of 0x8 bit to remove the short preamble flag.
877 */
878 if (rxdesc->rate_mode == RATE_MODE_CCK)
879 rxdesc->signal &= ~0x8;
880
881 rxdesc->rssi =
882 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
883 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
884
885 rxdesc->noise =
886 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
887 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
888
889 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
890
891 /*
892 * Set RX IDX in register to inform hardware that we have handled
893 * this entry and it is available for reuse again.
894 */
895 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
896
897 /*
898 * Remove TXWI descriptor from start of buffer.
899 */
900 skb_pull(entry->skb, RXWI_DESC_SIZE);
901}
902
903/*
904 * Interrupt functions.
905 */
906static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
907{
908 struct data_queue *queue;
909 struct queue_entry *entry;
910 struct queue_entry *entry_done;
911 struct queue_entry_priv_pci *entry_priv;
912 struct txdone_entry_desc txdesc;
913 u32 word;
914 u32 reg;
915 u32 old_reg;
916 unsigned int type;
917 unsigned int index;
918 u16 mcs, real_mcs;
919
920 /*
921 * During each loop we will compare the freshly read
922 * TX_STA_FIFO register value with the value read from
923 * the previous loop. If the 2 values are equal then
924 * we should stop processing because the chance it
925 * quite big that the device has been unplugged and
926 * we risk going into an endless loop.
927 */
928 old_reg = 0;
929
930 while (1) {
931 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
932 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
933 break;
934
935 if (old_reg == reg)
936 break;
937 old_reg = reg;
938
939 /*
940 * Skip this entry when it contains an invalid
941 * queue identication number.
942 */
943 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
944 if (type >= QID_RX)
945 continue;
946
947 queue = rt2x00queue_get_queue(rt2x00dev, type);
948 if (unlikely(!queue))
949 continue;
950
951 /*
952 * Skip this entry when it contains an invalid
953 * index number.
954 */
955 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
956 if (unlikely(index >= queue->limit))
957 continue;
958
959 entry = &queue->entries[index];
960 entry_priv = entry->priv_data;
961 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
962
963 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
964 while (entry != entry_done) {
965 /*
966 * Catch up.
967 * Just report any entries we missed as failed.
968 */
969 WARNING(rt2x00dev,
970 "TX status report missed for entry %d\n",
971 entry_done->entry_idx);
972
973 txdesc.flags = 0;
974 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
975 txdesc.retry = 0;
976
977 rt2x00lib_txdone(entry_done, &txdesc);
978 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
979 }
980
981 /*
982 * Obtain the status about this packet.
983 */
984 txdesc.flags = 0;
985 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
986 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
987 else
988 __set_bit(TXDONE_FAILURE, &txdesc.flags);
989
990 /*
991 * Ralink has a retry mechanism using a global fallback
992 * table. We setup this fallback table to try immediate
993 * lower rate for all rates. In the TX_STA_FIFO,
994 * the MCS field contains the MCS used for the successfull
995 * transmission. If the first transmission succeed,
996 * we have mcs == tx_mcs. On the second transmission,
997 * we have mcs = tx_mcs - 1. So the number of
998 * retry is (tx_mcs - mcs).
999 */
1000 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1001 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1002 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1003 txdesc.retry = mcs - min(mcs, real_mcs);
1004
1005 rt2x00lib_txdone(entry, &txdesc);
1006 }
1007}
1008
1009static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1010{
1011 struct rt2x00_dev *rt2x00dev = dev_instance;
1012 u32 reg;
1013
1014 /* Read status and ACK all interrupts */
1015 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1016 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1017
1018 if (!reg)
1019 return IRQ_NONE;
1020
1021 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1022 return IRQ_HANDLED;
1023
1024 /*
1025 * 1 - Rx ring done interrupt.
1026 */
1027 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1028 rt2x00pci_rxdone(rt2x00dev);
1029
1030 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1031 rt2800pci_txdone(rt2x00dev);
1032
1033 return IRQ_HANDLED;
1034}
1035
1036/*
1037 * Device probe functions.
1038 */
1039static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1040{
1041 /*
1042 * Read EEPROM into buffer
1043 */
1044 if (rt2x00_is_soc(rt2x00dev))
1045 rt2800pci_read_eeprom_soc(rt2x00dev);
1046 else if (rt2800pci_efuse_detect(rt2x00dev))
1047 rt2800pci_read_eeprom_efuse(rt2x00dev);
1048 else
1049 rt2800pci_read_eeprom_pci(rt2x00dev);
1050
1051 return rt2800_validate_eeprom(rt2x00dev);
1052}
1053
1054static const struct rt2800_ops rt2800pci_rt2800_ops = {
1055 .register_read = rt2x00pci_register_read,
1056 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1057 .register_write = rt2x00pci_register_write,
1058 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1059
1060 .register_multiread = rt2x00pci_register_multiread,
1061 .register_multiwrite = rt2x00pci_register_multiwrite,
1062
1063 .regbusy_read = rt2x00pci_regbusy_read,
1064};
1065
1066static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1067{
1068 int retval;
1069
1070 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1071
1072 /*
1073 * Allocate eeprom data.
1074 */
1075 retval = rt2800pci_validate_eeprom(rt2x00dev);
1076 if (retval)
1077 return retval;
1078
1079 retval = rt2800_init_eeprom(rt2x00dev);
1080 if (retval)
1081 return retval;
1082
1083 /*
1084 * Initialize hw specifications.
1085 */
1086 retval = rt2800_probe_hw_mode(rt2x00dev);
1087 if (retval)
1088 return retval;
1089
1090 /*
1091 * This device has multiple filters for control frames
1092 * and has a separate filter for PS Poll frames.
1093 */
1094 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1095 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1096
1097 /*
1098 * This device requires firmware.
1099 */
1100 if (!rt2x00_is_soc(rt2x00dev))
1101 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1102 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1103 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1104 if (!modparam_nohwcrypt)
1105 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1106
1107 /*
1108 * Set the rssi offset.
1109 */
1110 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1111
1112 return 0;
1113}
1114
1115static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1116 .irq_handler = rt2800pci_interrupt,
1117 .probe_hw = rt2800pci_probe_hw,
1118 .get_firmware_name = rt2800pci_get_firmware_name,
1119 .check_firmware = rt2800pci_check_firmware,
1120 .load_firmware = rt2800pci_load_firmware,
1121 .initialize = rt2x00pci_initialize,
1122 .uninitialize = rt2x00pci_uninitialize,
1123 .get_entry_state = rt2800pci_get_entry_state,
1124 .clear_entry = rt2800pci_clear_entry,
1125 .set_device_state = rt2800pci_set_device_state,
1126 .rfkill_poll = rt2800_rfkill_poll,
1127 .link_stats = rt2800_link_stats,
1128 .reset_tuner = rt2800_reset_tuner,
1129 .link_tuner = rt2800_link_tuner,
1130 .write_tx_desc = rt2800pci_write_tx_desc,
1131 .write_tx_data = rt2x00pci_write_tx_data,
1132 .write_beacon = rt2800pci_write_beacon,
1133 .kick_tx_queue = rt2800pci_kick_tx_queue,
1134 .kill_tx_queue = rt2800pci_kill_tx_queue,
1135 .fill_rxdone = rt2800pci_fill_rxdone,
1136 .config_shared_key = rt2800_config_shared_key,
1137 .config_pairwise_key = rt2800_config_pairwise_key,
1138 .config_filter = rt2800_config_filter,
1139 .config_intf = rt2800_config_intf,
1140 .config_erp = rt2800_config_erp,
1141 .config_ant = rt2800_config_ant,
1142 .config = rt2800_config,
1143};
1144
1145static const struct data_queue_desc rt2800pci_queue_rx = {
1146 .entry_num = RX_ENTRIES,
1147 .data_size = AGGREGATION_SIZE,
1148 .desc_size = RXD_DESC_SIZE,
1149 .priv_size = sizeof(struct queue_entry_priv_pci),
1150};
1151
1152static const struct data_queue_desc rt2800pci_queue_tx = {
1153 .entry_num = TX_ENTRIES,
1154 .data_size = AGGREGATION_SIZE,
1155 .desc_size = TXD_DESC_SIZE,
1156 .priv_size = sizeof(struct queue_entry_priv_pci),
1157};
1158
1159static const struct data_queue_desc rt2800pci_queue_bcn = {
1160 .entry_num = 8 * BEACON_ENTRIES,
1161 .data_size = 0, /* No DMA required for beacons */
1162 .desc_size = TXWI_DESC_SIZE,
1163 .priv_size = sizeof(struct queue_entry_priv_pci),
1164};
1165
1166static const struct rt2x00_ops rt2800pci_ops = {
1167 .name = KBUILD_MODNAME,
1168 .max_sta_intf = 1,
1169 .max_ap_intf = 8,
1170 .eeprom_size = EEPROM_SIZE,
1171 .rf_size = RF_SIZE,
1172 .tx_queues = NUM_TX_QUEUES,
1173 .extra_tx_headroom = TXWI_DESC_SIZE,
1174 .rx = &rt2800pci_queue_rx,
1175 .tx = &rt2800pci_queue_tx,
1176 .bcn = &rt2800pci_queue_bcn,
1177 .lib = &rt2800pci_rt2x00_ops,
1178 .hw = &rt2800_mac80211_ops,
1179#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1180 .debugfs = &rt2800_rt2x00debug,
1181#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1182};
1183
1184/*
1185 * RT2800pci module information.
1186 */
1187static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1188 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1189 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1190 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1191 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1192 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1193 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1194 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1195 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1196 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1197 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1198 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1199 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1200#ifdef CONFIG_RT2800PCI_RT30XX
1201 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1202 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1203 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1204 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1205#endif
1206#ifdef CONFIG_RT2800PCI_RT35XX
1207 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1208 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1209 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1210 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1211#endif
1212 { 0, }
1213};
1214
1215MODULE_AUTHOR(DRV_PROJECT);
1216MODULE_VERSION(DRV_VERSION);
1217MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1218MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1219#ifdef CONFIG_RT2800PCI_PCI
1220MODULE_FIRMWARE(FIRMWARE_RT2860);
1221MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1222#endif /* CONFIG_RT2800PCI_PCI */
1223MODULE_LICENSE("GPL");
1224
1225#ifdef CONFIG_RT2800PCI_SOC
1226static int rt2800soc_probe(struct platform_device *pdev)
1227{
1228 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1229}
1230
1231static struct platform_driver rt2800soc_driver = {
1232 .driver = {
1233 .name = "rt2800_wmac",
1234 .owner = THIS_MODULE,
1235 .mod_name = KBUILD_MODNAME,
1236 },
1237 .probe = rt2800soc_probe,
1238 .remove = __devexit_p(rt2x00soc_remove),
1239 .suspend = rt2x00soc_suspend,
1240 .resume = rt2x00soc_resume,
1241};
1242#endif /* CONFIG_RT2800PCI_SOC */
1243
1244#ifdef CONFIG_RT2800PCI_PCI
1245static struct pci_driver rt2800pci_driver = {
1246 .name = KBUILD_MODNAME,
1247 .id_table = rt2800pci_device_table,
1248 .probe = rt2x00pci_probe,
1249 .remove = __devexit_p(rt2x00pci_remove),
1250 .suspend = rt2x00pci_suspend,
1251 .resume = rt2x00pci_resume,
1252};
1253#endif /* CONFIG_RT2800PCI_PCI */
1254
1255static int __init rt2800pci_init(void)
1256{
1257 int ret = 0;
1258
1259#ifdef CONFIG_RT2800PCI_SOC
1260 ret = platform_driver_register(&rt2800soc_driver);
1261 if (ret)
1262 return ret;
1263#endif
1264#ifdef CONFIG_RT2800PCI_PCI
1265 ret = pci_register_driver(&rt2800pci_driver);
1266 if (ret) {
1267#ifdef CONFIG_RT2800PCI_SOC
1268 platform_driver_unregister(&rt2800soc_driver);
1269#endif
1270 return ret;
1271 }
1272#endif
1273
1274 return ret;
1275}
1276
1277static void __exit rt2800pci_exit(void)
1278{
1279#ifdef CONFIG_RT2800PCI_PCI
1280 pci_unregister_driver(&rt2800pci_driver);
1281#endif
1282#ifdef CONFIG_RT2800PCI_SOC
1283 platform_driver_unregister(&rt2800soc_driver);
1284#endif
1285}
1286
1287module_init(rt2800pci_init);
1288module_exit(rt2800pci_exit);
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
new file mode 100644
index 000000000000..afc8e7da27cb
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
@@ -0,0 +1,159 @@
1/*
2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/*
29 Module: rt2800pci
30 Abstract: Data structures and registers for the rt2800pci module.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34#ifndef RT2800PCI_H
35#define RT2800PCI_H
36
37/*
38 * PCI registers.
39 */
40
41/*
42 * E2PROM_CSR: EEPROM control register.
43 * RELOAD: Write 1 to reload eeprom content.
44 * TYPE: 0: 93c46, 1:93c66.
45 * LOAD_STATUS: 1:loading, 0:done.
46 */
47#define E2PROM_CSR 0x0004
48#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
49#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
50#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
51#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
52#define E2PROM_CSR_TYPE FIELD32(0x00000030)
53#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
54#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
55
56/*
57 * Queue register offset macros
58 */
59#define TX_QUEUE_REG_OFFSET 0x10
60#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
61#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
62#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
63#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
64
65/*
66 * 8051 firmware image.
67 */
68#define FIRMWARE_RT2860 "rt2860.bin"
69#define FIRMWARE_IMAGE_BASE 0x2000
70
71/*
72 * DMA descriptor defines.
73 */
74#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
75#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
76
77/*
78 * TX descriptor format for TX, PRIO and Beacon Ring.
79 */
80
81/*
82 * Word0
83 */
84#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
85
86/*
87 * Word1
88 */
89#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
90#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
91#define TXD_W1_BURST FIELD32(0x00008000)
92#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
93#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
94#define TXD_W1_DMA_DONE FIELD32(0x80000000)
95
96/*
97 * Word2
98 */
99#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
100
101/*
102 * Word3
103 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
104 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
105 * 0:MGMT, 1:HCCA 2:EDCA
106 */
107#define TXD_W3_WIV FIELD32(0x01000000)
108#define TXD_W3_QSEL FIELD32(0x06000000)
109#define TXD_W3_TCO FIELD32(0x20000000)
110#define TXD_W3_UCO FIELD32(0x40000000)
111#define TXD_W3_ICO FIELD32(0x80000000)
112
113/*
114 * RX descriptor format for RX Ring.
115 */
116
117/*
118 * Word0
119 */
120#define RXD_W0_SDP0 FIELD32(0xffffffff)
121
122/*
123 * Word1
124 */
125#define RXD_W1_SDL1 FIELD32(0x00003fff)
126#define RXD_W1_SDL0 FIELD32(0x3fff0000)
127#define RXD_W1_LS0 FIELD32(0x40000000)
128#define RXD_W1_DMA_DONE FIELD32(0x80000000)
129
130/*
131 * Word2
132 */
133#define RXD_W2_SDP1 FIELD32(0xffffffff)
134
135/*
136 * Word3
137 * AMSDU: RX with 802.3 header, not 802.11 header.
138 * DECRYPTED: This frame is being decrypted.
139 */
140#define RXD_W3_BA FIELD32(0x00000001)
141#define RXD_W3_DATA FIELD32(0x00000002)
142#define RXD_W3_NULLDATA FIELD32(0x00000004)
143#define RXD_W3_FRAG FIELD32(0x00000008)
144#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
145#define RXD_W3_MULTICAST FIELD32(0x00000020)
146#define RXD_W3_BROADCAST FIELD32(0x00000040)
147#define RXD_W3_MY_BSS FIELD32(0x00000080)
148#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
149#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
150#define RXD_W3_AMSDU FIELD32(0x00000800)
151#define RXD_W3_HTC FIELD32(0x00001000)
152#define RXD_W3_RSSI FIELD32(0x00002000)
153#define RXD_W3_L2PAD FIELD32(0x00004000)
154#define RXD_W3_AMPDU FIELD32(0x00008000)
155#define RXD_W3_DECRYPTED FIELD32(0x00010000)
156#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
157#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
158
159#endif /* RT2800PCI_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 9fe770f7d7bb..d27d7d5d850c 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -1,5 +1,9 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
6 Copyright (C) 2009 Axel Kollhofer <rain_maker@root-forum.org>
3 <http://rt2x00.serialmonkey.com> 7 <http://rt2x00.serialmonkey.com>
4 8
5 This program is free software; you can redistribute it and/or modify 9 This program is free software; you can redistribute it and/or modify
@@ -34,6 +38,8 @@
34 38
35#include "rt2x00.h" 39#include "rt2x00.h"
36#include "rt2x00usb.h" 40#include "rt2x00usb.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
37#include "rt2800usb.h" 43#include "rt2800usb.h"
38 44
39/* 45/*
@@ -44,1027 +50,6 @@ module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 50MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45 51
46/* 52/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 mutex_lock(&rt2x00dev->csr_mutex);
76
77 /*
78 * Wait until the BBP becomes available, afterwards we
79 * can safely write the new data into the register.
80 */
81 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
82 reg = 0;
83 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
84 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
85 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
86 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
87
88 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
89 }
90
91 mutex_unlock(&rt2x00dev->csr_mutex);
92}
93
94static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95 const unsigned int word, u8 *value)
96{
97 u32 reg;
98
99 mutex_lock(&rt2x00dev->csr_mutex);
100
101 /*
102 * Wait until the BBP becomes available, afterwards we
103 * can safely write the read request into the register.
104 * After the data has been written, we wait until hardware
105 * returns the correct value, if at any time the register
106 * doesn't become available in time, reg will be 0xffffffff
107 * which means we return 0xff to the caller.
108 */
109 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
110 reg = 0;
111 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
112 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
113 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
114
115 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
116
117 WAIT_FOR_BBP(rt2x00dev, &reg);
118 }
119
120 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
121
122 mutex_unlock(&rt2x00dev->csr_mutex);
123}
124
125static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
130 mutex_lock(&rt2x00dev->csr_mutex);
131
132 /*
133 * Wait until the RFCSR becomes available, afterwards we
134 * can safely write the new data into the register.
135 */
136 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
137 reg = 0;
138 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
139 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
140 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
141 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
142
143 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
144 }
145
146 mutex_unlock(&rt2x00dev->csr_mutex);
147}
148
149static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
150 const unsigned int word, u8 *value)
151{
152 u32 reg;
153
154 mutex_lock(&rt2x00dev->csr_mutex);
155
156 /*
157 * Wait until the RFCSR becomes available, afterwards we
158 * can safely write the read request into the register.
159 * After the data has been written, we wait until hardware
160 * returns the correct value, if at any time the register
161 * doesn't become available in time, reg will be 0xffffffff
162 * which means we return 0xff to the caller.
163 */
164 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
165 reg = 0;
166 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
167 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
168 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
169
170 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
171
172 WAIT_FOR_RFCSR(rt2x00dev, &reg);
173 }
174
175 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
176
177 mutex_unlock(&rt2x00dev->csr_mutex);
178}
179
180static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
181 const unsigned int word, const u32 value)
182{
183 u32 reg;
184
185 mutex_lock(&rt2x00dev->csr_mutex);
186
187 /*
188 * Wait until the RF becomes available, afterwards we
189 * can safely write the new data into the register.
190 */
191 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
192 reg = 0;
193 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
194 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
195 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
196 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
197
198 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
199 rt2x00_rf_write(rt2x00dev, word, value);
200 }
201
202 mutex_unlock(&rt2x00dev->csr_mutex);
203}
204
205static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
206 const u8 command, const u8 token,
207 const u8 arg0, const u8 arg1)
208{
209 u32 reg;
210
211 mutex_lock(&rt2x00dev->csr_mutex);
212
213 /*
214 * Wait until the MCU becomes available, afterwards we
215 * can safely write the new data into the register.
216 */
217 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
218 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
219 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
220 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
221 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
222 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
223
224 reg = 0;
225 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
226 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
227 }
228
229 mutex_unlock(&rt2x00dev->csr_mutex);
230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
233static const struct rt2x00debug rt2800usb_rt2x00debug = {
234 .owner = THIS_MODULE,
235 .csr = {
236 .read = rt2x00usb_register_read,
237 .write = rt2x00usb_register_write,
238 .flags = RT2X00DEBUGFS_OFFSET,
239 .word_base = CSR_REG_BASE,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_base = EEPROM_BASE,
247 .word_size = sizeof(u16),
248 .word_count = EEPROM_SIZE / sizeof(u16),
249 },
250 .bbp = {
251 .read = rt2800usb_bbp_read,
252 .write = rt2800usb_bbp_write,
253 .word_base = BBP_BASE,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt2800usb_rf_write,
260 .word_base = RF_BASE,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
268{
269 u32 reg;
270
271 rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
272 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
273}
274
275#ifdef CONFIG_RT2X00_LIB_LEDS
276static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
277 enum led_brightness brightness)
278{
279 struct rt2x00_led *led =
280 container_of(led_cdev, struct rt2x00_led, led_dev);
281 unsigned int enabled = brightness != LED_OFF;
282 unsigned int bg_mode =
283 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
284 unsigned int polarity =
285 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
286 EEPROM_FREQ_LED_POLARITY);
287 unsigned int ledmode =
288 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
289 EEPROM_FREQ_LED_MODE);
290
291 if (led->type == LED_TYPE_RADIO) {
292 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
293 enabled ? 0x20 : 0);
294 } else if (led->type == LED_TYPE_ASSOC) {
295 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
296 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
297 } else if (led->type == LED_TYPE_QUALITY) {
298 /*
299 * The brightness is divided into 6 levels (0 - 5),
300 * The specs tell us the following levels:
301 * 0, 1 ,3, 7, 15, 31
302 * to determine the level in a simple way we can simply
303 * work with bitshifting:
304 * (1 << level) - 1
305 */
306 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
307 (1 << brightness / (LED_FULL / 6)) - 1,
308 polarity);
309 }
310}
311
312static int rt2800usb_blink_set(struct led_classdev *led_cdev,
313 unsigned long *delay_on,
314 unsigned long *delay_off)
315{
316 struct rt2x00_led *led =
317 container_of(led_cdev, struct rt2x00_led, led_dev);
318 u32 reg;
319
320 rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
321 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
322 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
323 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
324 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
325 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
326 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
327 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
328 rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
329
330 return 0;
331}
332
333static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
334 struct rt2x00_led *led,
335 enum led_type type)
336{
337 led->rt2x00dev = rt2x00dev;
338 led->type = type;
339 led->led_dev.brightness_set = rt2800usb_brightness_set;
340 led->led_dev.blink_set = rt2800usb_blink_set;
341 led->flags = LED_INITIALIZED;
342}
343#endif /* CONFIG_RT2X00_LIB_LEDS */
344
345/*
346 * Configuration handlers.
347 */
348static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
349 struct rt2x00lib_crypto *crypto,
350 struct ieee80211_key_conf *key)
351{
352 struct mac_wcid_entry wcid_entry;
353 struct mac_iveiv_entry iveiv_entry;
354 u32 offset;
355 u32 reg;
356
357 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
358
359 rt2x00usb_register_read(rt2x00dev, offset, &reg);
360 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
361 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
362 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
363 (crypto->cmd == SET_KEY) * crypto->cipher);
364 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
365 (crypto->cmd == SET_KEY) * crypto->bssidx);
366 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
367 rt2x00usb_register_write(rt2x00dev, offset, reg);
368
369 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
370
371 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
372 if ((crypto->cipher == CIPHER_TKIP) ||
373 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
374 (crypto->cipher == CIPHER_AES))
375 iveiv_entry.iv[3] |= 0x20;
376 iveiv_entry.iv[3] |= key->keyidx << 6;
377 rt2x00usb_register_multiwrite(rt2x00dev, offset,
378 &iveiv_entry, sizeof(iveiv_entry));
379
380 offset = MAC_WCID_ENTRY(key->hw_key_idx);
381
382 memset(&wcid_entry, 0, sizeof(wcid_entry));
383 if (crypto->cmd == SET_KEY)
384 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
385 rt2x00usb_register_multiwrite(rt2x00dev, offset,
386 &wcid_entry, sizeof(wcid_entry));
387}
388
389static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
390 struct rt2x00lib_crypto *crypto,
391 struct ieee80211_key_conf *key)
392{
393 struct hw_key_entry key_entry;
394 struct rt2x00_field32 field;
395 int timeout;
396 u32 offset;
397 u32 reg;
398
399 if (crypto->cmd == SET_KEY) {
400 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
401
402 memcpy(key_entry.key, crypto->key,
403 sizeof(key_entry.key));
404 memcpy(key_entry.tx_mic, crypto->tx_mic,
405 sizeof(key_entry.tx_mic));
406 memcpy(key_entry.rx_mic, crypto->rx_mic,
407 sizeof(key_entry.rx_mic));
408
409 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
410 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
411 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
412 USB_VENDOR_REQUEST_OUT,
413 offset, &key_entry,
414 sizeof(key_entry),
415 timeout);
416 }
417
418 /*
419 * The cipher types are stored over multiple registers
420 * starting with SHARED_KEY_MODE_BASE each word will have
421 * 32 bits and contains the cipher types for 2 bssidx each.
422 * Using the correct defines correctly will cause overhead,
423 * so just calculate the correct offset.
424 */
425 field.bit_offset = 4 * (key->hw_key_idx % 8);
426 field.bit_mask = 0x7 << field.bit_offset;
427
428 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
429
430 rt2x00usb_register_read(rt2x00dev, offset, &reg);
431 rt2x00_set_field32(&reg, field,
432 (crypto->cmd == SET_KEY) * crypto->cipher);
433 rt2x00usb_register_write(rt2x00dev, offset, reg);
434
435 /*
436 * Update WCID information
437 */
438 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
439
440 return 0;
441}
442
443static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
444 struct rt2x00lib_crypto *crypto,
445 struct ieee80211_key_conf *key)
446{
447 struct hw_key_entry key_entry;
448 int timeout;
449 u32 offset;
450
451 if (crypto->cmd == SET_KEY) {
452 /*
453 * 1 pairwise key is possible per AID, this means that the AID
454 * equals our hw_key_idx. Make sure the WCID starts _after_ the
455 * last possible shared key entry.
456 */
457 if (crypto->aid > (256 - 32))
458 return -ENOSPC;
459
460 key->hw_key_idx = 32 + crypto->aid;
461
462 memcpy(key_entry.key, crypto->key,
463 sizeof(key_entry.key));
464 memcpy(key_entry.tx_mic, crypto->tx_mic,
465 sizeof(key_entry.tx_mic));
466 memcpy(key_entry.rx_mic, crypto->rx_mic,
467 sizeof(key_entry.rx_mic));
468
469 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
470 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
471 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
472 USB_VENDOR_REQUEST_OUT,
473 offset, &key_entry,
474 sizeof(key_entry),
475 timeout);
476 }
477
478 /*
479 * Update WCID information
480 */
481 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
482
483 return 0;
484}
485
486static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
487 const unsigned int filter_flags)
488{
489 u32 reg;
490
491 /*
492 * Start configuration steps.
493 * Note that the version error will always be dropped
494 * and broadcast frames will always be accepted since
495 * there is no filter for it at this time.
496 */
497 rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
498 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
499 !(filter_flags & FIF_FCSFAIL));
500 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
501 !(filter_flags & FIF_PLCPFAIL));
502 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
503 !(filter_flags & FIF_PROMISC_IN_BSS));
504 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
505 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
506 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
507 !(filter_flags & FIF_ALLMULTI));
508 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
510 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
511 !(filter_flags & FIF_CONTROL));
512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
513 !(filter_flags & FIF_CONTROL));
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
515 !(filter_flags & FIF_CONTROL));
516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
517 !(filter_flags & FIF_CONTROL));
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
519 !(filter_flags & FIF_CONTROL));
520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
521 !(filter_flags & FIF_PSPOLL));
522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
523 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
525 !(filter_flags & FIF_CONTROL));
526 rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
527}
528
529static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
530 struct rt2x00_intf *intf,
531 struct rt2x00intf_conf *conf,
532 const unsigned int flags)
533{
534 unsigned int beacon_base;
535 u32 reg;
536
537 if (flags & CONFIG_UPDATE_TYPE) {
538 /*
539 * Clear current synchronisation setup.
540 * For the Beacon base registers we only need to clear
541 * the first byte since that byte contains the VALID and OWNER
542 * bits which (when set to 0) will invalidate the entire beacon.
543 */
544 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
545 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
546
547 /*
548 * Enable synchronisation.
549 */
550 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
551 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
552 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
553 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
554 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
555 }
556
557 if (flags & CONFIG_UPDATE_MAC) {
558 reg = le32_to_cpu(conf->mac[1]);
559 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
560 conf->mac[1] = cpu_to_le32(reg);
561
562 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
563 conf->mac, sizeof(conf->mac));
564 }
565
566 if (flags & CONFIG_UPDATE_BSSID) {
567 reg = le32_to_cpu(conf->bssid[1]);
568 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
569 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
570 conf->bssid[1] = cpu_to_le32(reg);
571
572 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
573 conf->bssid, sizeof(conf->bssid));
574 }
575}
576
577static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
578 struct rt2x00lib_erp *erp)
579{
580 u32 reg;
581
582 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
583 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
584 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
585
586 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
587 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
588 !!erp->short_preamble);
589 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
590 !!erp->short_preamble);
591 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
592
593 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
594 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
595 erp->cts_protection ? 2 : 0);
596 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
597
598 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
599 erp->basic_rates);
600 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
601
602 rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
603 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
604 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
605 rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
606
607 rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
608 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
609 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
610 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
611 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
612 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
613 rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
614
615 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
616 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
617 erp->beacon_int * 16);
618 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
619}
620
621static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
622 struct antenna_setup *ant)
623{
624 u8 r1;
625 u8 r3;
626
627 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
628 rt2800usb_bbp_read(rt2x00dev, 3, &r3);
629
630 /*
631 * Configure the TX antenna.
632 */
633 switch ((int)ant->tx) {
634 case 1:
635 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
636 break;
637 case 2:
638 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
639 break;
640 case 3:
641 /* Do nothing */
642 break;
643 }
644
645 /*
646 * Configure the RX antenna.
647 */
648 switch ((int)ant->rx) {
649 case 1:
650 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
651 break;
652 case 2:
653 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
654 break;
655 case 3:
656 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
657 break;
658 }
659
660 rt2800usb_bbp_write(rt2x00dev, 3, r3);
661 rt2800usb_bbp_write(rt2x00dev, 1, r1);
662}
663
664static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
665 struct rt2x00lib_conf *libconf)
666{
667 u16 eeprom;
668 short lna_gain;
669
670 if (libconf->rf.channel <= 14) {
671 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
672 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
673 } else if (libconf->rf.channel <= 64) {
674 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
675 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
676 } else if (libconf->rf.channel <= 128) {
677 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
678 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
679 } else {
680 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
681 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
682 }
683
684 rt2x00dev->lna_gain = lna_gain;
685}
686
687static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
688 struct ieee80211_conf *conf,
689 struct rf_channel *rf,
690 struct channel_info *info)
691{
692 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
693
694 if (rt2x00dev->default_ant.tx == 1)
695 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
696
697 if (rt2x00dev->default_ant.rx == 1) {
698 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
699 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
700 } else if (rt2x00dev->default_ant.rx == 2)
701 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
702
703 if (rf->channel > 14) {
704 /*
705 * When TX power is below 0, we should increase it by 7 to
706 * make it a positive value (Minumum value is -7).
707 * However this means that values between 0 and 7 have
708 * double meaning, and we should set a 7DBm boost flag.
709 */
710 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
711 (info->tx_power1 >= 0));
712
713 if (info->tx_power1 < 0)
714 info->tx_power1 += 7;
715
716 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
717 TXPOWER_A_TO_DEV(info->tx_power1));
718
719 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
720 (info->tx_power2 >= 0));
721
722 if (info->tx_power2 < 0)
723 info->tx_power2 += 7;
724
725 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
726 TXPOWER_A_TO_DEV(info->tx_power2));
727 } else {
728 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
729 TXPOWER_G_TO_DEV(info->tx_power1));
730 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
731 TXPOWER_G_TO_DEV(info->tx_power2));
732 }
733
734 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
735
736 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
737 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
738 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
739 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
740
741 udelay(200);
742
743 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
744 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
745 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
746 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
747
748 udelay(200);
749
750 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
751 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
752 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
753 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
754}
755
756static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
757 struct ieee80211_conf *conf,
758 struct rf_channel *rf,
759 struct channel_info *info)
760{
761 u8 rfcsr;
762
763 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
764 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
765
766 rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
767 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
768 rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
769
770 rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
771 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
772 TXPOWER_G_TO_DEV(info->tx_power1));
773 rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
774
775 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
776 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
777 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
778
779 rt2800usb_rfcsr_write(rt2x00dev, 24,
780 rt2x00dev->calibration[conf_is_ht40(conf)]);
781
782 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
783 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
784 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
785}
786
787static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
788 struct ieee80211_conf *conf,
789 struct rf_channel *rf,
790 struct channel_info *info)
791{
792 u32 reg;
793 unsigned int tx_pin;
794 u8 bbp;
795
796 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
797 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
798 else
799 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
800
801 /*
802 * Change BBP settings
803 */
804 rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
805 rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
806 rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
807 rt2800usb_bbp_write(rt2x00dev, 86, 0);
808
809 if (rf->channel <= 14) {
810 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
811 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
812 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
813 } else {
814 rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
815 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
816 }
817 } else {
818 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
819
820 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
821 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
822 else
823 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
824 }
825
826 rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
827 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
828 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
829 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
830 rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
831
832 tx_pin = 0;
833
834 /* Turn on unused PA or LNA when not using 1T or 1R */
835 if (rt2x00dev->default_ant.tx != 1) {
836 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
837 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
838 }
839
840 /* Turn on unused PA or LNA when not using 1T or 1R */
841 if (rt2x00dev->default_ant.rx != 1) {
842 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
843 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
844 }
845
846 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
847 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
848 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
849 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
850 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
851 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
852
853 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
854
855 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
856 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
857 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
858
859 rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
860 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
861 rt2800usb_bbp_write(rt2x00dev, 3, bbp);
862
863 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
864 if (conf_is_ht40(conf)) {
865 rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
866 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
867 rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
868 } else {
869 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
870 rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
871 rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
872 }
873 }
874
875 msleep(1);
876}
877
878static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
879 const int txpower)
880{
881 u32 reg;
882 u32 value = TXPOWER_G_TO_DEV(txpower);
883 u8 r1;
884
885 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
886 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
887 rt2800usb_bbp_write(rt2x00dev, 1, r1);
888
889 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
890 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
891 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
892 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
893 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
894 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
895 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
896 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
897 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
898 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
899
900 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
901 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
902 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
903 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
904 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
905 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
906 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
907 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
908 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
909 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
910
911 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
914 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
915 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
916 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
917 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
918 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
919 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
920 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
921
922 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
927 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
928 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
929 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
931 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
932
933 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
938 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
939}
940
941static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
942 struct rt2x00lib_conf *libconf)
943{
944 u32 reg;
945
946 rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
947 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
948 libconf->conf->short_frame_max_tx_count);
949 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
950 libconf->conf->long_frame_max_tx_count);
951 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
952 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
953 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
954 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
955 rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
956}
957
958static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
959 struct rt2x00lib_conf *libconf)
960{
961 enum dev_state state =
962 (libconf->conf->flags & IEEE80211_CONF_PS) ?
963 STATE_SLEEP : STATE_AWAKE;
964 u32 reg;
965
966 if (state == STATE_SLEEP) {
967 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
968
969 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
970 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
971 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
972 libconf->conf->listen_interval - 1);
973 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
974 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
975
976 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
977 } else {
978 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
979
980 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
981 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
982 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
983 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
984 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
985 }
986}
987
988static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
989 struct rt2x00lib_conf *libconf,
990 const unsigned int flags)
991{
992 /* Always recalculate LNA gain before changing configuration */
993 rt2800usb_config_lna_gain(rt2x00dev, libconf);
994
995 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
996 rt2800usb_config_channel(rt2x00dev, libconf->conf,
997 &libconf->rf, &libconf->channel);
998 if (flags & IEEE80211_CONF_CHANGE_POWER)
999 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1000 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1001 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1002 if (flags & IEEE80211_CONF_CHANGE_PS)
1003 rt2800usb_config_ps(rt2x00dev, libconf);
1004}
1005
1006/*
1007 * Link tuning
1008 */
1009static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1010 struct link_qual *qual)
1011{
1012 u32 reg;
1013
1014 /*
1015 * Update FCS error count from register.
1016 */
1017 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1018 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1019}
1020
1021static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1022{
1023 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1024 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1025 return 0x1c + (2 * rt2x00dev->lna_gain);
1026 else
1027 return 0x2e + rt2x00dev->lna_gain;
1028 }
1029
1030 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1031 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1032 else
1033 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1034}
1035
1036static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1037 struct link_qual *qual, u8 vgc_level)
1038{
1039 if (qual->vgc_level != vgc_level) {
1040 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1041 qual->vgc_level = vgc_level;
1042 qual->vgc_level_reg = vgc_level;
1043 }
1044}
1045
1046static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1047 struct link_qual *qual)
1048{
1049 rt2800usb_set_vgc(rt2x00dev, qual,
1050 rt2800usb_get_default_vgc(rt2x00dev));
1051}
1052
1053static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1054 struct link_qual *qual, const u32 count)
1055{
1056 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1057 return;
1058
1059 /*
1060 * When RSSI is better then -80 increase VGC level with 0x10
1061 */
1062 rt2800usb_set_vgc(rt2x00dev, qual,
1063 rt2800usb_get_default_vgc(rt2x00dev) +
1064 ((qual->rssi > -80) * 0x10));
1065}
1066
1067/*
1068 * Firmware functions 53 * Firmware functions
1069 */ 54 */
1070static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) 55static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -1107,7 +92,6 @@ static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1107static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev, 92static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1108 const u8 *data, const size_t len) 93 const u8 *data, const size_t len)
1109{ 94{
1110 u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1111 size_t offset = 0; 95 size_t offset = 0;
1112 96
1113 /* 97 /*
@@ -1115,7 +99,7 @@ static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1115 * There are 2 variations of the rt2870 firmware. 99 * There are 2 variations of the rt2870 firmware.
1116 * a) size: 4kb 100 * a) size: 4kb
1117 * b) size: 8kb 101 * b) size: 8kb
1118 * Note that (b) contains 2 seperate firmware blobs of 4k 102 * Note that (b) contains 2 separate firmware blobs of 4k
1119 * within the file. The first blob is the same firmware as (a), 103 * within the file. The first blob is the same firmware as (a),
1120 * but the second blob is for the additional chipsets. 104 * but the second blob is for the additional chipsets.
1121 */ 105 */
@@ -1126,14 +110,14 @@ static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1126 * Check if we need the upper 4kb firmware data or not. 110 * Check if we need the upper 4kb firmware data or not.
1127 */ 111 */
1128 if ((len == 4096) && 112 if ((len == 4096) &&
1129 (chipset != 0x2860) && 113 !rt2x00_rt(rt2x00dev, RT2860) &&
1130 (chipset != 0x2872) && 114 !rt2x00_rt(rt2x00dev, RT2872) &&
1131 (chipset != 0x3070)) 115 !rt2x00_rt(rt2x00dev, RT3070))
1132 return FW_BAD_VERSION; 116 return FW_BAD_VERSION;
1133 117
1134 /* 118 /*
1135 * 8kb firmware files must be checked as if it were 119 * 8kb firmware files must be checked as if it were
1136 * 2 seperate firmware files. 120 * 2 separate firmware files.
1137 */ 121 */
1138 while (offset < len) { 122 while (offset < len) {
1139 if (!rt2800usb_check_crc(data + offset, 4096)) 123 if (!rt2800usb_check_crc(data + offset, 4096))
@@ -1153,14 +137,13 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1153 u32 reg; 137 u32 reg;
1154 u32 offset; 138 u32 offset;
1155 u32 length; 139 u32 length;
1156 u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1157 140
1158 /* 141 /*
1159 * Check which section of the firmware we need. 142 * Check which section of the firmware we need.
1160 */ 143 */
1161 if ((chipset == 0x2860) || 144 if (rt2x00_rt(rt2x00dev, RT2860) ||
1162 (chipset == 0x2872) || 145 rt2x00_rt(rt2x00dev, RT2872) ||
1163 (chipset == 0x3070)) { 146 rt2x00_rt(rt2x00dev, RT3070)) {
1164 offset = 0; 147 offset = 0;
1165 length = 4096; 148 length = 4096;
1166 } else { 149 } else {
@@ -1172,7 +155,7 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1172 * Wait for stable hardware. 155 * Wait for stable hardware.
1173 */ 156 */
1174 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 157 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1175 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); 158 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1176 if (reg && reg != ~0) 159 if (reg && reg != ~0)
1177 break; 160 break;
1178 msleep(1); 161 msleep(1);
@@ -1192,8 +175,8 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1192 data + offset, length, 175 data + offset, length,
1193 REGISTER_TIMEOUT32(length)); 176 REGISTER_TIMEOUT32(length));
1194 177
1195 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 178 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1196 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 179 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1197 180
1198 /* 181 /*
1199 * Send firmware request to device to load firmware, 182 * Send firmware request to device to load firmware,
@@ -1208,18 +191,18 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1208 } 191 }
1209 192
1210 msleep(10); 193 msleep(10);
1211 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 194 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1212 195
1213 /* 196 /*
1214 * Send signal to firmware during boot time. 197 * Send signal to firmware during boot time.
1215 */ 198 */
1216 rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0); 199 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1217 200
1218 if ((chipset == 0x3070) || 201 if (rt2x00_rt(rt2x00dev, RT3070) ||
1219 (chipset == 0x3071) || 202 rt2x00_rt(rt2x00dev, RT3071) ||
1220 (chipset == 0x3572)) { 203 rt2x00_rt(rt2x00dev, RT3572)) {
1221 udelay(200); 204 udelay(200);
1222 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 205 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1223 udelay(10); 206 udelay(10);
1224 } 207 }
1225 208
@@ -1227,7 +210,7 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1227 * Wait for device to stabilize. 210 * Wait for device to stabilize.
1228 */ 211 */
1229 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 212 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1230 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 213 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1231 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 214 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1232 break; 215 break;
1233 msleep(1); 216 msleep(1);
@@ -1241,536 +224,14 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1241 /* 224 /*
1242 * Initialize firmware. 225 * Initialize firmware.
1243 */ 226 */
1244 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 227 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1245 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 228 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1246 msleep(1); 229 msleep(1);
1247 230
1248 return 0; 231 return 0;
1249} 232}
1250 233
1251/* 234/*
1252 * Initialization functions.
1253 */
1254static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1255{
1256 u32 reg;
1257 unsigned int i;
1258
1259 /*
1260 * Wait untill BBP and RF are ready.
1261 */
1262 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1263 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1264 if (reg && reg != ~0)
1265 break;
1266 msleep(1);
1267 }
1268
1269 if (i == REGISTER_BUSY_COUNT) {
1270 ERROR(rt2x00dev, "Unstable hardware.\n");
1271 return -EBUSY;
1272 }
1273
1274 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1275 rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1276
1277 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1278 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1279 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1280 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1281
1282 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1283
1284 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1285 USB_MODE_RESET, REGISTER_TIMEOUT);
1286
1287 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1288
1289 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1290 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1291 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1292 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1293 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1294 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1295
1296 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1297 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1298 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1299 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1300 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1301 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1302
1303 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1304 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1305
1306 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1307
1308 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1309 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1310 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1311 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1312 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1313 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1314 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1315 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1316
1317 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1318 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1319 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1320 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1321 } else {
1322 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1323 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1324 }
1325
1326 rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1327 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1328 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1329 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1330 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1331 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1332 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1333 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1334 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1335 rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1336
1337 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1338 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1339 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1340 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1341
1342 rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1343 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1344 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1345 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1346 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1347 else
1348 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1349 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1350 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1351 rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1352
1353 rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1354
1355 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1356 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1357 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1358 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1359 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1360 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1361 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1362
1363 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1364 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1365 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1366 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1367 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1368 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1369 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1370 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1371 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1372 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1373 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1374
1375 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1376 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1377 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1378 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1379 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1380 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1381 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1382 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1383 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1384 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1385 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1386
1387 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1388 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1389 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1390 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1391 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1392 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1393 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1394 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1395 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1396 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1397 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1398
1399 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1400 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1401 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1402 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1403 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1404 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1405 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1406 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1407 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1408 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1409 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1410
1411 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1412 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1413 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1414 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1415 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1416 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1417 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1418 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1419 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1420 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1421 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1422
1423 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1424 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1425 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1426 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1427 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1428 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1429 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1430 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1431 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1432 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1433 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1434
1435 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1436
1437 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1438 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1439 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1440 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1441 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1442 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1443 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1444 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1445 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1446 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1447 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1448
1449 rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1450 rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1451
1452 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1453 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1454 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1455 IEEE80211_MAX_RTS_THRESHOLD);
1456 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1457 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1458
1459 rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1460 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1461
1462 /*
1463 * ASIC will keep garbage value after boot, clear encryption keys.
1464 */
1465 for (i = 0; i < 4; i++)
1466 rt2x00usb_register_write(rt2x00dev,
1467 SHARED_KEY_MODE_ENTRY(i), 0);
1468
1469 for (i = 0; i < 256; i++) {
1470 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1471 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1472 wcid, sizeof(wcid));
1473
1474 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1475 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1476 }
1477
1478 /*
1479 * Clear all beacons
1480 * For the Beacon base registers we only need to clear
1481 * the first byte since that byte contains the VALID and OWNER
1482 * bits which (when set to 0) will invalidate the entire beacon.
1483 */
1484 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1485 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1486 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1487 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1488 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1489 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1490 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1491 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1492
1493 rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1494 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1495 rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1496
1497 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1498 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1499 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1500 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1501 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1502 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1503 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1504 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1505 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1506 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1507
1508 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1509 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1510 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1511 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1512 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1513 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1514 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1515 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1516 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1517 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1518
1519 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1520 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1521 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1522 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1523 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1524 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1525 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1526 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1527 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1528 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1529
1530 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1531 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1532 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1533 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1534 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1535 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1536
1537 /*
1538 * We must clear the error counters.
1539 * These registers are cleared on read,
1540 * so we may pass a useless variable to store the value.
1541 */
1542 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1543 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1544 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1545 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1546 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1547 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1548
1549 return 0;
1550}
1551
1552static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1553{
1554 unsigned int i;
1555 u32 reg;
1556
1557 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1558 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1559 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1560 return 0;
1561
1562 udelay(REGISTER_BUSY_DELAY);
1563 }
1564
1565 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1566 return -EACCES;
1567}
1568
1569static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1570{
1571 unsigned int i;
1572 u8 value;
1573
1574 /*
1575 * BBP was enabled after firmware was loaded,
1576 * but we need to reactivate it now.
1577 */
1578 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1579 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1580 msleep(1);
1581
1582 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1583 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1584 if ((value != 0xff) && (value != 0x00))
1585 return 0;
1586 udelay(REGISTER_BUSY_DELAY);
1587 }
1588
1589 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1590 return -EACCES;
1591}
1592
1593static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1594{
1595 unsigned int i;
1596 u16 eeprom;
1597 u8 reg_id;
1598 u8 value;
1599
1600 if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1601 rt2800usb_wait_bbp_ready(rt2x00dev)))
1602 return -EACCES;
1603
1604 rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1605 rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1606 rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1607 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1608 rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1609 rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1610 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1611 rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1612 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1613 rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1614 rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1615 rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1616 rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1617 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1618
1619 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1620 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1621 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1622 }
1623
1624 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1625 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1626 }
1627
1628 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1629 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1630 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1631 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1632 }
1633
1634 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1635 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1636
1637 if (eeprom != 0xffff && eeprom != 0x0000) {
1638 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1639 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1640 rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1641 }
1642 }
1643
1644 return 0;
1645}
1646
1647static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1648 bool bw40, u8 rfcsr24, u8 filter_target)
1649{
1650 unsigned int i;
1651 u8 bbp;
1652 u8 rfcsr;
1653 u8 passband;
1654 u8 stopband;
1655 u8 overtuned = 0;
1656
1657 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1658
1659 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1660 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1661 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1662
1663 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1664 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1665 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1666
1667 /*
1668 * Set power & frequency of passband test tone
1669 */
1670 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1671
1672 for (i = 0; i < 100; i++) {
1673 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1674 msleep(1);
1675
1676 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1677 if (passband)
1678 break;
1679 }
1680
1681 /*
1682 * Set power & frequency of stopband test tone
1683 */
1684 rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1685
1686 for (i = 0; i < 100; i++) {
1687 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1688 msleep(1);
1689
1690 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1691
1692 if ((passband - stopband) <= filter_target) {
1693 rfcsr24++;
1694 overtuned += ((passband - stopband) == filter_target);
1695 } else
1696 break;
1697
1698 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1699 }
1700
1701 rfcsr24 -= !!overtuned;
1702
1703 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1704 return rfcsr24;
1705}
1706
1707static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1708{
1709 u8 rfcsr;
1710 u8 bbp;
1711
1712 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1713 return 0;
1714
1715 /*
1716 * Init RF calibration.
1717 */
1718 rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1719 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1720 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1721 msleep(1);
1722 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1723 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1724
1725 rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1726 rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1727 rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1728 rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1729 rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1730 rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1731 rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1732 rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1733 rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1734 rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1735 rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1736 rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1737 rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1738 rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1739 rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1740 rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1741 rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1742 rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1743 rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1744 rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1745
1746 /*
1747 * Set RX Filter calibration for 20MHz and 40MHz
1748 */
1749 rt2x00dev->calibration[0] =
1750 rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1751 rt2x00dev->calibration[1] =
1752 rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1753
1754 /*
1755 * Set back to initial state
1756 */
1757 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1758
1759 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1760 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1761 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1762
1763 /*
1764 * set BBP back to BW20
1765 */
1766 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1767 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1768 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1769
1770 return 0;
1771}
1772
1773/*
1774 * Device state switch handlers. 235 * Device state switch handlers.
1775 */ 236 */
1776static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev, 237static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
@@ -1778,29 +239,11 @@ static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1778{ 239{
1779 u32 reg; 240 u32 reg;
1780 241
1781 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 242 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1782 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 243 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1783 (state == STATE_RADIO_RX_ON) || 244 (state == STATE_RADIO_RX_ON) ||
1784 (state == STATE_RADIO_RX_ON_LINK)); 245 (state == STATE_RADIO_RX_ON_LINK));
1785 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 246 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1786}
1787
1788static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1789{
1790 unsigned int i;
1791 u32 reg;
1792
1793 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1794 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1795 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1796 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1797 return 0;
1798
1799 msleep(1);
1800 }
1801
1802 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1803 return -EACCES;
1804} 247}
1805 248
1806static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev) 249static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1811,30 +254,28 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1811 /* 254 /*
1812 * Initialize all registers. 255 * Initialize all registers.
1813 */ 256 */
1814 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) || 257 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
1815 rt2800usb_init_registers(rt2x00dev) || 258 rt2800_init_registers(rt2x00dev) ||
1816 rt2800usb_init_bbp(rt2x00dev) || 259 rt2800_init_bbp(rt2x00dev) ||
1817 rt2800usb_init_rfcsr(rt2x00dev))) 260 rt2800_init_rfcsr(rt2x00dev)))
1818 return -EIO; 261 return -EIO;
1819 262
1820 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 263 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1821 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 264 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1822 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 265 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1823 266
1824 udelay(50); 267 udelay(50);
1825 268
1826 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 269 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1827 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 270 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1828 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 271 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1829 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 272 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1830 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 273 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1831 274
1832 275
1833 rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg); 276 rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1834 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0); 277 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1835 /* Don't use bulk in aggregation when working with USB 1.1 */ 278 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN, 0);
1836 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1837 (rt2x00dev->rx->usb_maxpacket == 512));
1838 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128); 279 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1839 /* 280 /*
1840 * Total room for RX frames in kilobytes, PBF might still exceed 281 * Total room for RX frames in kilobytes, PBF might still exceed
@@ -1844,26 +285,26 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1844 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3); 285 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1845 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1); 286 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1846 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1); 287 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1847 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg); 288 rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
1848 289
1849 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 290 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1850 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 291 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1851 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); 292 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1852 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 293 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1853 294
1854 /* 295 /*
1855 * Initialize LED control 296 * Initialize LED control
1856 */ 297 */
1857 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word); 298 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1858 rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff, 299 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1859 word & 0xff, (word >> 8) & 0xff); 300 word & 0xff, (word >> 8) & 0xff);
1860 301
1861 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word); 302 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1862 rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff, 303 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1863 word & 0xff, (word >> 8) & 0xff); 304 word & 0xff, (word >> 8) & 0xff);
1864 305
1865 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word); 306 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1866 rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff, 307 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1867 word & 0xff, (word >> 8) & 0xff); 308 word & 0xff, (word >> 8) & 0xff);
1868 309
1869 return 0; 310 return 0;
@@ -1873,17 +314,17 @@ static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1873{ 314{
1874 u32 reg; 315 u32 reg;
1875 316
1876 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 317 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1877 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 318 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1878 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 319 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1879 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 320 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1880 321
1881 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 322 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1882 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0); 323 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1883 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0); 324 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
1884 325
1885 /* Wait for DMA, ignore error */ 326 /* Wait for DMA, ignore error */
1886 rt2800usb_wait_wpdma_ready(rt2x00dev); 327 rt2800_wait_wpdma_ready(rt2x00dev);
1887 328
1888 rt2x00usb_disable_radio(rt2x00dev); 329 rt2x00usb_disable_radio(rt2x00dev);
1889} 330}
@@ -1892,9 +333,9 @@ static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1892 enum dev_state state) 333 enum dev_state state)
1893{ 334{
1894 if (state == STATE_AWAKE) 335 if (state == STATE_AWAKE)
1895 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); 336 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1896 else 337 else
1897 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2); 338 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1898 339
1899 return 0; 340 return 0;
1900} 341}
@@ -2048,9 +489,9 @@ static void rt2800usb_write_beacon(struct queue_entry *entry)
2048 * Disable beaconing while we are reloading the beacon data, 489 * Disable beaconing while we are reloading the beacon data,
2049 * otherwise we might be sending out invalid data. 490 * otherwise we might be sending out invalid data.
2050 */ 491 */
2051 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 492 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2052 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 493 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2053 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg); 494 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2054 495
2055 /* 496 /*
2056 * Write entire beacon with descriptor to register. 497 * Write entire beacon with descriptor to register.
@@ -2093,12 +534,12 @@ static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2093 return; 534 return;
2094 } 535 }
2095 536
2096 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 537 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2097 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) { 538 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2098 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 539 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2099 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 540 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2100 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 541 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2101 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg); 542 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2102 } 543 }
2103} 544}
2104 545
@@ -2110,30 +551,46 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2110{ 551{
2111 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 552 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2112 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 553 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2113 __le32 *rxd = (__le32 *)entry->skb->data; 554 __le32 *rxi = (__le32 *)entry->skb->data;
2114 __le32 *rxwi; 555 __le32 *rxwi;
2115 u32 rxd0; 556 __le32 *rxd;
557 u32 rxi0;
2116 u32 rxwi0; 558 u32 rxwi0;
2117 u32 rxwi1; 559 u32 rxwi1;
2118 u32 rxwi2; 560 u32 rxwi2;
2119 u32 rxwi3; 561 u32 rxwi3;
562 u32 rxd0;
563 int rx_pkt_len;
564
565 /*
566 * RX frame format is :
567 * | RXINFO | RXWI | header | L2 pad | payload | pad | RXD | USB pad |
568 * |<------------ rx_pkt_len -------------->|
569 */
570 rt2x00_desc_read(rxi, 0, &rxi0);
571 rx_pkt_len = rt2x00_get_field32(rxi0, RXINFO_W0_USB_DMA_RX_PKT_LEN);
572
573 rxwi = (__le32 *)(entry->skb->data + RXINFO_DESC_SIZE);
574
575 /*
576 * FIXME : we need to check for rx_pkt_len validity
577 */
578 rxd = (__le32 *)(entry->skb->data + RXINFO_DESC_SIZE + rx_pkt_len);
2120 579
2121 /* 580 /*
2122 * Copy descriptor to the skbdesc->desc buffer, making it safe from 581 * Copy descriptor to the skbdesc->desc buffer, making it safe from
2123 * moving of frame data in rt2x00usb. 582 * moving of frame data in rt2x00usb.
2124 */ 583 */
2125 memcpy(skbdesc->desc, rxd, skbdesc->desc_len); 584 memcpy(skbdesc->desc, rxi, skbdesc->desc_len);
2126 rxd = (__le32 *)skbdesc->desc;
2127 rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2128 585
2129 /* 586 /*
2130 * It is now safe to read the descriptor on all architectures. 587 * It is now safe to read the descriptor on all architectures.
2131 */ 588 */
2132 rt2x00_desc_read(rxd, 0, &rxd0);
2133 rt2x00_desc_read(rxwi, 0, &rxwi0); 589 rt2x00_desc_read(rxwi, 0, &rxwi0);
2134 rt2x00_desc_read(rxwi, 1, &rxwi1); 590 rt2x00_desc_read(rxwi, 1, &rxwi1);
2135 rt2x00_desc_read(rxwi, 2, &rxwi2); 591 rt2x00_desc_read(rxwi, 2, &rxwi2);
2136 rt2x00_desc_read(rxwi, 3, &rxwi3); 592 rt2x00_desc_read(rxwi, 3, &rxwi3);
593 rt2x00_desc_read(rxd, 0, &rxd0);
2137 594
2138 if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR)) 595 if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2139 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 596 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
@@ -2162,10 +619,8 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2162 if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS)) 619 if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2163 rxdesc->dev_flags |= RXDONE_MY_BSS; 620 rxdesc->dev_flags |= RXDONE_MY_BSS;
2164 621
2165 if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) { 622 if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD))
2166 rxdesc->dev_flags |= RXDONE_L2PAD; 623 rxdesc->dev_flags |= RXDONE_L2PAD;
2167 skbdesc->flags |= SKBDESC_L2_PADDED;
2168 }
2169 624
2170 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI)) 625 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2171 rxdesc->flags |= RX_FLAG_SHORT_GI; 626 rxdesc->flags |= RX_FLAG_SHORT_GI;
@@ -2200,7 +655,6 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2200 * Remove RXWI descriptor from start of buffer. 655 * Remove RXWI descriptor from start of buffer.
2201 */ 656 */
2202 skb_pull(entry->skb, skbdesc->desc_len); 657 skb_pull(entry->skb, skbdesc->desc_len);
2203 skb_trim(entry->skb, rxdesc->size);
2204} 658}
2205 659
2206/* 660/*
@@ -2208,402 +662,33 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2208 */ 662 */
2209static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) 663static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2210{ 664{
2211 u16 word; 665 if (rt2800_efuse_detect(rt2x00dev))
2212 u8 *mac; 666 rt2800_read_eeprom_efuse(rt2x00dev);
2213 u8 default_lna_gain; 667 else
2214 668 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom,
2215 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE); 669 EEPROM_SIZE);
2216
2217 /*
2218 * Start validation of the data that has been read.
2219 */
2220 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2221 if (!is_valid_ether_addr(mac)) {
2222 random_ether_addr(mac);
2223 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2224 }
2225
2226 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2227 if (word == 0xffff) {
2228 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2229 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2230 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2231 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2232 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2233 } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2234 /*
2235 * There is a max of 2 RX streams for RT2870 series
2236 */
2237 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2238 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2239 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2240 }
2241
2242 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2243 if (word == 0xffff) {
2244 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2245 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2246 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2247 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2248 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2249 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2250 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2251 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2252 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2253 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2254 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2255 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2256 }
2257
2258 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2259 if ((word & 0x00ff) == 0x00ff) {
2260 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2261 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2262 LED_MODE_TXRX_ACTIVITY);
2263 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2264 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2265 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2266 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2267 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2268 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2269 }
2270
2271 /*
2272 * During the LNA validation we are going to use
2273 * lna0 as correct value. Note that EEPROM_LNA
2274 * is never validated.
2275 */
2276 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2277 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2278
2279 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2280 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2281 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2282 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2283 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2284 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2285
2286 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2287 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2288 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2289 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2290 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2291 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2292 default_lna_gain);
2293 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2294
2295 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2296 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2297 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2298 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2299 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2300 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2301
2302 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2303 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2304 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2305 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2306 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2307 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2308 default_lna_gain);
2309 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2310 670
2311 return 0; 671 return rt2800_validate_eeprom(rt2x00dev);
2312} 672}
2313 673
2314static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev) 674static const struct rt2800_ops rt2800usb_rt2800_ops = {
2315{ 675 .register_read = rt2x00usb_register_read,
2316 u32 reg; 676 .register_read_lock = rt2x00usb_register_read_lock,
2317 u16 value; 677 .register_write = rt2x00usb_register_write,
2318 u16 eeprom; 678 .register_write_lock = rt2x00usb_register_write_lock,
2319
2320 /*
2321 * Read EEPROM word for configuration.
2322 */
2323 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2324
2325 /*
2326 * Identify RF chipset.
2327 */
2328 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2329 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2330 rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2331
2332 /*
2333 * The check for rt2860 is not a typo, some rt2870 hardware
2334 * identifies itself as rt2860 in the CSR register.
2335 */
2336 if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2337 !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2338 !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2339 !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2340 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2341 return -ENODEV;
2342 }
2343
2344 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2345 !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2346 !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2347 !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2348 !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2349 !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2350 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2351 return -ENODEV;
2352 }
2353
2354 /*
2355 * Identify default antenna configuration.
2356 */
2357 rt2x00dev->default_ant.tx =
2358 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2359 rt2x00dev->default_ant.rx =
2360 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2361
2362 /*
2363 * Read frequency offset and RF programming sequence.
2364 */
2365 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2366 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2367
2368 /*
2369 * Read external LNA informations.
2370 */
2371 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2372
2373 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2374 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2375 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2376 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2377
2378 /*
2379 * Detect if this device has an hardware controlled radio.
2380 */
2381 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2382 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2383
2384 /*
2385 * Store led settings, for correct led behaviour.
2386 */
2387#ifdef CONFIG_RT2X00_LIB_LEDS
2388 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2389 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2390 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2391 679
2392 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, 680 .register_multiread = rt2x00usb_register_multiread,
2393 &rt2x00dev->led_mcu_reg); 681 .register_multiwrite = rt2x00usb_register_multiwrite,
2394#endif /* CONFIG_RT2X00_LIB_LEDS */
2395 682
2396 return 0; 683 .regbusy_read = rt2x00usb_regbusy_read,
2397}
2398
2399/*
2400 * RF value list for rt2870
2401 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2402 */
2403static const struct rf_channel rf_vals[] = {
2404 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2405 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2406 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2407 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2408 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2409 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2410 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2411 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2412 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2413 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2414 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2415 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2416 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2417 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2418
2419 /* 802.11 UNI / HyperLan 2 */
2420 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2421 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2422 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2423 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2424 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2425 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2426 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2427 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2428 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2429 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2430 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2431 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2432
2433 /* 802.11 HyperLan 2 */
2434 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2435 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2436 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2437 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2438 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2439 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2440 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2441 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2442 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2443 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2444 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2445 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2446 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2447 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2448 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2449 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2450
2451 /* 802.11 UNII */
2452 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2453 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2454 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2455 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2456 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2457 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2458 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2459 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2460 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2461 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2462 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2463
2464 /* 802.11 Japan */
2465 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2466 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2467 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2468 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2469 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2470 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2471 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2472}; 684};
2473 685
2474/*
2475 * RF value list for rt3070
2476 * Supports: 2.4 GHz
2477 */
2478static const struct rf_channel rf_vals_3070[] = {
2479 {1, 241, 2, 2 },
2480 {2, 241, 2, 7 },
2481 {3, 242, 2, 2 },
2482 {4, 242, 2, 7 },
2483 {5, 243, 2, 2 },
2484 {6, 243, 2, 7 },
2485 {7, 244, 2, 2 },
2486 {8, 244, 2, 7 },
2487 {9, 245, 2, 2 },
2488 {10, 245, 2, 7 },
2489 {11, 246, 2, 2 },
2490 {12, 246, 2, 7 },
2491 {13, 247, 2, 2 },
2492 {14, 248, 2, 4 },
2493};
2494
2495static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2496{
2497 struct hw_mode_spec *spec = &rt2x00dev->spec;
2498 struct channel_info *info;
2499 char *tx_power1;
2500 char *tx_power2;
2501 unsigned int i;
2502 u16 eeprom;
2503
2504 /*
2505 * Initialize all hw fields.
2506 */
2507 rt2x00dev->hw->flags =
2508 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2509 IEEE80211_HW_SIGNAL_DBM |
2510 IEEE80211_HW_SUPPORTS_PS |
2511 IEEE80211_HW_PS_NULLFUNC_STACK;
2512 rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2513
2514 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2515 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2516 rt2x00_eeprom_addr(rt2x00dev,
2517 EEPROM_MAC_ADDR_0));
2518
2519 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2520
2521 /*
2522 * Initialize HT information.
2523 */
2524 spec->ht.ht_supported = true;
2525 spec->ht.cap =
2526 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2527 IEEE80211_HT_CAP_GRN_FLD |
2528 IEEE80211_HT_CAP_SGI_20 |
2529 IEEE80211_HT_CAP_SGI_40 |
2530 IEEE80211_HT_CAP_TX_STBC |
2531 IEEE80211_HT_CAP_RX_STBC |
2532 IEEE80211_HT_CAP_PSMP_SUPPORT;
2533 spec->ht.ampdu_factor = 3;
2534 spec->ht.ampdu_density = 4;
2535 spec->ht.mcs.tx_params =
2536 IEEE80211_HT_MCS_TX_DEFINED |
2537 IEEE80211_HT_MCS_TX_RX_DIFF |
2538 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2539 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2540
2541 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2542 case 3:
2543 spec->ht.mcs.rx_mask[2] = 0xff;
2544 case 2:
2545 spec->ht.mcs.rx_mask[1] = 0xff;
2546 case 1:
2547 spec->ht.mcs.rx_mask[0] = 0xff;
2548 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2549 break;
2550 }
2551
2552 /*
2553 * Initialize hw_mode information.
2554 */
2555 spec->supported_bands = SUPPORT_BAND_2GHZ;
2556 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2557
2558 if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2559 rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2560 spec->num_channels = 14;
2561 spec->channels = rf_vals;
2562 } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2563 rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2564 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2565 spec->num_channels = ARRAY_SIZE(rf_vals);
2566 spec->channels = rf_vals;
2567 } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2568 rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2569 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2570 spec->channels = rf_vals_3070;
2571 }
2572
2573 /*
2574 * Create channel information array
2575 */
2576 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2577 if (!info)
2578 return -ENOMEM;
2579
2580 spec->channels_info = info;
2581
2582 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2583 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2584
2585 for (i = 0; i < 14; i++) {
2586 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2587 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2588 }
2589
2590 if (spec->num_channels > 14) {
2591 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2592 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2593
2594 for (i = 14; i < spec->num_channels; i++) {
2595 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2596 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2597 }
2598 }
2599
2600 return 0;
2601}
2602
2603static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev) 686static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2604{ 687{
2605 int retval; 688 int retval;
2606 689
690 rt2x00dev->priv = (void *)&rt2800usb_rt2800_ops;
691
2607 /* 692 /*
2608 * Allocate eeprom data. 693 * Allocate eeprom data.
2609 */ 694 */
@@ -2611,14 +696,14 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2611 if (retval) 696 if (retval)
2612 return retval; 697 return retval;
2613 698
2614 retval = rt2800usb_init_eeprom(rt2x00dev); 699 retval = rt2800_init_eeprom(rt2x00dev);
2615 if (retval) 700 if (retval)
2616 return retval; 701 return retval;
2617 702
2618 /* 703 /*
2619 * Initialize hw specifications. 704 * Initialize hw specifications.
2620 */ 705 */
2621 retval = rt2800usb_probe_hw_mode(rt2x00dev); 706 retval = rt2800_probe_hw_mode(rt2x00dev);
2622 if (retval) 707 if (retval)
2623 return retval; 708 return retval;
2624 709
@@ -2645,162 +730,6 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2645 return 0; 730 return 0;
2646} 731}
2647 732
2648/*
2649 * IEEE80211 stack callback functions.
2650 */
2651static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2652 u32 *iv32, u16 *iv16)
2653{
2654 struct rt2x00_dev *rt2x00dev = hw->priv;
2655 struct mac_iveiv_entry iveiv_entry;
2656 u32 offset;
2657
2658 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2659 rt2x00usb_register_multiread(rt2x00dev, offset,
2660 &iveiv_entry, sizeof(iveiv_entry));
2661
2662 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2663 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2664}
2665
2666static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2667{
2668 struct rt2x00_dev *rt2x00dev = hw->priv;
2669 u32 reg;
2670 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2671
2672 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2673 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2674 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2675
2676 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2677 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2678 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2679
2680 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2681 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2682 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2683
2684 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2685 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2686 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2687
2688 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2689 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2690 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2691
2692 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2693 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2694 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2695
2696 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2697 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2698 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2699
2700 return 0;
2701}
2702
2703static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2704 const struct ieee80211_tx_queue_params *params)
2705{
2706 struct rt2x00_dev *rt2x00dev = hw->priv;
2707 struct data_queue *queue;
2708 struct rt2x00_field32 field;
2709 int retval;
2710 u32 reg;
2711 u32 offset;
2712
2713 /*
2714 * First pass the configuration through rt2x00lib, that will
2715 * update the queue settings and validate the input. After that
2716 * we are free to update the registers based on the value
2717 * in the queue parameter.
2718 */
2719 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2720 if (retval)
2721 return retval;
2722
2723 /*
2724 * We only need to perform additional register initialization
2725 * for WMM queues/
2726 */
2727 if (queue_idx >= 4)
2728 return 0;
2729
2730 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2731
2732 /* Update WMM TXOP register */
2733 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2734 field.bit_offset = (queue_idx & 1) * 16;
2735 field.bit_mask = 0xffff << field.bit_offset;
2736
2737 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2738 rt2x00_set_field32(&reg, field, queue->txop);
2739 rt2x00usb_register_write(rt2x00dev, offset, reg);
2740
2741 /* Update WMM registers */
2742 field.bit_offset = queue_idx * 4;
2743 field.bit_mask = 0xf << field.bit_offset;
2744
2745 rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2746 rt2x00_set_field32(&reg, field, queue->aifs);
2747 rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2748
2749 rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2750 rt2x00_set_field32(&reg, field, queue->cw_min);
2751 rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2752
2753 rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2754 rt2x00_set_field32(&reg, field, queue->cw_max);
2755 rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2756
2757 /* Update EDCA registers */
2758 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2759
2760 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2761 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2762 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2763 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2764 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2765 rt2x00usb_register_write(rt2x00dev, offset, reg);
2766
2767 return 0;
2768}
2769
2770static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2771{
2772 struct rt2x00_dev *rt2x00dev = hw->priv;
2773 u64 tsf;
2774 u32 reg;
2775
2776 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2777 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2778 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2779 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2780
2781 return tsf;
2782}
2783
2784static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2785 .tx = rt2x00mac_tx,
2786 .start = rt2x00mac_start,
2787 .stop = rt2x00mac_stop,
2788 .add_interface = rt2x00mac_add_interface,
2789 .remove_interface = rt2x00mac_remove_interface,
2790 .config = rt2x00mac_config,
2791 .configure_filter = rt2x00mac_configure_filter,
2792 .set_tim = rt2x00mac_set_tim,
2793 .set_key = rt2x00mac_set_key,
2794 .get_stats = rt2x00mac_get_stats,
2795 .get_tkip_seq = rt2800usb_get_tkip_seq,
2796 .set_rts_threshold = rt2800usb_set_rts_threshold,
2797 .bss_info_changed = rt2x00mac_bss_info_changed,
2798 .conf_tx = rt2800usb_conf_tx,
2799 .get_tx_stats = rt2x00mac_get_tx_stats,
2800 .get_tsf = rt2800usb_get_tsf,
2801 .rfkill_poll = rt2x00mac_rfkill_poll,
2802};
2803
2804static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = { 733static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2805 .probe_hw = rt2800usb_probe_hw, 734 .probe_hw = rt2800usb_probe_hw,
2806 .get_firmware_name = rt2800usb_get_firmware_name, 735 .get_firmware_name = rt2800usb_get_firmware_name,
@@ -2810,10 +739,10 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2810 .uninitialize = rt2x00usb_uninitialize, 739 .uninitialize = rt2x00usb_uninitialize,
2811 .clear_entry = rt2x00usb_clear_entry, 740 .clear_entry = rt2x00usb_clear_entry,
2812 .set_device_state = rt2800usb_set_device_state, 741 .set_device_state = rt2800usb_set_device_state,
2813 .rfkill_poll = rt2800usb_rfkill_poll, 742 .rfkill_poll = rt2800_rfkill_poll,
2814 .link_stats = rt2800usb_link_stats, 743 .link_stats = rt2800_link_stats,
2815 .reset_tuner = rt2800usb_reset_tuner, 744 .reset_tuner = rt2800_reset_tuner,
2816 .link_tuner = rt2800usb_link_tuner, 745 .link_tuner = rt2800_link_tuner,
2817 .write_tx_desc = rt2800usb_write_tx_desc, 746 .write_tx_desc = rt2800usb_write_tx_desc,
2818 .write_tx_data = rt2x00usb_write_tx_data, 747 .write_tx_data = rt2x00usb_write_tx_data,
2819 .write_beacon = rt2800usb_write_beacon, 748 .write_beacon = rt2800usb_write_beacon,
@@ -2821,19 +750,19 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2821 .kick_tx_queue = rt2800usb_kick_tx_queue, 750 .kick_tx_queue = rt2800usb_kick_tx_queue,
2822 .kill_tx_queue = rt2x00usb_kill_tx_queue, 751 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2823 .fill_rxdone = rt2800usb_fill_rxdone, 752 .fill_rxdone = rt2800usb_fill_rxdone,
2824 .config_shared_key = rt2800usb_config_shared_key, 753 .config_shared_key = rt2800_config_shared_key,
2825 .config_pairwise_key = rt2800usb_config_pairwise_key, 754 .config_pairwise_key = rt2800_config_pairwise_key,
2826 .config_filter = rt2800usb_config_filter, 755 .config_filter = rt2800_config_filter,
2827 .config_intf = rt2800usb_config_intf, 756 .config_intf = rt2800_config_intf,
2828 .config_erp = rt2800usb_config_erp, 757 .config_erp = rt2800_config_erp,
2829 .config_ant = rt2800usb_config_ant, 758 .config_ant = rt2800_config_ant,
2830 .config = rt2800usb_config, 759 .config = rt2800_config,
2831}; 760};
2832 761
2833static const struct data_queue_desc rt2800usb_queue_rx = { 762static const struct data_queue_desc rt2800usb_queue_rx = {
2834 .entry_num = RX_ENTRIES, 763 .entry_num = RX_ENTRIES,
2835 .data_size = AGGREGATION_SIZE, 764 .data_size = AGGREGATION_SIZE,
2836 .desc_size = RXD_DESC_SIZE + RXWI_DESC_SIZE, 765 .desc_size = RXINFO_DESC_SIZE + RXWI_DESC_SIZE,
2837 .priv_size = sizeof(struct queue_entry_priv_usb), 766 .priv_size = sizeof(struct queue_entry_priv_usb),
2838}; 767};
2839 768
@@ -2852,19 +781,20 @@ static const struct data_queue_desc rt2800usb_queue_bcn = {
2852}; 781};
2853 782
2854static const struct rt2x00_ops rt2800usb_ops = { 783static const struct rt2x00_ops rt2800usb_ops = {
2855 .name = KBUILD_MODNAME, 784 .name = KBUILD_MODNAME,
2856 .max_sta_intf = 1, 785 .max_sta_intf = 1,
2857 .max_ap_intf = 8, 786 .max_ap_intf = 8,
2858 .eeprom_size = EEPROM_SIZE, 787 .eeprom_size = EEPROM_SIZE,
2859 .rf_size = RF_SIZE, 788 .rf_size = RF_SIZE,
2860 .tx_queues = NUM_TX_QUEUES, 789 .tx_queues = NUM_TX_QUEUES,
2861 .rx = &rt2800usb_queue_rx, 790 .extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2862 .tx = &rt2800usb_queue_tx, 791 .rx = &rt2800usb_queue_rx,
2863 .bcn = &rt2800usb_queue_bcn, 792 .tx = &rt2800usb_queue_tx,
2864 .lib = &rt2800usb_rt2x00_ops, 793 .bcn = &rt2800usb_queue_bcn,
2865 .hw = &rt2800usb_mac80211_ops, 794 .lib = &rt2800usb_rt2x00_ops,
795 .hw = &rt2800_mac80211_ops,
2866#ifdef CONFIG_RT2X00_LIB_DEBUGFS 796#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2867 .debugfs = &rt2800usb_rt2x00debug, 797 .debugfs = &rt2800_rt2x00debug,
2868#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 798#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2869}; 799};
2870 800
@@ -2875,43 +805,27 @@ static struct usb_device_id rt2800usb_device_table[] = {
2875 /* Abocom */ 805 /* Abocom */
2876 { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) }, 806 { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2877 { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) }, 807 { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2878 { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2879 { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2880 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2881 { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) }, 808 { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2882 /* AirTies */
2883 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2884 /* Amigo */
2885 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2886 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2887 /* Amit */ 809 /* Amit */
2888 { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) }, 810 { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
811 /* Askey */
812 { USB_DEVICE(0x1690, 0x0740), USB_DEVICE_DATA(&rt2800usb_ops) },
2889 /* ASUS */ 813 /* ASUS */
2890 { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) }, 814 { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2891 { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) }, 815 { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2892 { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) }, 816 { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2893 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2894 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2895 /* AzureWave */ 817 /* AzureWave */
2896 { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) }, 818 { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2897 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2898 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2899 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2900 /* Belkin */ 819 /* Belkin */
2901 { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) }, 820 { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2902 { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) }, 821 { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2903 { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) }, 822 { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2904 { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2905 /* Buffalo */ 823 /* Buffalo */
2906 { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) }, 824 { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2907 { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2908 /* Conceptronic */ 825 /* Conceptronic */
2909 { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) }, 826 { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2910 { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) }, 827 { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2911 { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2912 { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) }, 828 { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2913 { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2914 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2915 { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) }, 829 { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2916 { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) }, 830 { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2917 { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) }, 831 { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -2920,83 +834,38 @@ static struct usb_device_id rt2800usb_device_table[] = {
2920 { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) }, 834 { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2921 { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) }, 835 { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2922 { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) }, 836 { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2923 { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2924 { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2925 /* D-Link */ 837 /* D-Link */
2926 { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) }, 838 { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2927 { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2928 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2929 { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2930 { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2931 { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2932 { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) }, 839 { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2933 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2934 /* Edimax */ 840 /* Edimax */
2935 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2936 { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) }, 841 { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2937 { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) }, 842 { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2938 /* Encore */
2939 { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2940 /* EnGenius */ 843 /* EnGenius */
2941 { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) }, 844 { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2942 { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) }, 845 { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2943 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2944 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2945 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2946 { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2947 /* Gemtek */
2948 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2949 /* Gigabyte */ 846 /* Gigabyte */
2950 { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) }, 847 { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2951 { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2952 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2953 /* Hawking */ 848 /* Hawking */
2954 { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) }, 849 { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2955 { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) }, 850 { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2956 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2957 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2958 /* I-O DATA */
2959 { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
2960 /* LevelOne */
2961 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2962 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2963 /* Linksys */ 851 /* Linksys */
2964 { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) }, 852 { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2965 { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) }, 853 { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2966 { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2967 /* Logitec */ 854 /* Logitec */
2968 { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) }, 855 { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2969 { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) }, 856 { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2970 { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) }, 857 { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2971 /* Motorola */ 858 /* Motorola */
2972 { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) }, 859 { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2973 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) }, 860 /* MSI */
2974 /* Ovislink */ 861 { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2975 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2976 /* Pegatron */
2977 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2978 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2979 { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
2980 /* Philips */ 862 /* Philips */
2981 { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) }, 863 { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2982 /* Planex */ 864 /* Planex */
2983 { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) }, 865 { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2984 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2985 { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2986 /* Qcom */
2987 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2988 /* Quanta */
2989 { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2990 /* Ralink */ 866 /* Ralink */
2991 { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
2992 { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2993 { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2994 { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) }, 867 { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2995 { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) }, 868 { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2996 { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2997 { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2998 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2999 { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
3000 /* Samsung */ 869 /* Samsung */
3001 { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) }, 870 { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3002 /* Siemens */ 871 /* Siemens */
@@ -3007,29 +876,18 @@ static struct usb_device_id rt2800usb_device_table[] = {
3007 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) }, 876 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3008 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) }, 877 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3009 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) }, 878 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3010 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3011 { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3012 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3013 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3014 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) }, 879 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3015 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3016 { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
3017 /* SMC */ 880 /* SMC */
3018 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) }, 881 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3019 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3020 { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) }, 882 { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3021 { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) }, 883 { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3022 { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) }, 884 { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3023 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3024 { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) }, 885 { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3025 { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) }, 886 { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3026 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3027 /* Sparklan */ 887 /* Sparklan */
3028 { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) }, 888 { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3029 /* Sweex */ 889 /* Sweex */
3030 { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
3031 { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) }, 890 { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
3032 { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3033 /* U-Media*/ 891 /* U-Media*/
3034 { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) }, 892 { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3035 /* ZCOM */ 893 /* ZCOM */
@@ -3038,11 +896,195 @@ static struct usb_device_id rt2800usb_device_table[] = {
3038 /* Zinwell */ 896 /* Zinwell */
3039 { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) }, 897 { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3040 { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) }, 898 { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
899 /* Zyxel */
900 { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
901#ifdef CONFIG_RT2800USB_RT30XX
902 /* Abocom */
903 { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
904 { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
905 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
906 /* AirTies */
907 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
908 /* AzureWave */
909 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
910 /* Conceptronic */
911 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
912 /* Corega */
913 { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
914 /* D-Link */
915 { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
916 { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
917 { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
918 { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
919 /* Edimax */
920 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
921 /* Encore */
922 { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
923 /* EnGenius */
924 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
925 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
926 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
927 /* Gigabyte */
928 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
929 /* I-O DATA */
930 { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
931 /* MSI */
932 { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
933 /* Pegatron */
934 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
935 { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
936 /* Planex */
937 { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
938 /* Quanta */
939 { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
940 /* Ralink */
941 { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
942 { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
943 { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
944 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
945 /* Sitecom */
946 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
947 { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
948 /* SMC */
949 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
950 /* Zinwell */
3041 { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) }, 951 { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
3042 { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) }, 952 { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
953#endif
954#ifdef CONFIG_RT2800USB_RT35XX
955 /* Askey */
956 { USB_DEVICE(0x1690, 0x0744), USB_DEVICE_DATA(&rt2800usb_ops) },
957 /* Cisco */
958 { USB_DEVICE(0x167b, 0x4001), USB_DEVICE_DATA(&rt2800usb_ops) },
959 /* EnGenius */
960 { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
961 /* I-O DATA */
962 { USB_DEVICE(0x04bb, 0x0944), USB_DEVICE_DATA(&rt2800usb_ops) },
963 /* Ralink */
964 { USB_DEVICE(0x148f, 0x3370), USB_DEVICE_DATA(&rt2800usb_ops) },
965 { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
966 { USB_DEVICE(0x148f, 0x8070), USB_DEVICE_DATA(&rt2800usb_ops) },
967 /* Sitecom */
968 { USB_DEVICE(0x0df6, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) },
969 /* Zinwell */
970 { USB_DEVICE(0x5a57, 0x0284), USB_DEVICE_DATA(&rt2800usb_ops) },
971#endif
972#ifdef CONFIG_RT2800USB_UNKNOWN
973 /*
974 * Unclear what kind of devices these are (they aren't supported by the
975 * vendor driver).
976 */
977 /* Allwin */
978 { USB_DEVICE(0x8516, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
979 { USB_DEVICE(0x8516, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
980 { USB_DEVICE(0x8516, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
981 { USB_DEVICE(0x8516, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
982 { USB_DEVICE(0x8516, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
983 { USB_DEVICE(0x8516, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
984 { USB_DEVICE(0x8516, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
985 /* Amigo */
986 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
987 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
988 /* Askey */
989 { USB_DEVICE(0x0930, 0x0a07), USB_DEVICE_DATA(&rt2800usb_ops) },
990 /* ASUS */
991 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
992 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
993 { USB_DEVICE(0x0b05, 0x1784), USB_DEVICE_DATA(&rt2800usb_ops) },
994 { USB_DEVICE(0x0b05, 0x1790), USB_DEVICE_DATA(&rt2800usb_ops) },
995 { USB_DEVICE(0x1761, 0x0b05), USB_DEVICE_DATA(&rt2800usb_ops) },
996 /* AzureWave */
997 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
998 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
999 { USB_DEVICE(0x13d3, 0x3305), USB_DEVICE_DATA(&rt2800usb_ops) },
1000 /* Belkin */
1001 { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
1002 /* Buffalo */
1003 { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
1004 { USB_DEVICE(0x0411, 0x0148), USB_DEVICE_DATA(&rt2800usb_ops) },
1005 { USB_DEVICE(0x0411, 0x0150), USB_DEVICE_DATA(&rt2800usb_ops) },
1006 { USB_DEVICE(0x0411, 0x015d), USB_DEVICE_DATA(&rt2800usb_ops) },
1007 /* Conceptronic */
1008 { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
1009 { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
1010 /* Corega */
1011 { USB_DEVICE(0x07aa, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) },
1012 { USB_DEVICE(0x07aa, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
1013 { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
1014 /* D-Link */
1015 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
1016 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
1017 { USB_DEVICE(0x07d1, 0x3c15), USB_DEVICE_DATA(&rt2800usb_ops) },
1018 { USB_DEVICE(0x07d1, 0x3c16), USB_DEVICE_DATA(&rt2800usb_ops) },
1019 /* Encore */
1020 { USB_DEVICE(0x203d, 0x14a1), USB_DEVICE_DATA(&rt2800usb_ops) },
1021 { USB_DEVICE(0x203d, 0x14a9), USB_DEVICE_DATA(&rt2800usb_ops) },
1022 /* EnGenius */
1023 { USB_DEVICE(0x1740, 0x9707), USB_DEVICE_DATA(&rt2800usb_ops) },
1024 { USB_DEVICE(0x1740, 0x9708), USB_DEVICE_DATA(&rt2800usb_ops) },
1025 { USB_DEVICE(0x1740, 0x9709), USB_DEVICE_DATA(&rt2800usb_ops) },
1026 /* Gemtek */
1027 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
1028 /* Gigabyte */
1029 { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
1030 /* Hawking */
1031 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
1032 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
1033 /* I-O DATA */
1034 { USB_DEVICE(0x04bb, 0x0947), USB_DEVICE_DATA(&rt2800usb_ops) },
1035 { USB_DEVICE(0x04bb, 0x0948), USB_DEVICE_DATA(&rt2800usb_ops) },
1036 /* LevelOne */
1037 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
1038 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
1039 /* Linksys */
1040 { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
1041 { USB_DEVICE(0x1737, 0x0078), USB_DEVICE_DATA(&rt2800usb_ops) },
1042 { USB_DEVICE(0x1737, 0x0079), USB_DEVICE_DATA(&rt2800usb_ops) },
1043 /* Motorola */
1044 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
1045 /* MSI */
1046 { USB_DEVICE(0x0db0, 0x3821), USB_DEVICE_DATA(&rt2800usb_ops) },
1047 { USB_DEVICE(0x0db0, 0x3822), USB_DEVICE_DATA(&rt2800usb_ops) },
1048 { USB_DEVICE(0x0db0, 0x3870), USB_DEVICE_DATA(&rt2800usb_ops) },
1049 { USB_DEVICE(0x0db0, 0x3871), USB_DEVICE_DATA(&rt2800usb_ops) },
1050 { USB_DEVICE(0x0db0, 0x821a), USB_DEVICE_DATA(&rt2800usb_ops) },
1051 { USB_DEVICE(0x0db0, 0x822a), USB_DEVICE_DATA(&rt2800usb_ops) },
1052 { USB_DEVICE(0x0db0, 0x870a), USB_DEVICE_DATA(&rt2800usb_ops) },
1053 { USB_DEVICE(0x0db0, 0x871a), USB_DEVICE_DATA(&rt2800usb_ops) },
1054 { USB_DEVICE(0x0db0, 0x899a), USB_DEVICE_DATA(&rt2800usb_ops) },
1055 /* Ovislink */
1056 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
1057 /* Para */
1058 { USB_DEVICE(0x20b8, 0x8888), USB_DEVICE_DATA(&rt2800usb_ops) },
1059 /* Pegatron */
1060 { USB_DEVICE(0x05a6, 0x0101), USB_DEVICE_DATA(&rt2800usb_ops) },
1061 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
1062 { USB_DEVICE(0x1d4d, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
1063 /* Planex */
1064 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
1065 /* Qcom */
1066 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
1067 /* Sitecom */
1068 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
1069 { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
1070 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
1071 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
1072 { USB_DEVICE(0x0df6, 0x0047), USB_DEVICE_DATA(&rt2800usb_ops) },
1073 { USB_DEVICE(0x0df6, 0x0048), USB_DEVICE_DATA(&rt2800usb_ops) },
1074 { USB_DEVICE(0x0df6, 0x004a), USB_DEVICE_DATA(&rt2800usb_ops) },
1075 { USB_DEVICE(0x0df6, 0x004d), USB_DEVICE_DATA(&rt2800usb_ops) },
1076 /* SMC */
1077 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
1078 { USB_DEVICE(0x083a, 0xa701), USB_DEVICE_DATA(&rt2800usb_ops) },
1079 { USB_DEVICE(0x083a, 0xa702), USB_DEVICE_DATA(&rt2800usb_ops) },
1080 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
1081 { USB_DEVICE(0x083a, 0xd522), USB_DEVICE_DATA(&rt2800usb_ops) },
1082 /* Sweex */
1083 { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
1084 { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3043 /* Zyxel */ 1085 /* Zyxel */
3044 { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3045 { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) }, 1086 { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
1087#endif
3046 { 0, } 1088 { 0, }
3047}; 1089};
3048 1090
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
index 4d9991c9a51c..d1d8ae94b4d4 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.h
+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
@@ -1,5 +1,9 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
6 Copyright (C) 2009 Axel Kollhofer <rain_maker@root-forum.org>
3 <http://rt2x00.serialmonkey.com> 7 <http://rt2x00.serialmonkey.com>
4 8
5 This program is free software; you can redistribute it and/or modify 9 This program is free software; you can redistribute it and/or modify
@@ -28,288 +32,10 @@
28#define RT2800USB_H 32#define RT2800USB_H
29 33
30/* 34/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 * RF3021 2.4G 1T2R
40 * RF3022 2.4G 2T2R
41 * RF3052 2.4G 2T2R
42 */
43#define RF2820 0x0001
44#define RF2850 0x0002
45#define RF2720 0x0003
46#define RF2750 0x0004
47#define RF3020 0x0005
48#define RF2020 0x0006
49#define RF3021 0x0007
50#define RF3022 0x0008
51#define RF3052 0x0009
52
53/*
54 * RT2870 version
55 */
56#define RT2860C_VERSION 0x28600100
57#define RT2860D_VERSION 0x28600101
58#define RT2880E_VERSION 0x28720200
59#define RT2883_VERSION 0x28830300
60#define RT3070_VERSION 0x30700200
61
62/*
63 * Signal information.
64 * Defaul offset is required for RSSI <-> dBm conversion.
65 */
66#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
67
68/*
69 * Register layout information.
70 */
71#define CSR_REG_BASE 0x1000
72#define CSR_REG_SIZE 0x0800
73#define EEPROM_BASE 0x0000
74#define EEPROM_SIZE 0x0110
75#define BBP_BASE 0x0000
76#define BBP_SIZE 0x0080
77#define RF_BASE 0x0004
78#define RF_SIZE 0x0010
79
80/*
81 * Number of TX queues.
82 */
83#define NUM_TX_QUEUES 4
84
85/*
86 * USB registers. 35 * USB registers.
87 */ 36 */
88 37
89/* 38/*
90 * HOST-MCU shared memory
91 */
92#define HOST_CMD_CSR 0x0404
93#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
94
95/*
96 * INT_SOURCE_CSR: Interrupt source register.
97 * Write one to clear corresponding bit.
98 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
99 */
100#define INT_SOURCE_CSR 0x0200
101#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
102#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
103#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
104#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
105#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
106#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
107#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
108#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
109#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
110#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
111#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
112#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
113#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
114#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
115#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
116#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
117#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
118#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
119
120/*
121 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
122 */
123#define INT_MASK_CSR 0x0204
124#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
125#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
126#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
127#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
128#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
129#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
130#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
131#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
132#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
133#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
134#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
135#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
136#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
137#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
138#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
139#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
140#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
141#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
142
143/*
144 * WPDMA_GLO_CFG
145 */
146#define WPDMA_GLO_CFG 0x0208
147#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
148#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
149#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
150#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
151#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
152#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
153#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
154#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
155#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
156
157/*
158 * WPDMA_RST_IDX
159 */
160#define WPDMA_RST_IDX 0x020c
161#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
162#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
163#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
164#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
165#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
166#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
167#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
168
169/*
170 * DELAY_INT_CFG
171 */
172#define DELAY_INT_CFG 0x0210
173#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
174#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
175#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
176#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
177#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
178#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
179
180/*
181 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
182 * AIFSN0: AC_BE
183 * AIFSN1: AC_BK
184 * AIFSN1: AC_VI
185 * AIFSN1: AC_VO
186 */
187#define WMM_AIFSN_CFG 0x0214
188#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
189#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
190#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
191#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
192
193/*
194 * WMM_CWMIN_CSR: CWmin for each EDCA AC
195 * CWMIN0: AC_BE
196 * CWMIN1: AC_BK
197 * CWMIN1: AC_VI
198 * CWMIN1: AC_VO
199 */
200#define WMM_CWMIN_CFG 0x0218
201#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
202#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
203#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
204#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
205
206/*
207 * WMM_CWMAX_CSR: CWmax for each EDCA AC
208 * CWMAX0: AC_BE
209 * CWMAX1: AC_BK
210 * CWMAX1: AC_VI
211 * CWMAX1: AC_VO
212 */
213#define WMM_CWMAX_CFG 0x021c
214#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
215#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
216#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
217#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
218
219/*
220 * AC_TXOP0: AC_BK/AC_BE TXOP register
221 * AC0TXOP: AC_BK in unit of 32us
222 * AC1TXOP: AC_BE in unit of 32us
223 */
224#define WMM_TXOP0_CFG 0x0220
225#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
226#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
227
228/*
229 * AC_TXOP1: AC_VO/AC_VI TXOP register
230 * AC2TXOP: AC_VI in unit of 32us
231 * AC3TXOP: AC_VO in unit of 32us
232 */
233#define WMM_TXOP1_CFG 0x0224
234#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
235#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
236
237/*
238 * GPIO_CTRL_CFG:
239 */
240#define GPIO_CTRL_CFG 0x0228
241#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
242#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
243#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
244#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
245#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
246#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
247#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
248#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
249#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
250
251/*
252 * MCU_CMD_CFG
253 */
254#define MCU_CMD_CFG 0x022c
255
256/*
257 * AC_BK register offsets
258 */
259#define TX_BASE_PTR0 0x0230
260#define TX_MAX_CNT0 0x0234
261#define TX_CTX_IDX0 0x0238
262#define TX_DTX_IDX0 0x023c
263
264/*
265 * AC_BE register offsets
266 */
267#define TX_BASE_PTR1 0x0240
268#define TX_MAX_CNT1 0x0244
269#define TX_CTX_IDX1 0x0248
270#define TX_DTX_IDX1 0x024c
271
272/*
273 * AC_VI register offsets
274 */
275#define TX_BASE_PTR2 0x0250
276#define TX_MAX_CNT2 0x0254
277#define TX_CTX_IDX2 0x0258
278#define TX_DTX_IDX2 0x025c
279
280/*
281 * AC_VO register offsets
282 */
283#define TX_BASE_PTR3 0x0260
284#define TX_MAX_CNT3 0x0264
285#define TX_CTX_IDX3 0x0268
286#define TX_DTX_IDX3 0x026c
287
288/*
289 * HCCA register offsets
290 */
291#define TX_BASE_PTR4 0x0270
292#define TX_MAX_CNT4 0x0274
293#define TX_CTX_IDX4 0x0278
294#define TX_DTX_IDX4 0x027c
295
296/*
297 * MGMT register offsets
298 */
299#define TX_BASE_PTR5 0x0280
300#define TX_MAX_CNT5 0x0284
301#define TX_CTX_IDX5 0x0288
302#define TX_DTX_IDX5 0x028c
303
304/*
305 * RX register offsets
306 */
307#define RX_BASE_PTR 0x0290
308#define RX_MAX_CNT 0x0294
309#define RX_CRX_IDX 0x0298
310#define RX_DRX_IDX 0x029c
311
312/*
313 * USB_DMA_CFG 39 * USB_DMA_CFG
314 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. 40 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
315 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. 41 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
@@ -343,1448 +69,18 @@
343#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff) 69#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
344 70
345/* 71/*
346 * PBF_SYS_CTRL
347 * HOST_RAM_WRITE: enable Host program ram write selection
348 */
349#define PBF_SYS_CTRL 0x0400
350#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
351#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
352
353/*
354 * PBF registers
355 * Most are for debug. Driver doesn't touch PBF register.
356 */
357#define PBF_CFG 0x0408
358#define PBF_MAX_PCNT 0x040c
359#define PBF_CTRL 0x0410
360#define PBF_INT_STA 0x0414
361#define PBF_INT_ENA 0x0418
362
363/*
364 * BCN_OFFSET0:
365 */
366#define BCN_OFFSET0 0x042c
367#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
368#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
369#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
370#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
371
372/*
373 * BCN_OFFSET1:
374 */
375#define BCN_OFFSET1 0x0430
376#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
377#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
378#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
379#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
380
381/*
382 * PBF registers
383 * Most are for debug. Driver doesn't touch PBF register.
384 */
385#define TXRXQ_PCNT 0x0438
386#define PBF_DBG 0x043c
387
388/*
389 * RF registers
390 */
391#define RF_CSR_CFG 0x0500
392#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
393#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
394#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
395#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
396
397/*
398 * MAC Control/Status Registers(CSR).
399 * Some values are set in TU, whereas 1 TU == 1024 us.
400 */
401
402/*
403 * MAC_CSR0: ASIC revision number.
404 * ASIC_REV: 0
405 * ASIC_VER: 2870
406 */
407#define MAC_CSR0 0x1000
408#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
409#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
410
411/*
412 * MAC_SYS_CTRL:
413 */
414#define MAC_SYS_CTRL 0x1004
415#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
416#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
417#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
418#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
419#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
420#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
421#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
422#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
423
424/*
425 * MAC_ADDR_DW0: STA MAC register 0
426 */
427#define MAC_ADDR_DW0 0x1008
428#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
429#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
430#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
431#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
432
433/*
434 * MAC_ADDR_DW1: STA MAC register 1
435 * UNICAST_TO_ME_MASK:
436 * Used to mask off bits from byte 5 of the MAC address
437 * to determine the UNICAST_TO_ME bit for RX frames.
438 * The full mask is complemented by BSS_ID_MASK:
439 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
440 */
441#define MAC_ADDR_DW1 0x100c
442#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
443#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
444#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
445
446/*
447 * MAC_BSSID_DW0: BSSID register 0
448 */
449#define MAC_BSSID_DW0 0x1010
450#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
451#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
452#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
453#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
454
455/*
456 * MAC_BSSID_DW1: BSSID register 1
457 * BSS_ID_MASK:
458 * 0: 1-BSSID mode (BSS index = 0)
459 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
460 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
461 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
462 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
463 * BSSID. This will make sure that those bits will be ignored
464 * when determining the MY_BSS of RX frames.
465 */
466#define MAC_BSSID_DW1 0x1014
467#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
468#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
469#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
470#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
471
472/*
473 * MAX_LEN_CFG: Maximum frame length register.
474 * MAX_MPDU: rt2860b max 16k bytes
475 * MAX_PSDU: Maximum PSDU length
476 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
477 */
478#define MAX_LEN_CFG 0x1018
479#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
480#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
481#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
482#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
483
484/*
485 * BBP_CSR_CFG: BBP serial control register
486 * VALUE: Register value to program into BBP
487 * REG_NUM: Selected BBP register
488 * READ_CONTROL: 0 write BBP, 1 read BBP
489 * BUSY: ASIC is busy executing BBP commands
490 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
491 * BBP_RW_MODE: 0 serial, 1 paralell
492 */
493#define BBP_CSR_CFG 0x101c
494#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
495#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
496#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
497#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
498#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
499#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
500
501/*
502 * RF_CSR_CFG0: RF control register
503 * REGID_AND_VALUE: Register value to program into RF
504 * BITWIDTH: Selected RF register
505 * STANDBYMODE: 0 high when standby, 1 low when standby
506 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
507 * BUSY: ASIC is busy executing RF commands
508 */
509#define RF_CSR_CFG0 0x1020
510#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
511#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
512#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
513#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
514#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
515#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
516
517/*
518 * RF_CSR_CFG1: RF control register
519 * REGID_AND_VALUE: Register value to program into RF
520 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
521 * 0: 3 system clock cycle (37.5usec)
522 * 1: 5 system clock cycle (62.5usec)
523 */
524#define RF_CSR_CFG1 0x1024
525#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
526#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
527
528/*
529 * RF_CSR_CFG2: RF control register
530 * VALUE: Register value to program into RF
531 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
532 * 0: 3 system clock cycle (37.5usec)
533 * 1: 5 system clock cycle (62.5usec)
534 */
535#define RF_CSR_CFG2 0x1028
536#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
537
538/*
539 * LED_CFG: LED control
540 * color LED's:
541 * 0: off
542 * 1: blinking upon TX2
543 * 2: periodic slow blinking
544 * 3: always on
545 * LED polarity:
546 * 0: active low
547 * 1: active high
548 */
549#define LED_CFG 0x102c
550#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
551#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
552#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
553#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
554#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
555#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
556#define LED_CFG_LED_POLAR FIELD32(0x40000000)
557
558/*
559 * XIFS_TIME_CFG: MAC timing
560 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
561 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
562 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
563 * when MAC doesn't reference BBP signal BBRXEND
564 * EIFS: unit 1us
565 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
566 *
567 */
568#define XIFS_TIME_CFG 0x1100
569#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
570#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
571#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
572#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
573#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
574
575/*
576 * BKOFF_SLOT_CFG:
577 */
578#define BKOFF_SLOT_CFG 0x1104
579#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
580#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
581
582/*
583 * NAV_TIME_CFG:
584 */
585#define NAV_TIME_CFG 0x1108
586#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
587#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
588#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
589#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
590
591/*
592 * CH_TIME_CFG: count as channel busy
593 */
594#define CH_TIME_CFG 0x110c
595
596/*
597 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
598 */
599#define PBF_LIFE_TIMER 0x1110
600
601/*
602 * BCN_TIME_CFG:
603 * BEACON_INTERVAL: in unit of 1/16 TU
604 * TSF_TICKING: Enable TSF auto counting
605 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
606 * BEACON_GEN: Enable beacon generator
607 */
608#define BCN_TIME_CFG 0x1114
609#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
610#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
611#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
612#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
613#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
614#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
615
616/*
617 * TBTT_SYNC_CFG:
618 */
619#define TBTT_SYNC_CFG 0x1118
620
621/*
622 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
623 */
624#define TSF_TIMER_DW0 0x111c
625#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
626
627/*
628 * TSF_TIMER_DW1: Local msb TSF timer, read-only
629 */
630#define TSF_TIMER_DW1 0x1120
631#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
632
633/*
634 * TBTT_TIMER: TImer remains till next TBTT, read-only
635 */
636#define TBTT_TIMER 0x1124
637
638/*
639 * INT_TIMER_CFG:
640 */
641#define INT_TIMER_CFG 0x1128
642
643/*
644 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
645 */
646#define INT_TIMER_EN 0x112c
647
648/*
649 * CH_IDLE_STA: channel idle time
650 */
651#define CH_IDLE_STA 0x1130
652
653/*
654 * CH_BUSY_STA: channel busy time
655 */
656#define CH_BUSY_STA 0x1134
657
658/*
659 * MAC_STATUS_CFG:
660 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
661 * if 1 or higher one of the 2 registers is busy.
662 */
663#define MAC_STATUS_CFG 0x1200
664#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
665
666/*
667 * PWR_PIN_CFG:
668 */
669#define PWR_PIN_CFG 0x1204
670
671/*
672 * AUTOWAKEUP_CFG: Manual power control / status register
673 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
674 * AUTOWAKE: 0:sleep, 1:awake
675 */
676#define AUTOWAKEUP_CFG 0x1208
677#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
678#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
679#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
680
681/*
682 * EDCA_AC0_CFG:
683 */
684#define EDCA_AC0_CFG 0x1300
685#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
686#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
687#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
688#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
689
690/*
691 * EDCA_AC1_CFG:
692 */
693#define EDCA_AC1_CFG 0x1304
694#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
695#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
696#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
697#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
698
699/*
700 * EDCA_AC2_CFG:
701 */
702#define EDCA_AC2_CFG 0x1308
703#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
704#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
705#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
706#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
707
708/*
709 * EDCA_AC3_CFG:
710 */
711#define EDCA_AC3_CFG 0x130c
712#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
713#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
714#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
715#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
716
717/*
718 * EDCA_TID_AC_MAP:
719 */
720#define EDCA_TID_AC_MAP 0x1310
721
722/*
723 * TX_PWR_CFG_0:
724 */
725#define TX_PWR_CFG_0 0x1314
726#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
727#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
728#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
729#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
730#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
731#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
732#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
733#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
734
735/*
736 * TX_PWR_CFG_1:
737 */
738#define TX_PWR_CFG_1 0x1318
739#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
740#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
741#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
742#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
743#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
744#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
745#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
746#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
747
748/*
749 * TX_PWR_CFG_2:
750 */
751#define TX_PWR_CFG_2 0x131c
752#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
753#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
754#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
755#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
756#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
757#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
758#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
759#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
760
761/*
762 * TX_PWR_CFG_3:
763 */
764#define TX_PWR_CFG_3 0x1320
765#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
766#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
767#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
768#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
769#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
770#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
771#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
772#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
773
774/*
775 * TX_PWR_CFG_4:
776 */
777#define TX_PWR_CFG_4 0x1324
778#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
779#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
780#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
781#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
782
783/*
784 * TX_PIN_CFG:
785 */
786#define TX_PIN_CFG 0x1328
787#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
788#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
789#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
790#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
791#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
792#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
793#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
794#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
795#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
796#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
797#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
798#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
799#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
800#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
801#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
802#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
803#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
804#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
805#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
806#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
807
808/*
809 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
810 */
811#define TX_BAND_CFG 0x132c
812#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
813#define TX_BAND_CFG_A FIELD32(0x00000002)
814#define TX_BAND_CFG_BG FIELD32(0x00000004)
815
816/*
817 * TX_SW_CFG0:
818 */
819#define TX_SW_CFG0 0x1330
820
821/*
822 * TX_SW_CFG1:
823 */
824#define TX_SW_CFG1 0x1334
825
826/*
827 * TX_SW_CFG2:
828 */
829#define TX_SW_CFG2 0x1338
830
831/*
832 * TXOP_THRES_CFG:
833 */
834#define TXOP_THRES_CFG 0x133c
835
836/*
837 * TXOP_CTRL_CFG:
838 */
839#define TXOP_CTRL_CFG 0x1340
840
841/*
842 * TX_RTS_CFG:
843 * RTS_THRES: unit:byte
844 * RTS_FBK_EN: enable rts rate fallback
845 */
846#define TX_RTS_CFG 0x1344
847#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
848#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
849#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
850
851/*
852 * TX_TIMEOUT_CFG:
853 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
854 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
855 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
856 * it is recommended that:
857 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
858 */
859#define TX_TIMEOUT_CFG 0x1348
860#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
861#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
862#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
863
864/*
865 * TX_RTY_CFG:
866 * SHORT_RTY_LIMIT: short retry limit
867 * LONG_RTY_LIMIT: long retry limit
868 * LONG_RTY_THRE: Long retry threshoold
869 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
870 * 0:expired by retry limit, 1: expired by mpdu life timer
871 * AGG_RTY_MODE: Aggregate MPDU retry mode
872 * 0:expired by retry limit, 1: expired by mpdu life timer
873 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
874 */
875#define TX_RTY_CFG 0x134c
876#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
877#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
878#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
879#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
880#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
881#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
882
883/*
884 * TX_LINK_CFG:
885 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
886 * MFB_ENABLE: TX apply remote MFB 1:enable
887 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
888 * 0: not apply remote remote unsolicit (MFS=7)
889 * TX_MRQ_EN: MCS request TX enable
890 * TX_RDG_EN: RDG TX enable
891 * TX_CF_ACK_EN: Piggyback CF-ACK enable
892 * REMOTE_MFB: remote MCS feedback
893 * REMOTE_MFS: remote MCS feedback sequence number
894 */
895#define TX_LINK_CFG 0x1350
896#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
897#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
898#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
899#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
900#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
901#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
902#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
903#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
904
905/*
906 * HT_FBK_CFG0:
907 */
908#define HT_FBK_CFG0 0x1354
909#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
910#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
911#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
912#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
913#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
914#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
915#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
916#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
917
918/*
919 * HT_FBK_CFG1:
920 */
921#define HT_FBK_CFG1 0x1358
922#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
923#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
924#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
925#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
926#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
927#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
928#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
929#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
930
931/*
932 * LG_FBK_CFG0:
933 */
934#define LG_FBK_CFG0 0x135c
935#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
936#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
937#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
938#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
939#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
940#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
941#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
942#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
943
944/*
945 * LG_FBK_CFG1:
946 */
947#define LG_FBK_CFG1 0x1360
948#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
949#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
950#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
951#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
952
953/*
954 * CCK_PROT_CFG: CCK Protection
955 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
956 * PROTECT_CTRL: Protection control frame type for CCK TX
957 * 0:none, 1:RTS/CTS, 2:CTS-to-self
958 * PROTECT_NAV: TXOP protection type for CCK TX
959 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
960 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
961 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
962 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
963 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
964 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
965 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
966 * RTS_TH_EN: RTS threshold enable on CCK TX
967 */
968#define CCK_PROT_CFG 0x1364
969#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
970#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
971#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
972#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
973#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
974#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
975#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
976#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
977#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
978#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
979
980/*
981 * OFDM_PROT_CFG: OFDM Protection
982 */
983#define OFDM_PROT_CFG 0x1368
984#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
985#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
986#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
987#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
988#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
989#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
990#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
991#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
992#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
993#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
994
995/*
996 * MM20_PROT_CFG: MM20 Protection
997 */
998#define MM20_PROT_CFG 0x136c
999#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1000#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1001#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1002#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1003#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1004#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1005#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1006#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1007#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1008#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1009
1010/*
1011 * MM40_PROT_CFG: MM40 Protection
1012 */
1013#define MM40_PROT_CFG 0x1370
1014#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1015#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1016#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1017#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1018#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1019#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1020#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1021#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1022#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1023#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1024
1025/*
1026 * GF20_PROT_CFG: GF20 Protection
1027 */
1028#define GF20_PROT_CFG 0x1374
1029#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1030#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1031#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1032#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1033#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1034#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1035#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1036#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1037#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1038#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1039
1040/*
1041 * GF40_PROT_CFG: GF40 Protection
1042 */
1043#define GF40_PROT_CFG 0x1378
1044#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1045#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1046#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1047#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1048#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1049#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1050#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1051#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1052#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1053#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1054
1055/*
1056 * EXP_CTS_TIME:
1057 */
1058#define EXP_CTS_TIME 0x137c
1059
1060/*
1061 * EXP_ACK_TIME:
1062 */
1063#define EXP_ACK_TIME 0x1380
1064
1065/*
1066 * RX_FILTER_CFG: RX configuration register.
1067 */
1068#define RX_FILTER_CFG 0x1400
1069#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1070#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1071#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1072#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1073#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1074#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1075#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1076#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1077#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1078#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1079#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1080#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1081#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1082#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1083#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1084#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1085#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1086
1087/*
1088 * AUTO_RSP_CFG:
1089 * AUTORESPONDER: 0: disable, 1: enable
1090 * BAC_ACK_POLICY: 0:long, 1:short preamble
1091 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1092 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1093 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1094 * DUAL_CTS_EN: Power bit value in control frame
1095 * ACK_CTS_PSM_BIT:Power bit value in control frame
1096 */
1097#define AUTO_RSP_CFG 0x1404
1098#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1099#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1100#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1101#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1102#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1103#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1104#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1105
1106/*
1107 * LEGACY_BASIC_RATE:
1108 */
1109#define LEGACY_BASIC_RATE 0x1408
1110
1111/*
1112 * HT_BASIC_RATE:
1113 */
1114#define HT_BASIC_RATE 0x140c
1115
1116/*
1117 * HT_CTRL_CFG:
1118 */
1119#define HT_CTRL_CFG 0x1410
1120
1121/*
1122 * SIFS_COST_CFG:
1123 */
1124#define SIFS_COST_CFG 0x1414
1125
1126/*
1127 * RX_PARSER_CFG:
1128 * Set NAV for all received frames
1129 */
1130#define RX_PARSER_CFG 0x1418
1131
1132/*
1133 * TX_SEC_CNT0:
1134 */
1135#define TX_SEC_CNT0 0x1500
1136
1137/*
1138 * RX_SEC_CNT0:
1139 */
1140#define RX_SEC_CNT0 0x1504
1141
1142/*
1143 * CCMP_FC_MUTE:
1144 */
1145#define CCMP_FC_MUTE 0x1508
1146
1147/*
1148 * TXOP_HLDR_ADDR0:
1149 */
1150#define TXOP_HLDR_ADDR0 0x1600
1151
1152/*
1153 * TXOP_HLDR_ADDR1:
1154 */
1155#define TXOP_HLDR_ADDR1 0x1604
1156
1157/*
1158 * TXOP_HLDR_ET:
1159 */
1160#define TXOP_HLDR_ET 0x1608
1161
1162/*
1163 * QOS_CFPOLL_RA_DW0:
1164 */
1165#define QOS_CFPOLL_RA_DW0 0x160c
1166
1167/*
1168 * QOS_CFPOLL_RA_DW1:
1169 */
1170#define QOS_CFPOLL_RA_DW1 0x1610
1171
1172/*
1173 * QOS_CFPOLL_QC:
1174 */
1175#define QOS_CFPOLL_QC 0x1614
1176
1177/*
1178 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1179 */
1180#define RX_STA_CNT0 0x1700
1181#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1182#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1183
1184/*
1185 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1186 */
1187#define RX_STA_CNT1 0x1704
1188#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1189#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1190
1191/*
1192 * RX_STA_CNT2:
1193 */
1194#define RX_STA_CNT2 0x1708
1195#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1196#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1197
1198/*
1199 * TX_STA_CNT0: TX Beacon count
1200 */
1201#define TX_STA_CNT0 0x170c
1202#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1203#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1204
1205/*
1206 * TX_STA_CNT1: TX tx count
1207 */
1208#define TX_STA_CNT1 0x1710
1209#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1210#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1211
1212/*
1213 * TX_STA_CNT2: TX tx count
1214 */
1215#define TX_STA_CNT2 0x1714
1216#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1217#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1218
1219/*
1220 * TX_STA_FIFO: TX Result for specific PID status fifo register
1221 */
1222#define TX_STA_FIFO 0x1718
1223#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1224#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1225#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1226#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1227#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1228#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1229#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1230
1231/*
1232 * TX_AGG_CNT: Debug counter
1233 */
1234#define TX_AGG_CNT 0x171c
1235#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1236#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1237
1238/*
1239 * TX_AGG_CNT0:
1240 */
1241#define TX_AGG_CNT0 0x1720
1242#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1243#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1244
1245/*
1246 * TX_AGG_CNT1:
1247 */
1248#define TX_AGG_CNT1 0x1724
1249#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1250#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1251
1252/*
1253 * TX_AGG_CNT2:
1254 */
1255#define TX_AGG_CNT2 0x1728
1256#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1257#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1258
1259/*
1260 * TX_AGG_CNT3:
1261 */
1262#define TX_AGG_CNT3 0x172c
1263#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1264#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1265
1266/*
1267 * TX_AGG_CNT4:
1268 */
1269#define TX_AGG_CNT4 0x1730
1270#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1271#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1272
1273/*
1274 * TX_AGG_CNT5:
1275 */
1276#define TX_AGG_CNT5 0x1734
1277#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1278#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1279
1280/*
1281 * TX_AGG_CNT6:
1282 */
1283#define TX_AGG_CNT6 0x1738
1284#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1285#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1286
1287/*
1288 * TX_AGG_CNT7:
1289 */
1290#define TX_AGG_CNT7 0x173c
1291#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1292#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1293
1294/*
1295 * MPDU_DENSITY_CNT:
1296 * TX_ZERO_DEL: TX zero length delimiter count
1297 * RX_ZERO_DEL: RX zero length delimiter count
1298 */
1299#define MPDU_DENSITY_CNT 0x1740
1300#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1301#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1302
1303/*
1304 * Security key table memory.
1305 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1306 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1307 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1308 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1309 * SHARED_KEY_TABLE_BASE: 32 bytes * 32-entry
1310 * SHARED_KEY_MODE_BASE: 4 bits * 32-entry
1311 */
1312#define MAC_WCID_BASE 0x1800
1313#define PAIRWISE_KEY_TABLE_BASE 0x4000
1314#define MAC_IVEIV_TABLE_BASE 0x6000
1315#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1316#define SHARED_KEY_TABLE_BASE 0x6c00
1317#define SHARED_KEY_MODE_BASE 0x7000
1318
1319#define MAC_WCID_ENTRY(__idx) \
1320 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1321#define PAIRWISE_KEY_ENTRY(__idx) \
1322 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1323#define MAC_IVEIV_ENTRY(__idx) \
1324 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1325#define MAC_WCID_ATTR_ENTRY(__idx) \
1326 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1327#define SHARED_KEY_ENTRY(__idx) \
1328 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1329#define SHARED_KEY_MODE_ENTRY(__idx) \
1330 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1331
1332struct mac_wcid_entry {
1333 u8 mac[6];
1334 u8 reserved[2];
1335} __attribute__ ((packed));
1336
1337struct hw_key_entry {
1338 u8 key[16];
1339 u8 tx_mic[8];
1340 u8 rx_mic[8];
1341} __attribute__ ((packed));
1342
1343struct mac_iveiv_entry {
1344 u8 iv[8];
1345} __attribute__ ((packed));
1346
1347/*
1348 * MAC_WCID_ATTRIBUTE:
1349 */
1350#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1351#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1352#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1353#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1354
1355/*
1356 * SHARED_KEY_MODE:
1357 */
1358#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1359#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1360#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1361#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1362#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1363#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1364#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1365#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1366
1367/*
1368 * HOST-MCU communication
1369 */
1370
1371/*
1372 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1373 */
1374#define H2M_MAILBOX_CSR 0x7010
1375#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1376#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1377#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1378#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1379
1380/*
1381 * H2M_MAILBOX_CID:
1382 */
1383#define H2M_MAILBOX_CID 0x7014
1384#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1385#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1386#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1387#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1388
1389/*
1390 * H2M_MAILBOX_STATUS:
1391 */
1392#define H2M_MAILBOX_STATUS 0x701c
1393
1394/*
1395 * H2M_INT_SRC:
1396 */
1397#define H2M_INT_SRC 0x7024
1398
1399/*
1400 * H2M_BBP_AGENT:
1401 */
1402#define H2M_BBP_AGENT 0x7028
1403
1404/*
1405 * MCU_LEDCS: LED control for MCU Mailbox.
1406 */
1407#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1408#define MCU_LEDCS_POLARITY FIELD8(0x01)
1409
1410/*
1411 * HW_CS_CTS_BASE:
1412 * Carrier-sense CTS frame base address.
1413 * It's where mac stores carrier-sense frame for carrier-sense function.
1414 */
1415#define HW_CS_CTS_BASE 0x7700
1416
1417/*
1418 * HW_DFS_CTS_BASE:
1419 * FS CTS frame base address. It's where mac stores CTS frame for DFS.
1420 */
1421#define HW_DFS_CTS_BASE 0x7780
1422
1423/*
1424 * TXRX control registers - base address 0x3000
1425 */
1426
1427/*
1428 * TXRX_CSR1:
1429 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1430 */
1431#define TXRX_CSR1 0x77d0
1432
1433/*
1434 * HW_DEBUG_SETTING_BASE:
1435 * since NULL frame won't be that long (256 byte)
1436 * We steal 16 tail bytes to save debugging settings
1437 */
1438#define HW_DEBUG_SETTING_BASE 0x77f0
1439#define HW_DEBUG_SETTING_BASE2 0x7770
1440
1441/*
1442 * HW_BEACON_BASE
1443 * In order to support maximum 8 MBSS and its maximum length
1444 * is 512 bytes for each beacon
1445 * Three section discontinue memory segments will be used.
1446 * 1. The original region for BCN 0~3
1447 * 2. Extract memory from FCE table for BCN 4~5
1448 * 3. Extract memory from Pair-wise key table for BCN 6~7
1449 * It occupied those memory of wcid 238~253 for BCN 6
1450 * and wcid 222~237 for BCN 7
1451 *
1452 * IMPORTANT NOTE: Not sure why legacy driver does this,
1453 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1454 */
1455#define HW_BEACON_BASE0 0x7800
1456#define HW_BEACON_BASE1 0x7a00
1457#define HW_BEACON_BASE2 0x7c00
1458#define HW_BEACON_BASE3 0x7e00
1459#define HW_BEACON_BASE4 0x7200
1460#define HW_BEACON_BASE5 0x7400
1461#define HW_BEACON_BASE6 0x5dc0
1462#define HW_BEACON_BASE7 0x5bc0
1463
1464#define HW_BEACON_OFFSET(__index) \
1465 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1466 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1467 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1468
1469/*
1470 * 8051 firmware image. 72 * 8051 firmware image.
1471 */ 73 */
1472#define FIRMWARE_RT2870 "rt2870.bin" 74#define FIRMWARE_RT2870 "rt2870.bin"
1473#define FIRMWARE_IMAGE_BASE 0x3000 75#define FIRMWARE_IMAGE_BASE 0x3000
1474 76
1475/* 77/*
1476 * BBP registers.
1477 * The wordsize of the BBP is 8 bits.
1478 */
1479
1480/*
1481 * BBP 1: TX Antenna
1482 */
1483#define BBP1_TX_POWER FIELD8(0x07)
1484#define BBP1_TX_ANTENNA FIELD8(0x18)
1485
1486/*
1487 * BBP 3: RX Antenna
1488 */
1489#define BBP3_RX_ANTENNA FIELD8(0x18)
1490#define BBP3_HT40_PLUS FIELD8(0x20)
1491
1492/*
1493 * BBP 4: Bandwidth
1494 */
1495#define BBP4_TX_BF FIELD8(0x01)
1496#define BBP4_BANDWIDTH FIELD8(0x18)
1497
1498/*
1499 * RFCSR registers
1500 * The wordsize of the RFCSR is 8 bits.
1501 */
1502
1503/*
1504 * RFCSR 6:
1505 */
1506#define RFCSR6_R FIELD8(0x03)
1507
1508/*
1509 * RFCSR 7:
1510 */
1511#define RFCSR7_RF_TUNING FIELD8(0x01)
1512
1513/*
1514 * RFCSR 12:
1515 */
1516#define RFCSR12_TX_POWER FIELD8(0x1f)
1517
1518/*
1519 * RFCSR 22:
1520 */
1521#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1522
1523/*
1524 * RFCSR 23:
1525 */
1526#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1527
1528/*
1529 * RFCSR 30:
1530 */
1531#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1532
1533/*
1534 * RF registers
1535 */
1536
1537/*
1538 * RF 2
1539 */
1540#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1541#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1542#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1543
1544/*
1545 * RF 3
1546 */
1547#define RF3_TXPOWER_G FIELD32(0x00003e00)
1548#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1549#define RF3_TXPOWER_A FIELD32(0x00003c00)
1550
1551/*
1552 * RF 4
1553 */
1554#define RF4_TXPOWER_G FIELD32(0x000007c0)
1555#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1556#define RF4_TXPOWER_A FIELD32(0x00000780)
1557#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1558#define RF4_HT40 FIELD32(0x00200000)
1559
1560/*
1561 * EEPROM content.
1562 * The wordsize of the EEPROM is 16 bits.
1563 */
1564
1565/*
1566 * EEPROM Version
1567 */
1568#define EEPROM_VERSION 0x0001
1569#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1570#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1571
1572/*
1573 * HW MAC address.
1574 */
1575#define EEPROM_MAC_ADDR_0 0x0002
1576#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1577#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1578#define EEPROM_MAC_ADDR_1 0x0003
1579#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1580#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1581#define EEPROM_MAC_ADDR_2 0x0004
1582#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1583#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1584
1585/*
1586 * EEPROM ANTENNA config
1587 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1588 * TXPATH: 1: 1T, 2: 2T
1589 */
1590#define EEPROM_ANTENNA 0x001a
1591#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1592#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1593#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1594
1595/*
1596 * EEPROM NIC config
1597 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1598 */
1599#define EEPROM_NIC 0x001b
1600#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1601#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1602#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1603#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1604#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1605#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1606#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1607#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1608#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1609#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1610
1611/*
1612 * EEPROM frequency
1613 */
1614#define EEPROM_FREQ 0x001d
1615#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1616#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1617#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1618
1619/*
1620 * EEPROM LED
1621 * POLARITY_RDY_G: Polarity RDY_G setting.
1622 * POLARITY_RDY_A: Polarity RDY_A setting.
1623 * POLARITY_ACT: Polarity ACT setting.
1624 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1625 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1626 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1627 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1628 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1629 * LED_MODE: Led mode.
1630 */
1631#define EEPROM_LED1 0x001e
1632#define EEPROM_LED2 0x001f
1633#define EEPROM_LED3 0x0020
1634#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1635#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1636#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1637#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1638#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1639#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1640#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1641#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1642#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1643
1644/*
1645 * EEPROM LNA
1646 */
1647#define EEPROM_LNA 0x0022
1648#define EEPROM_LNA_BG FIELD16(0x00ff)
1649#define EEPROM_LNA_A0 FIELD16(0xff00)
1650
1651/*
1652 * EEPROM RSSI BG offset
1653 */
1654#define EEPROM_RSSI_BG 0x0023
1655#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1656#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1657
1658/*
1659 * EEPROM RSSI BG2 offset
1660 */
1661#define EEPROM_RSSI_BG2 0x0024
1662#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1663#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1664
1665/*
1666 * EEPROM RSSI A offset
1667 */
1668#define EEPROM_RSSI_A 0x0025
1669#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1670#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1671
1672/*
1673 * EEPROM RSSI A2 offset
1674 */
1675#define EEPROM_RSSI_A2 0x0026
1676#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1677#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1678
1679/*
1680 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1681 * This is delta in 40MHZ.
1682 * VALUE: Tx Power dalta value (MAX=4)
1683 * TYPE: 1: Plus the delta value, 0: minus the delta value
1684 * TXPOWER: Enable:
1685 */
1686#define EEPROM_TXPOWER_DELTA 0x0028
1687#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1688#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1689#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1690
1691/*
1692 * EEPROM TXPOWER 802.11BG
1693 */
1694#define EEPROM_TXPOWER_BG1 0x0029
1695#define EEPROM_TXPOWER_BG2 0x0030
1696#define EEPROM_TXPOWER_BG_SIZE 7
1697#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1698#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1699
1700/*
1701 * EEPROM TXPOWER 802.11A
1702 */
1703#define EEPROM_TXPOWER_A1 0x003c
1704#define EEPROM_TXPOWER_A2 0x0053
1705#define EEPROM_TXPOWER_A_SIZE 6
1706#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1707#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1708
1709/*
1710 * EEPROM TXpower byrate: 20MHZ power
1711 */
1712#define EEPROM_TXPOWER_BYRATE 0x006f
1713
1714/*
1715 * EEPROM BBP.
1716 */
1717#define EEPROM_BBP_START 0x0078
1718#define EEPROM_BBP_SIZE 16
1719#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1720#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1721
1722/*
1723 * MCU mailbox commands.
1724 */
1725#define MCU_SLEEP 0x30
1726#define MCU_WAKEUP 0x31
1727#define MCU_RADIO_OFF 0x35
1728#define MCU_CURRENT 0x36
1729#define MCU_LED 0x50
1730#define MCU_LED_STRENGTH 0x51
1731#define MCU_LED_1 0x52
1732#define MCU_LED_2 0x53
1733#define MCU_LED_3 0x54
1734#define MCU_RADAR 0x60
1735#define MCU_BOOT_SIGNAL 0x72
1736#define MCU_BBP_SIGNAL 0x80
1737#define MCU_POWER_SAVE 0x83
1738
1739/*
1740 * MCU mailbox tokens
1741 */
1742#define TOKEN_WAKUP 3
1743
1744/*
1745 * DMA descriptor defines. 78 * DMA descriptor defines.
1746 */ 79 */
1747#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
1748#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) ) 80#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1749#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) ) 81#define RXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1750#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
1751#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) ) 82#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1752 83#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
1753/*
1754 * TX descriptor format for TX, PRIO and Beacon Ring.
1755 */
1756
1757/*
1758 * Word0
1759 */
1760#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
1761
1762/*
1763 * Word1
1764 */
1765#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
1766#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
1767#define TXD_W1_BURST FIELD32(0x00008000)
1768#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
1769#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
1770#define TXD_W1_DMA_DONE FIELD32(0x80000000)
1771
1772/*
1773 * Word2
1774 */
1775#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
1776
1777/*
1778 * Word3
1779 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1780 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1781 * 0:MGMT, 1:HCCA 2:EDCA
1782 */
1783#define TXD_W3_WIV FIELD32(0x01000000)
1784#define TXD_W3_QSEL FIELD32(0x06000000)
1785#define TXD_W3_TCO FIELD32(0x20000000)
1786#define TXD_W3_UCO FIELD32(0x40000000)
1787#define TXD_W3_ICO FIELD32(0x80000000)
1788 84
1789/* 85/*
1790 * TX Info structure 86 * TX Info structure
@@ -1807,50 +103,52 @@ struct mac_iveiv_entry {
1807#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000) 103#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
1808 104
1809/* 105/*
1810 * TX WI structure 106 * RX Info structure
107 */
108
109/*
110 * Word 0
111 */
112
113#define RXINFO_W0_USB_DMA_RX_PKT_LEN FIELD32(0x0000ffff)
114
115/*
116 * RX WI structure
1811 */ 117 */
1812 118
1813/* 119/*
1814 * Word0 120 * Word0
1815 * FRAG: 1 To inform TKIP engine this is a fragment.
1816 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1817 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1818 * BW: Channel bandwidth 20MHz or 40 MHz
1819 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1820 */ 121 */
1821#define TXWI_W0_FRAG FIELD32(0x00000001) 122#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1822#define TXWI_W0_MIMO_PS FIELD32(0x00000002) 123#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1823#define TXWI_W0_CF_ACK FIELD32(0x00000004) 124#define RXWI_W0_BSSID FIELD32(0x00001c00)
1824#define TXWI_W0_TS FIELD32(0x00000008) 125#define RXWI_W0_UDF FIELD32(0x0000e000)
1825#define TXWI_W0_AMPDU FIELD32(0x00000010) 126#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1826#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) 127#define RXWI_W0_TID FIELD32(0xf0000000)
1827#define TXWI_W0_TX_OP FIELD32(0x00000300)
1828#define TXWI_W0_MCS FIELD32(0x007f0000)
1829#define TXWI_W0_BW FIELD32(0x00800000)
1830#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1831#define TXWI_W0_STBC FIELD32(0x06000000)
1832#define TXWI_W0_IFS FIELD32(0x08000000)
1833#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1834 128
1835/* 129/*
1836 * Word1 130 * Word1
1837 */ 131 */
1838#define TXWI_W1_ACK FIELD32(0x00000001) 132#define RXWI_W1_FRAG FIELD32(0x0000000f)
1839#define TXWI_W1_NSEQ FIELD32(0x00000002) 133#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1840#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) 134#define RXWI_W1_MCS FIELD32(0x007f0000)
1841#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) 135#define RXWI_W1_BW FIELD32(0x00800000)
1842#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 136#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1843#define TXWI_W1_PACKETID FIELD32(0xf0000000) 137#define RXWI_W1_STBC FIELD32(0x06000000)
138#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1844 139
1845/* 140/*
1846 * Word2 141 * Word2
1847 */ 142 */
1848#define TXWI_W2_IV FIELD32(0xffffffff) 143#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
144#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
145#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1849 146
1850/* 147/*
1851 * Word3 148 * Word3
1852 */ 149 */
1853#define TXWI_W3_EIV FIELD32(0xffffffff) 150#define RXWI_W3_SNR0 FIELD32(0x000000ff)
151#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1854 152
1855/* 153/*
1856 * RX descriptor format for RX Ring. 154 * RX descriptor format for RX Ring.
@@ -1888,64 +186,4 @@ struct mac_iveiv_entry {
1888#define RXD_W0_LAST_AMSDU FIELD32(0x00080000) 186#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
1889#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000) 187#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
1890 188
1891/*
1892 * RX WI structure
1893 */
1894
1895/*
1896 * Word0
1897 */
1898#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1899#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1900#define RXWI_W0_BSSID FIELD32(0x00001c00)
1901#define RXWI_W0_UDF FIELD32(0x0000e000)
1902#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1903#define RXWI_W0_TID FIELD32(0xf0000000)
1904
1905/*
1906 * Word1
1907 */
1908#define RXWI_W1_FRAG FIELD32(0x0000000f)
1909#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1910#define RXWI_W1_MCS FIELD32(0x007f0000)
1911#define RXWI_W1_BW FIELD32(0x00800000)
1912#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1913#define RXWI_W1_STBC FIELD32(0x06000000)
1914#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1915
1916/*
1917 * Word2
1918 */
1919#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1920#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1921#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1922
1923/*
1924 * Word3
1925 */
1926#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1927#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1928
1929/*
1930 * Macros for converting txpower from EEPROM to mac80211 value
1931 * and from mac80211 value to register value.
1932 */
1933#define MIN_G_TXPOWER 0
1934#define MIN_A_TXPOWER -7
1935#define MAX_G_TXPOWER 31
1936#define MAX_A_TXPOWER 15
1937#define DEFAULT_TXPOWER 5
1938
1939#define TXPOWER_G_FROM_DEV(__txpower) \
1940 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1941
1942#define TXPOWER_G_TO_DEV(__txpower) \
1943 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1944
1945#define TXPOWER_A_FROM_DEV(__txpower) \
1946 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1947
1948#define TXPOWER_A_TO_DEV(__txpower) \
1949 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1950
1951#endif /* RT2800USB_H */ 189#endif /* RT2800USB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 27bc6b7fbfde..d9daa9c406fa 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
3 <http://rt2x00.serialmonkey.com> 4 <http://rt2x00.serialmonkey.com>
4 5
5 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
@@ -103,6 +104,12 @@
103#define GET_DURATION_RES(__size, __rate)(((__size) * 8 * 10) % (__rate)) 104#define GET_DURATION_RES(__size, __rate)(((__size) * 8 * 10) % (__rate))
104 105
105/* 106/*
107 * Determine the number of L2 padding bytes required between the header and
108 * the payload.
109 */
110#define L2PAD_SIZE(__hdrlen) (-(__hdrlen) & 3)
111
112/*
106 * Determine the alignment requirement, 113 * Determine the alignment requirement,
107 * to make sure the 802.11 payload is padded to a 4-byte boundrary 114 * to make sure the 802.11 payload is padded to a 4-byte boundrary
108 * we must determine the address of the payload and calculate the 115 * we must determine the address of the payload and calculate the
@@ -112,6 +119,12 @@
112 ( ((unsigned long)((__skb)->data + (__header))) & 3 ) 119 ( ((unsigned long)((__skb)->data + (__header))) & 3 )
113 120
114/* 121/*
122 * Constants for extra TX headroom for alignment purposes.
123 */
124#define RT2X00_ALIGN_SIZE 4 /* Only whole frame needs alignment */
125#define RT2X00_L2PAD_SIZE 8 /* Both header & payload need alignment */
126
127/*
115 * Standard timing and size defines. 128 * Standard timing and size defines.
116 * These values should follow the ieee80211 specifications. 129 * These values should follow the ieee80211 specifications.
117 */ 130 */
@@ -144,6 +157,12 @@ struct avg_val {
144 int avg_weight; 157 int avg_weight;
145}; 158};
146 159
160enum rt2x00_chip_intf {
161 RT2X00_CHIP_INTF_PCI,
162 RT2X00_CHIP_INTF_USB,
163 RT2X00_CHIP_INTF_SOC,
164};
165
147/* 166/*
148 * Chipset identification 167 * Chipset identification
149 * The chipset on the device is composed of a RT and RF chip. 168 * The chipset on the device is composed of a RT and RF chip.
@@ -151,17 +170,28 @@ struct avg_val {
151 */ 170 */
152struct rt2x00_chip { 171struct rt2x00_chip {
153 u16 rt; 172 u16 rt;
154#define RT2460 0x0101 173#define RT2460 0x2460
155#define RT2560 0x0201 174#define RT2560 0x2560
156#define RT2570 0x1201 175#define RT2570 0x2570
157#define RT2561s 0x0301 /* Turbo */ 176#define RT2661 0x2661
158#define RT2561 0x0302 177#define RT2573 0x2573
159#define RT2661 0x0401 178#define RT2860 0x2860 /* 2.4GHz PCI/CB */
160#define RT2571 0x1300 179#define RT2870 0x2870
161#define RT2870 0x1600 180#define RT2872 0x2872
181#define RT2880 0x2880 /* WSOC */
182#define RT2883 0x2883 /* WSOC */
183#define RT2890 0x2890 /* 2.4GHz PCIe */
184#define RT3052 0x3052 /* WSOC */
185#define RT3070 0x3070
186#define RT3071 0x3071
187#define RT3090 0x3090 /* 2.4GHz PCIe */
188#define RT3390 0x3390
189#define RT3572 0x3572
162 190
163 u16 rf; 191 u16 rf;
164 u32 rev; 192 u16 rev;
193
194 enum rt2x00_chip_intf intf;
165}; 195};
166 196
167/* 197/*
@@ -299,13 +329,6 @@ struct link {
299 struct avg_val avg_rssi; 329 struct avg_val avg_rssi;
300 330
301 /* 331 /*
302 * Currently precalculated percentages of successful
303 * TX and RX frames.
304 */
305 int rx_percentage;
306 int tx_percentage;
307
308 /*
309 * Work structure for scheduling periodic link tuning. 332 * Work structure for scheduling periodic link tuning.
310 */ 333 */
311 struct delayed_work work; 334 struct delayed_work work;
@@ -579,6 +602,7 @@ struct rt2x00_ops {
579 const unsigned int eeprom_size; 602 const unsigned int eeprom_size;
580 const unsigned int rf_size; 603 const unsigned int rf_size;
581 const unsigned int tx_queues; 604 const unsigned int tx_queues;
605 const unsigned int extra_tx_headroom;
582 const struct data_queue_desc *rx; 606 const struct data_queue_desc *rx;
583 const struct data_queue_desc *tx; 607 const struct data_queue_desc *tx;
584 const struct data_queue_desc *bcn; 608 const struct data_queue_desc *bcn;
@@ -835,9 +859,23 @@ struct rt2x00_dev {
835 * Firmware image. 859 * Firmware image.
836 */ 860 */
837 const struct firmware *fw; 861 const struct firmware *fw;
862
863 /*
864 * Driver specific data.
865 */
866 void *priv;
838}; 867};
839 868
840/* 869/*
870 * Register defines.
871 * Some registers require multiple attempts before success,
872 * in those cases REGISTER_BUSY_COUNT attempts should be
873 * taken with a REGISTER_BUSY_DELAY interval.
874 */
875#define REGISTER_BUSY_COUNT 5
876#define REGISTER_BUSY_DELAY 100
877
878/*
841 * Generic RF access. 879 * Generic RF access.
842 * The RF is being accessed by word index. 880 * The RF is being accessed by word index.
843 */ 881 */
@@ -881,48 +919,57 @@ static inline void rt2x00_eeprom_write(struct rt2x00_dev *rt2x00dev,
881 * Chipset handlers 919 * Chipset handlers
882 */ 920 */
883static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev, 921static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev,
884 const u16 rt, const u16 rf, const u32 rev) 922 const u16 rt, const u16 rf, const u16 rev)
885{ 923{
886 INFO(rt2x00dev,
887 "Chipset detected - rt: %04x, rf: %04x, rev: %08x.\n",
888 rt, rf, rev);
889
890 rt2x00dev->chip.rt = rt; 924 rt2x00dev->chip.rt = rt;
891 rt2x00dev->chip.rf = rf; 925 rt2x00dev->chip.rf = rf;
892 rt2x00dev->chip.rev = rev; 926 rt2x00dev->chip.rev = rev;
927
928 INFO(rt2x00dev,
929 "Chipset detected - rt: %04x, rf: %04x, rev: %04x.\n",
930 rt2x00dev->chip.rt, rt2x00dev->chip.rf, rt2x00dev->chip.rev);
893} 931}
894 932
895static inline void rt2x00_set_chip_rt(struct rt2x00_dev *rt2x00dev, 933static inline char rt2x00_rt(struct rt2x00_dev *rt2x00dev, const u16 rt)
896 const u16 rt)
897{ 934{
898 rt2x00dev->chip.rt = rt; 935 return (rt2x00dev->chip.rt == rt);
936}
937
938static inline char rt2x00_rf(struct rt2x00_dev *rt2x00dev, const u16 rf)
939{
940 return (rt2x00dev->chip.rf == rf);
941}
942
943static inline u16 rt2x00_rev(struct rt2x00_dev *rt2x00dev)
944{
945 return rt2x00dev->chip.rev;
899} 946}
900 947
901static inline void rt2x00_set_chip_rf(struct rt2x00_dev *rt2x00dev, 948static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev,
902 const u16 rf, const u32 rev) 949 enum rt2x00_chip_intf intf)
903{ 950{
904 rt2x00_set_chip(rt2x00dev, rt2x00dev->chip.rt, rf, rev); 951 rt2x00dev->chip.intf = intf;
905} 952}
906 953
907static inline char rt2x00_rt(const struct rt2x00_chip *chipset, const u16 chip) 954static inline bool rt2x00_intf(struct rt2x00_dev *rt2x00dev,
955 enum rt2x00_chip_intf intf)
908{ 956{
909 return (chipset->rt == chip); 957 return (rt2x00dev->chip.intf == intf);
910} 958}
911 959
912static inline char rt2x00_rf(const struct rt2x00_chip *chipset, const u16 chip) 960static inline bool rt2x00_is_pci(struct rt2x00_dev *rt2x00dev)
913{ 961{
914 return (chipset->rf == chip); 962 return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
915} 963}
916 964
917static inline u32 rt2x00_rev(const struct rt2x00_chip *chipset) 965static inline bool rt2x00_is_usb(struct rt2x00_dev *rt2x00dev)
918{ 966{
919 return chipset->rev; 967 return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_USB);
920} 968}
921 969
922static inline bool rt2x00_check_rev(const struct rt2x00_chip *chipset, 970static inline bool rt2x00_is_soc(struct rt2x00_dev *rt2x00dev)
923 const u32 mask, const u32 rev)
924{ 971{
925 return ((chipset->rev & mask) == rev); 972 return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_SOC);
926} 973}
927 974
928/** 975/**
@@ -964,9 +1011,9 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
964int rt2x00mac_start(struct ieee80211_hw *hw); 1011int rt2x00mac_start(struct ieee80211_hw *hw);
965void rt2x00mac_stop(struct ieee80211_hw *hw); 1012void rt2x00mac_stop(struct ieee80211_hw *hw);
966int rt2x00mac_add_interface(struct ieee80211_hw *hw, 1013int rt2x00mac_add_interface(struct ieee80211_hw *hw,
967 struct ieee80211_if_init_conf *conf); 1014 struct ieee80211_vif *vif);
968void rt2x00mac_remove_interface(struct ieee80211_hw *hw, 1015void rt2x00mac_remove_interface(struct ieee80211_hw *hw,
969 struct ieee80211_if_init_conf *conf); 1016 struct ieee80211_vif *vif);
970int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed); 1017int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed);
971void rt2x00mac_configure_filter(struct ieee80211_hw *hw, 1018void rt2x00mac_configure_filter(struct ieee80211_hw *hw,
972 unsigned int changed_flags, 1019 unsigned int changed_flags,
@@ -983,8 +1030,6 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
983#endif /* CONFIG_RT2X00_LIB_CRYPTO */ 1030#endif /* CONFIG_RT2X00_LIB_CRYPTO */
984int rt2x00mac_get_stats(struct ieee80211_hw *hw, 1031int rt2x00mac_get_stats(struct ieee80211_hw *hw,
985 struct ieee80211_low_level_stats *stats); 1032 struct ieee80211_low_level_stats *stats);
986int rt2x00mac_get_tx_stats(struct ieee80211_hw *hw,
987 struct ieee80211_tx_queue_stats *stats);
988void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw, 1033void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
989 struct ieee80211_vif *vif, 1034 struct ieee80211_vif *vif,
990 struct ieee80211_bss_conf *bss_conf, 1035 struct ieee80211_bss_conf *bss_conf,
diff --git a/drivers/net/wireless/rt2x00/rt2x00config.c b/drivers/net/wireless/rt2x00/rt2x00config.c
index 40a201e2e151..098315a271ca 100644
--- a/drivers/net/wireless/rt2x00/rt2x00config.c
+++ b/drivers/net/wireless/rt2x00/rt2x00config.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/rt2x00/rt2x00crypto.c b/drivers/net/wireless/rt2x00/rt2x00crypto.c
index de36837dcf86..d291c7862e10 100644
--- a/drivers/net/wireless/rt2x00/rt2x00crypto.c
+++ b/drivers/net/wireless/rt2x00/rt2x00crypto.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/rt2x00/rt2x00debug.c b/drivers/net/wireless/rt2x00/rt2x00debug.c
index 68bc9bb1dbf9..9569fb4e5bc5 100644
--- a/drivers/net/wireless/rt2x00/rt2x00debug.c
+++ b/drivers/net/wireless/rt2x00/rt2x00debug.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -28,6 +28,7 @@
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/poll.h> 29#include <linux/poll.h>
30#include <linux/sched.h> 30#include <linux/sched.h>
31#include <linux/slab.h>
31#include <linux/uaccess.h> 32#include <linux/uaccess.h>
32 33
33#include "rt2x00.h" 34#include "rt2x00.h"
@@ -109,7 +110,7 @@ struct rt2x00debug_intf {
109 110
110 /* 111 /*
111 * HW crypto statistics. 112 * HW crypto statistics.
112 * All statistics are stored seperately per cipher type. 113 * All statistics are stored separately per cipher type.
113 */ 114 */
114 struct rt2x00debug_crypto crypto_stats[CIPHER_MAX]; 115 struct rt2x00debug_crypto crypto_stats[CIPHER_MAX];
115 116
@@ -184,7 +185,7 @@ void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
184 dump_hdr->data_length = cpu_to_le32(skb->len); 185 dump_hdr->data_length = cpu_to_le32(skb->len);
185 dump_hdr->chip_rt = cpu_to_le16(rt2x00dev->chip.rt); 186 dump_hdr->chip_rt = cpu_to_le16(rt2x00dev->chip.rt);
186 dump_hdr->chip_rf = cpu_to_le16(rt2x00dev->chip.rf); 187 dump_hdr->chip_rf = cpu_to_le16(rt2x00dev->chip.rf);
187 dump_hdr->chip_rev = cpu_to_le32(rt2x00dev->chip.rev); 188 dump_hdr->chip_rev = cpu_to_le16(rt2x00dev->chip.rev);
188 dump_hdr->type = cpu_to_le16(type); 189 dump_hdr->type = cpu_to_le16(type);
189 dump_hdr->queue_index = desc->entry->queue->qid; 190 dump_hdr->queue_index = desc->entry->queue->qid;
190 dump_hdr->entry_index = desc->entry->entry_idx; 191 dump_hdr->entry_index = desc->entry->entry_idx;
@@ -573,7 +574,7 @@ static struct dentry *rt2x00debug_create_file_chipset(const char *name,
573 blob->data = data; 574 blob->data = data;
574 data += sprintf(data, "rt chip:\t%04x\n", intf->rt2x00dev->chip.rt); 575 data += sprintf(data, "rt chip:\t%04x\n", intf->rt2x00dev->chip.rt);
575 data += sprintf(data, "rf chip:\t%04x\n", intf->rt2x00dev->chip.rf); 576 data += sprintf(data, "rf chip:\t%04x\n", intf->rt2x00dev->chip.rf);
576 data += sprintf(data, "revision:\t%08x\n", intf->rt2x00dev->chip.rev); 577 data += sprintf(data, "revision:\t%04x\n", intf->rt2x00dev->chip.rev);
577 data += sprintf(data, "\n"); 578 data += sprintf(data, "\n");
578 data += sprintf(data, "register\tbase\twords\twordsize\n"); 579 data += sprintf(data, "register\tbase\twords\twordsize\n");
579 data += sprintf(data, "csr\t%d\t%d\t%d\n", 580 data += sprintf(data, "csr\t%d\t%d\t%d\n",
diff --git a/drivers/net/wireless/rt2x00/rt2x00debug.h b/drivers/net/wireless/rt2x00/rt2x00debug.h
index 035cbc98c593..fa11409cb5c6 100644
--- a/drivers/net/wireless/rt2x00/rt2x00debug.h
+++ b/drivers/net/wireless/rt2x00/rt2x00debug.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
index 73bbec58341e..eda73ba735a6 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dev.c
+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -25,6 +25,7 @@
25 25
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/slab.h>
28 29
29#include "rt2x00.h" 30#include "rt2x00.h"
30#include "rt2x00lib.h" 31#include "rt2x00lib.h"
@@ -205,6 +206,7 @@ void rt2x00lib_txdone(struct queue_entry *entry,
205 enum data_queue_qid qid = skb_get_queue_mapping(entry->skb); 206 enum data_queue_qid qid = skb_get_queue_mapping(entry->skb);
206 unsigned int header_length = ieee80211_get_hdrlen_from_skb(entry->skb); 207 unsigned int header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
207 u8 rate_idx, rate_flags, retry_rates; 208 u8 rate_idx, rate_flags, retry_rates;
209 u8 skbdesc_flags = skbdesc->flags;
208 unsigned int i; 210 unsigned int i;
209 bool success; 211 bool success;
210 212
@@ -287,12 +289,12 @@ void rt2x00lib_txdone(struct queue_entry *entry,
287 } 289 }
288 290
289 /* 291 /*
290 * Only send the status report to mac80211 when TX status was 292 * Only send the status report to mac80211 when it's a frame
291 * requested by it. If this was a extra frame coming through 293 * that originated in mac80211. If this was a extra frame coming
292 * a mac80211 library call (RTS/CTS) then we should not send the 294 * through a mac80211 library call (RTS/CTS) then we should not
293 * status report back. 295 * send the status report back.
294 */ 296 */
295 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) 297 if (!(skbdesc_flags & SKBDESC_NOT_MAC80211))
296 ieee80211_tx_status_irqsafe(rt2x00dev->hw, entry->skb); 298 ieee80211_tx_status_irqsafe(rt2x00dev->hw, entry->skb);
297 else 299 else
298 dev_kfree_skb_irq(entry->skb); 300 dev_kfree_skb_irq(entry->skb);
@@ -384,9 +386,6 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
384 memset(&rxdesc, 0, sizeof(rxdesc)); 386 memset(&rxdesc, 0, sizeof(rxdesc));
385 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc); 387 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
386 388
387 /* Trim buffer to correct size */
388 skb_trim(entry->skb, rxdesc.size);
389
390 /* 389 /*
391 * The data behind the ieee80211 header must be 390 * The data behind the ieee80211 header must be
392 * aligned on a 4 byte boundary. 391 * aligned on a 4 byte boundary.
@@ -396,18 +395,23 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
396 /* 395 /*
397 * Hardware might have stripped the IV/EIV/ICV data, 396 * Hardware might have stripped the IV/EIV/ICV data,
398 * in that case it is possible that the data was 397 * in that case it is possible that the data was
399 * provided seperately (through hardware descriptor) 398 * provided separately (through hardware descriptor)
400 * in which case we should reinsert the data into the frame. 399 * in which case we should reinsert the data into the frame.
401 */ 400 */
402 if ((rxdesc.dev_flags & RXDONE_CRYPTO_IV) && 401 if ((rxdesc.dev_flags & RXDONE_CRYPTO_IV) &&
403 (rxdesc.flags & RX_FLAG_IV_STRIPPED)) 402 (rxdesc.flags & RX_FLAG_IV_STRIPPED))
404 rt2x00crypto_rx_insert_iv(entry->skb, header_length, 403 rt2x00crypto_rx_insert_iv(entry->skb, header_length,
405 &rxdesc); 404 &rxdesc);
406 else if (rxdesc.dev_flags & RXDONE_L2PAD) 405 else if (header_length &&
406 (rxdesc.size > header_length) &&
407 (rxdesc.dev_flags & RXDONE_L2PAD))
407 rt2x00queue_remove_l2pad(entry->skb, header_length); 408 rt2x00queue_remove_l2pad(entry->skb, header_length);
408 else 409 else
409 rt2x00queue_align_payload(entry->skb, header_length); 410 rt2x00queue_align_payload(entry->skb, header_length);
410 411
412 /* Trim buffer to correct size */
413 skb_trim(entry->skb, rxdesc.size);
414
411 /* 415 /*
412 * Check if the frame was received using HT. In that case, 416 * Check if the frame was received using HT. In that case,
413 * the rate is the MCS index and should be passed to mac80211 417 * the rate is the MCS index and should be passed to mac80211
@@ -430,7 +434,6 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
430 434
431 rx_status->mactime = rxdesc.timestamp; 435 rx_status->mactime = rxdesc.timestamp;
432 rx_status->rate_idx = rate_idx; 436 rx_status->rate_idx = rate_idx;
433 rx_status->qual = rt2x00link_calculate_signal(rt2x00dev, rxdesc.rssi);
434 rx_status->signal = rxdesc.rssi; 437 rx_status->signal = rxdesc.rssi;
435 rx_status->noise = rxdesc.noise; 438 rx_status->noise = rxdesc.noise;
436 rx_status->flag = rxdesc.flags; 439 rx_status->flag = rxdesc.flags;
@@ -684,6 +687,21 @@ static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev)
684 rt2x00dev->hw->queues = rt2x00dev->ops->tx_queues; 687 rt2x00dev->hw->queues = rt2x00dev->ops->tx_queues;
685 688
686 /* 689 /*
690 * Initialize extra TX headroom required.
691 */
692 rt2x00dev->hw->extra_tx_headroom =
693 max_t(unsigned int, IEEE80211_TX_STATUS_HEADROOM,
694 rt2x00dev->ops->extra_tx_headroom);
695
696 /*
697 * Take TX headroom required for alignment into account.
698 */
699 if (test_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags))
700 rt2x00dev->hw->extra_tx_headroom += RT2X00_L2PAD_SIZE;
701 else if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags))
702 rt2x00dev->hw->extra_tx_headroom += RT2X00_ALIGN_SIZE;
703
704 /*
687 * Register HW. 705 * Register HW.
688 */ 706 */
689 status = ieee80211_register_hw(rt2x00dev->hw); 707 status = ieee80211_register_hw(rt2x00dev->hw);
diff --git a/drivers/net/wireless/rt2x00/rt2x00dump.h b/drivers/net/wireless/rt2x00/rt2x00dump.h
index fdedb5122928..727019a748e7 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dump.h
+++ b/drivers/net/wireless/rt2x00/rt2x00dump.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/rt2x00/rt2x00firmware.c b/drivers/net/wireless/rt2x00/rt2x00firmware.c
index d2deea2f2679..34beb00c4347 100644
--- a/drivers/net/wireless/rt2x00/rt2x00firmware.c
+++ b/drivers/net/wireless/rt2x00/rt2x00firmware.c
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
3 <http://rt2x00.serialmonkey.com> 4 <http://rt2x00.serialmonkey.com>
4 5
5 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/rt2x00/rt2x00ht.c b/drivers/net/wireless/rt2x00/rt2x00ht.c
index e3cec839e540..1056c92143a8 100644
--- a/drivers/net/wireless/rt2x00/rt2x00ht.c
+++ b/drivers/net/wireless/rt2x00/rt2x00ht.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/rt2x00/rt2x00leds.c b/drivers/net/wireless/rt2x00/rt2x00leds.c
index 49671fed91d7..ca585e34d00e 100644
--- a/drivers/net/wireless/rt2x00/rt2x00leds.c
+++ b/drivers/net/wireless/rt2x00/rt2x00leds.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/rt2x00/rt2x00leds.h b/drivers/net/wireless/rt2x00/rt2x00leds.h
index 1046977e6a12..3b46f0c3332a 100644
--- a/drivers/net/wireless/rt2x00/rt2x00leds.h
+++ b/drivers/net/wireless/rt2x00/rt2x00leds.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -33,8 +33,6 @@ enum led_type {
33 LED_TYPE_QUALITY, 33 LED_TYPE_QUALITY,
34}; 34};
35 35
36#ifdef CONFIG_RT2X00_LIB_LEDS
37
38struct rt2x00_led { 36struct rt2x00_led {
39 struct rt2x00_dev *rt2x00dev; 37 struct rt2x00_dev *rt2x00dev;
40 struct led_classdev led_dev; 38 struct led_classdev led_dev;
@@ -45,6 +43,4 @@ struct rt2x00_led {
45#define LED_REGISTERED ( 1 << 1 ) 43#define LED_REGISTERED ( 1 << 1 )
46}; 44};
47 45
48#endif /* CONFIG_RT2X00_LIB_LEDS */
49
50#endif /* RT2X00LEDS_H */ 46#endif /* RT2X00LEDS_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h
index 567f029a8cda..be2e37fb4071 100644
--- a/drivers/net/wireless/rt2x00/rt2x00lib.h
+++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
3 <http://rt2x00.serialmonkey.com> 4 <http://rt2x00.serialmonkey.com>
4 5
5 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
@@ -161,8 +162,10 @@ void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length);
161 * rt2x00queue_write_tx_frame - Write TX frame to hardware 162 * rt2x00queue_write_tx_frame - Write TX frame to hardware
162 * @queue: Queue over which the frame should be send 163 * @queue: Queue over which the frame should be send
163 * @skb: The skb to send 164 * @skb: The skb to send
165 * @local: frame is not from mac80211
164 */ 166 */
165int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb); 167int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
168 bool local);
166 169
167/** 170/**
168 * rt2x00queue_update_beacon - Send new beacon from mac80211 to hardware 171 * rt2x00queue_update_beacon - Send new beacon from mac80211 to hardware
@@ -223,19 +226,6 @@ void rt2x00link_update_stats(struct rt2x00_dev *rt2x00dev,
223 struct rxdone_entry_desc *rxdesc); 226 struct rxdone_entry_desc *rxdesc);
224 227
225/** 228/**
226 * rt2x00link_calculate_signal - Calculate signal quality
227 * @rt2x00dev: Pointer to &struct rt2x00_dev.
228 * @rssi: RX Frame RSSI
229 *
230 * Calculate the signal quality of a frame based on the rssi
231 * measured during the receiving of the frame and the global
232 * link quality statistics measured since the start of the
233 * link tuning. The result is a value between 0 and 100 which
234 * is an indication of the signal quality.
235 */
236int rt2x00link_calculate_signal(struct rt2x00_dev *rt2x00dev, int rssi);
237
238/**
239 * rt2x00link_start_tuner - Start periodic link tuner work 229 * rt2x00link_start_tuner - Start periodic link tuner work
240 * @rt2x00dev: Pointer to &struct rt2x00_dev. 230 * @rt2x00dev: Pointer to &struct rt2x00_dev.
241 * 231 *
diff --git a/drivers/net/wireless/rt2x00/rt2x00link.c b/drivers/net/wireless/rt2x00/rt2x00link.c
index c708d0be9155..0efbf5a6c254 100644
--- a/drivers/net/wireless/rt2x00/rt2x00link.c
+++ b/drivers/net/wireless/rt2x00/rt2x00link.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -36,24 +36,6 @@
36#define DEFAULT_RSSI -128 36#define DEFAULT_RSSI -128
37 37
38/* 38/*
39 * When no TX/RX percentage could be calculated due to lack of
40 * frames on the air, we fallback to a percentage of 50%.
41 * This will assure we will get at least get some decent value
42 * when the link tuner starts.
43 * The value will be dropped and overwritten with the correct (measured)
44 * value anyway during the first run of the link tuner.
45 */
46#define DEFAULT_PERCENTAGE 50
47
48/*
49 * Small helper macro for percentage calculation
50 * This is a very simple macro with the only catch that it will
51 * produce a default value in case no total value was provided.
52 */
53#define PERCENTAGE(__value, __total) \
54 ( (__total) ? (((__value) * 100) / (__total)) : (DEFAULT_PERCENTAGE) )
55
56/*
57 * Helper struct and macro to work with moving/walking averages. 39 * Helper struct and macro to work with moving/walking averages.
58 * When adding a value to the average value the following calculation 40 * When adding a value to the average value the following calculation
59 * is needed: 41 * is needed:
@@ -91,27 +73,6 @@
91 __new; \ 73 __new; \
92}) 74})
93 75
94/*
95 * For calculating the Signal quality we have determined
96 * the total number of success and failed RX and TX frames.
97 * With the addition of the average RSSI value we can determine
98 * the link quality using the following algorithm:
99 *
100 * rssi_percentage = (avg_rssi * 100) / rssi_offset
101 * rx_percentage = (rx_success * 100) / rx_total
102 * tx_percentage = (tx_success * 100) / tx_total
103 * avg_signal = ((WEIGHT_RSSI * avg_rssi) +
104 * (WEIGHT_TX * tx_percentage) +
105 * (WEIGHT_RX * rx_percentage)) / 100
106 *
107 * This value should then be checked to not be greater then 100.
108 * This means the values of WEIGHT_RSSI, WEIGHT_RX, WEIGHT_TX must
109 * sum up to 100 as well.
110 */
111#define WEIGHT_RSSI 20
112#define WEIGHT_RX 40
113#define WEIGHT_TX 40
114
115static int rt2x00link_antenna_get_link_rssi(struct rt2x00_dev *rt2x00dev) 76static int rt2x00link_antenna_get_link_rssi(struct rt2x00_dev *rt2x00dev)
116{ 77{
117 struct link_ant *ant = &rt2x00dev->link.ant; 78 struct link_ant *ant = &rt2x00dev->link.ant;
@@ -304,46 +265,6 @@ void rt2x00link_update_stats(struct rt2x00_dev *rt2x00dev,
304 ant->rssi_ant = MOVING_AVERAGE(ant->rssi_ant, rxdesc->rssi); 265 ant->rssi_ant = MOVING_AVERAGE(ant->rssi_ant, rxdesc->rssi);
305} 266}
306 267
307static void rt2x00link_precalculate_signal(struct rt2x00_dev *rt2x00dev)
308{
309 struct link *link = &rt2x00dev->link;
310 struct link_qual *qual = &rt2x00dev->link.qual;
311
312 link->rx_percentage =
313 PERCENTAGE(qual->rx_success, qual->rx_failed + qual->rx_success);
314 link->tx_percentage =
315 PERCENTAGE(qual->tx_success, qual->tx_failed + qual->tx_success);
316}
317
318int rt2x00link_calculate_signal(struct rt2x00_dev *rt2x00dev, int rssi)
319{
320 struct link *link = &rt2x00dev->link;
321 int rssi_percentage = 0;
322 int signal;
323
324 /*
325 * We need a positive value for the RSSI.
326 */
327 if (rssi < 0)
328 rssi += rt2x00dev->rssi_offset;
329
330 /*
331 * Calculate the different percentages,
332 * which will be used for the signal.
333 */
334 rssi_percentage = PERCENTAGE(rssi, rt2x00dev->rssi_offset);
335
336 /*
337 * Add the individual percentages and use the WEIGHT
338 * defines to calculate the current link signal.
339 */
340 signal = ((WEIGHT_RSSI * rssi_percentage) +
341 (WEIGHT_TX * link->tx_percentage) +
342 (WEIGHT_RX * link->rx_percentage)) / 100;
343
344 return max_t(int, signal, 100);
345}
346
347void rt2x00link_start_tuner(struct rt2x00_dev *rt2x00dev) 268void rt2x00link_start_tuner(struct rt2x00_dev *rt2x00dev)
348{ 269{
349 struct link *link = &rt2x00dev->link; 270 struct link *link = &rt2x00dev->link;
@@ -357,9 +278,6 @@ void rt2x00link_start_tuner(struct rt2x00_dev *rt2x00dev)
357 if (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count) 278 if (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count)
358 return; 279 return;
359 280
360 link->rx_percentage = DEFAULT_PERCENTAGE;
361 link->tx_percentage = DEFAULT_PERCENTAGE;
362
363 rt2x00link_reset_tuner(rt2x00dev, false); 281 rt2x00link_reset_tuner(rt2x00dev, false);
364 282
365 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags)) 283 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
@@ -448,12 +366,6 @@ static void rt2x00link_tuner(struct work_struct *work)
448 rt2x00dev->ops->lib->link_tuner(rt2x00dev, qual, link->count); 366 rt2x00dev->ops->lib->link_tuner(rt2x00dev, qual, link->count);
449 367
450 /* 368 /*
451 * Precalculate a portion of the link signal which is
452 * in based on the tx/rx success/failure counters.
453 */
454 rt2x00link_precalculate_signal(rt2x00dev);
455
456 /*
457 * Send a signal to the led to update the led signal strength. 369 * Send a signal to the led to update the led signal strength.
458 */ 370 */
459 rt2x00leds_led_quality(rt2x00dev, qual->rssi); 371 rt2x00leds_led_quality(rt2x00dev, qual->rssi);
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c
index 929b85f34f38..abbd857ec759 100644
--- a/drivers/net/wireless/rt2x00/rt2x00mac.c
+++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -66,7 +66,6 @@ static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
66 rts_info = IEEE80211_SKB_CB(skb); 66 rts_info = IEEE80211_SKB_CB(skb);
67 rts_info->control.rates[0].flags &= ~IEEE80211_TX_RC_USE_RTS_CTS; 67 rts_info->control.rates[0].flags &= ~IEEE80211_TX_RC_USE_RTS_CTS;
68 rts_info->control.rates[0].flags &= ~IEEE80211_TX_RC_USE_CTS_PROTECT; 68 rts_info->control.rates[0].flags &= ~IEEE80211_TX_RC_USE_CTS_PROTECT;
69 rts_info->flags &= ~IEEE80211_TX_CTL_REQ_TX_STATUS;
70 69
71 if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) 70 if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
72 rts_info->flags |= IEEE80211_TX_CTL_NO_ACK; 71 rts_info->flags |= IEEE80211_TX_CTL_NO_ACK;
@@ -91,7 +90,7 @@ static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
91 frag_skb->data, data_length, tx_info, 90 frag_skb->data, data_length, tx_info,
92 (struct ieee80211_rts *)(skb->data)); 91 (struct ieee80211_rts *)(skb->data));
93 92
94 retval = rt2x00queue_write_tx_frame(queue, skb); 93 retval = rt2x00queue_write_tx_frame(queue, skb, true);
95 if (retval) { 94 if (retval) {
96 dev_kfree_skb_any(skb); 95 dev_kfree_skb_any(skb);
97 WARNING(rt2x00dev, "Failed to send RTS/CTS frame.\n"); 96 WARNING(rt2x00dev, "Failed to send RTS/CTS frame.\n");
@@ -104,10 +103,8 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
104{ 103{
105 struct rt2x00_dev *rt2x00dev = hw->priv; 104 struct rt2x00_dev *rt2x00dev = hw->priv;
106 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 105 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
107 struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
108 enum data_queue_qid qid = skb_get_queue_mapping(skb); 106 enum data_queue_qid qid = skb_get_queue_mapping(skb);
109 struct data_queue *queue; 107 struct data_queue *queue;
110 u16 frame_control;
111 108
112 /* 109 /*
113 * Mac80211 might be calling this function while we are trying 110 * Mac80211 might be calling this function while we are trying
@@ -142,7 +139,6 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
142 * either RTS or CTS-to-self frame and handles everything 139 * either RTS or CTS-to-self frame and handles everything
143 * inside the hardware. 140 * inside the hardware.
144 */ 141 */
145 frame_control = le16_to_cpu(ieee80211hdr->frame_control);
146 if ((tx_info->control.rates[0].flags & (IEEE80211_TX_RC_USE_RTS_CTS | 142 if ((tx_info->control.rates[0].flags & (IEEE80211_TX_RC_USE_RTS_CTS |
147 IEEE80211_TX_RC_USE_CTS_PROTECT)) && 143 IEEE80211_TX_RC_USE_CTS_PROTECT)) &&
148 !rt2x00dev->ops->hw->set_rts_threshold) { 144 !rt2x00dev->ops->hw->set_rts_threshold) {
@@ -153,7 +149,7 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
153 goto exit_fail; 149 goto exit_fail;
154 } 150 }
155 151
156 if (rt2x00queue_write_tx_frame(queue, skb)) 152 if (rt2x00queue_write_tx_frame(queue, skb, false))
157 goto exit_fail; 153 goto exit_fail;
158 154
159 if (rt2x00queue_threshold(queue)) 155 if (rt2x00queue_threshold(queue))
@@ -191,10 +187,10 @@ void rt2x00mac_stop(struct ieee80211_hw *hw)
191EXPORT_SYMBOL_GPL(rt2x00mac_stop); 187EXPORT_SYMBOL_GPL(rt2x00mac_stop);
192 188
193int rt2x00mac_add_interface(struct ieee80211_hw *hw, 189int rt2x00mac_add_interface(struct ieee80211_hw *hw,
194 struct ieee80211_if_init_conf *conf) 190 struct ieee80211_vif *vif)
195{ 191{
196 struct rt2x00_dev *rt2x00dev = hw->priv; 192 struct rt2x00_dev *rt2x00dev = hw->priv;
197 struct rt2x00_intf *intf = vif_to_intf(conf->vif); 193 struct rt2x00_intf *intf = vif_to_intf(vif);
198 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); 194 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
199 struct queue_entry *entry = NULL; 195 struct queue_entry *entry = NULL;
200 unsigned int i; 196 unsigned int i;
@@ -207,7 +203,7 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
207 !test_bit(DEVICE_STATE_STARTED, &rt2x00dev->flags)) 203 !test_bit(DEVICE_STATE_STARTED, &rt2x00dev->flags))
208 return -ENODEV; 204 return -ENODEV;
209 205
210 switch (conf->type) { 206 switch (vif->type) {
211 case NL80211_IFTYPE_AP: 207 case NL80211_IFTYPE_AP:
212 /* 208 /*
213 * We don't support mixed combinations of 209 * We don't support mixed combinations of
@@ -267,7 +263,7 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
267 * increase interface count and start initialization. 263 * increase interface count and start initialization.
268 */ 264 */
269 265
270 if (conf->type == NL80211_IFTYPE_AP) 266 if (vif->type == NL80211_IFTYPE_AP)
271 rt2x00dev->intf_ap_count++; 267 rt2x00dev->intf_ap_count++;
272 else 268 else
273 rt2x00dev->intf_sta_count++; 269 rt2x00dev->intf_sta_count++;
@@ -277,16 +273,16 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
277 mutex_init(&intf->beacon_skb_mutex); 273 mutex_init(&intf->beacon_skb_mutex);
278 intf->beacon = entry; 274 intf->beacon = entry;
279 275
280 if (conf->type == NL80211_IFTYPE_AP) 276 if (vif->type == NL80211_IFTYPE_AP)
281 memcpy(&intf->bssid, conf->mac_addr, ETH_ALEN); 277 memcpy(&intf->bssid, vif->addr, ETH_ALEN);
282 memcpy(&intf->mac, conf->mac_addr, ETH_ALEN); 278 memcpy(&intf->mac, vif->addr, ETH_ALEN);
283 279
284 /* 280 /*
285 * The MAC adddress must be configured after the device 281 * The MAC adddress must be configured after the device
286 * has been initialized. Otherwise the device can reset 282 * has been initialized. Otherwise the device can reset
287 * the MAC registers. 283 * the MAC registers.
288 */ 284 */
289 rt2x00lib_config_intf(rt2x00dev, intf, conf->type, intf->mac, NULL); 285 rt2x00lib_config_intf(rt2x00dev, intf, vif->type, intf->mac, NULL);
290 286
291 /* 287 /*
292 * Some filters depend on the current working mode. We can force 288 * Some filters depend on the current working mode. We can force
@@ -300,10 +296,10 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
300EXPORT_SYMBOL_GPL(rt2x00mac_add_interface); 296EXPORT_SYMBOL_GPL(rt2x00mac_add_interface);
301 297
302void rt2x00mac_remove_interface(struct ieee80211_hw *hw, 298void rt2x00mac_remove_interface(struct ieee80211_hw *hw,
303 struct ieee80211_if_init_conf *conf) 299 struct ieee80211_vif *vif)
304{ 300{
305 struct rt2x00_dev *rt2x00dev = hw->priv; 301 struct rt2x00_dev *rt2x00dev = hw->priv;
306 struct rt2x00_intf *intf = vif_to_intf(conf->vif); 302 struct rt2x00_intf *intf = vif_to_intf(vif);
307 303
308 /* 304 /*
309 * Don't allow interfaces to be remove while 305 * Don't allow interfaces to be remove while
@@ -311,11 +307,11 @@ void rt2x00mac_remove_interface(struct ieee80211_hw *hw,
311 * no interface is present. 307 * no interface is present.
312 */ 308 */
313 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) || 309 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) ||
314 (conf->type == NL80211_IFTYPE_AP && !rt2x00dev->intf_ap_count) || 310 (vif->type == NL80211_IFTYPE_AP && !rt2x00dev->intf_ap_count) ||
315 (conf->type != NL80211_IFTYPE_AP && !rt2x00dev->intf_sta_count)) 311 (vif->type != NL80211_IFTYPE_AP && !rt2x00dev->intf_sta_count))
316 return; 312 return;
317 313
318 if (conf->type == NL80211_IFTYPE_AP) 314 if (vif->type == NL80211_IFTYPE_AP)
319 rt2x00dev->intf_ap_count--; 315 rt2x00dev->intf_ap_count--;
320 else 316 else
321 rt2x00dev->intf_sta_count--; 317 rt2x00dev->intf_sta_count--;
@@ -559,22 +555,6 @@ int rt2x00mac_get_stats(struct ieee80211_hw *hw,
559} 555}
560EXPORT_SYMBOL_GPL(rt2x00mac_get_stats); 556EXPORT_SYMBOL_GPL(rt2x00mac_get_stats);
561 557
562int rt2x00mac_get_tx_stats(struct ieee80211_hw *hw,
563 struct ieee80211_tx_queue_stats *stats)
564{
565 struct rt2x00_dev *rt2x00dev = hw->priv;
566 unsigned int i;
567
568 for (i = 0; i < rt2x00dev->ops->tx_queues; i++) {
569 stats[i].len = rt2x00dev->tx[i].length;
570 stats[i].limit = rt2x00dev->tx[i].limit;
571 stats[i].count = rt2x00dev->tx[i].count;
572 }
573
574 return 0;
575}
576EXPORT_SYMBOL_GPL(rt2x00mac_get_tx_stats);
577
578void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw, 558void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
579 struct ieee80211_vif *vif, 559 struct ieee80211_vif *vif,
580 struct ieee80211_bss_conf *bss_conf, 560 struct ieee80211_bss_conf *bss_conf,
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index cdd5154bd4c0..cf3f1c0c4382 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -27,6 +27,7 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/pci.h> 29#include <linux/pci.h>
30#include <linux/slab.h>
30 31
31#include "rt2x00.h" 32#include "rt2x00.h"
32#include "rt2x00pci.h" 33#include "rt2x00pci.h"
@@ -41,6 +42,9 @@ int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
41{ 42{
42 unsigned int i; 43 unsigned int i;
43 44
45 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
46 return 0;
47
44 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 48 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
45 rt2x00pci_register_read(rt2x00dev, offset, reg); 49 rt2x00pci_register_read(rt2x00dev, offset, reg);
46 if (!rt2x00_get_field32(*reg, field)) 50 if (!rt2x00_get_field32(*reg, field))
@@ -269,7 +273,6 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
269 struct ieee80211_hw *hw; 273 struct ieee80211_hw *hw;
270 struct rt2x00_dev *rt2x00dev; 274 struct rt2x00_dev *rt2x00dev;
271 int retval; 275 int retval;
272 u16 chip;
273 276
274 retval = pci_request_regions(pci_dev, pci_name(pci_dev)); 277 retval = pci_request_regions(pci_dev, pci_name(pci_dev));
275 if (retval) { 278 if (retval) {
@@ -310,11 +313,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
310 rt2x00dev->irq = pci_dev->irq; 313 rt2x00dev->irq = pci_dev->irq;
311 rt2x00dev->name = pci_name(pci_dev); 314 rt2x00dev->name = pci_name(pci_dev);
312 315
313 /* 316 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
314 * Determine RT chipset by reading PCI header.
315 */
316 pci_read_config_word(pci_dev, PCI_DEVICE_ID, &chip);
317 rt2x00_set_chip_rt(rt2x00dev, chip);
318 317
319 retval = rt2x00pci_alloc_reg(rt2x00dev); 318 retval = rt2x00pci_alloc_reg(rt2x00dev);
320 if (retval) 319 if (retval)
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index 15a12487e04b..8149ff68410a 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -27,6 +27,7 @@
27#define RT2X00PCI_H 27#define RT2X00PCI_H
28 28
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/pci.h>
30 31
31/* 32/*
32 * This variable should be used with the 33 * This variable should be used with the
@@ -35,15 +36,6 @@
35#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops) 36#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops)
36 37
37/* 38/*
38 * Register defines.
39 * Some registers require multiple attempts before success,
40 * in those cases REGISTER_BUSY_COUNT attempts should be
41 * taken with a REGISTER_BUSY_DELAY interval.
42 */
43#define REGISTER_BUSY_COUNT 5
44#define REGISTER_BUSY_DELAY 100
45
46/*
47 * Register access. 39 * Register access.
48 */ 40 */
49static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev, 41static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev,
@@ -53,10 +45,9 @@ static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev,
53 *value = readl(rt2x00dev->csr.base + offset); 45 *value = readl(rt2x00dev->csr.base + offset);
54} 46}
55 47
56static inline void 48static inline void rt2x00pci_register_multiread(struct rt2x00_dev *rt2x00dev,
57rt2x00pci_register_multiread(struct rt2x00_dev *rt2x00dev, 49 const unsigned int offset,
58 const unsigned int offset, 50 void *value, const u32 length)
59 void *value, const u16 length)
60{ 51{
61 memcpy_fromio(value, rt2x00dev->csr.base + offset, length); 52 memcpy_fromio(value, rt2x00dev->csr.base + offset, length);
62} 53}
@@ -68,10 +59,10 @@ static inline void rt2x00pci_register_write(struct rt2x00_dev *rt2x00dev,
68 writel(value, rt2x00dev->csr.base + offset); 59 writel(value, rt2x00dev->csr.base + offset);
69} 60}
70 61
71static inline void 62static inline void rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,
72rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev, 63 const unsigned int offset,
73 const unsigned int offset, 64 const void *value,
74 const void *value, const u16 length) 65 const u32 length)
75{ 66{
76 memcpy_toio(rt2x00dev->csr.base + offset, value, length); 67 memcpy_toio(rt2x00dev->csr.base + offset, value, length);
77} 68}
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index 577029efe320..a0bd36fc4d2e 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -1,5 +1,6 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
3 <http://rt2x00.serialmonkey.com> 4 <http://rt2x00.serialmonkey.com>
4 5
5 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
@@ -23,6 +24,7 @@
23 Abstract: rt2x00 queue specific routines. 24 Abstract: rt2x00 queue specific routines.
24 */ 25 */
25 26
27#include <linux/slab.h>
26#include <linux/kernel.h> 28#include <linux/kernel.h>
27#include <linux/module.h> 29#include <linux/module.h>
28#include <linux/dma-mapping.h> 30#include <linux/dma-mapping.h>
@@ -103,7 +105,7 @@ void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
103 * is also mapped to the DMA so it can be used for transfering 105 * is also mapped to the DMA so it can be used for transfering
104 * additional descriptor information to the hardware. 106 * additional descriptor information to the hardware.
105 */ 107 */
106 skb_push(skb, rt2x00dev->hw->extra_tx_headroom); 108 skb_push(skb, rt2x00dev->ops->extra_tx_headroom);
107 109
108 skbdesc->skb_dma = 110 skbdesc->skb_dma =
109 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE); 111 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
@@ -111,7 +113,7 @@ void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
111 /* 113 /*
112 * Restore data pointer to original location again. 114 * Restore data pointer to original location again.
113 */ 115 */
114 skb_pull(skb, rt2x00dev->hw->extra_tx_headroom); 116 skb_pull(skb, rt2x00dev->ops->extra_tx_headroom);
115 117
116 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX; 118 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
117} 119}
@@ -133,7 +135,7 @@ void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
133 * by the driver, but it was actually mapped to DMA. 135 * by the driver, but it was actually mapped to DMA.
134 */ 136 */
135 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, 137 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
136 skb->len + rt2x00dev->hw->extra_tx_headroom, 138 skb->len + rt2x00dev->ops->extra_tx_headroom,
137 DMA_TO_DEVICE); 139 DMA_TO_DEVICE);
138 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX; 140 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
139 } 141 }
@@ -161,10 +163,10 @@ void rt2x00queue_align_frame(struct sk_buff *skb)
161 skb_trim(skb, frame_length); 163 skb_trim(skb, frame_length);
162} 164}
163 165
164void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_lengt) 166void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_length)
165{ 167{
166 unsigned int frame_length = skb->len; 168 unsigned int frame_length = skb->len;
167 unsigned int align = ALIGN_SIZE(skb, header_lengt); 169 unsigned int align = ALIGN_SIZE(skb, header_length);
168 170
169 if (!align) 171 if (!align)
170 return; 172 return;
@@ -176,55 +178,45 @@ void rt2x00queue_align_payload(struct sk_buff *skb, unsigned int header_lengt)
176 178
177void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length) 179void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
178{ 180{
179 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 181 unsigned int payload_length = skb->len - header_length;
180 unsigned int frame_length = skb->len;
181 unsigned int header_align = ALIGN_SIZE(skb, 0); 182 unsigned int header_align = ALIGN_SIZE(skb, 0);
182 unsigned int payload_align = ALIGN_SIZE(skb, header_length); 183 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
183 unsigned int l2pad = 4 - (payload_align - header_align); 184 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
184 185
185 if (header_align == payload_align) { 186 /*
186 /* 187 * Adjust the header alignment if the payload needs to be moved more
187 * Both header and payload must be moved the same 188 * than the header.
188 * amount of bytes to align them properly. This means 189 */
189 * we don't use the L2 padding but just move the entire 190 if (payload_align > header_align)
190 * frame. 191 header_align += 4;
191 */
192 rt2x00queue_align_frame(skb);
193 } else if (!payload_align) {
194 /*
195 * Simple L2 padding, only the header needs to be moved,
196 * the payload is already properly aligned.
197 */
198 skb_push(skb, header_align);
199 memmove(skb->data, skb->data + header_align, frame_length);
200 skbdesc->flags |= SKBDESC_L2_PADDED;
201 } else {
202 /*
203 *
204 * Complicated L2 padding, both header and payload need
205 * to be moved. By default we only move to the start
206 * of the buffer, so our header alignment needs to be
207 * increased if there is not enough room for the header
208 * to be moved.
209 */
210 if (payload_align > header_align)
211 header_align += 4;
212 192
213 skb_push(skb, header_align); 193 /* There is nothing to do if no alignment is needed */
214 memmove(skb->data, skb->data + header_align, header_length); 194 if (!header_align)
195 return;
196
197 /* Reserve the amount of space needed in front of the frame */
198 skb_push(skb, header_align);
199
200 /*
201 * Move the header.
202 */
203 memmove(skb->data, skb->data + header_align, header_length);
204
205 /* Move the payload, if present and if required */
206 if (payload_length && payload_align)
215 memmove(skb->data + header_length + l2pad, 207 memmove(skb->data + header_length + l2pad,
216 skb->data + header_length + l2pad + header_align, 208 skb->data + header_length + l2pad + payload_align,
217 frame_length - header_length); 209 payload_length);
218 skbdesc->flags |= SKBDESC_L2_PADDED; 210
219 } 211 /* Trim the skb to the correct size */
212 skb_trim(skb, header_length + l2pad + payload_length);
220} 213}
221 214
222void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length) 215void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
223{ 216{
224 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 217 unsigned int l2pad = L2PAD_SIZE(header_length);
225 unsigned int l2pad = 4 - (header_length & 3);
226 218
227 if (!l2pad || (skbdesc->flags & SKBDESC_L2_PADDED)) 219 if (!l2pad)
228 return; 220 return;
229 221
230 memmove(skb->data + l2pad, skb->data, header_length); 222 memmove(skb->data + l2pad, skb->data, header_length);
@@ -345,7 +337,9 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
345 * Header and alignment information. 337 * Header and alignment information.
346 */ 338 */
347 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb); 339 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
348 txdesc->l2pad = ALIGN_SIZE(entry->skb, txdesc->header_length); 340 if (test_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags) &&
341 (entry->skb->len > txdesc->header_length))
342 txdesc->l2pad = L2PAD_SIZE(txdesc->header_length);
349 343
350 /* 344 /*
351 * Check whether this frame is to be acked. 345 * Check whether this frame is to be acked.
@@ -386,10 +380,13 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
386 380
387 /* 381 /*
388 * Beacons and probe responses require the tsf timestamp 382 * Beacons and probe responses require the tsf timestamp
389 * to be inserted into the frame. 383 * to be inserted into the frame, except for a frame that has been injected
384 * through a monitor interface. This latter is needed for testing a
385 * monitor interface.
390 */ 386 */
391 if (ieee80211_is_beacon(hdr->frame_control) || 387 if ((ieee80211_is_beacon(hdr->frame_control) ||
392 ieee80211_is_probe_resp(hdr->frame_control)) 388 ieee80211_is_probe_resp(hdr->frame_control)) &&
389 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
393 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); 390 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
394 391
395 /* 392 /*
@@ -453,7 +450,8 @@ static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
453 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid); 450 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
454} 451}
455 452
456int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb) 453int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
454 bool local)
457{ 455{
458 struct ieee80211_tx_info *tx_info; 456 struct ieee80211_tx_info *tx_info;
459 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX); 457 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
@@ -494,10 +492,13 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
494 skbdesc->tx_rate_idx = rate_idx; 492 skbdesc->tx_rate_idx = rate_idx;
495 skbdesc->tx_rate_flags = rate_flags; 493 skbdesc->tx_rate_flags = rate_flags;
496 494
495 if (local)
496 skbdesc->flags |= SKBDESC_NOT_MAC80211;
497
497 /* 498 /*
498 * When hardware encryption is supported, and this frame 499 * When hardware encryption is supported, and this frame
499 * is to be encrypted, we should strip the IV/EIV data from 500 * is to be encrypted, we should strip the IV/EIV data from
500 * the frame so we can provide it to the driver seperately. 501 * the frame so we can provide it to the driver separately.
501 */ 502 */
502 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && 503 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
503 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { 504 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index a5591fb2b191..c1e482bb37b3 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -92,14 +92,14 @@ enum data_queue_qid {
92 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX 92 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX
93 * @SKBDESC_IV_STRIPPED: Frame contained a IV/EIV provided by 93 * @SKBDESC_IV_STRIPPED: Frame contained a IV/EIV provided by
94 * mac80211 but was stripped for processing by the driver. 94 * mac80211 but was stripped for processing by the driver.
95 * @SKBDESC_L2_PADDED: Payload has been padded for 4-byte alignment, 95 * @SKBDESC_NOT_MAC80211: Frame didn't originate from mac80211,
96 * the padded bytes are located between header and payload. 96 * don't try to pass it back.
97 */ 97 */
98enum skb_frame_desc_flags { 98enum skb_frame_desc_flags {
99 SKBDESC_DMA_MAPPED_RX = 1 << 0, 99 SKBDESC_DMA_MAPPED_RX = 1 << 0,
100 SKBDESC_DMA_MAPPED_TX = 1 << 1, 100 SKBDESC_DMA_MAPPED_TX = 1 << 1,
101 SKBDESC_IV_STRIPPED = 1 << 2, 101 SKBDESC_IV_STRIPPED = 1 << 2,
102 SKBDESC_L2_PADDED = 1 << 3 102 SKBDESC_NOT_MAC80211 = 1 << 3,
103}; 103};
104 104
105/** 105/**
diff --git a/drivers/net/wireless/rt2x00/rt2x00reg.h b/drivers/net/wireless/rt2x00/rt2x00reg.h
index 983e52e127a7..603bfc0adaa3 100644
--- a/drivers/net/wireless/rt2x00/rt2x00reg.h
+++ b/drivers/net/wireless/rt2x00/rt2x00reg.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
diff --git a/drivers/net/wireless/rt2x00/rt2x00soc.c b/drivers/net/wireless/rt2x00/rt2x00soc.c
new file mode 100644
index 000000000000..fc98063de71d
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2x00soc.c
@@ -0,0 +1,160 @@
1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2004 - 2009 Felix Fietkau <nbd@openwrt.org>
4 <http://rt2x00.serialmonkey.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the
18 Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22/*
23 Module: rt2x00soc
24 Abstract: rt2x00 generic soc device routines.
25 */
26
27#include <linux/bug.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/platform_device.h>
31#include <linux/slab.h>
32
33#include "rt2x00.h"
34#include "rt2x00soc.h"
35
36static void rt2x00soc_free_reg(struct rt2x00_dev *rt2x00dev)
37{
38 kfree(rt2x00dev->rf);
39 rt2x00dev->rf = NULL;
40
41 kfree(rt2x00dev->eeprom);
42 rt2x00dev->eeprom = NULL;
43}
44
45static int rt2x00soc_alloc_reg(struct rt2x00_dev *rt2x00dev)
46{
47 struct platform_device *pdev = to_platform_device(rt2x00dev->dev);
48 struct resource *res;
49
50 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
51 if (!res)
52 return -ENODEV;
53
54 rt2x00dev->csr.base = (void __iomem *)KSEG1ADDR(res->start);
55 if (!rt2x00dev->csr.base)
56 goto exit;
57
58 rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
59 if (!rt2x00dev->eeprom)
60 goto exit;
61
62 rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
63 if (!rt2x00dev->rf)
64 goto exit;
65
66 return 0;
67
68exit:
69 ERROR_PROBE("Failed to allocate registers.\n");
70 rt2x00soc_free_reg(rt2x00dev);
71
72 return -ENOMEM;
73}
74
75int rt2x00soc_probe(struct platform_device *pdev, const struct rt2x00_ops *ops)
76{
77 struct ieee80211_hw *hw;
78 struct rt2x00_dev *rt2x00dev;
79 int retval;
80
81 hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
82 if (!hw) {
83 ERROR_PROBE("Failed to allocate hardware.\n");
84 return -ENOMEM;
85 }
86
87 platform_set_drvdata(pdev, hw);
88
89 rt2x00dev = hw->priv;
90 rt2x00dev->dev = &pdev->dev;
91 rt2x00dev->ops = ops;
92 rt2x00dev->hw = hw;
93 rt2x00dev->irq = platform_get_irq(pdev, 0);
94 rt2x00dev->name = pdev->dev.driver->name;
95
96 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_SOC);
97
98 retval = rt2x00soc_alloc_reg(rt2x00dev);
99 if (retval)
100 goto exit_free_device;
101
102 retval = rt2x00lib_probe_dev(rt2x00dev);
103 if (retval)
104 goto exit_free_reg;
105
106 return 0;
107
108exit_free_reg:
109 rt2x00soc_free_reg(rt2x00dev);
110
111exit_free_device:
112 ieee80211_free_hw(hw);
113
114 return retval;
115}
116EXPORT_SYMBOL_GPL(rt2x00soc_probe);
117
118int rt2x00soc_remove(struct platform_device *pdev)
119{
120 struct ieee80211_hw *hw = platform_get_drvdata(pdev);
121 struct rt2x00_dev *rt2x00dev = hw->priv;
122
123 /*
124 * Free all allocated data.
125 */
126 rt2x00lib_remove_dev(rt2x00dev);
127 rt2x00soc_free_reg(rt2x00dev);
128 ieee80211_free_hw(hw);
129
130 return 0;
131}
132EXPORT_SYMBOL_GPL(rt2x00soc_remove);
133
134#ifdef CONFIG_PM
135int rt2x00soc_suspend(struct platform_device *pdev, pm_message_t state)
136{
137 struct ieee80211_hw *hw = platform_get_drvdata(pdev);
138 struct rt2x00_dev *rt2x00dev = hw->priv;
139
140 return rt2x00lib_suspend(rt2x00dev, state);
141}
142EXPORT_SYMBOL_GPL(rt2x00soc_suspend);
143
144int rt2x00soc_resume(struct platform_device *pdev)
145{
146 struct ieee80211_hw *hw = platform_get_drvdata(pdev);
147 struct rt2x00_dev *rt2x00dev = hw->priv;
148
149 return rt2x00lib_resume(rt2x00dev);
150}
151EXPORT_SYMBOL_GPL(rt2x00soc_resume);
152#endif /* CONFIG_PM */
153
154/*
155 * rt2x00soc module information.
156 */
157MODULE_AUTHOR(DRV_PROJECT);
158MODULE_VERSION(DRV_VERSION);
159MODULE_DESCRIPTION("rt2x00 soc library");
160MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/rt2x00/rt2x00soc.h b/drivers/net/wireless/rt2x00/rt2x00soc.h
new file mode 100644
index 000000000000..474cbfc1efc7
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2x00soc.h
@@ -0,0 +1,42 @@
1/*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00soc
23 Abstract: Data structures for the rt2x00soc module.
24 */
25
26#ifndef RT2X00SOC_H
27#define RT2X00SOC_H
28
29/*
30 * SoC driver handlers.
31 */
32int rt2x00soc_probe(struct platform_device *pdev, const struct rt2x00_ops *ops);
33int rt2x00soc_remove(struct platform_device *pdev);
34#ifdef CONFIG_PM
35int rt2x00soc_suspend(struct platform_device *pdev, pm_message_t state);
36int rt2x00soc_resume(struct platform_device *pdev);
37#else
38#define rt2x00soc_suspend NULL
39#define rt2x00soc_resume NULL
40#endif /* CONFIG_PM */
41
42#endif /* RT2X00SOC_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index f02b48a90593..f9a7f8b17411 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -25,6 +25,7 @@
25 25
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/slab.h>
28#include <linux/usb.h> 29#include <linux/usb.h>
29#include <linux/bug.h> 30#include <linux/bug.h>
30 31
@@ -160,7 +161,7 @@ EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request_large_buff);
160 161
161int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev, 162int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
162 const unsigned int offset, 163 const unsigned int offset,
163 struct rt2x00_field32 field, 164 const struct rt2x00_field32 field,
164 u32 *reg) 165 u32 *reg)
165{ 166{
166 unsigned int i; 167 unsigned int i;
@@ -653,6 +654,8 @@ int rt2x00usb_probe(struct usb_interface *usb_intf,
653 rt2x00dev->ops = ops; 654 rt2x00dev->ops = ops;
654 rt2x00dev->hw = hw; 655 rt2x00dev->hw = hw;
655 656
657 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_USB);
658
656 retval = rt2x00usb_alloc_reg(rt2x00dev); 659 retval = rt2x00usb_alloc_reg(rt2x00dev);
657 if (retval) 660 if (retval)
658 goto exit_free_device; 661 goto exit_free_device;
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h
index bd2d59c85f1b..3da6841b5d42 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.h
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -26,6 +26,8 @@
26#ifndef RT2X00USB_H 26#ifndef RT2X00USB_H
27#define RT2X00USB_H 27#define RT2X00USB_H
28 28
29#include <linux/usb.h>
30
29#define to_usb_device_intf(d) \ 31#define to_usb_device_intf(d) \
30({ \ 32({ \
31 struct usb_interface *intf = to_usb_interface(d); \ 33 struct usb_interface *intf = to_usb_interface(d); \
@@ -39,17 +41,11 @@
39#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops) 41#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops)
40 42
41/* 43/*
42 * Register defines.
43 * Some registers require multiple attempts before success,
44 * in those cases REGISTER_BUSY_COUNT attempts should be
45 * taken with a REGISTER_BUSY_DELAY interval.
46 * For USB vendor requests we need to pass a timeout 44 * For USB vendor requests we need to pass a timeout
47 * time in ms, for this we use the REGISTER_TIMEOUT, 45 * time in ms, for this we use the REGISTER_TIMEOUT,
48 * however when loading firmware a higher value is 46 * however when loading firmware a higher value is
49 * required. In that case we use the REGISTER_TIMEOUT_FIRMWARE. 47 * required. In that case we use the REGISTER_TIMEOUT_FIRMWARE.
50 */ 48 */
51#define REGISTER_BUSY_COUNT 5
52#define REGISTER_BUSY_DELAY 100
53#define REGISTER_TIMEOUT 500 49#define REGISTER_TIMEOUT 500
54#define REGISTER_TIMEOUT_FIRMWARE 1000 50#define REGISTER_TIMEOUT_FIRMWARE 1000
55 51
@@ -232,7 +228,7 @@ static inline int rt2x00usb_eeprom_read(struct rt2x00_dev *rt2x00dev,
232} 228}
233 229
234/** 230/**
235 * rt2x00usb_regbusy_read - Read 32bit register word 231 * rt2x00usb_register_read - Read 32bit register word
236 * @rt2x00dev: Device pointer, see &struct rt2x00_dev. 232 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
237 * @offset: Register offset 233 * @offset: Register offset
238 * @value: Pointer to where register contents should be stored 234 * @value: Pointer to where register contents should be stored
@@ -340,12 +336,13 @@ static inline void rt2x00usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
340 * through rt2x00usb_vendor_request_buff(). 336 * through rt2x00usb_vendor_request_buff().
341 */ 337 */
342static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev, 338static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
343 const unsigned int offset, 339 const unsigned int offset,
344 void *value, const u32 length) 340 const void *value,
341 const u32 length)
345{ 342{
346 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE, 343 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
347 USB_VENDOR_REQUEST_OUT, offset, 344 USB_VENDOR_REQUEST_OUT, offset,
348 value, length, 345 (void *)value, length,
349 REGISTER_TIMEOUT32(length)); 346 REGISTER_TIMEOUT32(length));
350} 347}
351 348
@@ -364,7 +361,7 @@ static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
364 */ 361 */
365int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev, 362int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
366 const unsigned int offset, 363 const unsigned int offset,
367 struct rt2x00_field32 field, 364 const struct rt2x00_field32 field,
368 u32 *reg); 365 u32 *reg);
369 366
370/* 367/*
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index b20e3eac9d67..432e75f960b7 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -30,6 +30,7 @@
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/module.h> 32#include <linux/module.h>
33#include <linux/slab.h>
33#include <linux/pci.h> 34#include <linux/pci.h>
34#include <linux/eeprom_93cx6.h> 35#include <linux/eeprom_93cx6.h>
35 36
@@ -51,7 +52,7 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
51 * These indirect registers work with busy bits, 52 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access 53 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay 54 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time, 55 * between each attempt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed, 56 * the access attempt is considered to have failed,
56 * and we will print an error. 57 * and we will print an error.
57 */ 58 */
@@ -386,7 +387,7 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
386 * The driver does not support the IV/EIV generation 387 * The driver does not support the IV/EIV generation
387 * in hardware. However it doesn't support the IV/EIV 388 * in hardware. However it doesn't support the IV/EIV
388 * inside the ieee80211 frame either, but requires it 389 * inside the ieee80211 frame either, but requires it
389 * to be provided seperately for the descriptor. 390 * to be provided separately for the descriptor.
390 * rt2x00lib will cut the IV/EIV data out of all frames 391 * rt2x00lib will cut the IV/EIV data out of all frames
391 * given to us by mac80211, but we must tell mac80211 392 * given to us by mac80211, but we must tell mac80211
392 * to generate the IV/EIV data. 393 * to generate the IV/EIV data.
@@ -397,7 +398,7 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
397 /* 398 /*
398 * SEC_CSR0 contains only single-bit fields to indicate 399 * SEC_CSR0 contains only single-bit fields to indicate
399 * a particular key is valid. Because using the FIELD32() 400 * a particular key is valid. Because using the FIELD32()
400 * defines directly will cause a lot of overhead we use 401 * defines directly will cause a lot of overhead, we use
401 * a calculation to determine the correct bit directly. 402 * a calculation to determine the correct bit directly.
402 */ 403 */
403 mask = 1 << key->hw_key_idx; 404 mask = 1 << key->hw_key_idx;
@@ -425,11 +426,11 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
425 /* 426 /*
426 * rt2x00lib can't determine the correct free 427 * rt2x00lib can't determine the correct free
427 * key_idx for pairwise keys. We have 2 registers 428 * key_idx for pairwise keys. We have 2 registers
428 * with key valid bits. The goal is simple, read 429 * with key valid bits. The goal is simple: read
429 * the first register, if that is full move to 430 * the first register. If that is full, move to
430 * the next register. 431 * the next register.
431 * When both registers are full, we drop the key, 432 * When both registers are full, we drop the key.
432 * otherwise we use the first invalid entry. 433 * Otherwise, we use the first invalid entry.
433 */ 434 */
434 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg); 435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
435 if (reg && reg == ~0) { 436 if (reg && reg == ~0) {
@@ -464,8 +465,8 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
464 &addr_entry, sizeof(addr_entry)); 465 &addr_entry, sizeof(addr_entry));
465 466
466 /* 467 /*
467 * Enable pairwise lookup table for given BSS idx, 468 * Enable pairwise lookup table for given BSS idx.
468 * without this received frames will not be decrypted 469 * Without this, received frames will not be decrypted
469 * by the hardware. 470 * by the hardware.
470 */ 471 */
471 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg); 472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
@@ -476,7 +477,7 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
476 * The driver does not support the IV/EIV generation 477 * The driver does not support the IV/EIV generation
477 * in hardware. However it doesn't support the IV/EIV 478 * in hardware. However it doesn't support the IV/EIV
478 * inside the ieee80211 frame either, but requires it 479 * inside the ieee80211 frame either, but requires it
479 * to be provided seperately for the descriptor. 480 * to be provided separately for the descriptor.
480 * rt2x00lib will cut the IV/EIV data out of all frames 481 * rt2x00lib will cut the IV/EIV data out of all frames
481 * given to us by mac80211, but we must tell mac80211 482 * given to us by mac80211, but we must tell mac80211
482 * to generate the IV/EIV data. 483 * to generate the IV/EIV data.
@@ -487,7 +488,7 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
487 /* 488 /*
488 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate 489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
489 * a particular key is valid. Because using the FIELD32() 490 * a particular key is valid. Because using the FIELD32()
490 * defines directly will cause a lot of overhead we use 491 * defines directly will cause a lot of overhead, we use
491 * a calculation to determine the correct bit directly. 492 * a calculation to determine the correct bit directly.
492 */ 493 */
493 if (key->hw_key_idx < 32) { 494 if (key->hw_key_idx < 32) {
@@ -556,7 +557,7 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
556 if (flags & CONFIG_UPDATE_TYPE) { 557 if (flags & CONFIG_UPDATE_TYPE) {
557 /* 558 /*
558 * Clear current synchronisation setup. 559 * Clear current synchronisation setup.
559 * For the Beacon base registers we only need to clear 560 * For the Beacon base registers, we only need to clear
560 * the first byte since that byte contains the VALID and OWNER 561 * the first byte since that byte contains the VALID and OWNER
561 * bits which (when set to 0) will invalidate the entire beacon. 562 * bits which (when set to 0) will invalidate the entire beacon.
562 */ 563 */
@@ -637,8 +638,7 @@ static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
637 rt61pci_bbp_read(rt2x00dev, 4, &r4); 638 rt61pci_bbp_read(rt2x00dev, 4, &r4);
638 rt61pci_bbp_read(rt2x00dev, 77, &r77); 639 rt61pci_bbp_read(rt2x00dev, 77, &r77);
639 640
640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 641 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
641 rt2x00_rf(&rt2x00dev->chip, RF5325));
642 642
643 /* 643 /*
644 * Configure the RX antenna. 644 * Configure the RX antenna.
@@ -684,8 +684,7 @@ static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
684 rt61pci_bbp_read(rt2x00dev, 4, &r4); 684 rt61pci_bbp_read(rt2x00dev, 4, &r4);
685 rt61pci_bbp_read(rt2x00dev, 77, &r77); 685 rt61pci_bbp_read(rt2x00dev, 77, &r77);
686 686
687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
688 rt2x00_rf(&rt2x00dev->chip, RF2529));
689 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 688 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
690 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); 689 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
691 690
@@ -833,12 +832,11 @@ static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
833 832
834 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg); 833 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
835 834
836 if (rt2x00_rf(&rt2x00dev->chip, RF5225) || 835 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
837 rt2x00_rf(&rt2x00dev->chip, RF5325))
838 rt61pci_config_antenna_5x(rt2x00dev, ant); 836 rt61pci_config_antenna_5x(rt2x00dev, ant);
839 else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) 837 else if (rt2x00_rf(rt2x00dev, RF2527))
840 rt61pci_config_antenna_2x(rt2x00dev, ant); 838 rt61pci_config_antenna_2x(rt2x00dev, ant);
841 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) { 839 else if (rt2x00_rf(rt2x00dev, RF2529)) {
842 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) 840 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
843 rt61pci_config_antenna_2x(rt2x00dev, ant); 841 rt61pci_config_antenna_2x(rt2x00dev, ant);
844 else 842 else
@@ -879,8 +877,7 @@ static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
879 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 877 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
880 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 878 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
881 879
882 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) || 880 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
883 rt2x00_rf(&rt2x00dev->chip, RF2527));
884 881
885 rt61pci_bbp_read(rt2x00dev, 3, &r3); 882 rt61pci_bbp_read(rt2x00dev, 3, &r3);
886 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); 883 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
@@ -1135,16 +1132,18 @@ dynamic_cca_tune:
1135 */ 1132 */
1136static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 1133static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1137{ 1134{
1135 u16 chip;
1138 char *fw_name; 1136 char *fw_name;
1139 1137
1140 switch (rt2x00dev->chip.rt) { 1138 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1141 case RT2561: 1139 switch (chip) {
1140 case RT2561_PCI_ID:
1142 fw_name = FIRMWARE_RT2561; 1141 fw_name = FIRMWARE_RT2561;
1143 break; 1142 break;
1144 case RT2561s: 1143 case RT2561s_PCI_ID:
1145 fw_name = FIRMWARE_RT2561s; 1144 fw_name = FIRMWARE_RT2561s;
1146 break; 1145 break;
1147 case RT2661: 1146 case RT2661_PCI_ID:
1148 fw_name = FIRMWARE_RT2661; 1147 fw_name = FIRMWARE_RT2661;
1149 break; 1148 break;
1150 default: 1149 default:
@@ -1168,8 +1167,8 @@ static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1168 return FW_BAD_LENGTH; 1167 return FW_BAD_LENGTH;
1169 1168
1170 /* 1169 /*
1171 * The last 2 bytes in the firmware array are the crc checksum itself, 1170 * The last 2 bytes in the firmware array are the crc checksum itself.
1172 * this means that we should never pass those 2 bytes to the crc 1171 * This means that we should never pass those 2 bytes to the crc
1173 * algorithm. 1172 * algorithm.
1174 */ 1173 */
1175 fw_crc = (data[len - 2] << 8 | data[len - 1]); 1174 fw_crc = (data[len - 2] << 8 | data[len - 1]);
@@ -1986,7 +1985,7 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
1986 1985
1987 /* 1986 /*
1988 * Hardware has stripped IV/EIV data from 802.11 frame during 1987 * Hardware has stripped IV/EIV data from 802.11 frame during
1989 * decryption. It has provided the data seperately but rt2x00lib 1988 * decryption. It has provided the data separately but rt2x00lib
1990 * should decide if it should be reinserted. 1989 * should decide if it should be reinserted.
1991 */ 1990 */
1992 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 1991 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
@@ -2042,7 +2041,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2042 * During each loop we will compare the freshly read 2041 * During each loop we will compare the freshly read
2043 * STA_CSR4 register value with the value read from 2042 * STA_CSR4 register value with the value read from
2044 * the previous loop. If the 2 values are equal then 2043 * the previous loop. If the 2 values are equal then
2045 * we should stop processing because the chance it 2044 * we should stop processing because the chance is
2046 * quite big that the device has been unplugged and 2045 * quite big that the device has been unplugged and
2047 * we risk going into an endless loop. 2046 * we risk going into an endless loop.
2048 */ 2047 */
@@ -2299,12 +2298,13 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2299 */ 2298 */
2300 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 2299 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2301 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 2300 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2302 rt2x00_set_chip_rf(rt2x00dev, value, reg); 2301 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2302 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2303 2303
2304 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) && 2304 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2305 !rt2x00_rf(&rt2x00dev->chip, RF5325) && 2305 !rt2x00_rf(rt2x00dev, RF5325) &&
2306 !rt2x00_rf(&rt2x00dev->chip, RF2527) && 2306 !rt2x00_rf(rt2x00dev, RF2527) &&
2307 !rt2x00_rf(&rt2x00dev->chip, RF2529)) { 2307 !rt2x00_rf(rt2x00dev, RF2529)) {
2308 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 2308 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2309 return -ENODEV; 2309 return -ENODEV;
2310 } 2310 }
@@ -2330,7 +2330,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2330 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); 2330 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2331 2331
2332 /* 2332 /*
2333 * Detect if this device has an hardware controlled radio. 2333 * Detect if this device has a hardware controlled radio.
2334 */ 2334 */
2335 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 2335 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2336 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 2336 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
@@ -2355,11 +2355,11 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2355 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 2355 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2356 2356
2357 /* 2357 /*
2358 * When working with a RF2529 chip without double antenna 2358 * When working with a RF2529 chip without double antenna,
2359 * the antenna settings should be gathered from the NIC 2359 * the antenna settings should be gathered from the NIC
2360 * eeprom word. 2360 * eeprom word.
2361 */ 2361 */
2362 if (rt2x00_rf(&rt2x00dev->chip, RF2529) && 2362 if (rt2x00_rf(rt2x00dev, RF2529) &&
2363 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) { 2363 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2364 rt2x00dev->default_ant.rx = 2364 rt2x00dev->default_ant.rx =
2365 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED); 2365 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
@@ -2538,6 +2538,11 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2538 unsigned int i; 2538 unsigned int i;
2539 2539
2540 /* 2540 /*
2541 * Disable powersaving as default.
2542 */
2543 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2544
2545 /*
2541 * Initialize all hw fields. 2546 * Initialize all hw fields.
2542 */ 2547 */
2543 rt2x00dev->hw->flags = 2548 rt2x00dev->hw->flags =
@@ -2545,7 +2550,6 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2545 IEEE80211_HW_SIGNAL_DBM | 2550 IEEE80211_HW_SIGNAL_DBM |
2546 IEEE80211_HW_SUPPORTS_PS | 2551 IEEE80211_HW_SUPPORTS_PS |
2547 IEEE80211_HW_PS_NULLFUNC_STACK; 2552 IEEE80211_HW_PS_NULLFUNC_STACK;
2548 rt2x00dev->hw->extra_tx_headroom = 0;
2549 2553
2550 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 2554 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2551 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 2555 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
@@ -2566,8 +2570,7 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2566 spec->channels = rf_vals_seq; 2570 spec->channels = rf_vals_seq;
2567 } 2571 }
2568 2572
2569 if (rt2x00_rf(&rt2x00dev->chip, RF5225) || 2573 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2570 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2571 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2574 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2572 spec->num_channels = ARRAY_SIZE(rf_vals_seq); 2575 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2573 } 2576 }
@@ -2668,7 +2671,7 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2668 2671
2669 /* 2672 /*
2670 * We only need to perform additional register initialization 2673 * We only need to perform additional register initialization
2671 * for WMM queues/ 2674 * for WMM queues.
2672 */ 2675 */
2673 if (queue_idx >= 4) 2676 if (queue_idx >= 4)
2674 return 0; 2677 return 0;
@@ -2730,7 +2733,6 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
2730 .get_stats = rt2x00mac_get_stats, 2733 .get_stats = rt2x00mac_get_stats,
2731 .bss_info_changed = rt2x00mac_bss_info_changed, 2734 .bss_info_changed = rt2x00mac_bss_info_changed,
2732 .conf_tx = rt61pci_conf_tx, 2735 .conf_tx = rt61pci_conf_tx,
2733 .get_tx_stats = rt2x00mac_get_tx_stats,
2734 .get_tsf = rt61pci_get_tsf, 2736 .get_tsf = rt61pci_get_tsf,
2735 .rfkill_poll = rt2x00mac_rfkill_poll, 2737 .rfkill_poll = rt2x00mac_rfkill_poll,
2736}; 2738};
@@ -2787,26 +2789,27 @@ static const struct data_queue_desc rt61pci_queue_bcn = {
2787}; 2789};
2788 2790
2789static const struct rt2x00_ops rt61pci_ops = { 2791static const struct rt2x00_ops rt61pci_ops = {
2790 .name = KBUILD_MODNAME, 2792 .name = KBUILD_MODNAME,
2791 .max_sta_intf = 1, 2793 .max_sta_intf = 1,
2792 .max_ap_intf = 4, 2794 .max_ap_intf = 4,
2793 .eeprom_size = EEPROM_SIZE, 2795 .eeprom_size = EEPROM_SIZE,
2794 .rf_size = RF_SIZE, 2796 .rf_size = RF_SIZE,
2795 .tx_queues = NUM_TX_QUEUES, 2797 .tx_queues = NUM_TX_QUEUES,
2796 .rx = &rt61pci_queue_rx, 2798 .extra_tx_headroom = 0,
2797 .tx = &rt61pci_queue_tx, 2799 .rx = &rt61pci_queue_rx,
2798 .bcn = &rt61pci_queue_bcn, 2800 .tx = &rt61pci_queue_tx,
2799 .lib = &rt61pci_rt2x00_ops, 2801 .bcn = &rt61pci_queue_bcn,
2800 .hw = &rt61pci_mac80211_ops, 2802 .lib = &rt61pci_rt2x00_ops,
2803 .hw = &rt61pci_mac80211_ops,
2801#ifdef CONFIG_RT2X00_LIB_DEBUGFS 2804#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2802 .debugfs = &rt61pci_rt2x00debug, 2805 .debugfs = &rt61pci_rt2x00debug,
2803#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 2806#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2804}; 2807};
2805 2808
2806/* 2809/*
2807 * RT61pci module information. 2810 * RT61pci module information.
2808 */ 2811 */
2809static struct pci_device_id rt61pci_device_table[] = { 2812static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
2810 /* RT2561s */ 2813 /* RT2561s */
2811 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) }, 2814 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2812 /* RT2561 v2 */ 2815 /* RT2561 v2 */
diff --git a/drivers/net/wireless/rt2x00/rt61pci.h b/drivers/net/wireless/rt2x00/rt61pci.h
index 93eb699165cc..df80f1af22a4 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.h
+++ b/drivers/net/wireless/rt2x00/rt61pci.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -28,6 +28,13 @@
28#define RT61PCI_H 28#define RT61PCI_H
29 29
30/* 30/*
31 * RT chip PCI IDs.
32 */
33#define RT2561s_PCI_ID 0x0301
34#define RT2561_PCI_ID 0x0302
35#define RT2661_PCI_ID 0x0401
36
37/*
31 * RF chip defines. 38 * RF chip defines.
32 */ 39 */
33#define RF5225 0x0001 40#define RF5225 0x0001
@@ -37,7 +44,7 @@
37 44
38/* 45/*
39 * Signal information. 46 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion. 47 * Default offset is required for RSSI <-> dBm conversion.
41 */ 48 */
42#define DEFAULT_RSSI_OFFSET 120 49#define DEFAULT_RSSI_OFFSET 120
43 50
@@ -225,6 +232,8 @@ struct hw_pairwise_ta_entry {
225 * MAC_CSR0: ASIC revision number. 232 * MAC_CSR0: ASIC revision number.
226 */ 233 */
227#define MAC_CSR0 0x3000 234#define MAC_CSR0 0x3000
235#define MAC_CSR0_REVISION FIELD32(0x0000000f)
236#define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
228 237
229/* 238/*
230 * MAC_CSR1: System control register. 239 * MAC_CSR1: System control register.
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index 14e7bb210075..bb58d797fb72 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -30,6 +30,7 @@
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/module.h> 32#include <linux/module.h>
33#include <linux/slab.h>
33#include <linux/usb.h> 34#include <linux/usb.h>
34 35
35#include "rt2x00.h" 36#include "rt2x00.h"
@@ -136,8 +137,8 @@ static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
136 * all others contain 20 bits. 137 * all others contain 20 bits.
137 */ 138 */
138 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 139 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
139 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) || 140 20 + (rt2x00_rf(rt2x00dev, RF5225) ||
140 rt2x00_rf(&rt2x00dev->chip, RF2527))); 141 rt2x00_rf(rt2x00dev, RF2527)));
141 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0); 142 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
142 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1); 143 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
143 144
@@ -339,7 +340,7 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
339 * The driver does not support the IV/EIV generation 340 * The driver does not support the IV/EIV generation
340 * in hardware. However it doesn't support the IV/EIV 341 * in hardware. However it doesn't support the IV/EIV
341 * inside the ieee80211 frame either, but requires it 342 * inside the ieee80211 frame either, but requires it
342 * to be provided seperately for the descriptor. 343 * to be provided separately for the descriptor.
343 * rt2x00lib will cut the IV/EIV data out of all frames 344 * rt2x00lib will cut the IV/EIV data out of all frames
344 * given to us by mac80211, but we must tell mac80211 345 * given to us by mac80211, but we must tell mac80211
345 * to generate the IV/EIV data. 346 * to generate the IV/EIV data.
@@ -439,7 +440,7 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
439 * The driver does not support the IV/EIV generation 440 * The driver does not support the IV/EIV generation
440 * in hardware. However it doesn't support the IV/EIV 441 * in hardware. However it doesn't support the IV/EIV
441 * inside the ieee80211 frame either, but requires it 442 * inside the ieee80211 frame either, but requires it
442 * to be provided seperately for the descriptor. 443 * to be provided separately for the descriptor.
443 * rt2x00lib will cut the IV/EIV data out of all frames 444 * rt2x00lib will cut the IV/EIV data out of all frames
444 * given to us by mac80211, but we must tell mac80211 445 * given to us by mac80211, but we must tell mac80211
445 * to generate the IV/EIV data. 446 * to generate the IV/EIV data.
@@ -741,11 +742,9 @@ static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
741 742
742 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg); 743 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
743 744
744 if (rt2x00_rf(&rt2x00dev->chip, RF5226) || 745 if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
745 rt2x00_rf(&rt2x00dev->chip, RF5225))
746 rt73usb_config_antenna_5x(rt2x00dev, ant); 746 rt73usb_config_antenna_5x(rt2x00dev, ant);
747 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) || 747 else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
748 rt2x00_rf(&rt2x00dev->chip, RF2527))
749 rt73usb_config_antenna_2x(rt2x00dev, ant); 748 rt73usb_config_antenna_2x(rt2x00dev, ant);
750} 749}
751 750
@@ -779,8 +778,7 @@ static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
779 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 778 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
780 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 779 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
781 780
782 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) || 781 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
783 rt2x00_rf(&rt2x00dev->chip, RF2527));
784 782
785 rt73usb_bbp_read(rt2x00dev, 3, &r3); 783 rt73usb_bbp_read(rt2x00dev, 3, &r3);
786 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); 784 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
@@ -1210,8 +1208,7 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1210 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); 1208 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1211 1209
1212 reg = 0x000023b0; 1210 reg = 0x000023b0;
1213 if (rt2x00_rf(&rt2x00dev->chip, RF5225) || 1211 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1214 rt2x00_rf(&rt2x00dev->chip, RF2527))
1215 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1); 1212 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1216 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg); 1213 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1217 1214
@@ -1665,7 +1662,7 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry,
1665 1662
1666 /* 1663 /*
1667 * Hardware has stripped IV/EIV data from 802.11 frame during 1664 * Hardware has stripped IV/EIV data from 802.11 frame during
1668 * decryption. It has provided the data seperately but rt2x00lib 1665 * decryption. It has provided the data separately but rt2x00lib
1669 * should decide if it should be reinserted. 1666 * should decide if it should be reinserted.
1670 */ 1667 */
1671 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 1668 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
@@ -1824,18 +1821,18 @@ static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1824 */ 1821 */
1825 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1822 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1826 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1823 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1827 rt2x00_set_chip(rt2x00dev, RT2571, value, reg); 1824 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1825 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1828 1826
1829 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x000ffff0, 0x25730) || 1827 if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1830 rt2x00_check_rev(&rt2x00dev->chip, 0x0000000f, 0)) {
1831 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 1828 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1832 return -ENODEV; 1829 return -ENODEV;
1833 } 1830 }
1834 1831
1835 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) && 1832 if (!rt2x00_rf(rt2x00dev, RF5226) &&
1836 !rt2x00_rf(&rt2x00dev->chip, RF2528) && 1833 !rt2x00_rf(rt2x00dev, RF2528) &&
1837 !rt2x00_rf(&rt2x00dev->chip, RF5225) && 1834 !rt2x00_rf(rt2x00dev, RF5225) &&
1838 !rt2x00_rf(&rt2x00dev->chip, RF2527)) { 1835 !rt2x00_rf(rt2x00dev, RF2527)) {
1839 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 1836 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1840 return -ENODEV; 1837 return -ENODEV;
1841 } 1838 }
@@ -2068,7 +2065,6 @@ static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2068 IEEE80211_HW_SIGNAL_DBM | 2065 IEEE80211_HW_SIGNAL_DBM |
2069 IEEE80211_HW_SUPPORTS_PS | 2066 IEEE80211_HW_SUPPORTS_PS |
2070 IEEE80211_HW_PS_NULLFUNC_STACK; 2067 IEEE80211_HW_PS_NULLFUNC_STACK;
2071 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2072 2068
2073 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 2069 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2074 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 2070 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
@@ -2081,17 +2077,17 @@ static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2081 spec->supported_bands = SUPPORT_BAND_2GHZ; 2077 spec->supported_bands = SUPPORT_BAND_2GHZ;
2082 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 2078 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2083 2079
2084 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) { 2080 if (rt2x00_rf(rt2x00dev, RF2528)) {
2085 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528); 2081 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2086 spec->channels = rf_vals_bg_2528; 2082 spec->channels = rf_vals_bg_2528;
2087 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) { 2083 } else if (rt2x00_rf(rt2x00dev, RF5226)) {
2088 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2084 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2089 spec->num_channels = ARRAY_SIZE(rf_vals_5226); 2085 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2090 spec->channels = rf_vals_5226; 2086 spec->channels = rf_vals_5226;
2091 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) { 2087 } else if (rt2x00_rf(rt2x00dev, RF2527)) {
2092 spec->num_channels = 14; 2088 spec->num_channels = 14;
2093 spec->channels = rf_vals_5225_2527; 2089 spec->channels = rf_vals_5225_2527;
2094 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) { 2090 } else if (rt2x00_rf(rt2x00dev, RF5225)) {
2095 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2091 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2096 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527); 2092 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2097 spec->channels = rf_vals_5225_2527; 2093 spec->channels = rf_vals_5225_2527;
@@ -2249,7 +2245,6 @@ static const struct ieee80211_ops rt73usb_mac80211_ops = {
2249 .get_stats = rt2x00mac_get_stats, 2245 .get_stats = rt2x00mac_get_stats,
2250 .bss_info_changed = rt2x00mac_bss_info_changed, 2246 .bss_info_changed = rt2x00mac_bss_info_changed,
2251 .conf_tx = rt73usb_conf_tx, 2247 .conf_tx = rt73usb_conf_tx,
2252 .get_tx_stats = rt2x00mac_get_tx_stats,
2253 .get_tsf = rt73usb_get_tsf, 2248 .get_tsf = rt73usb_get_tsf,
2254 .rfkill_poll = rt2x00mac_rfkill_poll, 2249 .rfkill_poll = rt2x00mac_rfkill_poll,
2255}; 2250};
@@ -2305,19 +2300,20 @@ static const struct data_queue_desc rt73usb_queue_bcn = {
2305}; 2300};
2306 2301
2307static const struct rt2x00_ops rt73usb_ops = { 2302static const struct rt2x00_ops rt73usb_ops = {
2308 .name = KBUILD_MODNAME, 2303 .name = KBUILD_MODNAME,
2309 .max_sta_intf = 1, 2304 .max_sta_intf = 1,
2310 .max_ap_intf = 4, 2305 .max_ap_intf = 4,
2311 .eeprom_size = EEPROM_SIZE, 2306 .eeprom_size = EEPROM_SIZE,
2312 .rf_size = RF_SIZE, 2307 .rf_size = RF_SIZE,
2313 .tx_queues = NUM_TX_QUEUES, 2308 .tx_queues = NUM_TX_QUEUES,
2314 .rx = &rt73usb_queue_rx, 2309 .extra_tx_headroom = TXD_DESC_SIZE,
2315 .tx = &rt73usb_queue_tx, 2310 .rx = &rt73usb_queue_rx,
2316 .bcn = &rt73usb_queue_bcn, 2311 .tx = &rt73usb_queue_tx,
2317 .lib = &rt73usb_rt2x00_ops, 2312 .bcn = &rt73usb_queue_bcn,
2318 .hw = &rt73usb_mac80211_ops, 2313 .lib = &rt73usb_rt2x00_ops,
2314 .hw = &rt73usb_mac80211_ops,
2319#ifdef CONFIG_RT2X00_LIB_DEBUGFS 2315#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2320 .debugfs = &rt73usb_rt2x00debug, 2316 .debugfs = &rt73usb_rt2x00debug,
2321#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 2317#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2322}; 2318};
2323 2319
@@ -2353,9 +2349,12 @@ static struct usb_device_id rt73usb_device_table[] = {
2353 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) }, 2349 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
2354 /* Buffalo */ 2350 /* Buffalo */
2355 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) }, 2351 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2352 { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
2356 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, 2353 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2357 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) }, 2354 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2358 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) }, 2355 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
2356 /* CEIVA */
2357 { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
2359 /* CNet */ 2358 /* CNet */
2360 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, 2359 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2361 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) }, 2360 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
diff --git a/drivers/net/wireless/rt2x00/rt73usb.h b/drivers/net/wireless/rt2x00/rt73usb.h
index 81fe0be51c42..7abe7eb14555 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.h
+++ b/drivers/net/wireless/rt2x00/rt73usb.h
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -37,7 +37,7 @@
37 37
38/* 38/*
39 * Signal information. 39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion. 40 * Default offset is required for RSSI <-> dBm conversion.
41 */ 41 */
42#define DEFAULT_RSSI_OFFSET 120 42#define DEFAULT_RSSI_OFFSET 120
43 43
@@ -142,6 +142,8 @@ struct hw_pairwise_ta_entry {
142 * MAC_CSR0: ASIC revision number. 142 * MAC_CSR0: ASIC revision number.
143 */ 143 */
144#define MAC_CSR0 0x3000 144#define MAC_CSR0 0x3000
145#define MAC_CSR0_REVISION FIELD32(0x0000000f)
146#define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
145 147
146/* 148/*
147 * MAC_CSR1: System control register. 149 * MAC_CSR1: System control register.
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-29 16:39:22 -0400