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path: root/drivers/net/wireless/rt2x00/rt2800lib.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800lib.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c397
1 files changed, 326 insertions, 71 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index b93516d832fb..540c94f8505a 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -923,8 +923,8 @@ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
923 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg); 923 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
924 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 924 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
925 } else { 925 } else {
926 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 926 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
927 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); 927 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
928 } 928 }
929} 929}
930EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 930EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
@@ -1570,10 +1570,10 @@ static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1570 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 1570 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1571 eesk_pin, 0); 1571 eesk_pin, 0);
1572 1572
1573 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 1573 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1574 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0); 1574 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1575 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3); 1575 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1576 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); 1576 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1577} 1577}
1578 1578
1579void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 1579void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
@@ -1615,6 +1615,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1615 case 1: 1615 case 1:
1616 if (rt2x00_rt(rt2x00dev, RT3070) || 1616 if (rt2x00_rt(rt2x00dev, RT3070) ||
1617 rt2x00_rt(rt2x00dev, RT3090) || 1617 rt2x00_rt(rt2x00dev, RT3090) ||
1618 rt2x00_rt(rt2x00dev, RT3352) ||
1618 rt2x00_rt(rt2x00dev, RT3390)) { 1619 rt2x00_rt(rt2x00dev, RT3390)) {
1619 rt2x00_eeprom_read(rt2x00dev, 1620 rt2x00_eeprom_read(rt2x00dev,
1620 EEPROM_NIC_CONF1, &eeprom); 1621 EEPROM_NIC_CONF1, &eeprom);
@@ -1762,36 +1763,15 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1762 1763
1763 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 1764 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1764 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 1765 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1766 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1767 rt2x00dev->default_ant.rx_chain_num <= 1);
1768 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1769 rt2x00dev->default_ant.rx_chain_num <= 2);
1765 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 1770 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1766 if (rt2x00_rt(rt2x00dev, RT3390)) { 1771 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1767 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1772 rt2x00dev->default_ant.tx_chain_num <= 1);
1768 rt2x00dev->default_ant.rx_chain_num == 1); 1773 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1769 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1774 rt2x00dev->default_ant.tx_chain_num <= 2);
1770 rt2x00dev->default_ant.tx_chain_num == 1);
1771 } else {
1772 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1773 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1774 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1775 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1776
1777 switch (rt2x00dev->default_ant.tx_chain_num) {
1778 case 1:
1779 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1780 /* fall through */
1781 case 2:
1782 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1783 break;
1784 }
1785
1786 switch (rt2x00dev->default_ant.rx_chain_num) {
1787 case 1:
1788 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1789 /* fall through */
1790 case 2:
1791 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1792 break;
1793 }
1794 }
1795 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 1775 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1796 1776
1797 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 1777 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
@@ -1995,13 +1975,13 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1995 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 1975 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1996 } 1976 }
1997 1977
1998 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 1978 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1999 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0); 1979 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2000 if (rf->channel <= 14) 1980 if (rf->channel <= 14)
2001 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1); 1981 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2002 else 1982 else
2003 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0); 1983 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2004 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); 1984 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2005 1985
2006 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 1986 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2007 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 1987 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
@@ -2053,6 +2033,60 @@ static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2053 } 2033 }
2054} 2034}
2055 2035
2036static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2037 struct ieee80211_conf *conf,
2038 struct rf_channel *rf,
2039 struct channel_info *info)
2040{
2041 u8 rfcsr;
2042
2043 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2044 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2045
2046 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2047 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2048 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2049
2050 if (info->default_power1 > POWER_BOUND)
2051 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2052 else
2053 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2054
2055 if (info->default_power2 > POWER_BOUND)
2056 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2057 else
2058 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2059
2060 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2061 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2062 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2063 else
2064 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2065
2066 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2067
2068 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2069 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2070 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2071
2072 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2073 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2074 else
2075 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2076
2077 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2078 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2079 else
2080 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2081
2082 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2083 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2084
2085 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2086
2087 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2088}
2089
2056static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2090static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2057 struct ieee80211_conf *conf, 2091 struct ieee80211_conf *conf,
2058 struct rf_channel *rf, 2092 struct rf_channel *rf,
@@ -2182,6 +2216,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2182 case RF3290: 2216 case RF3290:
2183 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 2217 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2184 break; 2218 break;
2219 case RF3322:
2220 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2221 break;
2185 case RF5360: 2222 case RF5360:
2186 case RF5370: 2223 case RF5370:
2187 case RF5372: 2224 case RF5372:
@@ -2194,6 +2231,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2194 } 2231 }
2195 2232
2196 if (rt2x00_rf(rt2x00dev, RF3290) || 2233 if (rt2x00_rf(rt2x00dev, RF3290) ||
2234 rt2x00_rf(rt2x00dev, RF3322) ||
2197 rt2x00_rf(rt2x00dev, RF5360) || 2235 rt2x00_rf(rt2x00dev, RF5360) ||
2198 rt2x00_rf(rt2x00dev, RF5370) || 2236 rt2x00_rf(rt2x00dev, RF5370) ||
2199 rt2x00_rf(rt2x00dev, RF5372) || 2237 rt2x00_rf(rt2x00dev, RF5372) ||
@@ -2212,10 +2250,17 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2212 /* 2250 /*
2213 * Change BBP settings 2251 * Change BBP settings
2214 */ 2252 */
2215 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 2253 if (rt2x00_rt(rt2x00dev, RT3352)) {
2216 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 2254 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2217 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 2255 rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
2218 rt2800_bbp_write(rt2x00dev, 86, 0); 2256 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2257 rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
2258 } else {
2259 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2260 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2261 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2262 rt2800_bbp_write(rt2x00dev, 86, 0);
2263 }
2219 2264
2220 if (rf->channel <= 14) { 2265 if (rf->channel <= 14) {
2221 if (!rt2x00_rt(rt2x00dev, RT5390) && 2266 if (!rt2x00_rt(rt2x00dev, RT5390) &&
@@ -2310,6 +2355,15 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2310 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg); 2355 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2311 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg); 2356 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2312 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg); 2357 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2358
2359 /*
2360 * Clear update flag
2361 */
2362 if (rt2x00_rt(rt2x00dev, RT3352)) {
2363 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2364 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2365 rt2800_bbp_write(rt2x00dev, 49, bbp);
2366 }
2313} 2367}
2314 2368
2315static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 2369static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
@@ -2821,23 +2875,32 @@ EXPORT_SYMBOL_GPL(rt2800_link_stats);
2821 2875
2822static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 2876static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2823{ 2877{
2878 u8 vgc;
2879
2824 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 2880 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2825 if (rt2x00_rt(rt2x00dev, RT3070) || 2881 if (rt2x00_rt(rt2x00dev, RT3070) ||
2826 rt2x00_rt(rt2x00dev, RT3071) || 2882 rt2x00_rt(rt2x00dev, RT3071) ||
2827 rt2x00_rt(rt2x00dev, RT3090) || 2883 rt2x00_rt(rt2x00dev, RT3090) ||
2828 rt2x00_rt(rt2x00dev, RT3290) || 2884 rt2x00_rt(rt2x00dev, RT3290) ||
2829 rt2x00_rt(rt2x00dev, RT3390) || 2885 rt2x00_rt(rt2x00dev, RT3390) ||
2886 rt2x00_rt(rt2x00dev, RT3572) ||
2830 rt2x00_rt(rt2x00dev, RT5390) || 2887 rt2x00_rt(rt2x00dev, RT5390) ||
2831 rt2x00_rt(rt2x00dev, RT5392)) 2888 rt2x00_rt(rt2x00dev, RT5392))
2832 return 0x1c + (2 * rt2x00dev->lna_gain); 2889 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
2833 else 2890 else
2834 return 0x2e + rt2x00dev->lna_gain; 2891 vgc = 0x2e + rt2x00dev->lna_gain;
2892 } else { /* 5GHZ band */
2893 if (rt2x00_rt(rt2x00dev, RT3572))
2894 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
2895 else {
2896 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2897 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2898 else
2899 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2900 }
2835 } 2901 }
2836 2902
2837 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 2903 return vgc;
2838 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2839 else
2840 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2841} 2904}
2842 2905
2843static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 2906static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
@@ -2998,11 +3061,15 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2998 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 3061 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2999 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 3062 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3000 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 3063 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3064 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3065 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3066 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3067 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3001 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 3068 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3002 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 3069 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3003 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 3070 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3004 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3071 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3005 rt2x00_rt(rt2x00dev, RT5392)) { 3072 rt2x00_rt(rt2x00dev, RT5392)) {
3006 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 3073 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3007 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 3074 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3008 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 3075 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
@@ -3378,6 +3445,11 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3378 rt2800_wait_bbp_ready(rt2x00dev))) 3445 rt2800_wait_bbp_ready(rt2x00dev)))
3379 return -EACCES; 3446 return -EACCES;
3380 3447
3448 if (rt2x00_rt(rt2x00dev, RT3352)) {
3449 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3450 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3451 }
3452
3381 if (rt2x00_rt(rt2x00dev, RT3290) || 3453 if (rt2x00_rt(rt2x00dev, RT3290) ||
3382 rt2x00_rt(rt2x00dev, RT5390) || 3454 rt2x00_rt(rt2x00dev, RT5390) ||
3383 rt2x00_rt(rt2x00dev, RT5392)) { 3455 rt2x00_rt(rt2x00dev, RT5392)) {
@@ -3388,15 +3460,20 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3388 3460
3389 if (rt2800_is_305x_soc(rt2x00dev) || 3461 if (rt2800_is_305x_soc(rt2x00dev) ||
3390 rt2x00_rt(rt2x00dev, RT3290) || 3462 rt2x00_rt(rt2x00dev, RT3290) ||
3463 rt2x00_rt(rt2x00dev, RT3352) ||
3391 rt2x00_rt(rt2x00dev, RT3572) || 3464 rt2x00_rt(rt2x00dev, RT3572) ||
3392 rt2x00_rt(rt2x00dev, RT5390) || 3465 rt2x00_rt(rt2x00dev, RT5390) ||
3393 rt2x00_rt(rt2x00dev, RT5392)) 3466 rt2x00_rt(rt2x00dev, RT5392))
3394 rt2800_bbp_write(rt2x00dev, 31, 0x08); 3467 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3395 3468
3469 if (rt2x00_rt(rt2x00dev, RT3352))
3470 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3471
3396 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 3472 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3397 rt2800_bbp_write(rt2x00dev, 66, 0x38); 3473 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3398 3474
3399 if (rt2x00_rt(rt2x00dev, RT3290) || 3475 if (rt2x00_rt(rt2x00dev, RT3290) ||
3476 rt2x00_rt(rt2x00dev, RT3352) ||
3400 rt2x00_rt(rt2x00dev, RT5390) || 3477 rt2x00_rt(rt2x00dev, RT5390) ||
3401 rt2x00_rt(rt2x00dev, RT5392)) 3478 rt2x00_rt(rt2x00dev, RT5392))
3402 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3479 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
@@ -3405,6 +3482,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3405 rt2800_bbp_write(rt2x00dev, 69, 0x16); 3482 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3406 rt2800_bbp_write(rt2x00dev, 73, 0x12); 3483 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3407 } else if (rt2x00_rt(rt2x00dev, RT3290) || 3484 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3485 rt2x00_rt(rt2x00dev, RT3352) ||
3408 rt2x00_rt(rt2x00dev, RT5390) || 3486 rt2x00_rt(rt2x00dev, RT5390) ||
3409 rt2x00_rt(rt2x00dev, RT5392)) { 3487 rt2x00_rt(rt2x00dev, RT5392)) {
3410 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3488 rt2800_bbp_write(rt2x00dev, 69, 0x12);
@@ -3436,15 +3514,17 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3436 } else if (rt2800_is_305x_soc(rt2x00dev)) { 3514 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3437 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 3515 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3438 rt2800_bbp_write(rt2x00dev, 80, 0x08); 3516 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3439 } else { 3517 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3440 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3441 }
3442
3443 if (rt2x00_rt(rt2x00dev, RT3290)) {
3444 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 3518 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3445 rt2800_bbp_write(rt2x00dev, 79, 0x18); 3519 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3446 rt2800_bbp_write(rt2x00dev, 80, 0x09); 3520 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3447 rt2800_bbp_write(rt2x00dev, 81, 0x33); 3521 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3522 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3523 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3524 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3525 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3526 } else {
3527 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3448 } 3528 }
3449 3529
3450 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3530 rt2800_bbp_write(rt2x00dev, 82, 0x62);
@@ -3465,18 +3545,21 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3465 rt2800_bbp_write(rt2x00dev, 84, 0x99); 3545 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3466 3546
3467 if (rt2x00_rt(rt2x00dev, RT3290) || 3547 if (rt2x00_rt(rt2x00dev, RT3290) ||
3548 rt2x00_rt(rt2x00dev, RT3352) ||
3468 rt2x00_rt(rt2x00dev, RT5390) || 3549 rt2x00_rt(rt2x00dev, RT5390) ||
3469 rt2x00_rt(rt2x00dev, RT5392)) 3550 rt2x00_rt(rt2x00dev, RT5392))
3470 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3551 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3471 else 3552 else
3472 rt2800_bbp_write(rt2x00dev, 86, 0x00); 3553 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3473 3554
3474 if (rt2x00_rt(rt2x00dev, RT5392)) 3555 if (rt2x00_rt(rt2x00dev, RT3352) ||
3556 rt2x00_rt(rt2x00dev, RT5392))
3475 rt2800_bbp_write(rt2x00dev, 88, 0x90); 3557 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3476 3558
3477 rt2800_bbp_write(rt2x00dev, 91, 0x04); 3559 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3478 3560
3479 if (rt2x00_rt(rt2x00dev, RT3290) || 3561 if (rt2x00_rt(rt2x00dev, RT3290) ||
3562 rt2x00_rt(rt2x00dev, RT3352) ||
3480 rt2x00_rt(rt2x00dev, RT5390) || 3563 rt2x00_rt(rt2x00dev, RT5390) ||
3481 rt2x00_rt(rt2x00dev, RT5392)) 3564 rt2x00_rt(rt2x00dev, RT5392))
3482 rt2800_bbp_write(rt2x00dev, 92, 0x02); 3565 rt2800_bbp_write(rt2x00dev, 92, 0x02);
@@ -3493,6 +3576,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3493 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 3576 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3494 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 3577 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3495 rt2x00_rt(rt2x00dev, RT3290) || 3578 rt2x00_rt(rt2x00dev, RT3290) ||
3579 rt2x00_rt(rt2x00dev, RT3352) ||
3496 rt2x00_rt(rt2x00dev, RT3572) || 3580 rt2x00_rt(rt2x00dev, RT3572) ||
3497 rt2x00_rt(rt2x00dev, RT5390) || 3581 rt2x00_rt(rt2x00dev, RT5390) ||
3498 rt2x00_rt(rt2x00dev, RT5392) || 3582 rt2x00_rt(rt2x00dev, RT5392) ||
@@ -3502,6 +3586,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3502 rt2800_bbp_write(rt2x00dev, 103, 0x00); 3586 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3503 3587
3504 if (rt2x00_rt(rt2x00dev, RT3290) || 3588 if (rt2x00_rt(rt2x00dev, RT3290) ||
3589 rt2x00_rt(rt2x00dev, RT3352) ||
3505 rt2x00_rt(rt2x00dev, RT5390) || 3590 rt2x00_rt(rt2x00dev, RT5390) ||
3506 rt2x00_rt(rt2x00dev, RT5392)) 3591 rt2x00_rt(rt2x00dev, RT5392))
3507 rt2800_bbp_write(rt2x00dev, 104, 0x92); 3592 rt2800_bbp_write(rt2x00dev, 104, 0x92);
@@ -3510,6 +3595,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3510 rt2800_bbp_write(rt2x00dev, 105, 0x01); 3595 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3511 else if (rt2x00_rt(rt2x00dev, RT3290)) 3596 else if (rt2x00_rt(rt2x00dev, RT3290))
3512 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 3597 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
3598 else if (rt2x00_rt(rt2x00dev, RT3352))
3599 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3513 else if (rt2x00_rt(rt2x00dev, RT5390) || 3600 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3514 rt2x00_rt(rt2x00dev, RT5392)) 3601 rt2x00_rt(rt2x00dev, RT5392))
3515 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 3602 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
@@ -3519,11 +3606,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3519 if (rt2x00_rt(rt2x00dev, RT3290) || 3606 if (rt2x00_rt(rt2x00dev, RT3290) ||
3520 rt2x00_rt(rt2x00dev, RT5390)) 3607 rt2x00_rt(rt2x00dev, RT5390))
3521 rt2800_bbp_write(rt2x00dev, 106, 0x03); 3608 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3609 else if (rt2x00_rt(rt2x00dev, RT3352))
3610 rt2800_bbp_write(rt2x00dev, 106, 0x05);
3522 else if (rt2x00_rt(rt2x00dev, RT5392)) 3611 else if (rt2x00_rt(rt2x00dev, RT5392))
3523 rt2800_bbp_write(rt2x00dev, 106, 0x12); 3612 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3524 else 3613 else
3525 rt2800_bbp_write(rt2x00dev, 106, 0x35); 3614 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3526 3615
3616 if (rt2x00_rt(rt2x00dev, RT3352))
3617 rt2800_bbp_write(rt2x00dev, 120, 0x50);
3618
3527 if (rt2x00_rt(rt2x00dev, RT3290) || 3619 if (rt2x00_rt(rt2x00dev, RT3290) ||
3528 rt2x00_rt(rt2x00dev, RT5390) || 3620 rt2x00_rt(rt2x00dev, RT5390) ||
3529 rt2x00_rt(rt2x00dev, RT5392)) 3621 rt2x00_rt(rt2x00dev, RT5392))
@@ -3534,6 +3626,9 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3534 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 3626 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3535 } 3627 }
3536 3628
3629 if (rt2x00_rt(rt2x00dev, RT3352))
3630 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
3631
3537 if (rt2x00_rt(rt2x00dev, RT3071) || 3632 if (rt2x00_rt(rt2x00dev, RT3071) ||
3538 rt2x00_rt(rt2x00dev, RT3090) || 3633 rt2x00_rt(rt2x00dev, RT3090) ||
3539 rt2x00_rt(rt2x00dev, RT3390) || 3634 rt2x00_rt(rt2x00dev, RT3390) ||
@@ -3574,6 +3669,28 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3574 rt2800_bbp_write(rt2x00dev, 3, value); 3669 rt2800_bbp_write(rt2x00dev, 3, value);
3575 } 3670 }
3576 3671
3672 if (rt2x00_rt(rt2x00dev, RT3352)) {
3673 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
3674 /* Set ITxBF timeout to 0x9c40=1000msec */
3675 rt2800_bbp_write(rt2x00dev, 179, 0x02);
3676 rt2800_bbp_write(rt2x00dev, 180, 0x00);
3677 rt2800_bbp_write(rt2x00dev, 182, 0x40);
3678 rt2800_bbp_write(rt2x00dev, 180, 0x01);
3679 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
3680 rt2800_bbp_write(rt2x00dev, 179, 0x00);
3681 /* Reprogram the inband interface to put right values in RXWI */
3682 rt2800_bbp_write(rt2x00dev, 142, 0x04);
3683 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
3684 rt2800_bbp_write(rt2x00dev, 142, 0x06);
3685 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
3686 rt2800_bbp_write(rt2x00dev, 142, 0x07);
3687 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
3688 rt2800_bbp_write(rt2x00dev, 142, 0x08);
3689 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
3690
3691 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
3692 }
3693
3577 if (rt2x00_rt(rt2x00dev, RT5390) || 3694 if (rt2x00_rt(rt2x00dev, RT5390) ||
3578 rt2x00_rt(rt2x00dev, RT5392)) { 3695 rt2x00_rt(rt2x00dev, RT5392)) {
3579 int ant, div_mode; 3696 int ant, div_mode;
@@ -3587,16 +3704,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3587 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { 3704 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3588 u32 reg; 3705 u32 reg;
3589 3706
3590 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 3707 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3591 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0); 3708 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
3592 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0); 3709 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
3593 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0); 3710 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
3594 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0); 3711 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
3595 if (ant == 0) 3712 if (ant == 0)
3596 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1); 3713 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
3597 else if (ant == 1) 3714 else if (ant == 1)
3598 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1); 3715 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
3599 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); 3716 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3600 } 3717 }
3601 3718
3602 /* This chip has hardware antenna diversity*/ 3719 /* This chip has hardware antenna diversity*/
@@ -3707,6 +3824,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3707 !rt2x00_rt(rt2x00dev, RT3071) && 3824 !rt2x00_rt(rt2x00dev, RT3071) &&
3708 !rt2x00_rt(rt2x00dev, RT3090) && 3825 !rt2x00_rt(rt2x00dev, RT3090) &&
3709 !rt2x00_rt(rt2x00dev, RT3290) && 3826 !rt2x00_rt(rt2x00dev, RT3290) &&
3827 !rt2x00_rt(rt2x00dev, RT3352) &&
3710 !rt2x00_rt(rt2x00dev, RT3390) && 3828 !rt2x00_rt(rt2x00dev, RT3390) &&
3711 !rt2x00_rt(rt2x00dev, RT3572) && 3829 !rt2x00_rt(rt2x00dev, RT3572) &&
3712 !rt2x00_rt(rt2x00dev, RT5390) && 3830 !rt2x00_rt(rt2x00dev, RT5390) &&
@@ -3903,6 +4021,70 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3903 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 4021 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3904 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 4022 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3905 return 0; 4023 return 0;
4024 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4025 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4026 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4027 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4028 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4029 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4030 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4031 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4032 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4033 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4034 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4035 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4036 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4037 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4038 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4039 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4040 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4041 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4042 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4043 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4044 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4045 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4046 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4047 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4048 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4049 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4050 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4051 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4052 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4053 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4054 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4055 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4056 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4057 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4058 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4059 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4060 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4061 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4062 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4063 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4064 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4065 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4066 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4067 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4068 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4069 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4070 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4071 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4072 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4073 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4074 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4075 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4076 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4077 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4078 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4079 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4080 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4081 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4082 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4083 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4084 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4085 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4086 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4087 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3906 } else if (rt2x00_rt(rt2x00dev, RT5390)) { 4088 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3907 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 4089 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3908 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 4090 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
@@ -4104,6 +4286,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4104 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 4286 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4105 } else if (rt2x00_rt(rt2x00dev, RT3071) || 4287 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4106 rt2x00_rt(rt2x00dev, RT3090) || 4288 rt2x00_rt(rt2x00dev, RT3090) ||
4289 rt2x00_rt(rt2x00dev, RT3352) ||
4107 rt2x00_rt(rt2x00dev, RT3390) || 4290 rt2x00_rt(rt2x00dev, RT3390) ||
4108 rt2x00_rt(rt2x00dev, RT3572)) { 4291 rt2x00_rt(rt2x00dev, RT3572)) {
4109 drv_data->calibration_bw20 = 4292 drv_data->calibration_bw20 =
@@ -4392,7 +4575,7 @@ void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4392} 4575}
4393EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 4576EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4394 4577
4395int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 4578static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4396{ 4579{
4397 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 4580 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4398 u16 word; 4581 u16 word;
@@ -4400,6 +4583,11 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4400 u8 default_lna_gain; 4583 u8 default_lna_gain;
4401 4584
4402 /* 4585 /*
4586 * Read the EEPROM.
4587 */
4588 rt2800_read_eeprom(rt2x00dev);
4589
4590 /*
4403 * Start validation of the data that has been read. 4591 * Start validation of the data that has been read.
4404 */ 4592 */
4405 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 4593 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
@@ -4521,9 +4709,8 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4521 4709
4522 return 0; 4710 return 0;
4523} 4711}
4524EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4525 4712
4526int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 4713static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4527{ 4714{
4528 u32 reg; 4715 u32 reg;
4529 u16 value; 4716 u16 value;
@@ -4562,6 +4749,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4562 case RT3071: 4749 case RT3071:
4563 case RT3090: 4750 case RT3090:
4564 case RT3290: 4751 case RT3290:
4752 case RT3352:
4565 case RT3390: 4753 case RT3390:
4566 case RT3572: 4754 case RT3572:
4567 case RT5390: 4755 case RT5390:
@@ -4584,6 +4772,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4584 case RF3052: 4772 case RF3052:
4585 case RF3290: 4773 case RF3290:
4586 case RF3320: 4774 case RF3320:
4775 case RF3322:
4587 case RF5360: 4776 case RF5360:
4588 case RF5370: 4777 case RF5370:
4589 case RF5372: 4778 case RF5372:
@@ -4608,6 +4797,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4608 4797
4609 if (rt2x00_rt(rt2x00dev, RT3070) || 4798 if (rt2x00_rt(rt2x00dev, RT3070) ||
4610 rt2x00_rt(rt2x00dev, RT3090) || 4799 rt2x00_rt(rt2x00dev, RT3090) ||
4800 rt2x00_rt(rt2x00dev, RT3352) ||
4611 rt2x00_rt(rt2x00dev, RT3390)) { 4801 rt2x00_rt(rt2x00dev, RT3390)) {
4612 value = rt2x00_get_field16(eeprom, 4802 value = rt2x00_get_field16(eeprom,
4613 EEPROM_NIC_CONF1_ANT_DIVERSITY); 4803 EEPROM_NIC_CONF1_ANT_DIVERSITY);
@@ -4681,7 +4871,6 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4681 4871
4682 return 0; 4872 return 0;
4683} 4873}
4684EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4685 4874
4686/* 4875/*
4687 * RF value list for rt28xx 4876 * RF value list for rt28xx
@@ -4824,7 +5013,7 @@ static const struct rf_channel rf_vals_3x[] = {
4824 {173, 0x61, 0, 9}, 5013 {173, 0x61, 0, 9},
4825}; 5014};
4826 5015
4827int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 5016static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4828{ 5017{
4829 struct hw_mode_spec *spec = &rt2x00dev->spec; 5018 struct hw_mode_spec *spec = &rt2x00dev->spec;
4830 struct channel_info *info; 5019 struct channel_info *info;
@@ -4901,6 +5090,7 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4901 rt2x00_rf(rt2x00dev, RF3022) || 5090 rt2x00_rf(rt2x00dev, RF3022) ||
4902 rt2x00_rf(rt2x00dev, RF3290) || 5091 rt2x00_rf(rt2x00dev, RF3290) ||
4903 rt2x00_rf(rt2x00dev, RF3320) || 5092 rt2x00_rf(rt2x00dev, RF3320) ||
5093 rt2x00_rf(rt2x00dev, RF3322) ||
4904 rt2x00_rf(rt2x00dev, RF5360) || 5094 rt2x00_rf(rt2x00dev, RF5360) ||
4905 rt2x00_rf(rt2x00dev, RF5370) || 5095 rt2x00_rf(rt2x00dev, RF5370) ||
4906 rt2x00_rf(rt2x00dev, RF5372) || 5096 rt2x00_rf(rt2x00dev, RF5372) ||
@@ -5000,7 +5190,72 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5000 5190
5001 return 0; 5191 return 0;
5002} 5192}
5003EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode); 5193
5194int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5195{
5196 int retval;
5197 u32 reg;
5198
5199 /*
5200 * Allocate eeprom data.
5201 */
5202 retval = rt2800_validate_eeprom(rt2x00dev);
5203 if (retval)
5204 return retval;
5205
5206 retval = rt2800_init_eeprom(rt2x00dev);
5207 if (retval)
5208 return retval;
5209
5210 /*
5211 * Enable rfkill polling by setting GPIO direction of the
5212 * rfkill switch GPIO pin correctly.
5213 */
5214 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5215 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
5216 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5217
5218 /*
5219 * Initialize hw specifications.
5220 */
5221 retval = rt2800_probe_hw_mode(rt2x00dev);
5222 if (retval)
5223 return retval;
5224
5225 /*
5226 * Set device capabilities.
5227 */
5228 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
5229 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
5230 if (!rt2x00_is_usb(rt2x00dev))
5231 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
5232
5233 /*
5234 * Set device requirements.
5235 */
5236 if (!rt2x00_is_soc(rt2x00dev))
5237 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
5238 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
5239 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
5240 if (!rt2800_hwcrypt_disabled(rt2x00dev))
5241 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
5242 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
5243 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
5244 if (rt2x00_is_usb(rt2x00dev))
5245 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
5246 else {
5247 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
5248 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
5249 }
5250
5251 /*
5252 * Set the rssi offset.
5253 */
5254 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
5255
5256 return 0;
5257}
5258EXPORT_SYMBOL_GPL(rt2800_probe_hw);
5004 5259
5005/* 5260/*
5006 * IEEE80211 stack callback functions. 5261 * IEEE80211 stack callback functions.
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 01:37:21 -0400