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path: root/drivers/net/wireless/iwlwifi/iwl-trans.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-trans.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans.c1926
1 files changed, 8 insertions, 1918 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans.c b/drivers/net/wireless/iwlwifi/iwl-trans.c
index b2e89077c684..1b20c4fb791b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans.c
@@ -60,1928 +60,18 @@
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 * 61 *
62 *****************************************************************************/ 62 *****************************************************************************/
63#include <linux/interrupt.h>
64#include <linux/debugfs.h>
65#include <linux/bitops.h>
66#include <linux/gfp.h>
67 63
68#include "iwl-trans.h" 64#include "iwl-trans.h"
69#include "iwl-trans-int-pcie.h"
70#include "iwl-csr.h"
71#include "iwl-prph.h"
72#include "iwl-shared.h"
73#include "iwl-eeprom.h"
74#include "iwl-agn-hw.h"
75 65
76static int iwl_trans_rx_alloc(struct iwl_trans *trans) 66int iwl_trans_send_cmd_pdu(struct iwl_trans *trans, u8 id,
67 u32 flags, u16 len, const void *data)
77{ 68{
78 struct iwl_trans_pcie *trans_pcie = 69 struct iwl_host_cmd cmd = {
79 IWL_TRANS_GET_PCIE_TRANS(trans); 70 .id = id,
80 struct iwl_rx_queue *rxq = &trans_pcie->rxq; 71 .len = { len, },
81 struct device *dev = bus(trans)->dev; 72 .data = { data, },
82 73 .flags = flags,
83 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
84
85 spin_lock_init(&rxq->lock);
86 INIT_LIST_HEAD(&rxq->rx_free);
87 INIT_LIST_HEAD(&rxq->rx_used);
88
89 if (WARN_ON(rxq->bd || rxq->rb_stts))
90 return -EINVAL;
91
92 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
93 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
94 &rxq->bd_dma, GFP_KERNEL);
95 if (!rxq->bd)
96 goto err_bd;
97 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
98
99 /*Allocate the driver's pointer to receive buffer status */
100 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
101 &rxq->rb_stts_dma, GFP_KERNEL);
102 if (!rxq->rb_stts)
103 goto err_rb_stts;
104 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
105
106 return 0;
107
108err_rb_stts:
109 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
110 rxq->bd, rxq->bd_dma);
111 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
112 rxq->bd = NULL;
113err_bd:
114 return -ENOMEM;
115}
116
117static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
118{
119 struct iwl_trans_pcie *trans_pcie =
120 IWL_TRANS_GET_PCIE_TRANS(trans);
121 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
122 int i;
123
124 /* Fill the rx_used queue with _all_ of the Rx buffers */
125 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
126 /* In the reset function, these buffers may have been allocated
127 * to an SKB, so we need to unmap and free potential storage */
128 if (rxq->pool[i].page != NULL) {
129 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
130 PAGE_SIZE << hw_params(trans).rx_page_order,
131 DMA_FROM_DEVICE);
132 __free_pages(rxq->pool[i].page,
133 hw_params(trans).rx_page_order);
134 rxq->pool[i].page = NULL;
135 }
136 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
137 }
138}
139
140static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
141 struct iwl_rx_queue *rxq)
142{
143 u32 rb_size;
144 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
145 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
146
147 rb_timeout = RX_RB_TIMEOUT;
148
149 if (iwlagn_mod_params.amsdu_size_8K)
150 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
151 else
152 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
153
154 /* Stop Rx DMA */
155 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
156
157 /* Reset driver's Rx queue write index */
158 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
159
160 /* Tell device where to find RBD circular buffer in DRAM */
161 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
162 (u32)(rxq->bd_dma >> 8));
163
164 /* Tell device where in DRAM to update its Rx status */
165 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
166 rxq->rb_stts_dma >> 4);
167
168 /* Enable Rx DMA
169 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
170 * the credit mechanism in 5000 HW RX FIFO
171 * Direct rx interrupts to hosts
172 * Rx buffer size 4 or 8k
173 * RB timeout 0x10
174 * 256 RBDs
175 */
176 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
177 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
178 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
179 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
180 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
181 rb_size|
182 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
183 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
184
185 /* Set interrupt coalescing timer to default (2048 usecs) */
186 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
187}
188
189static int iwl_rx_init(struct iwl_trans *trans)
190{
191 struct iwl_trans_pcie *trans_pcie =
192 IWL_TRANS_GET_PCIE_TRANS(trans);
193 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
194
195 int i, err;
196 unsigned long flags;
197
198 if (!rxq->bd) {
199 err = iwl_trans_rx_alloc(trans);
200 if (err)
201 return err;
202 }
203
204 spin_lock_irqsave(&rxq->lock, flags);
205 INIT_LIST_HEAD(&rxq->rx_free);
206 INIT_LIST_HEAD(&rxq->rx_used);
207
208 iwl_trans_rxq_free_rx_bufs(trans);
209
210 for (i = 0; i < RX_QUEUE_SIZE; i++)
211 rxq->queue[i] = NULL;
212
213 /* Set us so that we have processed and used all buffers, but have
214 * not restocked the Rx queue with fresh buffers */
215 rxq->read = rxq->write = 0;
216 rxq->write_actual = 0;
217 rxq->free_count = 0;
218 spin_unlock_irqrestore(&rxq->lock, flags);
219
220 iwlagn_rx_replenish(trans);
221
222 iwl_trans_rx_hw_init(trans, rxq);
223
224 spin_lock_irqsave(&trans->shrd->lock, flags);
225 rxq->need_update = 1;
226 iwl_rx_queue_update_write_ptr(trans, rxq);
227 spin_unlock_irqrestore(&trans->shrd->lock, flags);
228
229 return 0;
230}
231
232static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
233{
234 struct iwl_trans_pcie *trans_pcie =
235 IWL_TRANS_GET_PCIE_TRANS(trans);
236 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
237
238 unsigned long flags;
239
240 /*if rxq->bd is NULL, it means that nothing has been allocated,
241 * exit now */
242 if (!rxq->bd) {
243 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
244 return;
245 }
246
247 spin_lock_irqsave(&rxq->lock, flags);
248 iwl_trans_rxq_free_rx_bufs(trans);
249 spin_unlock_irqrestore(&rxq->lock, flags);
250
251 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
252 rxq->bd, rxq->bd_dma);
253 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
254 rxq->bd = NULL;
255
256 if (rxq->rb_stts)
257 dma_free_coherent(bus(trans)->dev,
258 sizeof(struct iwl_rb_status),
259 rxq->rb_stts, rxq->rb_stts_dma);
260 else
261 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
262 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
263 rxq->rb_stts = NULL;
264}
265
266static int iwl_trans_rx_stop(struct iwl_trans *trans)
267{
268
269 /* stop Rx DMA */
270 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
271 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
272 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
273}
274
275static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
276 struct iwl_dma_ptr *ptr, size_t size)
277{
278 if (WARN_ON(ptr->addr))
279 return -EINVAL;
280
281 ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
282 &ptr->dma, GFP_KERNEL);
283 if (!ptr->addr)
284 return -ENOMEM;
285 ptr->size = size;
286 return 0;
287}
288
289static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
290 struct iwl_dma_ptr *ptr)
291{
292 if (unlikely(!ptr->addr))
293 return;
294
295 dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
296 memset(ptr, 0, sizeof(*ptr));
297}
298
299static int iwl_trans_txq_alloc(struct iwl_trans *trans,
300 struct iwl_tx_queue *txq, int slots_num,
301 u32 txq_id)
302{
303 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
304 int i;
305
306 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
307 return -EINVAL;
308
309 txq->q.n_window = slots_num;
310
311 txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
312 GFP_KERNEL);
313 txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
314 GFP_KERNEL);
315
316 if (!txq->meta || !txq->cmd)
317 goto error;
318
319 if (txq_id == trans->shrd->cmd_queue)
320 for (i = 0; i < slots_num; i++) {
321 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
322 GFP_KERNEL);
323 if (!txq->cmd[i])
324 goto error;
325 }
326
327 /* Alloc driver data array and TFD circular buffer */
328 /* Driver private data, only for Tx (not command) queues,
329 * not shared with device. */
330 if (txq_id != trans->shrd->cmd_queue) {
331 txq->skbs = kzalloc(sizeof(txq->skbs[0]) *
332 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
333 if (!txq->skbs) {
334 IWL_ERR(trans, "kmalloc for auxiliary BD "
335 "structures failed\n");
336 goto error;
337 }
338 } else {
339 txq->skbs = NULL;
340 }
341
342 /* Circular buffer of transmit frame descriptors (TFDs),
343 * shared with device */
344 txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
345 &txq->q.dma_addr, GFP_KERNEL);
346 if (!txq->tfds) {
347 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
348 goto error;
349 }
350 txq->q.id = txq_id;
351
352 return 0;
353error:
354 kfree(txq->skbs);
355 txq->skbs = NULL;
356 /* since txq->cmd has been zeroed,
357 * all non allocated cmd[i] will be NULL */
358 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
359 for (i = 0; i < slots_num; i++)
360 kfree(txq->cmd[i]);
361 kfree(txq->meta);
362 kfree(txq->cmd);
363 txq->meta = NULL;
364 txq->cmd = NULL;
365
366 return -ENOMEM;
367
368}
369
370static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
371 int slots_num, u32 txq_id)
372{
373 int ret;
374
375 txq->need_update = 0;
376 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
377
378 /*
379 * For the default queues 0-3, set up the swq_id
380 * already -- all others need to get one later
381 * (if they need one at all).
382 */
383 if (txq_id < 4)
384 iwl_set_swq_id(txq, txq_id, txq_id);
385
386 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
387 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
388 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
389
390 /* Initialize queue's high/low-water marks, and head/tail indexes */
391 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
392 txq_id);
393 if (ret)
394 return ret;
395
396 /*
397 * Tell nic where to find circular buffer of Tx Frame Descriptors for
398 * given Tx queue, and enable the DMA channel used for that queue.
399 * Circular buffer (TFD queue in DRAM) physical base address */
400 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
401 txq->q.dma_addr >> 8);
402
403 return 0;
404}
405
406/**
407 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
408 */
409static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
410{
411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
412 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
413 struct iwl_queue *q = &txq->q;
414
415 if (!q->n_bd)
416 return;
417
418 while (q->write_ptr != q->read_ptr) {
419 /* The read_ptr needs to bound by q->n_window */
420 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr));
421 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
422 }
423}
424
425/**
426 * iwl_tx_queue_free - Deallocate DMA queue.
427 * @txq: Transmit queue to deallocate.
428 *
429 * Empty queue by removing and destroying all BD's.
430 * Free all buffers.
431 * 0-fill, but do not free "txq" descriptor structure.
432 */
433static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
434{
435 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
436 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
437 struct device *dev = bus(trans)->dev;
438 int i;
439 if (WARN_ON(!txq))
440 return;
441
442 iwl_tx_queue_unmap(trans, txq_id);
443
444 /* De-alloc array of command/tx buffers */
445
446 if (txq_id == trans->shrd->cmd_queue)
447 for (i = 0; i < txq->q.n_window; i++)
448 kfree(txq->cmd[i]);
449
450 /* De-alloc circular buffer of TFDs */
451 if (txq->q.n_bd) {
452 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
453 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
454 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
455 }
456
457 /* De-alloc array of per-TFD driver data */
458 kfree(txq->skbs);
459 txq->skbs = NULL;
460
461 /* deallocate arrays */
462 kfree(txq->cmd);
463 kfree(txq->meta);
464 txq->cmd = NULL;
465 txq->meta = NULL;
466
467 /* 0-fill queue descriptor structure */
468 memset(txq, 0, sizeof(*txq));
469}
470
471/**
472 * iwl_trans_tx_free - Free TXQ Context
473 *
474 * Destroy all TX DMA queues and structures
475 */
476static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
477{
478 int txq_id;
479 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
480
481 /* Tx queues */
482 if (trans_pcie->txq) {
483 for (txq_id = 0;
484 txq_id < hw_params(trans).max_txq_num; txq_id++)
485 iwl_tx_queue_free(trans, txq_id);
486 }
487
488 kfree(trans_pcie->txq);
489 trans_pcie->txq = NULL;
490
491 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
492
493 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
494}
495
496/**
497 * iwl_trans_tx_alloc - allocate TX context
498 * Allocate all Tx DMA structures and initialize them
499 *
500 * @param priv
501 * @return error code
502 */
503static int iwl_trans_tx_alloc(struct iwl_trans *trans)
504{
505 int ret;
506 int txq_id, slots_num;
507 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
508
509 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
510 sizeof(struct iwlagn_scd_bc_tbl);
511
512 /*It is not allowed to alloc twice, so warn when this happens.
513 * We cannot rely on the previous allocation, so free and fail */
514 if (WARN_ON(trans_pcie->txq)) {
515 ret = -EINVAL;
516 goto error;
517 }
518
519 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
520 scd_bc_tbls_size);
521 if (ret) {
522 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
523 goto error;
524 }
525
526 /* Alloc keep-warm buffer */
527 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
528 if (ret) {
529 IWL_ERR(trans, "Keep Warm allocation failed\n");
530 goto error;
531 }
532
533 trans_pcie->txq = kzalloc(sizeof(struct iwl_tx_queue) *
534 hw_params(trans).max_txq_num, GFP_KERNEL);
535 if (!trans_pcie->txq) {
536 IWL_ERR(trans, "Not enough memory for txq\n");
537 ret = ENOMEM;
538 goto error;
539 }
540
541 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
542 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
543 slots_num = (txq_id == trans->shrd->cmd_queue) ?
544 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
545 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
546 slots_num, txq_id);
547 if (ret) {
548 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
549 goto error;
550 }
551 }
552
553 return 0;
554
555error:
556 iwl_trans_pcie_tx_free(trans);
557
558 return ret;
559}
560static int iwl_tx_init(struct iwl_trans *trans)
561{
562 int ret;
563 int txq_id, slots_num;
564 unsigned long flags;
565 bool alloc = false;
566 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
567
568 if (!trans_pcie->txq) {
569 ret = iwl_trans_tx_alloc(trans);
570 if (ret)
571 goto error;
572 alloc = true;
573 }
574
575 spin_lock_irqsave(&trans->shrd->lock, flags);
576
577 /* Turn off all Tx DMA fifos */
578 iwl_write_prph(bus(trans), SCD_TXFACT, 0);
579
580 /* Tell NIC where to find the "keep warm" buffer */
581 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
582 trans_pcie->kw.dma >> 4);
583
584 spin_unlock_irqrestore(&trans->shrd->lock, flags);
585
586 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
587 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
588 slots_num = (txq_id == trans->shrd->cmd_queue) ?
589 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
590 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
591 slots_num, txq_id);
592 if (ret) {
593 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
594 goto error;
595 }
596 }
597
598 return 0;
599error:
600 /*Upon error, free only if we allocated something */
601 if (alloc)
602 iwl_trans_pcie_tx_free(trans);
603 return ret;
604}
605
606static void iwl_set_pwr_vmain(struct iwl_trans *trans)
607{
608/*
609 * (for documentation purposes)
610 * to set power to V_AUX, do:
611
612 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
613 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
614 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
615 ~APMG_PS_CTRL_MSK_PWR_SRC);
616 */
617
618 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
619 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
620 ~APMG_PS_CTRL_MSK_PWR_SRC);
621}
622
623static int iwl_nic_init(struct iwl_trans *trans)
624{
625 unsigned long flags;
626
627 /* nic_init */
628 spin_lock_irqsave(&trans->shrd->lock, flags);
629 iwl_apm_init(priv(trans));
630
631 /* Set interrupt coalescing calibration timer to default (512 usecs) */
632 iwl_write8(bus(trans), CSR_INT_COALESCING,
633 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
634
635 spin_unlock_irqrestore(&trans->shrd->lock, flags);
636
637 iwl_set_pwr_vmain(trans);
638
639 iwl_nic_config(priv(trans));
640
641 /* Allocate the RX queue, or reset if it is already allocated */
642 iwl_rx_init(trans);
643
644 /* Allocate or reset and init all Tx and Command queues */
645 if (iwl_tx_init(trans))
646 return -ENOMEM;
647
648 if (hw_params(trans).shadow_reg_enable) {
649 /* enable shadow regs in HW */
650 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
651 0x800FFFFF);
652 }
653
654 set_bit(STATUS_INIT, &trans->shrd->status);
655
656 return 0;
657}
658
659#define HW_READY_TIMEOUT (50)
660
661/* Note: returns poll_bit return value, which is >= 0 if success */
662static int iwl_set_hw_ready(struct iwl_trans *trans)
663{
664 int ret;
665
666 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
667 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
668
669 /* See if we got it */
670 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
671 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
672 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
673 HW_READY_TIMEOUT);
674
675 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
676 return ret;
677}
678
679/* Note: returns standard 0/-ERROR code */
680static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
681{
682 int ret;
683
684 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
685
686 ret = iwl_set_hw_ready(trans);
687 if (ret >= 0)
688 return 0;
689
690 /* If HW is not ready, prepare the conditions to check again */
691 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
692 CSR_HW_IF_CONFIG_REG_PREPARE);
693
694 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
695 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
696 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
697
698 if (ret < 0)
699 return ret;
700
701 /* HW should be ready by now, check again. */
702 ret = iwl_set_hw_ready(trans);
703 if (ret >= 0)
704 return 0;
705 return ret;
706}
707
708#define IWL_AC_UNSET -1
709
710struct queue_to_fifo_ac {
711 s8 fifo, ac;
712};
713
714static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
715 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
716 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
717 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
718 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
719 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
720 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
721 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
722 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
723 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
724 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
725 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
726};
727
728static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
729 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
730 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
731 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
732 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
733 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
734 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
735 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
736 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
737 { IWL_TX_FIFO_BE_IPAN, 2, },
738 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
739 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
740};
741
742static const u8 iwlagn_bss_ac_to_fifo[] = {
743 IWL_TX_FIFO_VO,
744 IWL_TX_FIFO_VI,
745 IWL_TX_FIFO_BE,
746 IWL_TX_FIFO_BK,
747};
748static const u8 iwlagn_bss_ac_to_queue[] = {
749 0, 1, 2, 3,
750};
751static const u8 iwlagn_pan_ac_to_fifo[] = {
752 IWL_TX_FIFO_VO_IPAN,
753 IWL_TX_FIFO_VI_IPAN,
754 IWL_TX_FIFO_BE_IPAN,
755 IWL_TX_FIFO_BK_IPAN,
756};
757static const u8 iwlagn_pan_ac_to_queue[] = {
758 7, 6, 5, 4,
759};
760
761static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
762{
763 int ret;
764 struct iwl_trans_pcie *trans_pcie =
765 IWL_TRANS_GET_PCIE_TRANS(trans);
766
767 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
768 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
769 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
770
771 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
772 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
773
774 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
775 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
776
777 if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
778 iwl_trans_pcie_prepare_card_hw(trans)) {
779 IWL_WARN(trans, "Exit HW not ready\n");
780 return -EIO;
781 }
782
783 /* If platform's RF_KILL switch is NOT set to KILL */
784 if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
785 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
786 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
787 else
788 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
789
790 if (iwl_is_rfkill(trans->shrd)) {
791 iwl_set_hw_rfkill_state(priv(trans), true);
792 iwl_enable_interrupts(trans);
793 return -ERFKILL;
794 }
795
796 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
797
798 ret = iwl_nic_init(trans);
799 if (ret) {
800 IWL_ERR(trans, "Unable to init nic\n");
801 return ret;
802 }
803
804 /* make sure rfkill handshake bits are cleared */
805 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
806 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
807 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
808
809 /* clear (again), then enable host interrupts */
810 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
811 iwl_enable_interrupts(trans);
812
813 /* really make sure rfkill handshake bits are cleared */
814 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
815 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
816
817 return 0;
818}
819
820/*
821 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
822 * must be called under priv->shrd->lock and mac access
823 */
824static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
825{
826 iwl_write_prph(bus(trans), SCD_TXFACT, mask);
827}
828
829static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
830{
831 const struct queue_to_fifo_ac *queue_to_fifo;
832 struct iwl_trans_pcie *trans_pcie =
833 IWL_TRANS_GET_PCIE_TRANS(trans);
834 u32 a;
835 unsigned long flags;
836 int i, chan;
837 u32 reg_val;
838
839 spin_lock_irqsave(&trans->shrd->lock, flags);
840
841 trans_pcie->scd_base_addr =
842 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
843 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
844 /* reset conext data memory */
845 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
846 a += 4)
847 iwl_write_targ_mem(bus(trans), a, 0);
848 /* reset tx status memory */
849 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
850 a += 4)
851 iwl_write_targ_mem(bus(trans), a, 0);
852 for (; a < trans_pcie->scd_base_addr +
853 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
854 a += 4)
855 iwl_write_targ_mem(bus(trans), a, 0);
856
857 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
858 trans_pcie->scd_bc_tbls.dma >> 10);
859
860 /* Enable DMA channel */
861 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
862 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
863 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
864 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
865
866 /* Update FH chicken bits */
867 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
868 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
869 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
870
871 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
872 SCD_QUEUECHAIN_SEL_ALL(trans));
873 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
874
875 /* initiate the queues */
876 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
877 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
878 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
879 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
880 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
881 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
882 SCD_CONTEXT_QUEUE_OFFSET(i) +
883 sizeof(u32),
884 ((SCD_WIN_SIZE <<
885 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
886 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
887 ((SCD_FRAME_LIMIT <<
888 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
889 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
890 }
891
892 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
893 IWL_MASK(0, hw_params(trans).max_txq_num));
894
895 /* Activate all Tx DMA/FIFO channels */
896 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
897
898 /* map queues to FIFOs */
899 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
900 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
901 else
902 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
903
904 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
905
906 /* make sure all queue are not stopped */
907 memset(&trans_pcie->queue_stopped[0], 0,
908 sizeof(trans_pcie->queue_stopped));
909 for (i = 0; i < 4; i++)
910 atomic_set(&trans_pcie->queue_stop_count[i], 0);
911
912 /* reset to 0 to enable all the queue first */
913 trans_pcie->txq_ctx_active_msk = 0;
914
915 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
916 IWLAGN_FIRST_AMPDU_QUEUE);
917 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
918 IWLAGN_FIRST_AMPDU_QUEUE);
919
920 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
921 int fifo = queue_to_fifo[i].fifo;
922 int ac = queue_to_fifo[i].ac;
923
924 iwl_txq_ctx_activate(trans_pcie, i);
925
926 if (fifo == IWL_TX_FIFO_UNUSED)
927 continue;
928
929 if (ac != IWL_AC_UNSET)
930 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
931 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
932 fifo, 0);
933 }
934
935 spin_unlock_irqrestore(&trans->shrd->lock, flags);
936
937 /* Enable L1-Active */
938 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
939 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
940}
941
942/**
943 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
944 */
945static int iwl_trans_tx_stop(struct iwl_trans *trans)
946{
947 int ch, txq_id;
948 unsigned long flags;
949 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
950
951 /* Turn off all Tx DMA fifos */
952 spin_lock_irqsave(&trans->shrd->lock, flags);
953
954 iwl_trans_txq_set_sched(trans, 0);
955
956 /* Stop each Tx DMA channel, and wait for it to be idle */
957 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
958 iwl_write_direct32(bus(trans),
959 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
960 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
961 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
962 1000))
963 IWL_ERR(trans, "Failing on timeout while stopping"
964 " DMA channel %d [0x%08x]", ch,
965 iwl_read_direct32(bus(trans),
966 FH_TSSR_TX_STATUS_REG));
967 }
968 spin_unlock_irqrestore(&trans->shrd->lock, flags);
969
970 if (!trans_pcie->txq) {
971 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
972 return 0;
973 }
974
975 /* Unmap DMA from host system and free skb's */
976 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
977 iwl_tx_queue_unmap(trans, txq_id);
978
979 return 0;
980}
981
982static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
983{
984 unsigned long flags;
985 struct iwl_trans_pcie *trans_pcie =
986 IWL_TRANS_GET_PCIE_TRANS(trans);
987
988 spin_lock_irqsave(&trans->shrd->lock, flags);
989 iwl_disable_interrupts(trans);
990 spin_unlock_irqrestore(&trans->shrd->lock, flags);
991
992 /* wait to make sure we flush pending tasklet*/
993 synchronize_irq(bus(trans)->irq);
994 tasklet_kill(&trans_pcie->irq_tasklet);
995}
996
997static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
998{
999 /* stop and reset the on-board processor */
1000 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1001
1002 /* tell the device to stop sending interrupts */
1003 iwl_trans_pcie_disable_sync_irq(trans);
1004
1005 /* device going down, Stop using ICT table */
1006 iwl_disable_ict(trans);
1007
1008 /*
1009 * If a HW restart happens during firmware loading,
1010 * then the firmware loading might call this function
1011 * and later it might be called again due to the
1012 * restart. So don't process again if the device is
1013 * already dead.
1014 */
1015 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1016 iwl_trans_tx_stop(trans);
1017 iwl_trans_rx_stop(trans);
1018
1019 /* Power-down device's busmaster DMA clocks */
1020 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1021 APMG_CLK_VAL_DMA_CLK_RQT);
1022 udelay(5);
1023 }
1024
1025 /* Make sure (redundant) we've released our request to stay awake */
1026 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1027 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1028
1029 /* Stop the device, and put it in low power state */
1030 iwl_apm_stop(priv(trans));
1031}
1032
1033static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1034 struct iwl_device_cmd *dev_cmd, u8 ctx, u8 sta_id)
1035{
1036 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1037 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1038 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1039 struct iwl_tx_cmd *tx_cmd = &dev_cmd->cmd.tx;
1040 struct iwl_cmd_meta *out_meta;
1041 struct iwl_tx_queue *txq;
1042 struct iwl_queue *q;
1043
1044 dma_addr_t phys_addr = 0;
1045 dma_addr_t txcmd_phys;
1046 dma_addr_t scratch_phys;
1047 u16 len, firstlen, secondlen;
1048 u16 seq_number = 0;
1049 u8 wait_write_ptr = 0;
1050 u8 txq_id;
1051 u8 tid = 0;
1052 bool is_agg = false;
1053 __le16 fc = hdr->frame_control;
1054 u8 hdr_len = ieee80211_hdrlen(fc);
1055
1056 /*
1057 * Send this frame after DTIM -- there's a special queue
1058 * reserved for this for contexts that support AP mode.
1059 */
1060 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1061 txq_id = trans_pcie->mcast_queue[ctx];
1062
1063 /*
1064 * The microcode will clear the more data
1065 * bit in the last frame it transmits.
1066 */
1067 hdr->frame_control |=
1068 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1069 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1070 txq_id = IWL_AUX_QUEUE;
1071 else
1072 txq_id =
1073 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1074
1075 if (ieee80211_is_data_qos(fc)) {
1076 u8 *qc = NULL;
1077 struct iwl_tid_data *tid_data;
1078 qc = ieee80211_get_qos_ctl(hdr);
1079 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1080 tid_data = &trans->shrd->tid_data[sta_id][tid];
1081
1082 if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
1083 return -1;
1084
1085 seq_number = tid_data->seq_number;
1086 seq_number &= IEEE80211_SCTL_SEQ;
1087 hdr->seq_ctrl = hdr->seq_ctrl &
1088 cpu_to_le16(IEEE80211_SCTL_FRAG);
1089 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1090 seq_number += 0x10;
1091 /* aggregation is on for this <sta,tid> */
1092 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1093 tid_data->agg.state == IWL_AGG_ON) {
1094 txq_id = tid_data->agg.txq_id;
1095 is_agg = true;
1096 }
1097 }
1098
1099 txq = &trans_pcie->txq[txq_id];
1100 q = &txq->q;
1101
1102 /* Set up driver data for this TFD */
1103 txq->skbs[q->write_ptr] = skb;
1104 txq->cmd[q->write_ptr] = dev_cmd;
1105
1106 dev_cmd->hdr.cmd = REPLY_TX;
1107 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1108 INDEX_TO_SEQ(q->write_ptr)));
1109
1110 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1111 out_meta = &txq->meta[q->write_ptr];
1112
1113 /*
1114 * Use the first empty entry in this queue's command buffer array
1115 * to contain the Tx command and MAC header concatenated together
1116 * (payload data will be in another buffer).
1117 * Size of this varies, due to varying MAC header length.
1118 * If end is not dword aligned, we'll have 2 extra bytes at the end
1119 * of the MAC header (device reads on dword boundaries).
1120 * We'll tell device about this padding later.
1121 */
1122 len = sizeof(struct iwl_tx_cmd) +
1123 sizeof(struct iwl_cmd_header) + hdr_len;
1124 firstlen = (len + 3) & ~3;
1125
1126 /* Tell NIC about any 2-byte padding after MAC header */
1127 if (firstlen != len)
1128 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1129
1130 /* Physical address of this Tx command's header (not MAC header!),
1131 * within command buffer array. */
1132 txcmd_phys = dma_map_single(bus(trans)->dev,
1133 &dev_cmd->hdr, firstlen,
1134 DMA_BIDIRECTIONAL);
1135 if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1136 return -1;
1137 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1138 dma_unmap_len_set(out_meta, len, firstlen);
1139
1140 if (!ieee80211_has_morefrags(fc)) {
1141 txq->need_update = 1;
1142 } else {
1143 wait_write_ptr = 1;
1144 txq->need_update = 0;
1145 }
1146
1147 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1148 * if any (802.11 null frames have no payload). */
1149 secondlen = skb->len - hdr_len;
1150 if (secondlen > 0) {
1151 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1152 secondlen, DMA_TO_DEVICE);
1153 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1154 dma_unmap_single(bus(trans)->dev,
1155 dma_unmap_addr(out_meta, mapping),
1156 dma_unmap_len(out_meta, len),
1157 DMA_BIDIRECTIONAL);
1158 return -1;
1159 }
1160 }
1161
1162 /* Attach buffers to TFD */
1163 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1164 if (secondlen > 0)
1165 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1166 secondlen, 0);
1167
1168 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1169 offsetof(struct iwl_tx_cmd, scratch);
1170
1171 /* take back ownership of DMA buffer to enable update */
1172 dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1173 DMA_BIDIRECTIONAL);
1174 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1175 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1176
1177 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1178 le16_to_cpu(dev_cmd->hdr.sequence));
1179 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1180 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1181 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1182
1183 /* Set up entry for this TFD in Tx byte-count array */
1184 if (is_agg)
1185 iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
1186 le16_to_cpu(tx_cmd->len));
1187
1188 dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1189 DMA_BIDIRECTIONAL);
1190
1191 trace_iwlwifi_dev_tx(priv(trans),
1192 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1193 sizeof(struct iwl_tfd),
1194 &dev_cmd->hdr, firstlen,
1195 skb->data + hdr_len, secondlen);
1196
1197 /* Tell device the write index *just past* this latest filled TFD */
1198 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1199 iwl_txq_update_write_ptr(trans, txq);
1200
1201 if (ieee80211_is_data_qos(fc)) {
1202 trans->shrd->tid_data[sta_id][tid].tfds_in_queue++;
1203 if (!ieee80211_has_morefrags(fc))
1204 trans->shrd->tid_data[sta_id][tid].seq_number =
1205 seq_number;
1206 }
1207
1208 /*
1209 * At this point the frame is "transmitted" successfully
1210 * and we will get a TX status notification eventually,
1211 * regardless of the value of ret. "ret" only indicates
1212 * whether or not we should update the write pointer.
1213 */
1214 if (iwl_queue_space(q) < q->high_mark) {
1215 if (wait_write_ptr) {
1216 txq->need_update = 1;
1217 iwl_txq_update_write_ptr(trans, txq);
1218 } else {
1219 iwl_stop_queue(trans, txq);
1220 }
1221 }
1222 return 0;
1223}
1224
1225static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1226{
1227 /* Remove all resets to allow NIC to operate */
1228 iwl_write32(bus(trans), CSR_RESET, 0);
1229}
1230
1231static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1232{
1233 struct iwl_trans_pcie *trans_pcie =
1234 IWL_TRANS_GET_PCIE_TRANS(trans);
1235 int err;
1236
1237 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1238
1239 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1240 iwl_irq_tasklet, (unsigned long)trans);
1241
1242 iwl_alloc_isr_ict(trans);
1243
1244 err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1245 DRV_NAME, trans);
1246 if (err) {
1247 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1248 iwl_free_isr_ict(trans);
1249 return err;
1250 }
1251
1252 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1253 return 0;
1254}
1255
1256static int iwlagn_txq_check_empty(struct iwl_trans *trans,
1257 int sta_id, u8 tid, int txq_id)
1258{
1259 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1260 struct iwl_queue *q = &trans_pcie->txq[txq_id].q;
1261 struct iwl_tid_data *tid_data = &trans->shrd->tid_data[sta_id][tid];
1262
1263 lockdep_assert_held(&trans->shrd->sta_lock);
1264
1265 switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
1266 case IWL_EMPTYING_HW_QUEUE_DELBA:
1267 /* We are reclaiming the last packet of the */
1268 /* aggregated HW queue */
1269 if ((txq_id == tid_data->agg.txq_id) &&
1270 (q->read_ptr == q->write_ptr)) {
1271 IWL_DEBUG_HT(trans,
1272 "HW queue empty: continue DELBA flow\n");
1273 iwl_trans_pcie_txq_agg_disable(trans, txq_id);
1274 tid_data->agg.state = IWL_AGG_OFF;
1275 iwl_stop_tx_ba_trans_ready(priv(trans),
1276 NUM_IWL_RXON_CTX,
1277 sta_id, tid);
1278 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1279 }
1280 break;
1281 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1282 /* We are reclaiming the last packet of the queue */
1283 if (tid_data->tfds_in_queue == 0) {
1284 IWL_DEBUG_HT(trans,
1285 "HW queue empty: continue ADDBA flow\n");
1286 tid_data->agg.state = IWL_AGG_ON;
1287 iwl_start_tx_ba_trans_ready(priv(trans),
1288 NUM_IWL_RXON_CTX,
1289 sta_id, tid);
1290 }
1291 break;
1292 }
1293
1294 return 0;
1295}
1296
1297static void iwl_free_tfds_in_queue(struct iwl_trans *trans,
1298 int sta_id, int tid, int freed)
1299{
1300 lockdep_assert_held(&trans->shrd->sta_lock);
1301
1302 if (trans->shrd->tid_data[sta_id][tid].tfds_in_queue >= freed)
1303 trans->shrd->tid_data[sta_id][tid].tfds_in_queue -= freed;
1304 else {
1305 IWL_DEBUG_TX(trans, "free more than tfds_in_queue (%u:%d)\n",
1306 trans->shrd->tid_data[sta_id][tid].tfds_in_queue,
1307 freed);
1308 trans->shrd->tid_data[sta_id][tid].tfds_in_queue = 0;
1309 }
1310}
1311
1312static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1313 int txq_id, int ssn, u32 status,
1314 struct sk_buff_head *skbs)
1315{
1316 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1317 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1318 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1319 int tfd_num = ssn & (txq->q.n_bd - 1);
1320 int freed = 0;
1321 u8 agg_state;
1322 bool cond;
1323
1324 txq->time_stamp = jiffies;
1325
1326 if (txq->sched_retry) {
1327 agg_state =
1328 trans->shrd->tid_data[txq->sta_id][txq->tid].agg.state;
1329 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1330 } else {
1331 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1332 }
1333
1334 if (txq->q.read_ptr != tfd_num) {
1335 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1336 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1337 ssn , tfd_num, txq_id, txq->swq_id);
1338 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1339 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1340 iwl_wake_queue(trans, txq);
1341 }
1342
1343 iwl_free_tfds_in_queue(trans, sta_id, tid, freed);
1344 iwlagn_txq_check_empty(trans, sta_id, tid, txq_id);
1345}
1346
1347static void iwl_trans_pcie_free(struct iwl_trans *trans)
1348{
1349 iwl_trans_pcie_tx_free(trans);
1350 iwl_trans_pcie_rx_free(trans);
1351 free_irq(bus(trans)->irq, trans);
1352 iwl_free_isr_ict(trans);
1353 trans->shrd->trans = NULL;
1354 kfree(trans);
1355}
1356
1357#ifdef CONFIG_PM
1358
1359static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1360{
1361 /*
1362 * This function is called when system goes into suspend state
1363 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1364 * first but since iwl_mac_stop() has no knowledge of who the caller is,
1365 * it will not call apm_ops.stop() to stop the DMA operation.
1366 * Calling apm_ops.stop here to make sure we stop the DMA.
1367 *
1368 * But of course ... if we have configured WoWLAN then we did other
1369 * things already :-)
1370 */
1371 if (!trans->shrd->wowlan)
1372 iwl_apm_stop(priv(trans));
1373
1374 return 0;
1375}
1376
1377static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1378{
1379 bool hw_rfkill = false;
1380
1381 iwl_enable_interrupts(trans);
1382
1383 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1384 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1385 hw_rfkill = true;
1386
1387 if (hw_rfkill)
1388 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1389 else
1390 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1391
1392 iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1393
1394 return 0;
1395}
1396#else /* CONFIG_PM */
1397static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1398{ return 0; }
1399
1400static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1401{ return 0; }
1402
1403#endif /* CONFIG_PM */
1404
1405static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1406 u8 ctx)
1407{
1408 u8 ac, txq_id;
1409 struct iwl_trans_pcie *trans_pcie =
1410 IWL_TRANS_GET_PCIE_TRANS(trans);
1411
1412 for (ac = 0; ac < AC_NUM; ac++) {
1413 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1414 IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n",
1415 ac,
1416 (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1417 ? "stopped" : "awake");
1418 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1419 }
1420}
1421
1422const struct iwl_trans_ops trans_ops_pcie;
1423
1424static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1425{
1426 struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1427 sizeof(struct iwl_trans_pcie),
1428 GFP_KERNEL);
1429 if (iwl_trans) {
1430 struct iwl_trans_pcie *trans_pcie =
1431 IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1432 iwl_trans->ops = &trans_ops_pcie;
1433 iwl_trans->shrd = shrd;
1434 trans_pcie->trans = iwl_trans;
1435 spin_lock_init(&iwl_trans->hcmd_lock);
1436 }
1437
1438 return iwl_trans;
1439}
1440
1441static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id)
1442{
1443 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1444
1445 iwl_stop_queue(trans, &trans_pcie->txq[txq_id]);
1446}
1447
1448#define IWL_FLUSH_WAIT_MS 2000
1449
1450static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1451{
1452 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1453 struct iwl_tx_queue *txq;
1454 struct iwl_queue *q;
1455 int cnt;
1456 unsigned long now = jiffies;
1457 int ret = 0;
1458
1459 /* waiting for all the tx frames complete might take a while */
1460 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1461 if (cnt == trans->shrd->cmd_queue)
1462 continue;
1463 txq = &trans_pcie->txq[cnt];
1464 q = &txq->q;
1465 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1466 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1467 msleep(1);
1468
1469 if (q->read_ptr != q->write_ptr) {
1470 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1471 ret = -ETIMEDOUT;
1472 break;
1473 }
1474 }
1475 return ret;
1476}
1477
1478/*
1479 * On every watchdog tick we check (latest) time stamp. If it does not
1480 * change during timeout period and queue is not empty we reset firmware.
1481 */
1482static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1483{
1484 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1485 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1486 struct iwl_queue *q = &txq->q;
1487 unsigned long timeout;
1488
1489 if (q->read_ptr == q->write_ptr) {
1490 txq->time_stamp = jiffies;
1491 return 0;
1492 }
1493
1494 timeout = txq->time_stamp +
1495 msecs_to_jiffies(hw_params(trans).wd_timeout);
1496
1497 if (time_after(jiffies, timeout)) {
1498 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1499 hw_params(trans).wd_timeout);
1500 IWL_ERR(trans, "Current read_ptr %d write_ptr %d\n",
1501 q->read_ptr, q->write_ptr);
1502 return 1;
1503 }
1504
1505 return 0;
1506}
1507
1508static const char *get_fh_string(int cmd)
1509{
1510 switch (cmd) {
1511 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1512 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1513 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1514 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1515 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1516 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1517 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1518 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1519 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1520 default:
1521 return "UNKNOWN";
1522 }
1523}
1524
1525int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1526{
1527 int i;
1528#ifdef CONFIG_IWLWIFI_DEBUG
1529 int pos = 0;
1530 size_t bufsz = 0;
1531#endif
1532 static const u32 fh_tbl[] = {
1533 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1534 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1535 FH_RSCSR_CHNL0_WPTR,
1536 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1537 FH_MEM_RSSR_SHARED_CTRL_REG,
1538 FH_MEM_RSSR_RX_STATUS_REG,
1539 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1540 FH_TSSR_TX_STATUS_REG,
1541 FH_TSSR_TX_ERROR_REG
1542 };
1543#ifdef CONFIG_IWLWIFI_DEBUG
1544 if (display) {
1545 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1546 *buf = kmalloc(bufsz, GFP_KERNEL);
1547 if (!*buf)
1548 return -ENOMEM;
1549 pos += scnprintf(*buf + pos, bufsz - pos,
1550 "FH register values:\n");
1551 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1552 pos += scnprintf(*buf + pos, bufsz - pos,
1553 " %34s: 0X%08x\n",
1554 get_fh_string(fh_tbl[i]),
1555 iwl_read_direct32(bus(trans), fh_tbl[i]));
1556 }
1557 return pos;
1558 }
1559#endif
1560 IWL_ERR(trans, "FH register values:\n");
1561 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1562 IWL_ERR(trans, " %34s: 0X%08x\n",
1563 get_fh_string(fh_tbl[i]),
1564 iwl_read_direct32(bus(trans), fh_tbl[i]));
1565 }
1566 return 0;
1567}
1568
1569static const char *get_csr_string(int cmd)
1570{
1571 switch (cmd) {
1572 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1573 IWL_CMD(CSR_INT_COALESCING);
1574 IWL_CMD(CSR_INT);
1575 IWL_CMD(CSR_INT_MASK);
1576 IWL_CMD(CSR_FH_INT_STATUS);
1577 IWL_CMD(CSR_GPIO_IN);
1578 IWL_CMD(CSR_RESET);
1579 IWL_CMD(CSR_GP_CNTRL);
1580 IWL_CMD(CSR_HW_REV);
1581 IWL_CMD(CSR_EEPROM_REG);
1582 IWL_CMD(CSR_EEPROM_GP);
1583 IWL_CMD(CSR_OTP_GP_REG);
1584 IWL_CMD(CSR_GIO_REG);
1585 IWL_CMD(CSR_GP_UCODE_REG);
1586 IWL_CMD(CSR_GP_DRIVER_REG);
1587 IWL_CMD(CSR_UCODE_DRV_GP1);
1588 IWL_CMD(CSR_UCODE_DRV_GP2);
1589 IWL_CMD(CSR_LED_REG);
1590 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1591 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1592 IWL_CMD(CSR_ANA_PLL_CFG);
1593 IWL_CMD(CSR_HW_REV_WA_REG);
1594 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1595 default:
1596 return "UNKNOWN";
1597 }
1598}
1599
1600void iwl_dump_csr(struct iwl_trans *trans)
1601{
1602 int i;
1603 static const u32 csr_tbl[] = {
1604 CSR_HW_IF_CONFIG_REG,
1605 CSR_INT_COALESCING,
1606 CSR_INT,
1607 CSR_INT_MASK,
1608 CSR_FH_INT_STATUS,
1609 CSR_GPIO_IN,
1610 CSR_RESET,
1611 CSR_GP_CNTRL,
1612 CSR_HW_REV,
1613 CSR_EEPROM_REG,
1614 CSR_EEPROM_GP,
1615 CSR_OTP_GP_REG,
1616 CSR_GIO_REG,
1617 CSR_GP_UCODE_REG,
1618 CSR_GP_DRIVER_REG,
1619 CSR_UCODE_DRV_GP1,
1620 CSR_UCODE_DRV_GP2,
1621 CSR_LED_REG,
1622 CSR_DRAM_INT_TBL_REG,
1623 CSR_GIO_CHICKEN_BITS,
1624 CSR_ANA_PLL_CFG,
1625 CSR_HW_REV_WA_REG,
1626 CSR_DBG_HPET_MEM_REG
1627 }; 74 };
1628 IWL_ERR(trans, "CSR values:\n");
1629 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1630 "CSR_INT_PERIODIC_REG)\n");
1631 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1632 IWL_ERR(trans, " %25s: 0X%08x\n",
1633 get_csr_string(csr_tbl[i]),
1634 iwl_read32(bus(trans), csr_tbl[i]));
1635 }
1636}
1637
1638#ifdef CONFIG_IWLWIFI_DEBUGFS
1639/* create and remove of files */
1640#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1641 if (!debugfs_create_file(#name, mode, parent, trans, \
1642 &iwl_dbgfs_##name##_ops)) \
1643 return -ENOMEM; \
1644} while (0)
1645
1646/* file operation */
1647#define DEBUGFS_READ_FUNC(name) \
1648static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1649 char __user *user_buf, \
1650 size_t count, loff_t *ppos);
1651
1652#define DEBUGFS_WRITE_FUNC(name) \
1653static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1654 const char __user *user_buf, \
1655 size_t count, loff_t *ppos);
1656
1657
1658static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1659{
1660 file->private_data = inode->i_private;
1661 return 0;
1662}
1663
1664#define DEBUGFS_READ_FILE_OPS(name) \
1665 DEBUGFS_READ_FUNC(name); \
1666static const struct file_operations iwl_dbgfs_##name##_ops = { \
1667 .read = iwl_dbgfs_##name##_read, \
1668 .open = iwl_dbgfs_open_file_generic, \
1669 .llseek = generic_file_llseek, \
1670};
1671 75
1672#define DEBUGFS_WRITE_FILE_OPS(name) \ 76 return iwl_trans_send_cmd(trans, &cmd);
1673 DEBUGFS_WRITE_FUNC(name); \
1674static const struct file_operations iwl_dbgfs_##name##_ops = { \
1675 .write = iwl_dbgfs_##name##_write, \
1676 .open = iwl_dbgfs_open_file_generic, \
1677 .llseek = generic_file_llseek, \
1678};
1679
1680#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1681 DEBUGFS_READ_FUNC(name); \
1682 DEBUGFS_WRITE_FUNC(name); \
1683static const struct file_operations iwl_dbgfs_##name##_ops = { \
1684 .write = iwl_dbgfs_##name##_write, \
1685 .read = iwl_dbgfs_##name##_read, \
1686 .open = iwl_dbgfs_open_file_generic, \
1687 .llseek = generic_file_llseek, \
1688};
1689
1690static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1691 char __user *user_buf,
1692 size_t count, loff_t *ppos)
1693{
1694 struct iwl_trans *trans = file->private_data;
1695 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1696 struct iwl_tx_queue *txq;
1697 struct iwl_queue *q;
1698 char *buf;
1699 int pos = 0;
1700 int cnt;
1701 int ret;
1702 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1703
1704 if (!trans_pcie->txq) {
1705 IWL_ERR(trans, "txq not ready\n");
1706 return -EAGAIN;
1707 }
1708 buf = kzalloc(bufsz, GFP_KERNEL);
1709 if (!buf)
1710 return -ENOMEM;
1711
1712 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1713 txq = &trans_pcie->txq[cnt];
1714 q = &txq->q;
1715 pos += scnprintf(buf + pos, bufsz - pos,
1716 "hwq %.2d: read=%u write=%u stop=%d"
1717 " swq_id=%#.2x (ac %d/hwq %d)\n",
1718 cnt, q->read_ptr, q->write_ptr,
1719 !!test_bit(cnt, trans_pcie->queue_stopped),
1720 txq->swq_id, txq->swq_id & 3,
1721 (txq->swq_id >> 2) & 0x1f);
1722 if (cnt >= 4)
1723 continue;
1724 /* for the ACs, display the stop count too */
1725 pos += scnprintf(buf + pos, bufsz - pos,
1726 " stop-count: %d\n",
1727 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1728 }
1729 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1730 kfree(buf);
1731 return ret;
1732} 77}
1733
1734static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1735 char __user *user_buf,
1736 size_t count, loff_t *ppos) {
1737 struct iwl_trans *trans = file->private_data;
1738 struct iwl_trans_pcie *trans_pcie =
1739 IWL_TRANS_GET_PCIE_TRANS(trans);
1740 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1741 char buf[256];
1742 int pos = 0;
1743 const size_t bufsz = sizeof(buf);
1744
1745 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1746 rxq->read);
1747 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1748 rxq->write);
1749 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1750 rxq->free_count);
1751 if (rxq->rb_stts) {
1752 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1753 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1754 } else {
1755 pos += scnprintf(buf + pos, bufsz - pos,
1756 "closed_rb_num: Not Allocated\n");
1757 }
1758 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1759}
1760
1761static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1762 char __user *user_buf,
1763 size_t count, loff_t *ppos)
1764{
1765 struct iwl_trans *trans = file->private_data;
1766 char *buf;
1767 int pos = 0;
1768 ssize_t ret = -ENOMEM;
1769
1770 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1771 if (buf) {
1772 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1773 kfree(buf);
1774 }
1775 return ret;
1776}
1777
1778static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1779 const char __user *user_buf,
1780 size_t count, loff_t *ppos)
1781{
1782 struct iwl_trans *trans = file->private_data;
1783 u32 event_log_flag;
1784 char buf[8];
1785 int buf_size;
1786
1787 memset(buf, 0, sizeof(buf));
1788 buf_size = min(count, sizeof(buf) - 1);
1789 if (copy_from_user(buf, user_buf, buf_size))
1790 return -EFAULT;
1791 if (sscanf(buf, "%d", &event_log_flag) != 1)
1792 return -EFAULT;
1793 if (event_log_flag == 1)
1794 iwl_dump_nic_event_log(trans, true, NULL, false);
1795
1796 return count;
1797}
1798
1799static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1800 char __user *user_buf,
1801 size_t count, loff_t *ppos) {
1802
1803 struct iwl_trans *trans = file->private_data;
1804 struct iwl_trans_pcie *trans_pcie =
1805 IWL_TRANS_GET_PCIE_TRANS(trans);
1806 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1807
1808 int pos = 0;
1809 char *buf;
1810 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1811 ssize_t ret;
1812
1813 buf = kzalloc(bufsz, GFP_KERNEL);
1814 if (!buf) {
1815 IWL_ERR(trans, "Can not allocate Buffer\n");
1816 return -ENOMEM;
1817 }
1818
1819 pos += scnprintf(buf + pos, bufsz - pos,
1820 "Interrupt Statistics Report:\n");
1821
1822 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1823 isr_stats->hw);
1824 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1825 isr_stats->sw);
1826 if (isr_stats->sw || isr_stats->hw) {
1827 pos += scnprintf(buf + pos, bufsz - pos,
1828 "\tLast Restarting Code: 0x%X\n",
1829 isr_stats->err_code);
1830 }
1831#ifdef CONFIG_IWLWIFI_DEBUG
1832 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1833 isr_stats->sch);
1834 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1835 isr_stats->alive);
1836#endif
1837 pos += scnprintf(buf + pos, bufsz - pos,
1838 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1839
1840 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1841 isr_stats->ctkill);
1842
1843 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1844 isr_stats->wakeup);
1845
1846 pos += scnprintf(buf + pos, bufsz - pos,
1847 "Rx command responses:\t\t %u\n", isr_stats->rx);
1848
1849 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1850 isr_stats->tx);
1851
1852 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1853 isr_stats->unhandled);
1854
1855 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1856 kfree(buf);
1857 return ret;
1858}
1859
1860static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1861 const char __user *user_buf,
1862 size_t count, loff_t *ppos)
1863{
1864 struct iwl_trans *trans = file->private_data;
1865 struct iwl_trans_pcie *trans_pcie =
1866 IWL_TRANS_GET_PCIE_TRANS(trans);
1867 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1868
1869 char buf[8];
1870 int buf_size;
1871 u32 reset_flag;
1872
1873 memset(buf, 0, sizeof(buf));
1874 buf_size = min(count, sizeof(buf) - 1);
1875 if (copy_from_user(buf, user_buf, buf_size))
1876 return -EFAULT;
1877 if (sscanf(buf, "%x", &reset_flag) != 1)
1878 return -EFAULT;
1879 if (reset_flag == 0)
1880 memset(isr_stats, 0, sizeof(*isr_stats));
1881
1882 return count;
1883}
1884
1885static ssize_t iwl_dbgfs_csr_write(struct file *file,
1886 const char __user *user_buf,
1887 size_t count, loff_t *ppos)
1888{
1889 struct iwl_trans *trans = file->private_data;
1890 char buf[8];
1891 int buf_size;
1892 int csr;
1893
1894 memset(buf, 0, sizeof(buf));
1895 buf_size = min(count, sizeof(buf) - 1);
1896 if (copy_from_user(buf, user_buf, buf_size))
1897 return -EFAULT;
1898 if (sscanf(buf, "%d", &csr) != 1)
1899 return -EFAULT;
1900
1901 iwl_dump_csr(trans);
1902
1903 return count;
1904}
1905
1906static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1907 char __user *user_buf,
1908 size_t count, loff_t *ppos)
1909{
1910 struct iwl_trans *trans = file->private_data;
1911 char *buf;
1912 int pos = 0;
1913 ssize_t ret = -EFAULT;
1914
1915 ret = pos = iwl_dump_fh(trans, &buf, true);
1916 if (buf) {
1917 ret = simple_read_from_buffer(user_buf,
1918 count, ppos, buf, pos);
1919 kfree(buf);
1920 }
1921
1922 return ret;
1923}
1924
1925DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1926DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1927DEBUGFS_READ_FILE_OPS(fh_reg);
1928DEBUGFS_READ_FILE_OPS(rx_queue);
1929DEBUGFS_READ_FILE_OPS(tx_queue);
1930DEBUGFS_WRITE_FILE_OPS(csr);
1931
1932/*
1933 * Create the debugfs files and directories
1934 *
1935 */
1936static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1937 struct dentry *dir)
1938{
1939 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1940 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1941 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1942 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1943 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1944 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1945 return 0;
1946}
1947#else
1948static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1949 struct dentry *dir)
1950{ return 0; }
1951
1952#endif /*CONFIG_IWLWIFI_DEBUGFS */
1953
1954const struct iwl_trans_ops trans_ops_pcie = {
1955 .alloc = iwl_trans_pcie_alloc,
1956 .request_irq = iwl_trans_pcie_request_irq,
1957 .start_device = iwl_trans_pcie_start_device,
1958 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1959 .stop_device = iwl_trans_pcie_stop_device,
1960
1961 .tx_start = iwl_trans_pcie_tx_start,
1962 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1963
1964 .send_cmd = iwl_trans_pcie_send_cmd,
1965 .send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
1966
1967 .tx = iwl_trans_pcie_tx,
1968 .reclaim = iwl_trans_pcie_reclaim,
1969
1970 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1971 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1972 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1973
1974 .kick_nic = iwl_trans_pcie_kick_nic,
1975
1976 .free = iwl_trans_pcie_free,
1977 .stop_queue = iwl_trans_pcie_stop_queue,
1978
1979 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1980
1981 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1982 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1983
1984 .suspend = iwl_trans_pcie_suspend,
1985 .resume = iwl_trans_pcie_resume,
1986};
1987
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-19 19:25:12 -0400