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path: root/drivers/net/wireless/iwlwifi/iwl-rx.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-rx.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-rx.c30
1 files changed, 19 insertions, 11 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c
index 38b2946b1d81..7cde9d76ff5d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-rx.c
@@ -376,7 +376,9 @@ int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
376{ 376{
377 int ret; 377 int ret;
378 unsigned long flags; 378 unsigned long flags;
379 unsigned int rb_size; 379 u32 rb_size;
380 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
381 const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */
380 382
381 spin_lock_irqsave(&priv->lock, flags); 383 spin_lock_irqsave(&priv->lock, flags);
382 ret = iwl_grab_nic_access(priv); 384 ret = iwl_grab_nic_access(priv);
@@ -398,26 +400,32 @@ int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
398 400
399 /* Tell device where to find RBD circular buffer in DRAM */ 401 /* Tell device where to find RBD circular buffer in DRAM */
400 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 402 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
401 rxq->dma_addr >> 8); 403 (u32)(rxq->dma_addr >> 8));
402 404
403 /* Tell device where in DRAM to update its Rx status */ 405 /* Tell device where in DRAM to update its Rx status */
404 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, 406 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
405 (priv->shared_phys + priv->rb_closed_offset) >> 4); 407 (priv->shared_phys + priv->rb_closed_offset) >> 4);
406 408
407 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */ 409 /* Enable Rx DMA
410 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set becuase of HW bug in
411 * the credit mechanism in 5000 HW RX FIFO
412 * Direct rx interrupts to hosts
413 * Rx buffer size 4 or 8k
414 * RB timeout 0x10
415 * 256 RBDs
416 */
408 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 417 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
409 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 418 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
419 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
410 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 420 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
411 rb_size | 421 rb_size|
412 /* 0x10 << 4 | */ 422 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
413 (RX_QUEUE_SIZE_LOG << 423 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
414 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
415
416 /*
417 * iwl_write32(priv,CSR_INT_COAL_REG,0);
418 */
419 424
420 iwl_release_nic_access(priv); 425 iwl_release_nic_access(priv);
426
427 iwl_write32(priv, CSR_INT_COALESCING, 0x40);
428
421 spin_unlock_irqrestore(&priv->lock, flags); 429 spin_unlock_irqrestore(&priv->lock, flags);
422 430
423 return 0; 431 return 0;