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path: root/drivers/net/wireless/iwlwifi/iwl-io.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-io.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.c193
1 files changed, 97 insertions, 96 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.c b/drivers/net/wireless/iwlwifi/iwl-io.c
index 83fdff381150..e2e3b5c9cf7f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.c
+++ b/drivers/net/wireless/iwlwifi/iwl-io.c
@@ -34,41 +34,41 @@
34 34
35#define IWL_POLL_INTERVAL 10 /* microseconds */ 35#define IWL_POLL_INTERVAL 10 /* microseconds */
36 36
37static inline void __iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask) 37static inline void __iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
38{ 38{
39 iwl_write32(bus, reg, iwl_read32(bus, reg) | mask); 39 iwl_write32(trans, reg, iwl_read32(trans, reg) | mask);
40} 40}
41 41
42static inline void __iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) 42static inline void __iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
43{ 43{
44 iwl_write32(bus, reg, iwl_read32(bus, reg) & ~mask); 44 iwl_write32(trans, reg, iwl_read32(trans, reg) & ~mask);
45} 45}
46 46
47void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask) 47void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
48{ 48{
49 unsigned long flags; 49 unsigned long flags;
50 50
51 spin_lock_irqsave(&bus->reg_lock, flags); 51 spin_lock_irqsave(&trans->reg_lock, flags);
52 __iwl_set_bit(bus, reg, mask); 52 __iwl_set_bit(trans, reg, mask);
53 spin_unlock_irqrestore(&bus->reg_lock, flags); 53 spin_unlock_irqrestore(&trans->reg_lock, flags);
54} 54}
55 55
56void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) 56void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
57{ 57{
58 unsigned long flags; 58 unsigned long flags;
59 59
60 spin_lock_irqsave(&bus->reg_lock, flags); 60 spin_lock_irqsave(&trans->reg_lock, flags);
61 __iwl_clear_bit(bus, reg, mask); 61 __iwl_clear_bit(trans, reg, mask);
62 spin_unlock_irqrestore(&bus->reg_lock, flags); 62 spin_unlock_irqrestore(&trans->reg_lock, flags);
63} 63}
64 64
65int iwl_poll_bit(struct iwl_bus *bus, u32 addr, 65int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
66 u32 bits, u32 mask, int timeout) 66 u32 bits, u32 mask, int timeout)
67{ 67{
68 int t = 0; 68 int t = 0;
69 69
70 do { 70 do {
71 if ((iwl_read32(bus, addr) & mask) == (bits & mask)) 71 if ((iwl_read32(trans, addr) & mask) == (bits & mask))
72 return t; 72 return t;
73 udelay(IWL_POLL_INTERVAL); 73 udelay(IWL_POLL_INTERVAL);
74 t += IWL_POLL_INTERVAL; 74 t += IWL_POLL_INTERVAL;
@@ -77,14 +77,15 @@ int iwl_poll_bit(struct iwl_bus *bus, u32 addr,
77 return -ETIMEDOUT; 77 return -ETIMEDOUT;
78} 78}
79 79
80int iwl_grab_nic_access_silent(struct iwl_bus *bus) 80int iwl_grab_nic_access_silent(struct iwl_trans *trans)
81{ 81{
82 int ret; 82 int ret;
83 83
84 lockdep_assert_held(&bus->reg_lock); 84 lockdep_assert_held(&trans->reg_lock);
85 85
86 /* this bit wakes up the NIC */ 86 /* this bit wakes up the NIC */
87 __iwl_set_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 87 __iwl_set_bit(trans, CSR_GP_CNTRL,
88 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
88 89
89 /* 90 /*
90 * These bits say the device is running, and should keep running for 91 * These bits say the device is running, and should keep running for
@@ -105,70 +106,70 @@ int iwl_grab_nic_access_silent(struct iwl_bus *bus)
105 * 5000 series and later (including 1000 series) have non-volatile SRAM, 106 * 5000 series and later (including 1000 series) have non-volatile SRAM,
106 * and do not save/restore SRAM when power cycling. 107 * and do not save/restore SRAM when power cycling.
107 */ 108 */
108 ret = iwl_poll_bit(bus, CSR_GP_CNTRL, 109 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
109 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 110 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
110 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 111 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
111 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 112 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
112 if (ret < 0) { 113 if (ret < 0) {
113 iwl_write32(bus, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 114 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
114 return -EIO; 115 return -EIO;
115 } 116 }
116 117
117 return 0; 118 return 0;
118} 119}
119 120
120int iwl_grab_nic_access(struct iwl_bus *bus) 121int iwl_grab_nic_access(struct iwl_trans *trans)
121{ 122{
122 int ret = iwl_grab_nic_access_silent(bus); 123 int ret = iwl_grab_nic_access_silent(trans);
123 if (ret) { 124 if (ret) {
124 u32 val = iwl_read32(bus, CSR_GP_CNTRL); 125 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
125 IWL_ERR(bus, 126 IWL_ERR(trans,
126 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); 127 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
127 } 128 }
128 129
129 return ret; 130 return ret;
130} 131}
131 132
132void iwl_release_nic_access(struct iwl_bus *bus) 133void iwl_release_nic_access(struct iwl_trans *trans)
133{ 134{
134 lockdep_assert_held(&bus->reg_lock); 135 lockdep_assert_held(&trans->reg_lock);
135 __iwl_clear_bit(bus, CSR_GP_CNTRL, 136 __iwl_clear_bit(trans, CSR_GP_CNTRL,
136 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 137 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
137} 138}
138 139
139u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg) 140u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
140{ 141{
141 u32 value; 142 u32 value;
142 unsigned long flags; 143 unsigned long flags;
143 144
144 spin_lock_irqsave(&bus->reg_lock, flags); 145 spin_lock_irqsave(&trans->reg_lock, flags);
145 iwl_grab_nic_access(bus); 146 iwl_grab_nic_access(trans);
146 value = iwl_read32(bus, reg); 147 value = iwl_read32(trans, reg);
147 iwl_release_nic_access(bus); 148 iwl_release_nic_access(trans);
148 spin_unlock_irqrestore(&bus->reg_lock, flags); 149 spin_unlock_irqrestore(&trans->reg_lock, flags);
149 150
150 return value; 151 return value;
151} 152}
152 153
153void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value) 154void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
154{ 155{
155 unsigned long flags; 156 unsigned long flags;
156 157
157 spin_lock_irqsave(&bus->reg_lock, flags); 158 spin_lock_irqsave(&trans->reg_lock, flags);
158 if (!iwl_grab_nic_access(bus)) { 159 if (!iwl_grab_nic_access(trans)) {
159 iwl_write32(bus, reg, value); 160 iwl_write32(trans, reg, value);
160 iwl_release_nic_access(bus); 161 iwl_release_nic_access(trans);
161 } 162 }
162 spin_unlock_irqrestore(&bus->reg_lock, flags); 163 spin_unlock_irqrestore(&trans->reg_lock, flags);
163} 164}
164 165
165int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask, 166int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
166 int timeout) 167 int timeout)
167{ 168{
168 int t = 0; 169 int t = 0;
169 170
170 do { 171 do {
171 if ((iwl_read_direct32(bus, addr) & mask) == mask) 172 if ((iwl_read_direct32(trans, addr) & mask) == mask)
172 return t; 173 return t;
173 udelay(IWL_POLL_INTERVAL); 174 udelay(IWL_POLL_INTERVAL);
174 t += IWL_POLL_INTERVAL; 175 t += IWL_POLL_INTERVAL;
@@ -177,135 +178,135 @@ int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask,
177 return -ETIMEDOUT; 178 return -ETIMEDOUT;
178} 179}
179 180
180static inline u32 __iwl_read_prph(struct iwl_bus *bus, u32 reg) 181static inline u32 __iwl_read_prph(struct iwl_trans *trans, u32 reg)
181{ 182{
182 iwl_write32(bus, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); 183 iwl_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
183 rmb(); 184 rmb();
184 return iwl_read32(bus, HBUS_TARG_PRPH_RDAT); 185 return iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
185} 186}
186 187
187static inline void __iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val) 188static inline void __iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
188{ 189{
189 iwl_write32(bus, HBUS_TARG_PRPH_WADDR, 190 iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
190 ((addr & 0x0000FFFF) | (3 << 24))); 191 ((addr & 0x0000FFFF) | (3 << 24)));
191 wmb(); 192 wmb();
192 iwl_write32(bus, HBUS_TARG_PRPH_WDAT, val); 193 iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
193} 194}
194 195
195u32 iwl_read_prph(struct iwl_bus *bus, u32 reg) 196u32 iwl_read_prph(struct iwl_trans *trans, u32 reg)
196{ 197{
197 unsigned long flags; 198 unsigned long flags;
198 u32 val; 199 u32 val;
199 200
200 spin_lock_irqsave(&bus->reg_lock, flags); 201 spin_lock_irqsave(&trans->reg_lock, flags);
201 iwl_grab_nic_access(bus); 202 iwl_grab_nic_access(trans);
202 val = __iwl_read_prph(bus, reg); 203 val = __iwl_read_prph(trans, reg);
203 iwl_release_nic_access(bus); 204 iwl_release_nic_access(trans);
204 spin_unlock_irqrestore(&bus->reg_lock, flags); 205 spin_unlock_irqrestore(&trans->reg_lock, flags);
205 return val; 206 return val;
206} 207}
207 208
208void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val) 209void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
209{ 210{
210 unsigned long flags; 211 unsigned long flags;
211 212
212 spin_lock_irqsave(&bus->reg_lock, flags); 213 spin_lock_irqsave(&trans->reg_lock, flags);
213 if (!iwl_grab_nic_access(bus)) { 214 if (!iwl_grab_nic_access(trans)) {
214 __iwl_write_prph(bus, addr, val); 215 __iwl_write_prph(trans, addr, val);
215 iwl_release_nic_access(bus); 216 iwl_release_nic_access(trans);
216 } 217 }
217 spin_unlock_irqrestore(&bus->reg_lock, flags); 218 spin_unlock_irqrestore(&trans->reg_lock, flags);
218} 219}
219 220
220void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask) 221void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
221{ 222{
222 unsigned long flags; 223 unsigned long flags;
223 224
224 spin_lock_irqsave(&bus->reg_lock, flags); 225 spin_lock_irqsave(&trans->reg_lock, flags);
225 iwl_grab_nic_access(bus); 226 iwl_grab_nic_access(trans);
226 __iwl_write_prph(bus, reg, __iwl_read_prph(bus, reg) | mask); 227 __iwl_write_prph(trans, reg, __iwl_read_prph(trans, reg) | mask);
227 iwl_release_nic_access(bus); 228 iwl_release_nic_access(trans);
228 spin_unlock_irqrestore(&bus->reg_lock, flags); 229 spin_unlock_irqrestore(&trans->reg_lock, flags);
229} 230}
230 231
231void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg, 232void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
232 u32 bits, u32 mask) 233 u32 bits, u32 mask)
233{ 234{
234 unsigned long flags; 235 unsigned long flags;
235 236
236 spin_lock_irqsave(&bus->reg_lock, flags); 237 spin_lock_irqsave(&trans->reg_lock, flags);
237 iwl_grab_nic_access(bus); 238 iwl_grab_nic_access(trans);
238 __iwl_write_prph(bus, reg, 239 __iwl_write_prph(trans, reg,
239 (__iwl_read_prph(bus, reg) & mask) | bits); 240 (__iwl_read_prph(trans, reg) & mask) | bits);
240 iwl_release_nic_access(bus); 241 iwl_release_nic_access(trans);
241 spin_unlock_irqrestore(&bus->reg_lock, flags); 242 spin_unlock_irqrestore(&trans->reg_lock, flags);
242} 243}
243 244
244void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask) 245void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
245{ 246{
246 unsigned long flags; 247 unsigned long flags;
247 u32 val; 248 u32 val;
248 249
249 spin_lock_irqsave(&bus->reg_lock, flags); 250 spin_lock_irqsave(&trans->reg_lock, flags);
250 iwl_grab_nic_access(bus); 251 iwl_grab_nic_access(trans);
251 val = __iwl_read_prph(bus, reg); 252 val = __iwl_read_prph(trans, reg);
252 __iwl_write_prph(bus, reg, (val & ~mask)); 253 __iwl_write_prph(trans, reg, (val & ~mask));
253 iwl_release_nic_access(bus); 254 iwl_release_nic_access(trans);
254 spin_unlock_irqrestore(&bus->reg_lock, flags); 255 spin_unlock_irqrestore(&trans->reg_lock, flags);
255} 256}
256 257
257void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr, 258void _iwl_read_targ_mem_words(struct iwl_trans *trans, u32 addr,
258 void *buf, int words) 259 void *buf, int words)
259{ 260{
260 unsigned long flags; 261 unsigned long flags;
261 int offs; 262 int offs;
262 u32 *vals = buf; 263 u32 *vals = buf;
263 264
264 spin_lock_irqsave(&bus->reg_lock, flags); 265 spin_lock_irqsave(&trans->reg_lock, flags);
265 iwl_grab_nic_access(bus); 266 iwl_grab_nic_access(trans);
266 267
267 iwl_write32(bus, HBUS_TARG_MEM_RADDR, addr); 268 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
268 rmb(); 269 rmb();
269 270
270 for (offs = 0; offs < words; offs++) 271 for (offs = 0; offs < words; offs++)
271 vals[offs] = iwl_read32(bus, HBUS_TARG_MEM_RDAT); 272 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
272 273
273 iwl_release_nic_access(bus); 274 iwl_release_nic_access(trans);
274 spin_unlock_irqrestore(&bus->reg_lock, flags); 275 spin_unlock_irqrestore(&trans->reg_lock, flags);
275} 276}
276 277
277u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr) 278u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr)
278{ 279{
279 u32 value; 280 u32 value;
280 281
281 _iwl_read_targ_mem_words(bus, addr, &value, 1); 282 _iwl_read_targ_mem_words(trans, addr, &value, 1);
282 283
283 return value; 284 return value;
284} 285}
285 286
286int _iwl_write_targ_mem_words(struct iwl_bus *bus, u32 addr, 287int _iwl_write_targ_mem_words(struct iwl_trans *trans, u32 addr,
287 void *buf, int words) 288 void *buf, int words)
288{ 289{
289 unsigned long flags; 290 unsigned long flags;
290 int offs, result = 0; 291 int offs, result = 0;
291 u32 *vals = buf; 292 u32 *vals = buf;
292 293
293 spin_lock_irqsave(&bus->reg_lock, flags); 294 spin_lock_irqsave(&trans->reg_lock, flags);
294 if (!iwl_grab_nic_access(bus)) { 295 if (!iwl_grab_nic_access(trans)) {
295 iwl_write32(bus, HBUS_TARG_MEM_WADDR, addr); 296 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
296 wmb(); 297 wmb();
297 298
298 for (offs = 0; offs < words; offs++) 299 for (offs = 0; offs < words; offs++)
299 iwl_write32(bus, HBUS_TARG_MEM_WDAT, vals[offs]); 300 iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
300 iwl_release_nic_access(bus); 301 iwl_release_nic_access(trans);
301 } else 302 } else
302 result = -EBUSY; 303 result = -EBUSY;
303 spin_unlock_irqrestore(&bus->reg_lock, flags); 304 spin_unlock_irqrestore(&trans->reg_lock, flags);
304 305
305 return result; 306 return result;
306} 307}
307 308
308int iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val) 309int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val)
309{ 310{
310 return _iwl_write_targ_mem_words(bus, addr, &val, 1); 311 return _iwl_write_targ_mem_words(trans, addr, &val, 1);
311} 312}