diff options
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-agn.c')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-agn.c | 266 |
1 files changed, 21 insertions, 245 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 7adc60ea03cb..28ac0d44555e 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
@@ -409,7 +409,7 @@ int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |||
409 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | 409 | * Tell nic where to find circular buffer of Tx Frame Descriptors for |
410 | * given Tx queue, and enable the DMA channel used for that queue. | 410 | * given Tx queue, and enable the DMA channel used for that queue. |
411 | * | 411 | * |
412 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | 412 | * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA |
413 | * channels supported in hardware. | 413 | * channels supported in hardware. |
414 | */ | 414 | */ |
415 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | 415 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, |
@@ -845,191 +845,6 @@ static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |||
845 | tasklet_kill(&priv->irq_tasklet); | 845 | tasklet_kill(&priv->irq_tasklet); |
846 | } | 846 | } |
847 | 847 | ||
848 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) | ||
849 | { | ||
850 | u32 inta, handled = 0; | ||
851 | u32 inta_fh; | ||
852 | unsigned long flags; | ||
853 | u32 i; | ||
854 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
855 | u32 inta_mask; | ||
856 | #endif | ||
857 | |||
858 | spin_lock_irqsave(&priv->lock, flags); | ||
859 | |||
860 | /* Ack/clear/reset pending uCode interrupts. | ||
861 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | ||
862 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | ||
863 | inta = iwl_read32(priv, CSR_INT); | ||
864 | iwl_write32(priv, CSR_INT, inta); | ||
865 | |||
866 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | ||
867 | * Any new interrupts that happen after this, either while we're | ||
868 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | ||
869 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | ||
870 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | ||
871 | |||
872 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
873 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { | ||
874 | /* just for debug */ | ||
875 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | ||
876 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | ||
877 | inta, inta_mask, inta_fh); | ||
878 | } | ||
879 | #endif | ||
880 | |||
881 | spin_unlock_irqrestore(&priv->lock, flags); | ||
882 | |||
883 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | ||
884 | * atomic, make sure that inta covers all the interrupts that | ||
885 | * we've discovered, even if FH interrupt came in just after | ||
886 | * reading CSR_INT. */ | ||
887 | if (inta_fh & CSR49_FH_INT_RX_MASK) | ||
888 | inta |= CSR_INT_BIT_FH_RX; | ||
889 | if (inta_fh & CSR49_FH_INT_TX_MASK) | ||
890 | inta |= CSR_INT_BIT_FH_TX; | ||
891 | |||
892 | /* Now service all interrupt bits discovered above. */ | ||
893 | if (inta & CSR_INT_BIT_HW_ERR) { | ||
894 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); | ||
895 | |||
896 | /* Tell the device to stop sending interrupts */ | ||
897 | iwl_disable_interrupts(priv); | ||
898 | |||
899 | priv->isr_stats.hw++; | ||
900 | iwl_irq_handle_error(priv); | ||
901 | |||
902 | handled |= CSR_INT_BIT_HW_ERR; | ||
903 | |||
904 | return; | ||
905 | } | ||
906 | |||
907 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
908 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { | ||
909 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ | ||
910 | if (inta & CSR_INT_BIT_SCD) { | ||
911 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | ||
912 | "the frame/frames.\n"); | ||
913 | priv->isr_stats.sch++; | ||
914 | } | ||
915 | |||
916 | /* Alive notification via Rx interrupt will do the real work */ | ||
917 | if (inta & CSR_INT_BIT_ALIVE) { | ||
918 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | ||
919 | priv->isr_stats.alive++; | ||
920 | } | ||
921 | } | ||
922 | #endif | ||
923 | /* Safely ignore these bits for debug checks below */ | ||
924 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | ||
925 | |||
926 | /* HW RF KILL switch toggled */ | ||
927 | if (inta & CSR_INT_BIT_RF_KILL) { | ||
928 | int hw_rf_kill = 0; | ||
929 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | ||
930 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | ||
931 | hw_rf_kill = 1; | ||
932 | |||
933 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", | ||
934 | hw_rf_kill ? "disable radio" : "enable radio"); | ||
935 | |||
936 | priv->isr_stats.rfkill++; | ||
937 | |||
938 | /* driver only loads ucode once setting the interface up. | ||
939 | * the driver allows loading the ucode even if the radio | ||
940 | * is killed. Hence update the killswitch state here. The | ||
941 | * rfkill handler will care about restarting if needed. | ||
942 | */ | ||
943 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | ||
944 | if (hw_rf_kill) | ||
945 | set_bit(STATUS_RF_KILL_HW, &priv->status); | ||
946 | else | ||
947 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | ||
948 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); | ||
949 | } | ||
950 | |||
951 | handled |= CSR_INT_BIT_RF_KILL; | ||
952 | } | ||
953 | |||
954 | /* Chip got too hot and stopped itself */ | ||
955 | if (inta & CSR_INT_BIT_CT_KILL) { | ||
956 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | ||
957 | priv->isr_stats.ctkill++; | ||
958 | handled |= CSR_INT_BIT_CT_KILL; | ||
959 | } | ||
960 | |||
961 | /* Error detected by uCode */ | ||
962 | if (inta & CSR_INT_BIT_SW_ERR) { | ||
963 | IWL_ERR(priv, "Microcode SW error detected. " | ||
964 | " Restarting 0x%X.\n", inta); | ||
965 | priv->isr_stats.sw++; | ||
966 | iwl_irq_handle_error(priv); | ||
967 | handled |= CSR_INT_BIT_SW_ERR; | ||
968 | } | ||
969 | |||
970 | /* | ||
971 | * uCode wakes up after power-down sleep. | ||
972 | * Tell device about any new tx or host commands enqueued, | ||
973 | * and about any Rx buffers made available while asleep. | ||
974 | */ | ||
975 | if (inta & CSR_INT_BIT_WAKEUP) { | ||
976 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | ||
977 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | ||
978 | for (i = 0; i < priv->hw_params.max_txq_num; i++) | ||
979 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | ||
980 | priv->isr_stats.wakeup++; | ||
981 | handled |= CSR_INT_BIT_WAKEUP; | ||
982 | } | ||
983 | |||
984 | /* All uCode command responses, including Tx command responses, | ||
985 | * Rx "responses" (frame-received notification), and other | ||
986 | * notifications from uCode come through here*/ | ||
987 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | ||
988 | iwl_rx_handle(priv); | ||
989 | priv->isr_stats.rx++; | ||
990 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | ||
991 | } | ||
992 | |||
993 | /* This "Tx" DMA channel is used only for loading uCode */ | ||
994 | if (inta & CSR_INT_BIT_FH_TX) { | ||
995 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); | ||
996 | priv->isr_stats.tx++; | ||
997 | handled |= CSR_INT_BIT_FH_TX; | ||
998 | /* Wake up uCode load routine, now that load is complete */ | ||
999 | priv->ucode_write_complete = 1; | ||
1000 | wake_up_interruptible(&priv->wait_command_queue); | ||
1001 | } | ||
1002 | |||
1003 | if (inta & ~handled) { | ||
1004 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | ||
1005 | priv->isr_stats.unhandled++; | ||
1006 | } | ||
1007 | |||
1008 | if (inta & ~(priv->inta_mask)) { | ||
1009 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", | ||
1010 | inta & ~priv->inta_mask); | ||
1011 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); | ||
1012 | } | ||
1013 | |||
1014 | /* Re-enable all interrupts */ | ||
1015 | /* only Re-enable if disabled by irq */ | ||
1016 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | ||
1017 | iwl_enable_interrupts(priv); | ||
1018 | /* Re-enable RF_KILL if it occurred */ | ||
1019 | else if (handled & CSR_INT_BIT_RF_KILL) | ||
1020 | iwl_enable_rfkill_int(priv); | ||
1021 | |||
1022 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
1023 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { | ||
1024 | inta = iwl_read32(priv, CSR_INT); | ||
1025 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | ||
1026 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | ||
1027 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " | ||
1028 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | ||
1029 | } | ||
1030 | #endif | ||
1031 | } | ||
1032 | |||
1033 | /* tasklet for iwlagn interrupt */ | 848 | /* tasklet for iwlagn interrupt */ |
1034 | static void iwl_irq_tasklet(struct iwl_priv *priv) | 849 | static void iwl_irq_tasklet(struct iwl_priv *priv) |
1035 | { | 850 | { |
@@ -1171,7 +986,7 @@ static void iwl_irq_tasklet(struct iwl_priv *priv) | |||
1171 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | 986 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1172 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | 987 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1173 | iwl_write32(priv, CSR_FH_INT_STATUS, | 988 | iwl_write32(priv, CSR_FH_INT_STATUS, |
1174 | CSR49_FH_INT_RX_MASK); | 989 | CSR_FH_INT_RX_MASK); |
1175 | } | 990 | } |
1176 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | 991 | if (inta & CSR_INT_BIT_RX_PERIODIC) { |
1177 | handled |= CSR_INT_BIT_RX_PERIODIC; | 992 | handled |= CSR_INT_BIT_RX_PERIODIC; |
@@ -1209,7 +1024,7 @@ static void iwl_irq_tasklet(struct iwl_priv *priv) | |||
1209 | 1024 | ||
1210 | /* This "Tx" DMA channel is used only for loading uCode */ | 1025 | /* This "Tx" DMA channel is used only for loading uCode */ |
1211 | if (inta & CSR_INT_BIT_FH_TX) { | 1026 | if (inta & CSR_INT_BIT_FH_TX) { |
1212 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | 1027 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
1213 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); | 1028 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
1214 | priv->isr_stats.tx++; | 1029 | priv->isr_stats.tx++; |
1215 | handled |= CSR_INT_BIT_FH_TX; | 1030 | handled |= CSR_INT_BIT_FH_TX; |
@@ -1444,28 +1259,19 @@ static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |||
1444 | 1259 | ||
1445 | switch (api_ver) { | 1260 | switch (api_ver) { |
1446 | default: | 1261 | default: |
1447 | /* | 1262 | hdr_size = 28; |
1448 | * 4965 doesn't revision the firmware file format | 1263 | if (ucode_raw->size < hdr_size) { |
1449 | * along with the API version, it always uses v1 | 1264 | IWL_ERR(priv, "File size too small!\n"); |
1450 | * file format. | 1265 | return -EINVAL; |
1451 | */ | ||
1452 | if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) != | ||
1453 | CSR_HW_REV_TYPE_4965) { | ||
1454 | hdr_size = 28; | ||
1455 | if (ucode_raw->size < hdr_size) { | ||
1456 | IWL_ERR(priv, "File size too small!\n"); | ||
1457 | return -EINVAL; | ||
1458 | } | ||
1459 | pieces->build = le32_to_cpu(ucode->u.v2.build); | ||
1460 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | ||
1461 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | ||
1462 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | ||
1463 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | ||
1464 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | ||
1465 | src = ucode->u.v2.data; | ||
1466 | break; | ||
1467 | } | 1266 | } |
1468 | /* fall through for 4965 */ | 1267 | pieces->build = le32_to_cpu(ucode->u.v2.build); |
1268 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | ||
1269 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | ||
1270 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | ||
1271 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | ||
1272 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | ||
1273 | src = ucode->u.v2.data; | ||
1274 | break; | ||
1469 | case 0: | 1275 | case 0: |
1470 | case 1: | 1276 | case 1: |
1471 | case 2: | 1277 | case 2: |
@@ -3348,6 +3154,10 @@ int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, | |||
3348 | } | 3154 | } |
3349 | break; | 3155 | break; |
3350 | case IEEE80211_AMPDU_TX_OPERATIONAL: | 3156 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
3157 | buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF); | ||
3158 | |||
3159 | iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size); | ||
3160 | |||
3351 | /* | 3161 | /* |
3352 | * If the limit is 0, then it wasn't initialised yet, | 3162 | * If the limit is 0, then it wasn't initialised yet, |
3353 | * use the default. We can do that since we take the | 3163 | * use the default. We can do that since we take the |
@@ -3750,12 +3560,8 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv) | |||
3750 | priv->watchdog.data = (unsigned long)priv; | 3560 | priv->watchdog.data = (unsigned long)priv; |
3751 | priv->watchdog.function = iwl_bg_watchdog; | 3561 | priv->watchdog.function = iwl_bg_watchdog; |
3752 | 3562 | ||
3753 | if (!priv->cfg->base_params->use_isr_legacy) | 3563 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) |
3754 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | 3564 | iwl_irq_tasklet, (unsigned long)priv); |
3755 | iwl_irq_tasklet, (unsigned long)priv); | ||
3756 | else | ||
3757 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | ||
3758 | iwl_irq_tasklet_legacy, (unsigned long)priv); | ||
3759 | } | 3565 | } |
3760 | 3566 | ||
3761 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) | 3567 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
@@ -3968,14 +3774,6 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
3968 | * 1. Allocating HW data | 3774 | * 1. Allocating HW data |
3969 | ************************/ | 3775 | ************************/ |
3970 | 3776 | ||
3971 | /* Disabling hardware scan means that mac80211 will perform scans | ||
3972 | * "the hard way", rather than using device's scan. */ | ||
3973 | if (cfg->mod_params->disable_hw_scan) { | ||
3974 | dev_printk(KERN_DEBUG, &(pdev->dev), | ||
3975 | "sw scan support is deprecated\n"); | ||
3976 | iwlagn_hw_ops.hw_scan = NULL; | ||
3977 | } | ||
3978 | |||
3979 | hw = iwl_alloc_all(cfg); | 3777 | hw = iwl_alloc_all(cfg); |
3980 | if (!hw) { | 3778 | if (!hw) { |
3981 | err = -ENOMEM; | 3779 | err = -ENOMEM; |
@@ -4585,43 +4383,21 @@ module_exit(iwl_exit); | |||
4585 | module_init(iwl_init); | 4383 | module_init(iwl_init); |
4586 | 4384 | ||
4587 | #ifdef CONFIG_IWLWIFI_DEBUG | 4385 | #ifdef CONFIG_IWLWIFI_DEBUG |
4588 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); | ||
4589 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); | ||
4590 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); | 4386 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
4591 | MODULE_PARM_DESC(debug, "debug output mask"); | 4387 | MODULE_PARM_DESC(debug, "debug output mask"); |
4592 | #endif | 4388 | #endif |
4593 | 4389 | ||
4594 | module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO); | ||
4595 | MODULE_PARM_DESC(swcrypto50, | ||
4596 | "using crypto in software (default 0 [hardware]) (deprecated)"); | ||
4597 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); | 4390 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); |
4598 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | 4391 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); |
4599 | module_param_named(queues_num50, | ||
4600 | iwlagn_mod_params.num_of_queues, int, S_IRUGO); | ||
4601 | MODULE_PARM_DESC(queues_num50, | ||
4602 | "number of hw queues in 50xx series (deprecated)"); | ||
4603 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); | 4392 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); |
4604 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | 4393 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
4605 | module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO); | ||
4606 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)"); | ||
4607 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); | 4394 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); |
4608 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | 4395 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); |
4609 | module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K, | ||
4610 | int, S_IRUGO); | ||
4611 | MODULE_PARM_DESC(amsdu_size_8K50, | ||
4612 | "enable 8K amsdu size in 50XX series (deprecated)"); | ||
4613 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, | 4396 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, |
4614 | int, S_IRUGO); | 4397 | int, S_IRUGO); |
4615 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | 4398 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); |
4616 | module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO); | ||
4617 | MODULE_PARM_DESC(fw_restart50, | ||
4618 | "restart firmware in case of error (deprecated)"); | ||
4619 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); | 4399 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); |
4620 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | 4400 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); |
4621 | module_param_named( | ||
4622 | disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO); | ||
4623 | MODULE_PARM_DESC(disable_hw_scan, | ||
4624 | "disable hardware scanning (default 0) (deprecated)"); | ||
4625 | 4401 | ||
4626 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | 4402 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, |
4627 | S_IRUGO); | 4403 | S_IRUGO); |