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path: root/drivers/net/wireless/iwlwifi/iwl-5000.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-5000.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000.c54
1 files changed, 0 insertions, 54 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index e61b67d0a18b..bec5f8c6841f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -124,10 +124,6 @@ static int iwl5000_apm_init(struct iwl_priv *priv)
124 return ret; 124 return ret;
125 } 125 }
126 126
127 ret = iwl_grab_nic_access(priv);
128 if (ret)
129 return ret;
130
131 /* enable DMA */ 127 /* enable DMA */
132 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 128 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
133 129
@@ -137,8 +133,6 @@ static int iwl5000_apm_init(struct iwl_priv *priv)
137 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 133 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
138 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 134 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
139 135
140 iwl_release_nic_access(priv);
141
142 return ret; 136 return ret;
143} 137}
144 138
@@ -165,12 +159,9 @@ static void iwl5000_apm_stop(struct iwl_priv *priv)
165static int iwl5000_apm_reset(struct iwl_priv *priv) 159static int iwl5000_apm_reset(struct iwl_priv *priv)
166{ 160{
167 int ret = 0; 161 int ret = 0;
168 unsigned long flags;
169 162
170 iwl5000_apm_stop_master(priv); 163 iwl5000_apm_stop_master(priv);
171 164
172 spin_lock_irqsave(&priv->lock, flags);
173
174 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 165 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
175 166
176 udelay(10); 167 udelay(10);
@@ -193,10 +184,6 @@ static int iwl5000_apm_reset(struct iwl_priv *priv)
193 goto out; 184 goto out;
194 } 185 }
195 186
196 ret = iwl_grab_nic_access(priv);
197 if (ret)
198 goto out;
199
200 /* enable DMA */ 187 /* enable DMA */
201 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 188 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
202 189
@@ -205,11 +192,7 @@ static int iwl5000_apm_reset(struct iwl_priv *priv)
205 /* disable L1-Active */ 192 /* disable L1-Active */
206 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 193 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
207 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
208
209 iwl_release_nic_access(priv);
210
211out: 195out:
212 spin_unlock_irqrestore(&priv->lock, flags);
213 196
214 return ret; 197 return ret;
215} 198}
@@ -252,11 +235,9 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
252 * (PCIe power is lost before PERST# is asserted), 235 * (PCIe power is lost before PERST# is asserted),
253 * causing ME FW to lose ownership and not being able to obtain it back. 236 * causing ME FW to lose ownership and not being able to obtain it back.
254 */ 237 */
255 iwl_grab_nic_access(priv);
256 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 238 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
257 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 239 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
258 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 240 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
259 iwl_release_nic_access(priv);
260 241
261 spin_unlock_irqrestore(&priv->lock, flags); 242 spin_unlock_irqrestore(&priv->lock, flags);
262} 243}
@@ -537,19 +518,9 @@ static int iwl5000_load_section(struct iwl_priv *priv,
537 struct fw_desc *image, 518 struct fw_desc *image,
538 u32 dst_addr) 519 u32 dst_addr)
539{ 520{
540 int ret = 0;
541 unsigned long flags;
542
543 dma_addr_t phy_addr = image->p_addr; 521 dma_addr_t phy_addr = image->p_addr;
544 u32 byte_cnt = image->len; 522 u32 byte_cnt = image->len;
545 523
546 spin_lock_irqsave(&priv->lock, flags);
547 ret = iwl_grab_nic_access(priv);
548 if (ret) {
549 spin_unlock_irqrestore(&priv->lock, flags);
550 return ret;
551 }
552
553 iwl_write_direct32(priv, 524 iwl_write_direct32(priv,
554 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 525 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
555 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 526 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
@@ -578,8 +549,6 @@ static int iwl5000_load_section(struct iwl_priv *priv,
578 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 549 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
579 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 550 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
580 551
581 iwl_release_nic_access(priv);
582 spin_unlock_irqrestore(&priv->lock, flags);
583 return 0; 552 return 0;
584} 553}
585 554
@@ -740,18 +709,11 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
740{ 709{
741 u32 a; 710 u32 a;
742 unsigned long flags; 711 unsigned long flags;
743 int ret;
744 int i, chan; 712 int i, chan;
745 u32 reg_val; 713 u32 reg_val;
746 714
747 spin_lock_irqsave(&priv->lock, flags); 715 spin_lock_irqsave(&priv->lock, flags);
748 716
749 ret = iwl_grab_nic_access(priv);
750 if (ret) {
751 spin_unlock_irqrestore(&priv->lock, flags);
752 return ret;
753 }
754
755 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 717 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
756 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 718 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
757 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 719 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
@@ -819,7 +781,6 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
819 iwl_txq_ctx_activate(priv, 8); 781 iwl_txq_ctx_activate(priv, 8);
820 iwl_txq_ctx_activate(priv, 9); 782 iwl_txq_ctx_activate(priv, 9);
821 783
822 iwl_release_nic_access(priv);
823 spin_unlock_irqrestore(&priv->lock, flags); 784 spin_unlock_irqrestore(&priv->lock, flags);
824 785
825 786
@@ -1000,7 +961,6 @@ static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1000 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 961 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1001{ 962{
1002 unsigned long flags; 963 unsigned long flags;
1003 int ret;
1004 u16 ra_tid; 964 u16 ra_tid;
1005 965
1006 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 966 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
@@ -1018,11 +978,6 @@ static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1018 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 978 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1019 979
1020 spin_lock_irqsave(&priv->lock, flags); 980 spin_lock_irqsave(&priv->lock, flags);
1021 ret = iwl_grab_nic_access(priv);
1022 if (ret) {
1023 spin_unlock_irqrestore(&priv->lock, flags);
1024 return ret;
1025 }
1026 981
1027 /* Stop this Tx queue before configuring it */ 982 /* Stop this Tx queue before configuring it */
1028 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 983 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
@@ -1058,7 +1013,6 @@ static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1058 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 1013 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1059 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 1014 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1060 1015
1061 iwl_release_nic_access(priv);
1062 spin_unlock_irqrestore(&priv->lock, flags); 1016 spin_unlock_irqrestore(&priv->lock, flags);
1063 1017
1064 return 0; 1018 return 0;
@@ -1067,8 +1021,6 @@ static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1067static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1021static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1068 u16 ssn_idx, u8 tx_fifo) 1022 u16 ssn_idx, u8 tx_fifo)
1069{ 1023{
1070 int ret;
1071
1072 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1024 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1073 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1025 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1074 IWL_ERR(priv, 1026 IWL_ERR(priv,
@@ -1078,10 +1030,6 @@ static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1078 return -EINVAL; 1030 return -EINVAL;
1079 } 1031 }
1080 1032
1081 ret = iwl_grab_nic_access(priv);
1082 if (ret)
1083 return ret;
1084
1085 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1033 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1086 1034
1087 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 1035 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
@@ -1095,8 +1043,6 @@ static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1095 iwl_txq_ctx_deactivate(priv, txq_id); 1043 iwl_txq_ctx_deactivate(priv, txq_id);
1096 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1044 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1097 1045
1098 iwl_release_nic_access(priv);
1099
1100 return 0; 1046 return 0;
1101} 1047}
1102 1048