diff options
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965.c')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-4965.c | 60 |
1 files changed, 2 insertions, 58 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c index 97131e63397e..4be7bd29ef6d 100644 --- a/drivers/net/wireless/iwlwifi/iwl-4965.c +++ b/drivers/net/wireless/iwlwifi/iwl-4965.c | |||
@@ -163,10 +163,6 @@ static int iwl4965_load_bsm(struct iwl_priv *priv) | |||
163 | inst_len = priv->ucode_init.len; | 163 | inst_len = priv->ucode_init.len; |
164 | data_len = priv->ucode_init_data.len; | 164 | data_len = priv->ucode_init_data.len; |
165 | 165 | ||
166 | ret = iwl_grab_nic_access(priv); | ||
167 | if (ret) | ||
168 | return ret; | ||
169 | |||
170 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); | 166 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
171 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | 167 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); |
172 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | 168 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); |
@@ -179,10 +175,8 @@ static int iwl4965_load_bsm(struct iwl_priv *priv) | |||
179 | _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image)); | 175 | _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image)); |
180 | 176 | ||
181 | ret = iwl4965_verify_bsm(priv); | 177 | ret = iwl4965_verify_bsm(priv); |
182 | if (ret) { | 178 | if (ret) |
183 | iwl_release_nic_access(priv); | ||
184 | return ret; | 179 | return ret; |
185 | } | ||
186 | 180 | ||
187 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | 181 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ |
188 | iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); | 182 | iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); |
@@ -211,7 +205,6 @@ static int iwl4965_load_bsm(struct iwl_priv *priv) | |||
211 | * (e.g. when powering back up after power-save shutdown) */ | 205 | * (e.g. when powering back up after power-save shutdown) */ |
212 | iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN); | 206 | iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN); |
213 | 207 | ||
214 | iwl_release_nic_access(priv); | ||
215 | 208 | ||
216 | return 0; | 209 | return 0; |
217 | } | 210 | } |
@@ -229,20 +222,12 @@ static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv) | |||
229 | { | 222 | { |
230 | dma_addr_t pinst; | 223 | dma_addr_t pinst; |
231 | dma_addr_t pdata; | 224 | dma_addr_t pdata; |
232 | unsigned long flags; | ||
233 | int ret = 0; | 225 | int ret = 0; |
234 | 226 | ||
235 | /* bits 35:4 for 4965 */ | 227 | /* bits 35:4 for 4965 */ |
236 | pinst = priv->ucode_code.p_addr >> 4; | 228 | pinst = priv->ucode_code.p_addr >> 4; |
237 | pdata = priv->ucode_data_backup.p_addr >> 4; | 229 | pdata = priv->ucode_data_backup.p_addr >> 4; |
238 | 230 | ||
239 | spin_lock_irqsave(&priv->lock, flags); | ||
240 | ret = iwl_grab_nic_access(priv); | ||
241 | if (ret) { | ||
242 | spin_unlock_irqrestore(&priv->lock, flags); | ||
243 | return ret; | ||
244 | } | ||
245 | |||
246 | /* Tell bootstrap uCode where to find image to load */ | 231 | /* Tell bootstrap uCode where to find image to load */ |
247 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); | 232 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
248 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | 233 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); |
@@ -253,10 +238,6 @@ static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv) | |||
253 | * that all new ptr/size info is in place */ | 238 | * that all new ptr/size info is in place */ |
254 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, | 239 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
255 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); | 240 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
256 | iwl_release_nic_access(priv); | ||
257 | |||
258 | spin_unlock_irqrestore(&priv->lock, flags); | ||
259 | |||
260 | IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); | 241 | IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); |
261 | 242 | ||
262 | return ret; | 243 | return ret; |
@@ -358,10 +339,6 @@ static int iwl4965_apm_init(struct iwl_priv *priv) | |||
358 | goto out; | 339 | goto out; |
359 | } | 340 | } |
360 | 341 | ||
361 | ret = iwl_grab_nic_access(priv); | ||
362 | if (ret) | ||
363 | goto out; | ||
364 | |||
365 | /* enable DMA */ | 342 | /* enable DMA */ |
366 | iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT | | 343 | iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT | |
367 | APMG_CLK_VAL_BSM_CLK_RQT); | 344 | APMG_CLK_VAL_BSM_CLK_RQT); |
@@ -372,7 +349,6 @@ static int iwl4965_apm_init(struct iwl_priv *priv) | |||
372 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | 349 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
373 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | 350 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
374 | 351 | ||
375 | iwl_release_nic_access(priv); | ||
376 | out: | 352 | out: |
377 | return ret; | 353 | return ret; |
378 | } | 354 | } |
@@ -454,11 +430,9 @@ static void iwl4965_apm_stop(struct iwl_priv *priv) | |||
454 | static int iwl4965_apm_reset(struct iwl_priv *priv) | 430 | static int iwl4965_apm_reset(struct iwl_priv *priv) |
455 | { | 431 | { |
456 | int ret = 0; | 432 | int ret = 0; |
457 | unsigned long flags; | ||
458 | 433 | ||
459 | iwl4965_apm_stop_master(priv); | 434 | iwl4965_apm_stop_master(priv); |
460 | 435 | ||
461 | spin_lock_irqsave(&priv->lock, flags); | ||
462 | 436 | ||
463 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | 437 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
464 | 438 | ||
@@ -475,9 +449,6 @@ static int iwl4965_apm_reset(struct iwl_priv *priv) | |||
475 | 449 | ||
476 | udelay(10); | 450 | udelay(10); |
477 | 451 | ||
478 | ret = iwl_grab_nic_access(priv); | ||
479 | if (ret) | ||
480 | goto out; | ||
481 | /* Enable DMA and BSM Clock */ | 452 | /* Enable DMA and BSM Clock */ |
482 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT | | 453 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT | |
483 | APMG_CLK_VAL_BSM_CLK_RQT); | 454 | APMG_CLK_VAL_BSM_CLK_RQT); |
@@ -488,14 +459,10 @@ static int iwl4965_apm_reset(struct iwl_priv *priv) | |||
488 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | 459 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
489 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | 460 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
490 | 461 | ||
491 | iwl_release_nic_access(priv); | ||
492 | |||
493 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | 462 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
494 | wake_up_interruptible(&priv->wait_command_queue); | 463 | wake_up_interruptible(&priv->wait_command_queue); |
495 | 464 | ||
496 | out: | 465 | out: |
497 | spin_unlock_irqrestore(&priv->lock, flags); | ||
498 | |||
499 | return ret; | 466 | return ret; |
500 | } | 467 | } |
501 | 468 | ||
@@ -681,18 +648,11 @@ static int iwl4965_alive_notify(struct iwl_priv *priv) | |||
681 | { | 648 | { |
682 | u32 a; | 649 | u32 a; |
683 | unsigned long flags; | 650 | unsigned long flags; |
684 | int ret; | ||
685 | int i, chan; | 651 | int i, chan; |
686 | u32 reg_val; | 652 | u32 reg_val; |
687 | 653 | ||
688 | spin_lock_irqsave(&priv->lock, flags); | 654 | spin_lock_irqsave(&priv->lock, flags); |
689 | 655 | ||
690 | ret = iwl_grab_nic_access(priv); | ||
691 | if (ret) { | ||
692 | spin_unlock_irqrestore(&priv->lock, flags); | ||
693 | return ret; | ||
694 | } | ||
695 | |||
696 | /* Clear 4965's internal Tx Scheduler data base */ | 656 | /* Clear 4965's internal Tx Scheduler data base */ |
697 | priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR); | 657 | priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR); |
698 | a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET; | 658 | a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET; |
@@ -759,10 +719,9 @@ static int iwl4965_alive_notify(struct iwl_priv *priv) | |||
759 | iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); | 719 | iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); |
760 | } | 720 | } |
761 | 721 | ||
762 | iwl_release_nic_access(priv); | ||
763 | spin_unlock_irqrestore(&priv->lock, flags); | 722 | spin_unlock_irqrestore(&priv->lock, flags); |
764 | 723 | ||
765 | return ret; | 724 | return 0; |
766 | } | 725 | } |
767 | 726 | ||
768 | static struct iwl_sensitivity_ranges iwl4965_sensitivity = { | 727 | static struct iwl_sensitivity_ranges iwl4965_sensitivity = { |
@@ -1840,8 +1799,6 @@ static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, | |||
1840 | static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | 1799 | static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
1841 | u16 ssn_idx, u8 tx_fifo) | 1800 | u16 ssn_idx, u8 tx_fifo) |
1842 | { | 1801 | { |
1843 | int ret = 0; | ||
1844 | |||
1845 | if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || | 1802 | if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || |
1846 | (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) { | 1803 | (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) { |
1847 | IWL_WARN(priv, | 1804 | IWL_WARN(priv, |
@@ -1851,10 +1808,6 @@ static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | |||
1851 | return -EINVAL; | 1808 | return -EINVAL; |
1852 | } | 1809 | } |
1853 | 1810 | ||
1854 | ret = iwl_grab_nic_access(priv); | ||
1855 | if (ret) | ||
1856 | return ret; | ||
1857 | |||
1858 | iwl4965_tx_queue_stop_scheduler(priv, txq_id); | 1811 | iwl4965_tx_queue_stop_scheduler(priv, txq_id); |
1859 | 1812 | ||
1860 | iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); | 1813 | iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); |
@@ -1868,8 +1821,6 @@ static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | |||
1868 | iwl_txq_ctx_deactivate(priv, txq_id); | 1821 | iwl_txq_ctx_deactivate(priv, txq_id); |
1869 | iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | 1822 | iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); |
1870 | 1823 | ||
1871 | iwl_release_nic_access(priv); | ||
1872 | |||
1873 | return 0; | 1824 | return 0; |
1874 | } | 1825 | } |
1875 | 1826 | ||
@@ -1911,7 +1862,6 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |||
1911 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) | 1862 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) |
1912 | { | 1863 | { |
1913 | unsigned long flags; | 1864 | unsigned long flags; |
1914 | int ret; | ||
1915 | u16 ra_tid; | 1865 | u16 ra_tid; |
1916 | 1866 | ||
1917 | if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || | 1867 | if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || |
@@ -1929,11 +1879,6 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |||
1929 | iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); | 1879 | iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
1930 | 1880 | ||
1931 | spin_lock_irqsave(&priv->lock, flags); | 1881 | spin_lock_irqsave(&priv->lock, flags); |
1932 | ret = iwl_grab_nic_access(priv); | ||
1933 | if (ret) { | ||
1934 | spin_unlock_irqrestore(&priv->lock, flags); | ||
1935 | return ret; | ||
1936 | } | ||
1937 | 1882 | ||
1938 | /* Stop this Tx queue before configuring it */ | 1883 | /* Stop this Tx queue before configuring it */ |
1939 | iwl4965_tx_queue_stop_scheduler(priv, txq_id); | 1884 | iwl4965_tx_queue_stop_scheduler(priv, txq_id); |
@@ -1966,7 +1911,6 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |||
1966 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | 1911 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1967 | iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | 1912 | iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); |
1968 | 1913 | ||
1969 | iwl_release_nic_access(priv); | ||
1970 | spin_unlock_irqrestore(&priv->lock, flags); | 1914 | spin_unlock_irqrestore(&priv->lock, flags); |
1971 | 1915 | ||
1972 | return 0; | 1916 | return 0; |