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-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-hw.h531
1 files changed, 22 insertions, 509 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index ffe1e9dfdec7..1a66b508a8ea 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -5,7 +5,7 @@
5 * 5 *
6 * GPL LICENSE SUMMARY 6 * GPL LICENSE SUMMARY
7 * 7 *
8 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. 8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as 11 * it under the terms of version 2 of the GNU General Public License as
@@ -30,7 +30,7 @@
30 * 30 *
31 * BSD LICENSE 31 * BSD LICENSE
32 * 32 *
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. 33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
34 * All rights reserved. 34 * All rights reserved.
35 * 35 *
36 * Redistribution and use in source and binary forms, with or without 36 * Redistribution and use in source and binary forms, with or without
@@ -92,316 +92,6 @@
92/* RSSI to dBm */ 92/* RSSI to dBm */
93#define IWL_RSSI_OFFSET 44 93#define IWL_RSSI_OFFSET 44
94 94
95/*
96 * EEPROM related constants, enums, and structures.
97 */
98
99/*
100 * EEPROM access time values:
101 *
102 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG,
103 * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit
104 * CSR_EEPROM_REG_BIT_CMD (0x2).
105 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
106 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
107 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
108 */
109#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
110#define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
111
112/*
113 * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
114 *
115 * IBSS and/or AP operation is allowed *only* on those channels with
116 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
117 * RADAR detection is not supported by the 4965 driver, but is a
118 * requirement for establishing a new network for legal operation on channels
119 * requiring RADAR detection or restricting ACTIVE scanning.
120 *
121 * NOTE: "WIDE" flag does not indicate anything about "FAT" 40 MHz channels.
122 * It only indicates that 20 MHz channel use is supported; FAT channel
123 * usage is indicated by a separate set of regulatory flags for each
124 * FAT channel pair.
125 *
126 * NOTE: Using a channel inappropriately will result in a uCode error!
127 */
128enum {
129 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
130 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
131 /* Bit 2 Reserved */
132 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
133 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
134 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
135 EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */
136 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
137};
138
139/* SKU Capabilities */
140#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
141#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
142
143/* *regulatory* channel data format in eeprom, one for each channel.
144 * There are separate entries for FAT (40 MHz) vs. normal (20 MHz) channels. */
145struct iwl4965_eeprom_channel {
146 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
147 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
148} __attribute__ ((packed));
149
150/* 4965 has two radio transmitters (and 3 radio receivers) */
151#define EEPROM_TX_POWER_TX_CHAINS (2)
152
153/* 4965 has room for up to 8 sets of txpower calibration data */
154#define EEPROM_TX_POWER_BANDS (8)
155
156/* 4965 factory calibration measures txpower gain settings for
157 * each of 3 target output levels */
158#define EEPROM_TX_POWER_MEASUREMENTS (3)
159
160/* 4965 driver does not work with txpower calibration version < 5.
161 * Look for this in calib_version member of struct iwl4965_eeprom. */
162#define EEPROM_TX_POWER_VERSION_NEW (5)
163
164
165/*
166 * 4965 factory calibration data for one txpower level, on one channel,
167 * measured on one of the 2 tx chains (radio transmitter and associated
168 * antenna). EEPROM contains:
169 *
170 * 1) Temperature (degrees Celsius) of device when measurement was made.
171 *
172 * 2) Gain table index used to achieve the target measurement power.
173 * This refers to the "well-known" gain tables (see iwl-4965-hw.h).
174 *
175 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
176 *
177 * 4) RF power amplifier detector level measurement (not used).
178 */
179struct iwl4965_eeprom_calib_measure {
180 u8 temperature; /* Device temperature (Celsius) */
181 u8 gain_idx; /* Index into gain table */
182 u8 actual_pow; /* Measured RF output power, half-dBm */
183 s8 pa_det; /* Power amp detector level (not used) */
184} __attribute__ ((packed));
185
186
187/*
188 * 4965 measurement set for one channel. EEPROM contains:
189 *
190 * 1) Channel number measured
191 *
192 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
193 * (a.k.a. "tx chains") (6 measurements altogether)
194 */
195struct iwl4965_eeprom_calib_ch_info {
196 u8 ch_num;
197 struct iwl4965_eeprom_calib_measure measurements[EEPROM_TX_POWER_TX_CHAINS]
198 [EEPROM_TX_POWER_MEASUREMENTS];
199} __attribute__ ((packed));
200
201/*
202 * 4965 txpower subband info.
203 *
204 * For each frequency subband, EEPROM contains the following:
205 *
206 * 1) First and last channels within range of the subband. "0" values
207 * indicate that this sample set is not being used.
208 *
209 * 2) Sample measurement sets for 2 channels close to the range endpoints.
210 */
211struct iwl4965_eeprom_calib_subband_info {
212 u8 ch_from; /* channel number of lowest channel in subband */
213 u8 ch_to; /* channel number of highest channel in subband */
214 struct iwl4965_eeprom_calib_ch_info ch1;
215 struct iwl4965_eeprom_calib_ch_info ch2;
216} __attribute__ ((packed));
217
218
219/*
220 * 4965 txpower calibration info. EEPROM contains:
221 *
222 * 1) Factory-measured saturation power levels (maximum levels at which
223 * tx power amplifier can output a signal without too much distortion).
224 * There is one level for 2.4 GHz band and one for 5 GHz band. These
225 * values apply to all channels within each of the bands.
226 *
227 * 2) Factory-measured power supply voltage level. This is assumed to be
228 * constant (i.e. same value applies to all channels/bands) while the
229 * factory measurements are being made.
230 *
231 * 3) Up to 8 sets of factory-measured txpower calibration values.
232 * These are for different frequency ranges, since txpower gain
233 * characteristics of the analog radio circuitry vary with frequency.
234 *
235 * Not all sets need to be filled with data;
236 * struct iwl4965_eeprom_calib_subband_info contains range of channels
237 * (0 if unused) for each set of data.
238 */
239struct iwl4965_eeprom_calib_info {
240 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
241 u8 saturation_power52; /* half-dBm */
242 s16 voltage; /* signed */
243 struct iwl4965_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
244} __attribute__ ((packed));
245
246
247/*
248 * 4965 EEPROM map
249 */
250struct iwl4965_eeprom {
251 u8 reserved0[16];
252#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
253 u16 device_id; /* abs.ofs: 16 */
254 u8 reserved1[2];
255#define EEPROM_PMC (2*0x0A) /* 2 bytes */
256 u16 pmc; /* abs.ofs: 20 */
257 u8 reserved2[20];
258#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
259 u8 mac_address[6]; /* abs.ofs: 42 */
260 u8 reserved3[58];
261#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
262 u16 board_revision; /* abs.ofs: 106 */
263 u8 reserved4[11];
264#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
265 u8 board_pba_number[9]; /* abs.ofs: 119 */
266 u8 reserved5[8];
267#define EEPROM_VERSION (2*0x44) /* 2 bytes */
268 u16 version; /* abs.ofs: 136 */
269#define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
270 u8 sku_cap; /* abs.ofs: 138 */
271#define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
272 u8 leds_mode; /* abs.ofs: 139 */
273#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
274 u16 oem_mode;
275#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
276 u16 wowlan_mode; /* abs.ofs: 142 */
277#define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
278 u16 leds_time_interval; /* abs.ofs: 144 */
279#define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
280 u8 leds_off_time; /* abs.ofs: 146 */
281#define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
282 u8 leds_on_time; /* abs.ofs: 147 */
283#define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
284 u8 almgor_m_version; /* abs.ofs: 148 */
285#define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
286 u8 antenna_switch_type; /* abs.ofs: 149 */
287 u8 reserved6[8];
288#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
289 u16 board_revision_4965; /* abs.ofs: 158 */
290 u8 reserved7[13];
291#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
292 u8 board_pba_number_4965[9]; /* abs.ofs: 173 */
293 u8 reserved8[10];
294#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
295 u8 sku_id[4]; /* abs.ofs: 192 */
296
297/*
298 * Per-channel regulatory data.
299 *
300 * Each channel that *might* be supported by 3945 or 4965 has a fixed location
301 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
302 * txpower (MSB).
303 *
304 * Entries immediately below are for 20 MHz channel width. FAT (40 MHz)
305 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
306 *
307 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
308 */
309#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
310 u16 band_1_count; /* abs.ofs: 196 */
311#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
312 struct iwl4965_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
313
314/*
315 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
316 * 5.0 GHz channels 7, 8, 11, 12, 16
317 * (4915-5080MHz) (none of these is ever supported)
318 */
319#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
320 u16 band_2_count; /* abs.ofs: 226 */
321#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
322 struct iwl4965_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
323
324/*
325 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
326 * (5170-5320MHz)
327 */
328#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
329 u16 band_3_count; /* abs.ofs: 254 */
330#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
331 struct iwl4965_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
332
333/*
334 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
335 * (5500-5700MHz)
336 */
337#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
338 u16 band_4_count; /* abs.ofs: 280 */
339#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
340 struct iwl4965_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
341
342/*
343 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
344 * (5725-5825MHz)
345 */
346#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
347 u16 band_5_count; /* abs.ofs: 304 */
348#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
349 struct iwl4965_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
350
351 u8 reserved10[2];
352
353
354/*
355 * 2.4 GHz FAT channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
356 *
357 * The channel listed is the center of the lower 20 MHz half of the channel.
358 * The overall center frequency is actually 2 channels (10 MHz) above that,
359 * and the upper half of each FAT channel is centered 4 channels (20 MHz) away
360 * from the lower half; e.g. the upper half of FAT channel 1 is channel 5,
361 * and the overall FAT channel width centers on channel 3.
362 *
363 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
364 * control channel to which to tune. RXON also specifies whether the
365 * control channel is the upper or lower half of a FAT channel.
366 *
367 * NOTE: 4965 does not support FAT channels on 2.4 GHz.
368 */
369#define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */
370 struct iwl4965_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */
371 u8 reserved11[2];
372
373/*
374 * 5.2 GHz FAT channels 36 (40), 44 (48), 52 (56), 60 (64),
375 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
376 */
377#define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */
378 struct iwl4965_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */
379 u8 reserved12[6];
380
381/*
382 * 4965 driver requires txpower calibration format version 5 or greater.
383 * Driver does not work with txpower calibration version < 5.
384 * This value is simply a 16-bit number, no major/minor versions here.
385 */
386#define EEPROM_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
387 u16 calib_version; /* abs.ofs: 364 */
388 u8 reserved13[2];
389 u8 reserved14[96]; /* abs.ofs: 368 */
390
391/*
392 * 4965 Txpower calibration data.
393 */
394#define EEPROM_IWL_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
395 struct iwl4965_eeprom_calib_info calib_info; /* abs.ofs: 464 */
396
397 u8 reserved16[140]; /* fill out to full 1024 byte block */
398
399
400} __attribute__ ((packed));
401
402#define IWL_EEPROM_IMAGE_SIZE 1024
403
404/* End of EEPROM */
405 95
406#include "iwl-4965-commands.h" 96#include "iwl-4965-commands.h"
407 97
@@ -410,182 +100,6 @@ struct iwl4965_eeprom {
410#define PCI_REG_WUM8 0x0E8 100#define PCI_REG_WUM8 0x0E8
411#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 101#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
412 102
413/*=== CSR (control and status registers) ===*/
414#define CSR_BASE (0x000)
415
416#define CSR_SW_VER (CSR_BASE+0x000)
417#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
418#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
419#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
420#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
421#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
422#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
423#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
424#define CSR_GP_CNTRL (CSR_BASE+0x024)
425
426/*
427 * Hardware revision info
428 * Bit fields:
429 * 31-8: Reserved
430 * 7-4: Type of device: 0x0 = 4965, 0xd = 3945
431 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
432 * 1-0: "Dash" value, as in A-1, etc.
433 *
434 * NOTE: Revision step affects calculation of CCK txpower for 4965.
435 */
436#define CSR_HW_REV (CSR_BASE+0x028)
437
438/* EEPROM reads */
439#define CSR_EEPROM_REG (CSR_BASE+0x02c)
440#define CSR_EEPROM_GP (CSR_BASE+0x030)
441#define CSR_GP_UCODE (CSR_BASE+0x044)
442#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
443#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
444#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
445#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
446#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
447
448/*
449 * Indicates hardware rev, to determine CCK backoff for txpower calculation.
450 * Bit fields:
451 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
452 */
453#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
454
455/* Hardware interface configuration bits */
456#define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)
457#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
458#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
459#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
460#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
461
462/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
463 * acknowledged (reset) by host writing "1" to flagged bits. */
464#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
465#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
466#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */
467#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
468#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
469#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
470#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
471#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
472#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
473#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
474#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
475
476#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
477 CSR_INT_BIT_HW_ERR | \
478 CSR_INT_BIT_FH_TX | \
479 CSR_INT_BIT_SW_ERR | \
480 CSR_INT_BIT_RF_KILL | \
481 CSR_INT_BIT_SW_RX | \
482 CSR_INT_BIT_WAKEUP | \
483 CSR_INT_BIT_ALIVE)
484
485/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
486#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
487#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
488#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
489#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
490#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
491#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
492
493#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
494 CSR_FH_INT_BIT_RX_CHNL1 | \
495 CSR_FH_INT_BIT_RX_CHNL0)
496
497#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
498 CSR_FH_INT_BIT_TX_CHNL0)
499
500
501/* RESET */
502#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
503#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
504#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
505#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
506#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
507
508/* GP (general purpose) CONTROL */
509#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
510#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
511#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
512#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
513
514#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
515
516#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
517#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
518#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
519
520
521/* EEPROM REG */
522#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
523#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
524
525/* EEPROM GP */
526#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
527#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
528#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
529
530/* UCODE DRV GP */
531#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
532#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
533#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
534#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
535
536/* GPIO */
537#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
538#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
539#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
540
541/* GI Chicken Bits */
542#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
543#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
544
545/*=== HBUS (Host-side Bus) ===*/
546#define HBUS_BASE (0x400)
547
548/*
549 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
550 * structures, error log, event log, verifying uCode load).
551 * First write to address register, then read from or write to data register
552 * to complete the job. Once the address register is set up, accesses to
553 * data registers auto-increment the address by one dword.
554 * Bit usage for address registers (read or write):
555 * 0-31: memory address within device
556 */
557#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
558#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
559#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
560#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
561
562/*
563 * Registers for accessing device's internal peripheral registers
564 * (e.g. SCD, BSM, etc.). First write to address register,
565 * then read from or write to data register to complete the job.
566 * Bit usage for address registers (read or write):
567 * 0-15: register address (offset) within device
568 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
569 */
570#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
571#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
572#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
573#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
574
575/*
576 * Per-Tx-queue write pointer (index, really!) (3945 and 4965).
577 * Driver sets this to indicate index to next TFD that driver will fill
578 * (1 past latest filled).
579 * Bit usage:
580 * 0-7: queue write index (0-255)
581 * 11-8: queue selector (0-15)
582 */
583#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
584
585#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
586
587#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
588
589#define TFD_QUEUE_SIZE_MAX (256) 103#define TFD_QUEUE_SIZE_MAX (256)
590 104
591#define IWL_NUM_SCAN_RATES (2) 105#define IWL_NUM_SCAN_RATES (2)
@@ -599,9 +113,6 @@ struct iwl4965_eeprom {
599#define TFD_TX_CMD_SLOTS 256 113#define TFD_TX_CMD_SLOTS 256
600#define TFD_CMD_SLOTS 32 114#define TFD_CMD_SLOTS 32
601 115
602#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl4965_cmd) - \
603 sizeof(struct iwl4965_cmd_meta))
604
605/* 116/*
606 * RX related structures and functions 117 * RX related structures and functions
607 */ 118 */
@@ -615,16 +126,18 @@ struct iwl4965_eeprom {
615/* Sizes and addresses for instruction and data memory (SRAM) in 126/* Sizes and addresses for instruction and data memory (SRAM) in
616 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ 127 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
617#define RTC_INST_LOWER_BOUND (0x000000) 128#define RTC_INST_LOWER_BOUND (0x000000)
618#define KDR_RTC_INST_UPPER_BOUND (0x018000) 129#define IWL49_RTC_INST_UPPER_BOUND (0x018000)
619 130
620#define RTC_DATA_LOWER_BOUND (0x800000) 131#define RTC_DATA_LOWER_BOUND (0x800000)
621#define KDR_RTC_DATA_UPPER_BOUND (0x80A000) 132#define IWL49_RTC_DATA_UPPER_BOUND (0x80A000)
622 133
623#define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND) 134#define IWL49_RTC_INST_SIZE \
624#define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND) 135 (IWL49_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
136#define IWL49_RTC_DATA_SIZE \
137 (IWL49_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
625 138
626#define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE 139#define IWL_MAX_INST_SIZE IWL49_RTC_INST_SIZE
627#define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE 140#define IWL_MAX_DATA_SIZE IWL49_RTC_DATA_SIZE
628 141
629/* Size of uCode instruction memory in bootstrap state machine */ 142/* Size of uCode instruction memory in bootstrap state machine */
630#define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE 143#define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
@@ -632,7 +145,7 @@ struct iwl4965_eeprom {
632static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr) 145static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr)
633{ 146{
634 return (addr >= RTC_DATA_LOWER_BOUND) && 147 return (addr >= RTC_DATA_LOWER_BOUND) &&
635 (addr < KDR_RTC_DATA_UPPER_BOUND); 148 (addr < IWL49_RTC_DATA_UPPER_BOUND);
636} 149}
637 150
638/********************* START TEMPERATURE *************************************/ 151/********************* START TEMPERATURE *************************************/
@@ -1872,10 +1385,10 @@ static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags)
1872 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array 1385 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
1873 * in DRAM containing 256 Transmit Frame Descriptors (TFDs). 1386 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
1874 */ 1387 */
1875#define IWL4965_MAX_WIN_SIZE 64 1388#define IWL4965_MAX_WIN_SIZE 64
1876#define IWL4965_QUEUE_SIZE 256 1389#define IWL4965_QUEUE_SIZE 256
1877#define IWL4965_NUM_FIFOS 7 1390#define IWL4965_NUM_FIFOS 7
1878#define IWL_MAX_NUM_QUEUES 16 1391#define IWL4965_MAX_NUM_QUEUES 16
1879 1392
1880 1393
1881/** 1394/**
@@ -2040,30 +1553,30 @@ struct iwl4965_sched_queue_byte_cnt_tbl {
2040 */ 1553 */
2041struct iwl4965_shared { 1554struct iwl4965_shared {
2042 struct iwl4965_sched_queue_byte_cnt_tbl 1555 struct iwl4965_sched_queue_byte_cnt_tbl
2043 queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES]; 1556 queues_byte_cnt_tbls[IWL4965_MAX_NUM_QUEUES];
2044 __le32 val0; 1557 __le32 rb_closed;
2045 1558
2046 /* __le32 rb_closed_stts_rb_num:12; */ 1559 /* __le32 rb_closed_stts_rb_num:12; */
2047#define IWL_rb_closed_stts_rb_num_POS 0 1560#define IWL_rb_closed_stts_rb_num_POS 0
2048#define IWL_rb_closed_stts_rb_num_LEN 12 1561#define IWL_rb_closed_stts_rb_num_LEN 12
2049#define IWL_rb_closed_stts_rb_num_SYM val0 1562#define IWL_rb_closed_stts_rb_num_SYM rb_closed
2050 /* __le32 rsrv1:4; */ 1563 /* __le32 rsrv1:4; */
2051 /* __le32 rb_closed_stts_rx_frame_num:12; */ 1564 /* __le32 rb_closed_stts_rx_frame_num:12; */
2052#define IWL_rb_closed_stts_rx_frame_num_POS 16 1565#define IWL_rb_closed_stts_rx_frame_num_POS 16
2053#define IWL_rb_closed_stts_rx_frame_num_LEN 12 1566#define IWL_rb_closed_stts_rx_frame_num_LEN 12
2054#define IWL_rb_closed_stts_rx_frame_num_SYM val0 1567#define IWL_rb_closed_stts_rx_frame_num_SYM rb_closed
2055 /* __le32 rsrv2:4; */ 1568 /* __le32 rsrv2:4; */
2056 1569
2057 __le32 val1; 1570 __le32 frm_finished;
2058 /* __le32 frame_finished_stts_rb_num:12; */ 1571 /* __le32 frame_finished_stts_rb_num:12; */
2059#define IWL_frame_finished_stts_rb_num_POS 0 1572#define IWL_frame_finished_stts_rb_num_POS 0
2060#define IWL_frame_finished_stts_rb_num_LEN 12 1573#define IWL_frame_finished_stts_rb_num_LEN 12
2061#define IWL_frame_finished_stts_rb_num_SYM val1 1574#define IWL_frame_finished_stts_rb_num_SYM frm_finished
2062 /* __le32 rsrv3:4; */ 1575 /* __le32 rsrv3:4; */
2063 /* __le32 frame_finished_stts_rx_frame_num:12; */ 1576 /* __le32 frame_finished_stts_rx_frame_num:12; */
2064#define IWL_frame_finished_stts_rx_frame_num_POS 16 1577#define IWL_frame_finished_stts_rx_frame_num_POS 16
2065#define IWL_frame_finished_stts_rx_frame_num_LEN 12 1578#define IWL_frame_finished_stts_rx_frame_num_LEN 12
2066#define IWL_frame_finished_stts_rx_frame_num_SYM val1 1579#define IWL_frame_finished_stts_rx_frame_num_SYM frm_finished
2067 /* __le32 rsrv4:4; */ 1580 /* __le32 rsrv4:4; */
2068 1581
2069 __le32 padding1; /* so that allocation will be aligned to 16B */ 1582 __le32 padding1; /* so that allocation will be aligned to 16B */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 12:32:54 -0500