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path: root/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
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Diffstat (limited to 'drivers/net/wireless/brcm80211/brcmsmac/aiutils.h')
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/aiutils.h148
1 files changed, 59 insertions, 89 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
index b51d1e421e24..f84c6f781692 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
@@ -17,6 +17,8 @@
17#ifndef _BRCM_AIUTILS_H_ 17#ifndef _BRCM_AIUTILS_H_
18#define _BRCM_AIUTILS_H_ 18#define _BRCM_AIUTILS_H_
19 19
20#include <linux/bcma/bcma.h>
21
20#include "types.h" 22#include "types.h"
21 23
22/* 24/*
@@ -144,26 +146,15 @@
144 * public (read-only) portion of aiutils handle returned by si_attach() 146 * public (read-only) portion of aiutils handle returned by si_attach()
145 */ 147 */
146struct si_pub { 148struct si_pub {
147 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
148 uint buscorerev; /* buscore rev */
149 uint buscoreidx; /* buscore index */
150 int ccrev; /* chip common core rev */ 149 int ccrev; /* chip common core rev */
151 u32 cccaps; /* chip common capabilities */ 150 u32 cccaps; /* chip common capabilities */
152 u32 cccaps_ext; /* chip common capabilities extension */
153 int pmurev; /* pmu core rev */ 151 int pmurev; /* pmu core rev */
154 u32 pmucaps; /* pmu capabilities */ 152 u32 pmucaps; /* pmu capabilities */
155 uint boardtype; /* board type */ 153 uint boardtype; /* board type */
156 uint boardvendor; /* board vendor */ 154 uint boardvendor; /* board vendor */
157 uint boardflags; /* board flags */
158 uint boardflags2; /* board flags2 */
159 uint chip; /* chip number */ 155 uint chip; /* chip number */
160 uint chiprev; /* chip revision */ 156 uint chiprev; /* chip revision */
161 uint chippkg; /* chip package option */ 157 uint chippkg; /* chip package option */
162 u32 chipst; /* chip status */
163 bool issim; /* chip is in simulation or emulation */
164 uint socirev; /* SOC interconnect rev */
165 bool pci_pr32414;
166
167}; 158};
168 159
169struct pci_dev; 160struct pci_dev;
@@ -179,38 +170,13 @@ struct gpioh_item {
179/* misc si info needed by some of the routines */ 170/* misc si info needed by some of the routines */
180struct si_info { 171struct si_info {
181 struct si_pub pub; /* back plane public state (must be first) */ 172 struct si_pub pub; /* back plane public state (must be first) */
182 struct pci_dev *pbus; /* handle to pci bus */ 173 struct bcma_bus *icbus; /* handle to soc interconnect bus */
183 uint dev_coreid; /* the core provides driver functions */ 174 struct pci_dev *pcibus; /* handle to pci bus */
184 void *intr_arg; /* interrupt callback function arg */
185 u32 (*intrsoff_fn) (void *intr_arg); /* turns chip interrupts off */
186 /* restore chip interrupts */
187 void (*intrsrestore_fn) (void *intr_arg, u32 arg);
188 /* check if interrupts are enabled */
189 bool (*intrsenabled_fn) (void *intr_arg);
190
191 struct pcicore_info *pch; /* PCI/E core handle */ 175 struct pcicore_info *pch; /* PCI/E core handle */
192 176 struct bcma_device *buscore;
193 struct list_head var_list; /* list of srom variables */ 177 struct list_head var_list; /* list of srom variables */
194 178
195 void __iomem *curmap; /* current regs va */ 179 u32 chipst; /* chip status */
196 void __iomem *regs[SI_MAXCORES]; /* other regs va */
197
198 uint curidx; /* current core index */
199 uint numcores; /* # discovered cores */
200 uint coreid[SI_MAXCORES]; /* id of each core */
201 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
202 void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
203 u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
204 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
205 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
206
207 void *curwrap; /* current wrapper va */
208 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
209 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
210
211 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
212 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
213 u32 oob_router; /* oob router registers for axi */
214}; 180};
215 181
216/* 182/*
@@ -223,52 +189,15 @@ struct si_info {
223 189
224 190
225/* AMBA Interconnect exported externs */ 191/* AMBA Interconnect exported externs */
226extern uint ai_flag(struct si_pub *sih); 192extern struct bcma_device *ai_findcore(struct si_pub *sih,
227extern void ai_setint(struct si_pub *sih, int siflag); 193 u16 coreid, u16 coreunit);
228extern uint ai_coreidx(struct si_pub *sih); 194extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
229extern uint ai_corevendor(struct si_pub *sih);
230extern uint ai_corerev(struct si_pub *sih);
231extern bool ai_iscoreup(struct si_pub *sih);
232extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
233extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
234extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
235extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
236 uint val);
237extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
238extern void ai_core_disable(struct si_pub *sih, u32 bits);
239extern int ai_numaddrspaces(struct si_pub *sih);
240extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
241extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
242extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
243 195
244/* === exported functions === */ 196/* === exported functions === */
245extern struct si_pub *ai_attach(void __iomem *regs, struct pci_dev *sdh); 197extern struct si_pub *ai_attach(struct bcma_bus *pbus);
246extern void ai_detach(struct si_pub *sih); 198extern void ai_detach(struct si_pub *sih);
247extern uint ai_coreid(struct si_pub *sih); 199extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
248extern uint ai_corerev(struct si_pub *sih);
249extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
250 uint val);
251extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
252extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
253extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
254extern bool ai_iscoreup(struct si_pub *sih);
255extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
256extern void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx);
257extern void __iomem *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
258extern void __iomem *ai_switch_core(struct si_pub *sih, uint coreid,
259 uint *origidx, uint *intr_val);
260extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
261extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
262extern void ai_core_disable(struct si_pub *sih, u32 bits);
263extern u32 ai_alp_clock(struct si_pub *sih);
264extern u32 ai_ilp_clock(struct si_pub *sih);
265extern void ai_pci_setup(struct si_pub *sih, uint coremask); 200extern void ai_pci_setup(struct si_pub *sih, uint coremask);
266extern void ai_setint(struct si_pub *sih, int siflag);
267extern bool ai_backplane64(struct si_pub *sih);
268extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
269 void *intrsrestore_fn,
270 void *intrsenabled_fn, void *intr_arg);
271extern void ai_deregister_intr_callback(struct si_pub *sih);
272extern void ai_clkctl_init(struct si_pub *sih); 201extern void ai_clkctl_init(struct si_pub *sih);
273extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih); 202extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
274extern bool ai_clkctl_cc(struct si_pub *sih, uint mode); 203extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
@@ -283,13 +212,6 @@ extern bool ai_is_otp_disabled(struct si_pub *sih);
283/* SPROM availability */ 212/* SPROM availability */
284extern bool ai_is_sprom_available(struct si_pub *sih); 213extern bool ai_is_sprom_available(struct si_pub *sih);
285 214
286/*
287 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
288 * The returned path is NULL terminated and has trailing '/'.
289 * Return 0 on success, nonzero otherwise.
290 */
291extern int ai_devpath(struct si_pub *sih, char *path, int size);
292
293extern void ai_pci_sleep(struct si_pub *sih); 215extern void ai_pci_sleep(struct si_pub *sih);
294extern void ai_pci_down(struct si_pub *sih); 216extern void ai_pci_down(struct si_pub *sih);
295extern void ai_pci_up(struct si_pub *sih); 217extern void ai_pci_up(struct si_pub *sih);
@@ -299,4 +221,52 @@ extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
299/* Enable Ex-PA for 4313 */ 221/* Enable Ex-PA for 4313 */
300extern void ai_epa_4313war(struct si_pub *sih); 222extern void ai_epa_4313war(struct si_pub *sih);
301 223
224extern uint ai_get_buscoretype(struct si_pub *sih);
225extern uint ai_get_buscorerev(struct si_pub *sih);
226
227static inline int ai_get_ccrev(struct si_pub *sih)
228{
229 return sih->ccrev;
230}
231
232static inline u32 ai_get_cccaps(struct si_pub *sih)
233{
234 return sih->cccaps;
235}
236
237static inline int ai_get_pmurev(struct si_pub *sih)
238{
239 return sih->pmurev;
240}
241
242static inline u32 ai_get_pmucaps(struct si_pub *sih)
243{
244 return sih->pmucaps;
245}
246
247static inline uint ai_get_boardtype(struct si_pub *sih)
248{
249 return sih->boardtype;
250}
251
252static inline uint ai_get_boardvendor(struct si_pub *sih)
253{
254 return sih->boardvendor;
255}
256
257static inline uint ai_get_chip_id(struct si_pub *sih)
258{
259 return sih->chip;
260}
261
262static inline uint ai_get_chiprev(struct si_pub *sih)
263{
264 return sih->chiprev;
265}
266
267static inline uint ai_get_chippkg(struct si_pub *sih)
268{
269 return sih->chippkg;
270}
271
302#endif /* _BRCM_AIUTILS_H_ */ 272#endif /* _BRCM_AIUTILS_H_ */