diff options
Diffstat (limited to 'drivers/net/wireless/brcm80211/brcmsmac/aiutils.c')
-rw-r--r-- | drivers/net/wireless/brcm80211/brcmsmac/aiutils.c | 190 |
1 files changed, 70 insertions, 120 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c index bb12ebc20377..7e5d41bd994a 100644 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c | |||
@@ -558,28 +558,26 @@ static bool ai_buscore_prep(struct si_info *sii) | |||
558 | } | 558 | } |
559 | 559 | ||
560 | static bool | 560 | static bool |
561 | ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx) | 561 | ai_buscore_setup(struct si_info *sii, struct bcma_device *cc) |
562 | { | 562 | { |
563 | bool pci, pcie; | 563 | bool pci, pcie; |
564 | uint i; | 564 | uint i; |
565 | uint pciidx, pcieidx, pcirev, pcierev; | 565 | uint pciidx, pcieidx, pcirev, pcierev; |
566 | struct chipcregs __iomem *cc; | ||
567 | |||
568 | cc = ai_setcoreidx(&sii->pub, SI_CC_IDX); | ||
569 | 566 | ||
570 | /* get chipcommon rev */ | 567 | /* get chipcommon rev */ |
571 | sii->pub.ccrev = (int)ai_corerev(&sii->pub); | 568 | sii->pub.ccrev = cc->id.rev; |
572 | 569 | ||
573 | /* get chipcommon chipstatus */ | 570 | /* get chipcommon chipstatus */ |
574 | if (ai_get_ccrev(&sii->pub) >= 11) | 571 | if (ai_get_ccrev(&sii->pub) >= 11) |
575 | sii->chipst = R_REG(&cc->chipstatus); | 572 | sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus)); |
576 | 573 | ||
577 | /* get chipcommon capabilites */ | 574 | /* get chipcommon capabilites */ |
578 | sii->pub.cccaps = R_REG(&cc->capabilities); | 575 | sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities)); |
579 | 576 | ||
580 | /* get pmu rev and caps */ | 577 | /* get pmu rev and caps */ |
581 | if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) { | 578 | if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) { |
582 | sii->pub.pmucaps = R_REG(&cc->pmucapabilities); | 579 | sii->pub.pmucaps = bcma_read32(cc, |
580 | CHIPCREGOFFS(pmucapabilities)); | ||
583 | sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; | 581 | sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; |
584 | } | 582 | } |
585 | 583 | ||
@@ -608,11 +606,6 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx) | |||
608 | pcierev = crev; | 606 | pcierev = crev; |
609 | pcie = true; | 607 | pcie = true; |
610 | } | 608 | } |
611 | |||
612 | /* find the core idx before entering this func. */ | ||
613 | if ((savewin && (savewin == sii->coresba[i])) || | ||
614 | (cc == sii->regs[i])) | ||
615 | *origidx = i; | ||
616 | } | 609 | } |
617 | 610 | ||
618 | if (pci && pcie) { | 611 | if (pci && pcie) { |
@@ -642,9 +635,6 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx) | |||
642 | return false; | 635 | return false; |
643 | } | 636 | } |
644 | 637 | ||
645 | /* return to the original core */ | ||
646 | ai_setcoreidx(&sii->pub, *origidx); | ||
647 | |||
648 | return true; | 638 | return true; |
649 | } | 639 | } |
650 | 640 | ||
@@ -668,9 +658,8 @@ static struct si_info *ai_doattach(struct si_info *sii, | |||
668 | void __iomem *regs = pbus->mmio; | 658 | void __iomem *regs = pbus->mmio; |
669 | struct si_pub *sih = &sii->pub; | 659 | struct si_pub *sih = &sii->pub; |
670 | u32 w, savewin; | 660 | u32 w, savewin; |
671 | struct chipcregs __iomem *cc; | 661 | struct bcma_device *cc; |
672 | uint socitype; | 662 | uint socitype; |
673 | uint origidx; | ||
674 | 663 | ||
675 | memset((unsigned char *) sii, 0, sizeof(struct si_info)); | 664 | memset((unsigned char *) sii, 0, sizeof(struct si_info)); |
676 | 665 | ||
@@ -683,10 +672,7 @@ static struct si_info *ai_doattach(struct si_info *sii, | |||
683 | sii->curwrap = sii->curmap + SI_CORE_SIZE; | 672 | sii->curwrap = sii->curmap + SI_CORE_SIZE; |
684 | 673 | ||
685 | /* switch to Chipcommon core */ | 674 | /* switch to Chipcommon core */ |
686 | bcma_read32(pbus->drv_cc.core, 0); | 675 | cc = pbus->drv_cc.core; |
687 | savewin = SI_ENUM_BASE; | ||
688 | |||
689 | cc = (struct chipcregs __iomem *) regs; | ||
690 | 676 | ||
691 | /* bus/core/clk setup for register access */ | 677 | /* bus/core/clk setup for register access */ |
692 | if (!ai_buscore_prep(sii)) | 678 | if (!ai_buscore_prep(sii)) |
@@ -699,7 +685,7 @@ static struct si_info *ai_doattach(struct si_info *sii, | |||
699 | * hosts w/o chipcommon), some way of recognizing them needs to | 685 | * hosts w/o chipcommon), some way of recognizing them needs to |
700 | * be added here. | 686 | * be added here. |
701 | */ | 687 | */ |
702 | w = R_REG(&cc->chipid); | 688 | w = bcma_read32(cc, CHIPCREGOFFS(chipid)); |
703 | socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; | 689 | socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; |
704 | /* Might as wll fill in chip id rev & pkg */ | 690 | /* Might as wll fill in chip id rev & pkg */ |
705 | sih->chip = w & CID_ID_MASK; | 691 | sih->chip = w & CID_ID_MASK; |
@@ -720,8 +706,7 @@ static struct si_info *ai_doattach(struct si_info *sii, | |||
720 | return NULL; | 706 | return NULL; |
721 | 707 | ||
722 | /* bus/core/clk setup */ | 708 | /* bus/core/clk setup */ |
723 | origidx = SI_CC_IDX; | 709 | if (!ai_buscore_setup(sii, cc)) |
724 | if (!ai_buscore_setup(sii, savewin, &origidx)) | ||
725 | goto exit; | 710 | goto exit; |
726 | 711 | ||
727 | /* Init nvram from sprom/otp if they exist */ | 712 | /* Init nvram from sprom/otp if they exist */ |
@@ -731,10 +716,8 @@ static struct si_info *ai_doattach(struct si_info *sii, | |||
731 | ai_nvram_process(sii); | 716 | ai_nvram_process(sii); |
732 | 717 | ||
733 | /* === NVRAM, clock is ready === */ | 718 | /* === NVRAM, clock is ready === */ |
734 | cc = (struct chipcregs __iomem *) ai_setcore(sih, CC_CORE_ID, 0); | 719 | bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0); |
735 | W_REG(&cc->gpiopullup, 0); | 720 | bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0); |
736 | W_REG(&cc->gpiopulldown, 0); | ||
737 | ai_setcoreidx(sih, origidx); | ||
738 | 721 | ||
739 | /* PMU specific initializations */ | 722 | /* PMU specific initializations */ |
740 | if (ai_get_cccaps(sih) & CC_CAP_PMU) { | 723 | if (ai_get_cccaps(sih) & CC_CAP_PMU) { |
@@ -990,11 +973,12 @@ uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val) | |||
990 | } | 973 | } |
991 | 974 | ||
992 | /* return the slow clock source - LPO, XTAL, or PCI */ | 975 | /* return the slow clock source - LPO, XTAL, or PCI */ |
993 | static uint ai_slowclk_src(struct si_info *sii) | 976 | static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc) |
994 | { | 977 | { |
995 | struct chipcregs __iomem *cc; | 978 | struct si_info *sii; |
996 | u32 val; | 979 | u32 val; |
997 | 980 | ||
981 | sii = (struct si_info *)sih; | ||
998 | if (ai_get_ccrev(&sii->pub) < 6) { | 982 | if (ai_get_ccrev(&sii->pub) < 6) { |
999 | pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT, | 983 | pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT, |
1000 | &val); | 984 | &val); |
@@ -1002,9 +986,8 @@ static uint ai_slowclk_src(struct si_info *sii) | |||
1002 | return SCC_SS_PCI; | 986 | return SCC_SS_PCI; |
1003 | return SCC_SS_XTAL; | 987 | return SCC_SS_XTAL; |
1004 | } else if (ai_get_ccrev(&sii->pub) < 10) { | 988 | } else if (ai_get_ccrev(&sii->pub) < 10) { |
1005 | cc = (struct chipcregs __iomem *) | 989 | return bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) & |
1006 | ai_setcoreidx(&sii->pub, sii->curidx); | 990 | SCC_SS_MASK; |
1007 | return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK; | ||
1008 | } else /* Insta-clock */ | 991 | } else /* Insta-clock */ |
1009 | return SCC_SS_XTAL; | 992 | return SCC_SS_XTAL; |
1010 | } | 993 | } |
@@ -1013,24 +996,24 @@ static uint ai_slowclk_src(struct si_info *sii) | |||
1013 | * return the ILP (slowclock) min or max frequency | 996 | * return the ILP (slowclock) min or max frequency |
1014 | * precondition: we've established the chip has dynamic clk control | 997 | * precondition: we've established the chip has dynamic clk control |
1015 | */ | 998 | */ |
1016 | static uint ai_slowclk_freq(struct si_info *sii, bool max_freq, | 999 | static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq, |
1017 | struct chipcregs __iomem *cc) | 1000 | struct bcma_device *cc) |
1018 | { | 1001 | { |
1019 | u32 slowclk; | 1002 | u32 slowclk; |
1020 | uint div; | 1003 | uint div; |
1021 | 1004 | ||
1022 | slowclk = ai_slowclk_src(sii); | 1005 | slowclk = ai_slowclk_src(sih, cc); |
1023 | if (ai_get_ccrev(&sii->pub) < 6) { | 1006 | if (ai_get_ccrev(sih) < 6) { |
1024 | if (slowclk == SCC_SS_PCI) | 1007 | if (slowclk == SCC_SS_PCI) |
1025 | return max_freq ? (PCIMAXFREQ / 64) | 1008 | return max_freq ? (PCIMAXFREQ / 64) |
1026 | : (PCIMINFREQ / 64); | 1009 | : (PCIMINFREQ / 64); |
1027 | else | 1010 | else |
1028 | return max_freq ? (XTALMAXFREQ / 32) | 1011 | return max_freq ? (XTALMAXFREQ / 32) |
1029 | : (XTALMINFREQ / 32); | 1012 | : (XTALMINFREQ / 32); |
1030 | } else if (ai_get_ccrev(&sii->pub) < 10) { | 1013 | } else if (ai_get_ccrev(sih) < 10) { |
1031 | div = 4 * | 1014 | div = 4 * |
1032 | (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> | 1015 | (((bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) & |
1033 | SCC_CD_SHIFT) + 1); | 1016 | SCC_CD_MASK) >> SCC_CD_SHIFT) + 1); |
1034 | if (slowclk == SCC_SS_LPO) | 1017 | if (slowclk == SCC_SS_LPO) |
1035 | return max_freq ? LPOMAXFREQ : LPOMINFREQ; | 1018 | return max_freq ? LPOMAXFREQ : LPOMINFREQ; |
1036 | else if (slowclk == SCC_SS_XTAL) | 1019 | else if (slowclk == SCC_SS_XTAL) |
@@ -1041,15 +1024,15 @@ static uint ai_slowclk_freq(struct si_info *sii, bool max_freq, | |||
1041 | : (PCIMINFREQ / div); | 1024 | : (PCIMINFREQ / div); |
1042 | } else { | 1025 | } else { |
1043 | /* Chipc rev 10 is InstaClock */ | 1026 | /* Chipc rev 10 is InstaClock */ |
1044 | div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT; | 1027 | div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl)); |
1045 | div = 4 * (div + 1); | 1028 | div = 4 * ((div >> SYCC_CD_SHIFT) + 1); |
1046 | return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div); | 1029 | return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div); |
1047 | } | 1030 | } |
1048 | return 0; | 1031 | return 0; |
1049 | } | 1032 | } |
1050 | 1033 | ||
1051 | static void | 1034 | static void |
1052 | ai_clkctl_setdelay(struct si_info *sii, struct chipcregs __iomem *cc) | 1035 | ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc) |
1053 | { | 1036 | { |
1054 | uint slowmaxfreq, pll_delay, slowclk; | 1037 | uint slowmaxfreq, pll_delay, slowclk; |
1055 | uint pll_on_delay, fref_sel_delay; | 1038 | uint pll_on_delay, fref_sel_delay; |
@@ -1062,47 +1045,40 @@ ai_clkctl_setdelay(struct si_info *sii, struct chipcregs __iomem *cc) | |||
1062 | * powered down by dynamic clk control logic. | 1045 | * powered down by dynamic clk control logic. |
1063 | */ | 1046 | */ |
1064 | 1047 | ||
1065 | slowclk = ai_slowclk_src(sii); | 1048 | slowclk = ai_slowclk_src(sih, cc); |
1066 | if (slowclk != SCC_SS_XTAL) | 1049 | if (slowclk != SCC_SS_XTAL) |
1067 | pll_delay += XTAL_ON_DELAY; | 1050 | pll_delay += XTAL_ON_DELAY; |
1068 | 1051 | ||
1069 | /* Starting with 4318 it is ILP that is used for the delays */ | 1052 | /* Starting with 4318 it is ILP that is used for the delays */ |
1070 | slowmaxfreq = | 1053 | slowmaxfreq = |
1071 | ai_slowclk_freq(sii, | 1054 | ai_slowclk_freq(sih, |
1072 | (ai_get_ccrev(&sii->pub) >= 10) ? false : true, cc); | 1055 | (ai_get_ccrev(sih) >= 10) ? false : true, cc); |
1073 | 1056 | ||
1074 | pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; | 1057 | pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; |
1075 | fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; | 1058 | fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; |
1076 | 1059 | ||
1077 | W_REG(&cc->pll_on_delay, pll_on_delay); | 1060 | bcma_write32(cc, CHIPCREGOFFS(pll_on_delay), pll_on_delay); |
1078 | W_REG(&cc->fref_sel_delay, fref_sel_delay); | 1061 | bcma_write32(cc, CHIPCREGOFFS(fref_sel_delay), fref_sel_delay); |
1079 | } | 1062 | } |
1080 | 1063 | ||
1081 | /* initialize power control delay registers */ | 1064 | /* initialize power control delay registers */ |
1082 | void ai_clkctl_init(struct si_pub *sih) | 1065 | void ai_clkctl_init(struct si_pub *sih) |
1083 | { | 1066 | { |
1084 | struct si_info *sii; | 1067 | struct bcma_device *cc; |
1085 | uint origidx = 0; | ||
1086 | struct chipcregs __iomem *cc; | ||
1087 | 1068 | ||
1088 | if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL)) | 1069 | if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL)) |
1089 | return; | 1070 | return; |
1090 | 1071 | ||
1091 | sii = (struct si_info *)sih; | 1072 | cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0); |
1092 | origidx = sii->curidx; | ||
1093 | cc = (struct chipcregs __iomem *) | ||
1094 | ai_setcore(sih, CC_CORE_ID, 0); | ||
1095 | if (cc == NULL) | 1073 | if (cc == NULL) |
1096 | return; | 1074 | return; |
1097 | 1075 | ||
1098 | /* set all Instaclk chip ILP to 1 MHz */ | 1076 | /* set all Instaclk chip ILP to 1 MHz */ |
1099 | if (ai_get_ccrev(sih) >= 10) | 1077 | if (ai_get_ccrev(sih) >= 10) |
1100 | SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, | 1078 | bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK, |
1101 | (ILP_DIV_1MHZ << SYCC_CD_SHIFT)); | 1079 | (ILP_DIV_1MHZ << SYCC_CD_SHIFT)); |
1102 | |||
1103 | ai_clkctl_setdelay(sii, cc); | ||
1104 | 1080 | ||
1105 | ai_setcoreidx(sih, origidx); | 1081 | ai_clkctl_setdelay(sih, cc); |
1106 | } | 1082 | } |
1107 | 1083 | ||
1108 | /* | 1084 | /* |
@@ -1112,8 +1088,7 @@ void ai_clkctl_init(struct si_pub *sih) | |||
1112 | u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih) | 1088 | u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih) |
1113 | { | 1089 | { |
1114 | struct si_info *sii; | 1090 | struct si_info *sii; |
1115 | uint origidx = 0; | 1091 | struct bcma_device *cc; |
1116 | struct chipcregs __iomem *cc; | ||
1117 | uint slowminfreq; | 1092 | uint slowminfreq; |
1118 | u16 fpdelay; | 1093 | u16 fpdelay; |
1119 | uint intr_val = 0; | 1094 | uint intr_val = 0; |
@@ -1130,19 +1105,17 @@ u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih) | |||
1130 | return 0; | 1105 | return 0; |
1131 | 1106 | ||
1132 | fpdelay = 0; | 1107 | fpdelay = 0; |
1133 | origidx = sii->curidx; | ||
1134 | INTR_OFF(sii, intr_val); | 1108 | INTR_OFF(sii, intr_val); |
1135 | cc = (struct chipcregs __iomem *) | 1109 | cc = ai_findcore(sih, CC_CORE_ID, 0); |
1136 | ai_setcore(sih, CC_CORE_ID, 0); | ||
1137 | if (cc == NULL) | 1110 | if (cc == NULL) |
1138 | goto done; | 1111 | goto done; |
1139 | 1112 | ||
1140 | slowminfreq = ai_slowclk_freq(sii, false, cc); | 1113 | |
1141 | fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + | 1114 | slowminfreq = ai_slowclk_freq(sih, false, cc); |
1142 | (slowminfreq - 1)) / slowminfreq; | 1115 | fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2) * 1000000) |
1116 | + (slowminfreq - 1)) / slowminfreq; | ||
1143 | 1117 | ||
1144 | done: | 1118 | done: |
1145 | ai_setcoreidx(sih, origidx); | ||
1146 | INTR_RESTORE(sii, intr_val); | 1119 | INTR_RESTORE(sii, intr_val); |
1147 | return fpdelay; | 1120 | return fpdelay; |
1148 | } | 1121 | } |
@@ -1213,8 +1186,7 @@ int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on) | |||
1213 | /* clk control mechanism through chipcommon, no policy checking */ | 1186 | /* clk control mechanism through chipcommon, no policy checking */ |
1214 | static bool _ai_clkctl_cc(struct si_info *sii, uint mode) | 1187 | static bool _ai_clkctl_cc(struct si_info *sii, uint mode) |
1215 | { | 1188 | { |
1216 | uint origidx = 0; | 1189 | struct bcma_device *cc; |
1217 | struct chipcregs __iomem *cc; | ||
1218 | u32 scc; | 1190 | u32 scc; |
1219 | uint intr_val = 0; | 1191 | uint intr_val = 0; |
1220 | 1192 | ||
@@ -1223,9 +1195,7 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode) | |||
1223 | return false; | 1195 | return false; |
1224 | 1196 | ||
1225 | INTR_OFF(sii, intr_val); | 1197 | INTR_OFF(sii, intr_val); |
1226 | origidx = sii->curidx; | 1198 | cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0); |
1227 | cc = (struct chipcregs __iomem *) | ||
1228 | ai_setcore(&sii->pub, CC_CORE_ID, 0); | ||
1229 | 1199 | ||
1230 | if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) && | 1200 | if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) && |
1231 | (ai_get_ccrev(&sii->pub) < 20)) | 1201 | (ai_get_ccrev(&sii->pub) < 20)) |
@@ -1239,19 +1209,19 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode) | |||
1239 | * on before we clear SCC_DYN_XTAL.. | 1209 | * on before we clear SCC_DYN_XTAL.. |
1240 | */ | 1210 | */ |
1241 | ai_clkctl_xtal(&sii->pub, XTAL, ON); | 1211 | ai_clkctl_xtal(&sii->pub, XTAL, ON); |
1242 | SET_REG(&cc->slow_clk_ctl, | 1212 | bcma_maskset32(cc, CHIPCREGOFFS(slow_clk_ctl), |
1243 | (SCC_XC | SCC_FS | SCC_IP), SCC_IP); | 1213 | (SCC_XC | SCC_FS | SCC_IP), SCC_IP); |
1244 | } else if (ai_get_ccrev(&sii->pub) < 20) { | 1214 | } else if (ai_get_ccrev(&sii->pub) < 20) { |
1245 | OR_REG(&cc->system_clk_ctl, SYCC_HR); | 1215 | bcma_set32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_HR); |
1246 | } else { | 1216 | } else { |
1247 | OR_REG(&cc->clk_ctl_st, CCS_FORCEHT); | 1217 | bcma_set32(cc, CHIPCREGOFFS(clk_ctl_st), CCS_FORCEHT); |
1248 | } | 1218 | } |
1249 | 1219 | ||
1250 | /* wait for the PLL */ | 1220 | /* wait for the PLL */ |
1251 | if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) { | 1221 | if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) { |
1252 | u32 htavail = CCS_HTAVAIL; | 1222 | u32 htavail = CCS_HTAVAIL; |
1253 | SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail) | 1223 | SPINWAIT(((bcma_read32(cc, CHIPCREGOFFS(clk_ctl_st)) & |
1254 | == 0), PMU_MAX_TRANSITION_DLY); | 1224 | htavail) == 0), PMU_MAX_TRANSITION_DLY); |
1255 | } else { | 1225 | } else { |
1256 | udelay(PLL_DELAY); | 1226 | udelay(PLL_DELAY); |
1257 | } | 1227 | } |
@@ -1259,11 +1229,11 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode) | |||
1259 | 1229 | ||
1260 | case CLK_DYNAMIC: /* enable dynamic clock control */ | 1230 | case CLK_DYNAMIC: /* enable dynamic clock control */ |
1261 | if (ai_get_ccrev(&sii->pub) < 10) { | 1231 | if (ai_get_ccrev(&sii->pub) < 10) { |
1262 | scc = R_REG(&cc->slow_clk_ctl); | 1232 | scc = bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)); |
1263 | scc &= ~(SCC_FS | SCC_IP | SCC_XC); | 1233 | scc &= ~(SCC_FS | SCC_IP | SCC_XC); |
1264 | if ((scc & SCC_SS_MASK) != SCC_SS_XTAL) | 1234 | if ((scc & SCC_SS_MASK) != SCC_SS_XTAL) |
1265 | scc |= SCC_XC; | 1235 | scc |= SCC_XC; |
1266 | W_REG(&cc->slow_clk_ctl, scc); | 1236 | bcma_write32(cc, CHIPCREGOFFS(slow_clk_ctl), scc); |
1267 | 1237 | ||
1268 | /* | 1238 | /* |
1269 | * for dynamic control, we have to | 1239 | * for dynamic control, we have to |
@@ -1273,9 +1243,9 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode) | |||
1273 | ai_clkctl_xtal(&sii->pub, XTAL, OFF); | 1243 | ai_clkctl_xtal(&sii->pub, XTAL, OFF); |
1274 | } else if (ai_get_ccrev(&sii->pub) < 20) { | 1244 | } else if (ai_get_ccrev(&sii->pub) < 20) { |
1275 | /* Instaclock */ | 1245 | /* Instaclock */ |
1276 | AND_REG(&cc->system_clk_ctl, ~SYCC_HR); | 1246 | bcma_mask32(cc, CHIPCREGOFFS(system_clk_ctl), ~SYCC_HR); |
1277 | } else { | 1247 | } else { |
1278 | AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT); | 1248 | bcma_mask32(cc, CHIPCREGOFFS(clk_ctl_st), ~CCS_FORCEHT); |
1279 | } | 1249 | } |
1280 | break; | 1250 | break; |
1281 | 1251 | ||
@@ -1284,7 +1254,6 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode) | |||
1284 | } | 1254 | } |
1285 | 1255 | ||
1286 | done: | 1256 | done: |
1287 | ai_setcoreidx(&sii->pub, origidx); | ||
1288 | INTR_RESTORE(sii, intr_val); | 1257 | INTR_RESTORE(sii, intr_val); |
1289 | return mode == CLK_FAST; | 1258 | return mode == CLK_FAST; |
1290 | } | 1259 | } |
@@ -1427,53 +1396,37 @@ u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority) | |||
1427 | 1396 | ||
1428 | void ai_chipcontrl_epa4331(struct si_pub *sih, bool on) | 1397 | void ai_chipcontrl_epa4331(struct si_pub *sih, bool on) |
1429 | { | 1398 | { |
1430 | struct si_info *sii; | 1399 | struct bcma_device *cc; |
1431 | struct chipcregs __iomem *cc; | ||
1432 | uint origidx; | ||
1433 | u32 val; | 1400 | u32 val; |
1434 | 1401 | ||
1435 | sii = (struct si_info *)sih; | 1402 | cc = ai_findcore(sih, CC_CORE_ID, 0); |
1436 | origidx = ai_coreidx(sih); | ||
1437 | |||
1438 | cc = (struct chipcregs __iomem *) ai_setcore(sih, CC_CORE_ID, 0); | ||
1439 | |||
1440 | val = R_REG(&cc->chipcontrol); | ||
1441 | 1403 | ||
1442 | if (on) { | 1404 | if (on) { |
1443 | if (ai_get_chippkg(sih) == 9 || ai_get_chippkg(sih) == 0xb) | 1405 | if (ai_get_chippkg(sih) == 9 || ai_get_chippkg(sih) == 0xb) |
1444 | /* Ext PA Controls for 4331 12x9 Package */ | 1406 | /* Ext PA Controls for 4331 12x9 Package */ |
1445 | W_REG(&cc->chipcontrol, val | | 1407 | bcma_set32(cc, CHIPCREGOFFS(chipcontrol), |
1446 | CCTRL4331_EXTPA_EN | | 1408 | CCTRL4331_EXTPA_EN | |
1447 | CCTRL4331_EXTPA_ON_GPIO2_5); | 1409 | CCTRL4331_EXTPA_ON_GPIO2_5); |
1448 | else | 1410 | else |
1449 | /* Ext PA Controls for 4331 12x12 Package */ | 1411 | /* Ext PA Controls for 4331 12x12 Package */ |
1450 | W_REG(&cc->chipcontrol, | 1412 | bcma_set32(cc, CHIPCREGOFFS(chipcontrol), |
1451 | val | CCTRL4331_EXTPA_EN); | 1413 | CCTRL4331_EXTPA_EN); |
1452 | } else { | 1414 | } else { |
1453 | val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5); | 1415 | val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5); |
1454 | W_REG(&cc->chipcontrol, val); | 1416 | bcma_mask32(cc, CHIPCREGOFFS(chipcontrol), |
1417 | ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5)); | ||
1455 | } | 1418 | } |
1456 | |||
1457 | ai_setcoreidx(sih, origidx); | ||
1458 | } | 1419 | } |
1459 | 1420 | ||
1460 | /* Enable BT-COEX & Ex-PA for 4313 */ | 1421 | /* Enable BT-COEX & Ex-PA for 4313 */ |
1461 | void ai_epa_4313war(struct si_pub *sih) | 1422 | void ai_epa_4313war(struct si_pub *sih) |
1462 | { | 1423 | { |
1463 | struct si_info *sii; | 1424 | struct bcma_device *cc; |
1464 | struct chipcregs __iomem *cc; | ||
1465 | uint origidx; | ||
1466 | |||
1467 | sii = (struct si_info *)sih; | ||
1468 | origidx = ai_coreidx(sih); | ||
1469 | 1425 | ||
1470 | cc = ai_setcore(sih, CC_CORE_ID, 0); | 1426 | cc = ai_findcore(sih, CC_CORE_ID, 0); |
1471 | 1427 | ||
1472 | /* EPA Fix */ | 1428 | /* EPA Fix */ |
1473 | W_REG(&cc->gpiocontrol, | 1429 | bcma_set32(cc, CHIPCREGOFFS(gpiocontrol), GPIO_CTRL_EPA_EN_MASK); |
1474 | R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK); | ||
1475 | |||
1476 | ai_setcoreidx(sih, origidx); | ||
1477 | } | 1430 | } |
1478 | 1431 | ||
1479 | /* check if the device is removed */ | 1432 | /* check if the device is removed */ |
@@ -1496,17 +1449,14 @@ bool ai_is_sprom_available(struct si_pub *sih) | |||
1496 | struct si_info *sii = (struct si_info *)sih; | 1449 | struct si_info *sii = (struct si_info *)sih; |
1497 | 1450 | ||
1498 | if (ai_get_ccrev(sih) >= 31) { | 1451 | if (ai_get_ccrev(sih) >= 31) { |
1499 | uint origidx; | 1452 | struct bcma_device *cc; |
1500 | struct chipcregs __iomem *cc; | ||
1501 | u32 sromctrl; | 1453 | u32 sromctrl; |
1502 | 1454 | ||
1503 | if ((ai_get_cccaps(sih) & CC_CAP_SROM) == 0) | 1455 | if ((ai_get_cccaps(sih) & CC_CAP_SROM) == 0) |
1504 | return false; | 1456 | return false; |
1505 | 1457 | ||
1506 | origidx = sii->curidx; | 1458 | cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0); |
1507 | cc = ai_setcoreidx(sih, SI_CC_IDX); | 1459 | sromctrl = bcma_read32(cc, CHIPCREGOFFS(sromcontrol)); |
1508 | sromctrl = R_REG(&cc->sromcontrol); | ||
1509 | ai_setcoreidx(sih, origidx); | ||
1510 | return sromctrl & SRC_PRESENT; | 1460 | return sromctrl & SRC_PRESENT; |
1511 | } | 1461 | } |
1512 | 1462 | ||