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-rw-r--r--drivers/net/wireless/ath/ath.h2
-rw-r--r--drivers/net/wireless/ath/ath5k/base.c6
-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile1
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c5
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c11
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h172
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_calib.c250
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c59
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c186
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_paprd.c15
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c97
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h52
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_rtt.c153
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_rtt.h28
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h (renamed from drivers/net/wireless/ath/ath9k/ar9480_1p0_initvals.h)62
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h (renamed from drivers/net/wireless/ath/ath9k/ar9480_2p0_initvals.h)68
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/common.c6
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c19
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h13
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h10
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c29
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c35
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c45
-rw-r--r--drivers/net/wireless/ath/ath9k/gpio.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/hw-ops.h7
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c158
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h39
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.h6
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c25
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c35
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h29
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c40
-rw-r--r--drivers/net/wireless/ath/carl9170/main.c1
39 files changed, 1098 insertions, 604 deletions
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index 4ed7f248a577..908fdbc3e0ee 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -71,9 +71,7 @@ struct ath_regulatory {
71 char alpha2[2]; 71 char alpha2[2];
72 u16 country_code; 72 u16 country_code;
73 u16 max_power_level; 73 u16 max_power_level;
74 u32 tp_scale;
75 u16 current_rd; 74 u16 current_rd;
76 u16 current_rd_ext;
77 int16_t power_limit; 75 int16_t power_limit;
78 struct reg_dmn_pair_mapping *regpair; 76 struct reg_dmn_pair_mapping *regpair;
79}; 77};
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index e9ea38d0fff6..b346d0492001 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -921,12 +921,6 @@ ath5k_txq_setup(struct ath5k_hw *ah,
921 */ 921 */
922 return ERR_PTR(qnum); 922 return ERR_PTR(qnum);
923 } 923 }
924 if (qnum >= ARRAY_SIZE(ah->txqs)) {
925 ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
926 qnum, ARRAY_SIZE(ah->txqs));
927 ath5k_hw_release_tx_queue(ah, qnum);
928 return ERR_PTR(-EINVAL);
929 }
930 txq = &ah->txqs[qnum]; 924 txq = &ah->txqs[qnum];
931 if (!txq->setup) { 925 if (!txq->setup) {
932 txq->qnum = qnum; 926 txq->qnum = qnum;
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 05a6fade7b1c..36ed3c46fec6 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -21,6 +21,7 @@ ath9k_hw-y:= \
21 ar5008_phy.o \ 21 ar5008_phy.o \
22 ar9002_calib.o \ 22 ar9002_calib.o \
23 ar9003_calib.o \ 23 ar9003_calib.o \
24 ar9003_rtt.o \
24 calib.o \ 25 calib.o \
25 eeprom.o \ 26 eeprom.o \
26 eeprom_def.o \ 27 eeprom_def.o \
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 01240d63896e..2776c3c1f506 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -504,9 +504,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
504 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, 504 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
505 ATH9K_ANI_CCK_WEAK_SIG_THR); 505 ATH9K_ANI_CCK_WEAK_SIG_THR);
506 506
507 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
508 ATH9K_RX_FILTER_PHYERR);
509
510 ath9k_ani_restart(ah); 507 ath9k_ani_restart(ah);
511 return; 508 return;
512 } 509 }
@@ -527,8 +524,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
527 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 524 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
528 aniState->firstepLevel); 525 aniState->firstepLevel);
529 526
530 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
531 ~ATH9K_RX_FILTER_PHYERR);
532 ath9k_ani_restart(ah); 527 ath9k_ani_restart(ah);
533 528
534 ENABLE_REGWRITE_BUFFER(ah); 529 ENABLE_REGWRITE_BUFFER(ah);
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index 0a749c8fa634..f199e9e25149 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -763,10 +763,8 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
763static int ar5008_hw_process_ini(struct ath_hw *ah, 763static int ar5008_hw_process_ini(struct ath_hw *ah,
764 struct ath9k_channel *chan) 764 struct ath9k_channel *chan)
765{ 765{
766 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
767 struct ath_common *common = ath9k_hw_common(ah); 766 struct ath_common *common = ath9k_hw_common(ah);
768 int i, regWrites = 0; 767 int i, regWrites = 0;
769 struct ieee80211_channel *channel = chan->chan;
770 u32 modesIndex, freqIndex; 768 u32 modesIndex, freqIndex;
771 769
772 switch (chan->chanmode) { 770 switch (chan->chanmode) {
@@ -903,14 +901,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
903 ar5008_hw_set_channel_regs(ah, chan); 901 ar5008_hw_set_channel_regs(ah, chan);
904 ar5008_hw_init_chain_masks(ah); 902 ar5008_hw_init_chain_masks(ah);
905 ath9k_olc_init(ah); 903 ath9k_olc_init(ah);
906 904 ath9k_hw_apply_txpower(ah, chan);
907 /* Set TX power */
908 ah->eep_ops->set_txpower(ah, chan,
909 ath9k_regd_get_ctl(regulatory, chan),
910 channel->max_antenna_gain * 2,
911 channel->max_power * 2,
912 min((u32) MAX_RATE_POWER,
913 (u32) regulatory->power_limit), false);
914 905
915 /* Write analog registers */ 906 /* Write analog registers */
916 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 907 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index 08e9341f6368..026f9de15d15 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -24,11 +24,11 @@ static const u32 ar9300_2p2_radio_postamble[][5] = {
24 {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31}, 24 {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
25 {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800}, 25 {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
26 {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20}, 26 {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
27 {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000}, 27 {0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
28 {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, 28 {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
29 {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000}, 29 {0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
30 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, 30 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
31 {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000}, 31 {0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
32 {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, 32 {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
33}; 33};
34 34
@@ -190,7 +190,7 @@ static const u32 ar9300_2p2_radio_core[][2] = {
190 {0x00016288, 0x05a20408}, 190 {0x00016288, 0x05a20408},
191 {0x0001628c, 0x00038c07}, 191 {0x0001628c, 0x00038c07},
192 {0x00016290, 0x00000004}, 192 {0x00016290, 0x00000004},
193 {0x00016294, 0x458aa14f}, 193 {0x00016294, 0x458a214f},
194 {0x00016380, 0x00000000}, 194 {0x00016380, 0x00000000},
195 {0x00016384, 0x00000000}, 195 {0x00016384, 0x00000000},
196 {0x00016388, 0x00800700}, 196 {0x00016388, 0x00800700},
@@ -835,107 +835,107 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
835 835
836static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = { 836static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
837 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 837 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
838 {0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352}, 838 {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
839 {0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584}, 839 {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
840 {0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800}, 840 {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
841 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, 841 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
842 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, 842 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
843 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 843 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
844 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, 844 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
845 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, 845 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
846 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, 846 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
847 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, 847 {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
848 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, 848 {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
849 {0x0000a518, 0x21002220, 0x21002220, 0x16000402, 0x16000402}, 849 {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
850 {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404}, 850 {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
851 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, 851 {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
852 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, 852 {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
853 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, 853 {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
854 {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20}, 854 {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
855 {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20}, 855 {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
856 {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22}, 856 {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
857 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24}, 857 {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
858 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640}, 858 {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
859 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, 859 {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
860 {0x0000a544, 0x52022470, 0x52022470, 0x3f001861, 0x3f001861}, 860 {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
861 {0x0000a548, 0x55022490, 0x55022490, 0x43001a81, 0x43001a81}, 861 {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
862 {0x0000a54c, 0x59022492, 0x59022492, 0x47001a83, 0x47001a83}, 862 {0x0000a54c, 0x5a08442e, 0x5a08442e, 0x47001a83, 0x47001a83},
863 {0x0000a550, 0x5d022692, 0x5d022692, 0x4a001c84, 0x4a001c84}, 863 {0x0000a550, 0x5e0a4431, 0x5e0a4431, 0x4a001c84, 0x4a001c84},
864 {0x0000a554, 0x61022892, 0x61022892, 0x4e001ce3, 0x4e001ce3}, 864 {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
865 {0x0000a558, 0x65024890, 0x65024890, 0x52001ce5, 0x52001ce5}, 865 {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
866 {0x0000a55c, 0x69024892, 0x69024892, 0x56001ce9, 0x56001ce9}, 866 {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
867 {0x0000a560, 0x6e024c92, 0x6e024c92, 0x5a001ceb, 0x5a001ceb}, 867 {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
868 {0x0000a564, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec}, 868 {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
869 {0x0000a568, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec}, 869 {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
870 {0x0000a56c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec}, 870 {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
871 {0x0000a570, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec}, 871 {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
872 {0x0000a574, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec}, 872 {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
873 {0x0000a578, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec}, 873 {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
874 {0x0000a57c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec}, 874 {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
875 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, 875 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
876 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, 876 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
877 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, 877 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
878 {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200}, 878 {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
879 {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202}, 879 {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
880 {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400}, 880 {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
881 {0x0000a598, 0x21802220, 0x21802220, 0x16800402, 0x16800402}, 881 {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
882 {0x0000a59c, 0x27802223, 0x27802223, 0x19800404, 0x19800404}, 882 {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
883 {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603}, 883 {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
884 {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02}, 884 {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
885 {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04}, 885 {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
886 {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20}, 886 {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
887 {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20}, 887 {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
888 {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22}, 888 {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
889 {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24}, 889 {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
890 {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640}, 890 {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
891 {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660}, 891 {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
892 {0x0000a5c4, 0x52822470, 0x52822470, 0x3f801861, 0x3f801861}, 892 {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
893 {0x0000a5c8, 0x55822490, 0x55822490, 0x43801a81, 0x43801a81}, 893 {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
894 {0x0000a5cc, 0x59822492, 0x59822492, 0x47801a83, 0x47801a83}, 894 {0x0000a5cc, 0x5a88442e, 0x5a88442e, 0x47801a83, 0x47801a83},
895 {0x0000a5d0, 0x5d822692, 0x5d822692, 0x4a801c84, 0x4a801c84}, 895 {0x0000a5d0, 0x5e8a4431, 0x5e8a4431, 0x4a801c84, 0x4a801c84},
896 {0x0000a5d4, 0x61822892, 0x61822892, 0x4e801ce3, 0x4e801ce3}, 896 {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
897 {0x0000a5d8, 0x65824890, 0x65824890, 0x52801ce5, 0x52801ce5}, 897 {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
898 {0x0000a5dc, 0x69824892, 0x69824892, 0x56801ce9, 0x56801ce9}, 898 {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
899 {0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x5a801ceb, 0x5a801ceb}, 899 {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
900 {0x0000a5e4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec}, 900 {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
901 {0x0000a5e8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec}, 901 {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
902 {0x0000a5ec, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec}, 902 {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
903 {0x0000a5f0, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec}, 903 {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
904 {0x0000a5f4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec}, 904 {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
905 {0x0000a5f8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec}, 905 {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
906 {0x0000a5fc, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec}, 906 {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
907 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 907 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
908 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 908 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
909 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 909 {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
910 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 910 {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
911 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 911 {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
912 {0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000}, 912 {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
913 {0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501}, 913 {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
914 {0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501}, 914 {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
915 {0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03}, 915 {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
916 {0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04}, 916 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
917 {0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04}, 917 {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
918 {0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005}, 918 {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
919 {0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005}, 919 {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
920 {0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005}, 920 {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
921 {0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005}, 921 {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
922 {0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005}, 922 {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
923 {0x0000b2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352}, 923 {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
924 {0x0000b2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584}, 924 {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
925 {0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800}, 925 {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
926 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, 926 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
927 {0x0000c2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352}, 927 {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
928 {0x0000c2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584}, 928 {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
929 {0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800}, 929 {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
930 {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, 930 {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
931 {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, 931 {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
932 {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, 932 {0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
933 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 933 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
934 {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, 934 {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
935 {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, 935 {0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
936 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 936 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
937 {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, 937 {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
938 {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, 938 {0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
939 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 939 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
940}; 940};
941 941
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index e4b1a8300854..16851cb109a6 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -17,8 +17,9 @@
17#include "hw.h" 17#include "hw.h"
18#include "hw-ops.h" 18#include "hw-ops.h"
19#include "ar9003_phy.h" 19#include "ar9003_phy.h"
20#include "ar9003_rtt.h"
20 21
21#define MAX_MEASUREMENT 8 22#define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
22#define MAX_MAG_DELTA 11 23#define MAX_MAG_DELTA 11
23#define MAX_PHS_DELTA 10 24#define MAX_PHS_DELTA 10
24 25
@@ -659,10 +660,12 @@ static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
659 660
660static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah, 661static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
661 u8 num_chains, 662 u8 num_chains,
662 struct coeff *coeff) 663 struct coeff *coeff,
664 bool is_reusable)
663{ 665{
664 int i, im, nmeasurement; 666 int i, im, nmeasurement;
665 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS]; 667 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
668 struct ath9k_hw_cal_data *caldata = ah->caldata;
666 669
667 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff)); 670 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
668 for (i = 0; i < MAX_MEASUREMENT / 2; i++) { 671 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
@@ -712,7 +715,13 @@ static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
712 REG_RMW_FIELD(ah, tx_corr_coeff[im][i], 715 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
713 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 716 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
714 coeff->iqc_coeff[0]); 717 coeff->iqc_coeff[0]);
718
719 if (caldata)
720 caldata->tx_corr_coeff[im][i] =
721 coeff->iqc_coeff[0];
715 } 722 }
723 if (caldata)
724 caldata->num_measures[i] = nmeasurement;
716 } 725 }
717 726
718 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, 727 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
@@ -720,8 +729,10 @@ static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
720 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0, 729 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
721 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1); 730 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
722 731
723 return; 732 if (caldata)
733 caldata->done_txiqcal_once = is_reusable;
724 734
735 return;
725} 736}
726 737
727static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah) 738static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
@@ -748,7 +759,7 @@ static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
748 return true; 759 return true;
749} 760}
750 761
751static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah) 762static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable)
752{ 763{
753 struct ath_common *common = ath9k_hw_common(ah); 764 struct ath_common *common = ath9k_hw_common(ah);
754 const u32 txiqcal_status[AR9300_MAX_CHAINS] = { 765 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
@@ -837,7 +848,8 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
837 coeff.phs_coeff[i][im] -= 128; 848 coeff.phs_coeff[i][im] -= 128;
838 } 849 }
839 } 850 }
840 ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff); 851 ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains,
852 &coeff, is_reusable);
841 853
842 return; 854 return;
843 855
@@ -845,11 +857,129 @@ tx_iqcal_fail:
845 ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n"); 857 ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
846 return; 858 return;
847} 859}
860
861static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
862{
863 struct ath9k_hw_cal_data *caldata = ah->caldata;
864 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
865 int i, im;
866
867 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
868 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
869 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
870 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
871 if (!AR_SREV_9485(ah)) {
872 tx_corr_coeff[i * 2][1] =
873 tx_corr_coeff[(i * 2) + 1][1] =
874 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
875
876 tx_corr_coeff[i * 2][2] =
877 tx_corr_coeff[(i * 2) + 1][2] =
878 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
879 }
880 }
881
882 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
883 if (!(ah->txchainmask & (1 << i)))
884 continue;
885
886 for (im = 0; im < caldata->num_measures[i]; im++) {
887 if ((im % 2) == 0)
888 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
889 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
890 caldata->tx_corr_coeff[im][i]);
891 else
892 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
893 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
894 caldata->tx_corr_coeff[im][i]);
895 }
896 }
897
898 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
899 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
900 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
901 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
902}
903
904static bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
905{
906 struct ath9k_rtt_hist *hist;
907 u32 *table;
908 int i;
909 bool restore;
910
911 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT) || !ah->caldata)
912 return false;
913
914 hist = &ah->caldata->rtt_hist;
915 ar9003_hw_rtt_enable(ah);
916 ar9003_hw_rtt_set_mask(ah, 0x10);
917 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
918 if (!(ah->rxchainmask & (1 << i)))
919 continue;
920 table = &hist->table[i][hist->num_readings][0];
921 ar9003_hw_rtt_load_hist(ah, i, table);
922 }
923 restore = ar9003_hw_rtt_force_restore(ah);
924 ar9003_hw_rtt_disable(ah);
925
926 return restore;
927}
928
848static bool ar9003_hw_init_cal(struct ath_hw *ah, 929static bool ar9003_hw_init_cal(struct ath_hw *ah,
849 struct ath9k_channel *chan) 930 struct ath9k_channel *chan)
850{ 931{
851 struct ath_common *common = ath9k_hw_common(ah); 932 struct ath_common *common = ath9k_hw_common(ah);
852 bool txiqcal_done = false; 933 struct ath9k_hw_cal_data *caldata = ah->caldata;
934 bool txiqcal_done = false, txclcal_done = false;
935 bool is_reusable = true, status = true;
936 bool run_rtt_cal = false, run_agc_cal;
937 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
938 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
939 AR_PHY_AGC_CONTROL_FLTR_CAL |
940 AR_PHY_AGC_CONTROL_PKDET_CAL;
941 int i, j;
942 u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
943 AR_PHY_CL_TAB_1,
944 AR_PHY_CL_TAB_2 };
945
946 if (rtt) {
947 if (!ar9003_hw_rtt_restore(ah, chan))
948 run_rtt_cal = true;
949
950 ath_dbg(common, ATH_DBG_CALIBRATE, "RTT restore %s\n",
951 run_rtt_cal ? "failed" : "succeed");
952 }
953 run_agc_cal = run_rtt_cal;
954
955 if (run_rtt_cal) {
956 ar9003_hw_rtt_enable(ah);
957 ar9003_hw_rtt_set_mask(ah, 0x00);
958 ar9003_hw_rtt_clear_hist(ah);
959 }
960
961 if (rtt && !run_rtt_cal) {
962 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
963 agc_supp_cals &= agc_ctrl;
964 agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
965 AR_PHY_AGC_CONTROL_FLTR_CAL |
966 AR_PHY_AGC_CONTROL_PKDET_CAL);
967 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
968 }
969
970 if (ah->enabled_cals & TX_CL_CAL) {
971 if (caldata && caldata->done_txclcal_once)
972 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
973 AR_PHY_CL_CAL_ENABLE);
974 else {
975 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
976 AR_PHY_CL_CAL_ENABLE);
977 run_agc_cal = true;
978 }
979 }
980
981 if (!(ah->enabled_cals & TX_IQ_CAL))
982 goto skip_tx_iqcal;
853 983
854 /* Do Tx IQ Calibration */ 984 /* Do Tx IQ Calibration */
855 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1, 985 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
@@ -860,30 +990,96 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
860 * For AR9485 or later chips, TxIQ cal runs as part of 990 * For AR9485 or later chips, TxIQ cal runs as part of
861 * AGC calibration 991 * AGC calibration
862 */ 992 */
863 if (AR_SREV_9485_OR_LATER(ah)) 993 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
864 txiqcal_done = true; 994 if (caldata && !caldata->done_txiqcal_once)
865 else { 995 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
866 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah); 996 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
867 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 997 else
868 udelay(5); 998 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
869 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 999 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
870 } 1000 txiqcal_done = run_agc_cal = true;
871 1001 goto skip_tx_iqcal;
872 /* Calibrate the AGC */ 1002 } else if (caldata && !caldata->done_txiqcal_once)
873 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 1003 run_agc_cal = true;
874 REG_READ(ah, AR_PHY_AGC_CONTROL) | 1004
875 AR_PHY_AGC_CONTROL_CAL); 1005 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
876 1006 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
877 /* Poll for offset calibration complete */ 1007 udelay(5);
878 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1008 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
879 0, AH_WAIT_TIMEOUT)) { 1009
1010skip_tx_iqcal:
1011 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1012 /* Calibrate the AGC */
1013 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1014 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1015 AR_PHY_AGC_CONTROL_CAL);
1016
1017 /* Poll for offset calibration complete */
1018 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1019 AR_PHY_AGC_CONTROL_CAL,
1020 0, AH_WAIT_TIMEOUT);
1021 }
1022 if (rtt && !run_rtt_cal) {
1023 agc_ctrl |= agc_supp_cals;
1024 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1025 }
1026
1027 if (!status) {
1028 if (run_rtt_cal)
1029 ar9003_hw_rtt_disable(ah);
1030
880 ath_dbg(common, ATH_DBG_CALIBRATE, 1031 ath_dbg(common, ATH_DBG_CALIBRATE,
881 "offset calibration failed to complete in 1ms; noisy environment?\n"); 1032 "offset calibration failed to complete in 1ms;"
1033 "noisy environment?\n");
882 return false; 1034 return false;
883 } 1035 }
884 1036
885 if (txiqcal_done) 1037 if (txiqcal_done)
886 ar9003_hw_tx_iq_cal_post_proc(ah); 1038 ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
1039 else if (caldata && caldata->done_txiqcal_once)
1040 ar9003_hw_tx_iq_cal_reload(ah);
1041
1042#define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
1043 if (caldata && (ah->enabled_cals & TX_CL_CAL)) {
1044 txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
1045 AR_PHY_AGC_CONTROL_CLC_SUCCESS);
1046 if (caldata->done_txclcal_once) {
1047 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1048 if (!(ah->txchainmask & (1 << i)))
1049 continue;
1050 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1051 REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
1052 caldata->tx_clcal[i][j]);
1053 }
1054 } else if (is_reusable && txclcal_done) {
1055 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1056 if (!(ah->txchainmask & (1 << i)))
1057 continue;
1058 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1059 caldata->tx_clcal[i][j] =
1060 REG_READ(ah,
1061 CL_TAB_ENTRY(cl_idx[i]));
1062 }
1063 caldata->done_txclcal_once = true;
1064 }
1065 }
1066#undef CL_TAB_ENTRY
1067
1068 if (run_rtt_cal && caldata) {
1069 struct ath9k_rtt_hist *hist = &caldata->rtt_hist;
1070 if (is_reusable && (hist->num_readings < RTT_HIST_MAX)) {
1071 u32 *table;
1072
1073 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1074 if (!(ah->rxchainmask & (1 << i)))
1075 continue;
1076 table = &hist->table[i][hist->num_readings][0];
1077 ar9003_hw_rtt_fill_hist(ah, i, table);
1078 }
1079 }
1080
1081 ar9003_hw_rtt_disable(ah);
1082 }
887 1083
888 ath9k_hw_loadnf(ah, chan); 1084 ath9k_hw_loadnf(ah, chan);
889 ath9k_hw_start_nfcal(ah, true); 1085 ath9k_hw_start_nfcal(ah, true);
@@ -912,8 +1108,8 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
912 if (ah->cal_list_curr) 1108 if (ah->cal_list_curr)
913 ath9k_hw_reset_calibration(ah, ah->cal_list_curr); 1109 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
914 1110
915 if (ah->caldata) 1111 if (caldata)
916 ah->caldata->CalValid = 0; 1112 caldata->CalValid = 0;
917 1113
918 return true; 1114 return true;
919} 1115}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index 51398f0063e2..3b262ba6b172 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -2995,8 +2995,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2995 return get_unaligned_be16(eep->macAddr + 4); 2995 return get_unaligned_be16(eep->macAddr + 4);
2996 case EEP_REG_0: 2996 case EEP_REG_0:
2997 return le16_to_cpu(pBase->regDmn[0]); 2997 return le16_to_cpu(pBase->regDmn[0]);
2998 case EEP_REG_1:
2999 return le16_to_cpu(pBase->regDmn[1]);
3000 case EEP_OP_CAP: 2998 case EEP_OP_CAP:
3001 return pBase->deviceCap; 2999 return pBase->deviceCap;
3002 case EEP_OP_MODE: 3000 case EEP_OP_MODE:
@@ -3021,6 +3019,10 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3021 return (pBase->miscConfiguration >> 0x3) & 0x1; 3019 return (pBase->miscConfiguration >> 0x3) & 0x1;
3022 case EEP_ANT_DIV_CTL1: 3020 case EEP_ANT_DIV_CTL1:
3023 return eep->base_ext1.ant_div_control; 3021 return eep->base_ext1.ant_div_control;
3022 case EEP_ANTENNA_GAIN_5G:
3023 return eep->modalHeader5G.antennaGain;
3024 case EEP_ANTENNA_GAIN_2G:
3025 return eep->modalHeader2G.antennaGain;
3024 default: 3026 default:
3025 return 0; 3027 return 0;
3026 } 3028 }
@@ -3554,7 +3556,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3554 3556
3555 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3557 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3556 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); 3558 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3557 else if (AR_SREV_9480(ah)) 3559 else if (AR_SREV_9462(ah))
3558 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3560 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3559 else { 3561 else {
3560 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3562 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3633,20 +3635,20 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3633 3635
3634 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); 3636 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3635 3637
3636 if (AR_SREV_9480(ah)) { 3638 if (AR_SREV_9462(ah)) {
3637 if (AR_SREV_9480_10(ah)) { 3639 if (AR_SREV_9462_10(ah)) {
3638 value &= ~AR_SWITCH_TABLE_COM_SPDT; 3640 value &= ~AR_SWITCH_TABLE_COM_SPDT;
3639 value |= 0x00100000; 3641 value |= 0x00100000;
3640 } 3642 }
3641 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3643 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3642 AR_SWITCH_TABLE_COM_AR9480_ALL, value); 3644 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3643 } else 3645 } else
3644 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3646 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3645 AR_SWITCH_TABLE_COM_ALL, value); 3647 AR_SWITCH_TABLE_COM_ALL, value);
3646 3648
3647 3649
3648 /* 3650 /*
3649 * AR9480 defines new switch table for BT/WLAN, 3651 * AR9462 defines new switch table for BT/WLAN,
3650 * here's new field name in XXX.ref for both 2G and 5G. 3652 * here's new field name in XXX.ref for both 2G and 5G.
3651 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044) 3653 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3652 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX 3654 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
@@ -3658,7 +3660,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3658 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE 3660 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3659 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE 3661 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3660 */ 3662 */
3661 if (AR_SREV_9480_20_OR_LATER(ah)) { 3663 if (AR_SREV_9462_20_OR_LATER(ah)) {
3662 value = ar9003_switch_com_spdt_get(ah, is2ghz); 3664 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3663 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, 3665 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3664 AR_SWITCH_TABLE_COM_SPDT_ALL, value); 3666 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
@@ -3907,7 +3909,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3907 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3909 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3908 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3910 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3909 return; 3911 return;
3910 } else if (AR_SREV_9480(ah)) { 3912 } else if (AR_SREV_9462(ah)) {
3911 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); 3913 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3912 REG_WRITE(ah, AR_PHY_PMU1, reg_val); 3914 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3913 } else { 3915 } else {
@@ -3938,7 +3940,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3938 while (!REG_READ_FIELD(ah, AR_PHY_PMU2, 3940 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3939 AR_PHY_PMU2_PGM)) 3941 AR_PHY_PMU2_PGM))
3940 udelay(10); 3942 udelay(10);
3941 } else if (AR_SREV_9480(ah)) 3943 } else if (AR_SREV_9462(ah))
3942 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); 3944 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3943 else { 3945 else {
3944 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | 3946 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
@@ -4525,7 +4527,7 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
4525 4527
4526 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope); 4528 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4527 4529
4528 if (AR_SREV_9480_20(ah)) 4530 if (AR_SREV_9462_20(ah))
4529 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, 4531 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4530 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope); 4532 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4531 4533
@@ -4764,20 +4766,14 @@ static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4764static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, 4766static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4765 struct ath9k_channel *chan, 4767 struct ath9k_channel *chan,
4766 u8 *pPwrArray, u16 cfgCtl, 4768 u8 *pPwrArray, u16 cfgCtl,
4767 u8 twiceAntennaReduction, 4769 u8 antenna_reduction,
4768 u8 twiceMaxRegulatoryPower,
4769 u16 powerLimit) 4770 u16 powerLimit)
4770{ 4771{
4771 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4772 struct ath_common *common = ath9k_hw_common(ah); 4772 struct ath_common *common = ath9k_hw_common(ah);
4773 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; 4773 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4774 u16 twiceMaxEdgePower = MAX_RATE_POWER; 4774 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4775 static const u16 tpScaleReductionTable[5] = {
4776 0, 3, 6, 9, MAX_RATE_POWER
4777 };
4778 int i; 4775 int i;
4779 int16_t twiceLargestAntenna; 4776 u16 scaledPower = 0, minCtlPower;
4780 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4781 static const u16 ctlModesFor11a[] = { 4777 static const u16 ctlModesFor11a[] = {
4782 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 4778 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4783 }; 4779 };
@@ -4795,28 +4791,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4795 bool is2ghz = IS_CHAN_2GHZ(chan); 4791 bool is2ghz = IS_CHAN_2GHZ(chan);
4796 4792
4797 ath9k_hw_get_channel_centers(ah, chan, &centers); 4793 ath9k_hw_get_channel_centers(ah, chan, &centers);
4798 4794 scaledPower = powerLimit - antenna_reduction;
4799 /* Compute TxPower reduction due to Antenna Gain */
4800 if (is2ghz)
4801 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4802 else
4803 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4804
4805 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4806 twiceLargestAntenna, 0);
4807
4808 /*
4809 * scaledPower is the minimum of the user input power level
4810 * and the regulatory allowed power level
4811 */
4812 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4813
4814 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4815 maxRegAllowedPower -=
4816 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4817 }
4818
4819 scaledPower = min(powerLimit, maxRegAllowedPower);
4820 4795
4821 /* 4796 /*
4822 * Reduce scaled Power by number of chains active to get 4797 * Reduce scaled Power by number of chains active to get
@@ -5003,7 +4978,6 @@ static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
5003static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, 4978static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5004 struct ath9k_channel *chan, u16 cfgCtl, 4979 struct ath9k_channel *chan, u16 cfgCtl,
5005 u8 twiceAntennaReduction, 4980 u8 twiceAntennaReduction,
5006 u8 twiceMaxRegulatoryPower,
5007 u8 powerLimit, bool test) 4981 u8 powerLimit, bool test)
5008{ 4982{
5009 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 4983 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
@@ -5056,7 +5030,6 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5056 ar9003_hw_set_power_per_rate_table(ah, chan, 5030 ar9003_hw_set_power_per_rate_table(ah, chan,
5057 targetPowerValT2, cfgCtl, 5031 targetPowerValT2, cfgCtl,
5058 twiceAntennaReduction, 5032 twiceAntennaReduction,
5059 twiceMaxRegulatoryPower,
5060 powerLimit); 5033 powerLimit);
5061 5034
5062 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) { 5035 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 901f417bb036..fb937ba93e0c 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -22,8 +22,8 @@
22#include "ar9330_1p1_initvals.h" 22#include "ar9330_1p1_initvals.h"
23#include "ar9330_1p2_initvals.h" 23#include "ar9330_1p2_initvals.h"
24#include "ar9580_1p0_initvals.h" 24#include "ar9580_1p0_initvals.h"
25#include "ar9480_1p0_initvals.h" 25#include "ar9462_1p0_initvals.h"
26#include "ar9480_2p0_initvals.h" 26#include "ar9462_2p0_initvals.h"
27 27
28/* General hardware code for the AR9003 hadware family */ 28/* General hardware code for the AR9003 hadware family */
29 29
@@ -35,13 +35,13 @@
35static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 35static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
36{ 36{
37#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \ 37#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
38 ar9480_pciephy_pll_on_clkreq_disable_L1_2p0 38 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
39 39
40#define AR9480_BB_CTX_COEFJ(x) \ 40#define AR9462_BB_CTX_COEFJ(x) \
41 ar9480_##x##_baseband_core_txfir_coeff_japan_2484 41 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
42 42
43#define AR9480_BBC_TXIFR_COEFFJ \ 43#define AR9462_BBC_TXIFR_COEFFJ \
44 ar9480_2p0_baseband_core_txfir_coeff_japan_2484 44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
45 if (AR_SREV_9330_11(ah)) { 45 if (AR_SREV_9330_11(ah)) {
46 /* mac */ 46 /* mac */
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -264,107 +264,107 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
264 ar9485_1_1_pcie_phy_clkreq_disable_L1, 264 ar9485_1_1_pcie_phy_clkreq_disable_L1,
265 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), 265 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
266 2); 266 2);
267 } else if (AR_SREV_9480_10(ah)) { 267 } else if (AR_SREV_9462_10(ah)) {
268 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 268 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_1p0_mac_core, 269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_1p0_mac_core,
270 ARRAY_SIZE(ar9480_1p0_mac_core), 2); 270 ARRAY_SIZE(ar9462_1p0_mac_core), 2);
271 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 271 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
272 ar9480_1p0_mac_postamble, 272 ar9462_1p0_mac_postamble,
273 ARRAY_SIZE(ar9480_1p0_mac_postamble), 273 ARRAY_SIZE(ar9462_1p0_mac_postamble),
274 5); 274 5);
275 275
276 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 276 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
278 ar9480_1p0_baseband_core, 278 ar9462_1p0_baseband_core,
279 ARRAY_SIZE(ar9480_1p0_baseband_core), 279 ARRAY_SIZE(ar9462_1p0_baseband_core),
280 2); 280 2);
281 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 281 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
282 ar9480_1p0_baseband_postamble, 282 ar9462_1p0_baseband_postamble,
283 ARRAY_SIZE(ar9480_1p0_baseband_postamble), 5); 283 ARRAY_SIZE(ar9462_1p0_baseband_postamble), 5);
284 284
285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
287 ar9480_1p0_radio_core, 287 ar9462_1p0_radio_core,
288 ARRAY_SIZE(ar9480_1p0_radio_core), 2); 288 ARRAY_SIZE(ar9462_1p0_radio_core), 2);
289 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 289 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
290 ar9480_1p0_radio_postamble, 290 ar9462_1p0_radio_postamble,
291 ARRAY_SIZE(ar9480_1p0_radio_postamble), 5); 291 ARRAY_SIZE(ar9462_1p0_radio_postamble), 5);
292 292
293 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 293 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
294 ar9480_1p0_soc_preamble, 294 ar9462_1p0_soc_preamble,
295 ARRAY_SIZE(ar9480_1p0_soc_preamble), 2); 295 ARRAY_SIZE(ar9462_1p0_soc_preamble), 2);
296 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 296 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
298 ar9480_1p0_soc_postamble, 298 ar9462_1p0_soc_postamble,
299 ARRAY_SIZE(ar9480_1p0_soc_postamble), 5); 299 ARRAY_SIZE(ar9462_1p0_soc_postamble), 5);
300 300
301 INIT_INI_ARRAY(&ah->iniModesRxGain, 301 INIT_INI_ARRAY(&ah->iniModesRxGain,
302 ar9480_common_rx_gain_table_1p0, 302 ar9462_common_rx_gain_table_1p0,
303 ARRAY_SIZE(ar9480_common_rx_gain_table_1p0), 2); 303 ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 2);
304 304
305 /* Awake -> Sleep Setting */ 305 /* Awake -> Sleep Setting */
306 INIT_INI_ARRAY(&ah->iniPcieSerdes, 306 INIT_INI_ARRAY(&ah->iniPcieSerdes,
307 ar9480_pcie_phy_clkreq_disable_L1_1p0, 307 ar9462_pcie_phy_clkreq_disable_L1_1p0,
308 ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0), 308 ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
309 2); 309 2);
310 310
311 /* Sleep -> Awake Setting */ 311 /* Sleep -> Awake Setting */
312 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 312 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
313 ar9480_pcie_phy_clkreq_disable_L1_1p0, 313 ar9462_pcie_phy_clkreq_disable_L1_1p0,
314 ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0), 314 ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
315 2); 315 2);
316 316
317 INIT_INI_ARRAY(&ah->iniModesAdditional, 317 INIT_INI_ARRAY(&ah->iniModesAdditional,
318 ar9480_modes_fast_clock_1p0, 318 ar9462_modes_fast_clock_1p0,
319 ARRAY_SIZE(ar9480_modes_fast_clock_1p0), 3); 319 ARRAY_SIZE(ar9462_modes_fast_clock_1p0), 3);
320 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 320 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
321 AR9480_BB_CTX_COEFJ(1p0), 321 AR9462_BB_CTX_COEFJ(1p0),
322 ARRAY_SIZE(AR9480_BB_CTX_COEFJ(1p0)), 2); 322 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(1p0)), 2);
323 323
324 } else if (AR_SREV_9480_20(ah)) { 324 } else if (AR_SREV_9462_20(ah)) {
325 325
326 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 326 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
327 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_2p0_mac_core, 327 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
328 ARRAY_SIZE(ar9480_2p0_mac_core), 2); 328 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
329 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 329 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
330 ar9480_2p0_mac_postamble, 330 ar9462_2p0_mac_postamble,
331 ARRAY_SIZE(ar9480_2p0_mac_postamble), 5); 331 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
332 332
333 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 333 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
334 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 334 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
335 ar9480_2p0_baseband_core, 335 ar9462_2p0_baseband_core,
336 ARRAY_SIZE(ar9480_2p0_baseband_core), 2); 336 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
337 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 337 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
338 ar9480_2p0_baseband_postamble, 338 ar9462_2p0_baseband_postamble,
339 ARRAY_SIZE(ar9480_2p0_baseband_postamble), 5); 339 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
340 340
341 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 341 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
342 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 342 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
343 ar9480_2p0_radio_core, 343 ar9462_2p0_radio_core,
344 ARRAY_SIZE(ar9480_2p0_radio_core), 2); 344 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
345 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 345 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
346 ar9480_2p0_radio_postamble, 346 ar9462_2p0_radio_postamble,
347 ARRAY_SIZE(ar9480_2p0_radio_postamble), 5); 347 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
348 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 348 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
349 ar9480_2p0_radio_postamble_sys2ant, 349 ar9462_2p0_radio_postamble_sys2ant,
350 ARRAY_SIZE(ar9480_2p0_radio_postamble_sys2ant), 350 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
351 5); 351 5);
352 352
353 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 353 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
354 ar9480_2p0_soc_preamble, 354 ar9462_2p0_soc_preamble,
355 ARRAY_SIZE(ar9480_2p0_soc_preamble), 2); 355 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
356 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 356 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
357 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 357 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
358 ar9480_2p0_soc_postamble, 358 ar9462_2p0_soc_postamble,
359 ARRAY_SIZE(ar9480_2p0_soc_postamble), 5); 359 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
360 360
361 INIT_INI_ARRAY(&ah->iniModesRxGain, 361 INIT_INI_ARRAY(&ah->iniModesRxGain,
362 ar9480_common_rx_gain_table_2p0, 362 ar9462_common_rx_gain_table_2p0,
363 ARRAY_SIZE(ar9480_common_rx_gain_table_2p0), 2); 363 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
364 364
365 INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR, 365 INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,
366 ar9480_2p0_BTCOEX_MAX_TXPWR_table, 366 ar9462_2p0_BTCOEX_MAX_TXPWR_table,
367 ARRAY_SIZE(ar9480_2p0_BTCOEX_MAX_TXPWR_table), 367 ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),
368 2); 368 2);
369 369
370 /* Awake -> Sleep Setting */ 370 /* Awake -> Sleep Setting */
@@ -380,15 +380,15 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
380 380
381 /* Fast clock modal settings */ 381 /* Fast clock modal settings */
382 INIT_INI_ARRAY(&ah->iniModesAdditional, 382 INIT_INI_ARRAY(&ah->iniModesAdditional,
383 ar9480_modes_fast_clock_2p0, 383 ar9462_modes_fast_clock_2p0,
384 ARRAY_SIZE(ar9480_modes_fast_clock_2p0), 3); 384 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
385 385
386 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 386 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
387 AR9480_BB_CTX_COEFJ(2p0), 387 AR9462_BB_CTX_COEFJ(2p0),
388 ARRAY_SIZE(AR9480_BB_CTX_COEFJ(2p0)), 2); 388 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
389 389
390 INIT_INI_ARRAY(&ah->ini_japan2484, AR9480_BBC_TXIFR_COEFFJ, 390 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
391 ARRAY_SIZE(AR9480_BBC_TXIFR_COEFFJ), 2); 391 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
392 392
393 } else if (AR_SREV_9580(ah)) { 393 } else if (AR_SREV_9580(ah)) {
394 /* mac */ 394 /* mac */
@@ -537,15 +537,15 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
537 ar9580_1p0_lowest_ob_db_tx_gain_table, 537 ar9580_1p0_lowest_ob_db_tx_gain_table,
538 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table), 538 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
539 5); 539 5);
540 else if (AR_SREV_9480_10(ah)) 540 else if (AR_SREV_9462_10(ah))
541 INIT_INI_ARRAY(&ah->iniModesTxGain, 541 INIT_INI_ARRAY(&ah->iniModesTxGain,
542 ar9480_modes_low_ob_db_tx_gain_table_1p0, 542 ar9462_modes_low_ob_db_tx_gain_table_1p0,
543 ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_1p0), 543 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_1p0),
544 5); 544 5);
545 else if (AR_SREV_9480_20(ah)) 545 else if (AR_SREV_9462_20(ah))
546 INIT_INI_ARRAY(&ah->iniModesTxGain, 546 INIT_INI_ARRAY(&ah->iniModesTxGain,
547 ar9480_modes_low_ob_db_tx_gain_table_2p0, 547 ar9462_modes_low_ob_db_tx_gain_table_2p0,
548 ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_2p0), 548 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
549 5); 549 5);
550 else 550 else
551 INIT_INI_ARRAY(&ah->iniModesTxGain, 551 INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -581,15 +581,15 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
581 ar9580_1p0_high_ob_db_tx_gain_table, 581 ar9580_1p0_high_ob_db_tx_gain_table,
582 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table), 582 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
583 5); 583 5);
584 else if (AR_SREV_9480_10(ah)) 584 else if (AR_SREV_9462_10(ah))
585 INIT_INI_ARRAY(&ah->iniModesTxGain, 585 INIT_INI_ARRAY(&ah->iniModesTxGain,
586 ar9480_modes_high_ob_db_tx_gain_table_1p0, 586 ar9462_modes_high_ob_db_tx_gain_table_1p0,
587 ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_1p0), 587 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_1p0),
588 5); 588 5);
589 else if (AR_SREV_9480_20(ah)) 589 else if (AR_SREV_9462_20(ah))
590 INIT_INI_ARRAY(&ah->iniModesTxGain, 590 INIT_INI_ARRAY(&ah->iniModesTxGain,
591 ar9480_modes_high_ob_db_tx_gain_table_2p0, 591 ar9462_modes_high_ob_db_tx_gain_table_2p0,
592 ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_2p0), 592 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
593 5); 593 5);
594 else 594 else
595 INIT_INI_ARRAY(&ah->iniModesTxGain, 595 INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -712,15 +712,15 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
712 ar9580_1p0_rx_gain_table, 712 ar9580_1p0_rx_gain_table,
713 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 713 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
714 2); 714 2);
715 else if (AR_SREV_9480_10(ah)) 715 else if (AR_SREV_9462_10(ah))
716 INIT_INI_ARRAY(&ah->iniModesRxGain, 716 INIT_INI_ARRAY(&ah->iniModesRxGain,
717 ar9480_common_rx_gain_table_1p0, 717 ar9462_common_rx_gain_table_1p0,
718 ARRAY_SIZE(ar9480_common_rx_gain_table_1p0), 718 ARRAY_SIZE(ar9462_common_rx_gain_table_1p0),
719 2); 719 2);
720 else if (AR_SREV_9480_20(ah)) 720 else if (AR_SREV_9462_20(ah))
721 INIT_INI_ARRAY(&ah->iniModesRxGain, 721 INIT_INI_ARRAY(&ah->iniModesRxGain,
722 ar9480_common_rx_gain_table_2p0, 722 ar9462_common_rx_gain_table_2p0,
723 ARRAY_SIZE(ar9480_common_rx_gain_table_2p0), 723 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
724 2); 724 2);
725 else 725 else
726 INIT_INI_ARRAY(&ah->iniModesRxGain, 726 INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -751,15 +751,15 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
751 ar9485Common_wo_xlna_rx_gain_1_1, 751 ar9485Common_wo_xlna_rx_gain_1_1,
752 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 752 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
753 2); 753 2);
754 else if (AR_SREV_9480_10(ah)) 754 else if (AR_SREV_9462_10(ah))
755 INIT_INI_ARRAY(&ah->iniModesRxGain, 755 INIT_INI_ARRAY(&ah->iniModesRxGain,
756 ar9480_common_wo_xlna_rx_gain_table_1p0, 756 ar9462_common_wo_xlna_rx_gain_table_1p0,
757 ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_1p0), 757 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_1p0),
758 2); 758 2);
759 else if (AR_SREV_9480_20(ah)) 759 else if (AR_SREV_9462_20(ah))
760 INIT_INI_ARRAY(&ah->iniModesRxGain, 760 INIT_INI_ARRAY(&ah->iniModesRxGain,
761 ar9480_common_wo_xlna_rx_gain_table_2p0, 761 ar9462_common_wo_xlna_rx_gain_table_2p0,
762 ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_2p0), 762 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
763 2); 763 2);
764 else if (AR_SREV_9580(ah)) 764 else if (AR_SREV_9580(ah))
765 INIT_INI_ARRAY(&ah->iniModesRxGain, 765 INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -775,14 +775,14 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
775 775
776static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 776static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
777{ 777{
778 if (AR_SREV_9480_10(ah)) 778 if (AR_SREV_9462_10(ah))
779 INIT_INI_ARRAY(&ah->iniModesRxGain, 779 INIT_INI_ARRAY(&ah->iniModesRxGain,
780 ar9480_common_mixed_rx_gain_table_1p0, 780 ar9462_common_mixed_rx_gain_table_1p0,
781 ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_1p0), 2); 781 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_1p0), 2);
782 else if (AR_SREV_9480_20(ah)) 782 else if (AR_SREV_9462_20(ah))
783 INIT_INI_ARRAY(&ah->iniModesRxGain, 783 INIT_INI_ARRAY(&ah->iniModesRxGain,
784 ar9480_common_mixed_rx_gain_table_2p0, 784 ar9462_common_mixed_rx_gain_table_2p0,
785 ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_2p0), 2); 785 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
786} 786}
787 787
788static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 788static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 6cabc85bf61b..b363cc06cfd9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -525,8 +525,8 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
525 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 525 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
526 else if (rxsp->status11 & AR_MichaelErr) 526 else if (rxsp->status11 & AR_MichaelErr)
527 rxs->rs_status |= ATH9K_RXERR_MIC; 527 rxs->rs_status |= ATH9K_RXERR_MIC;
528 else if (rxsp->status11 & AR_KeyMiss) 528 if (rxsp->status11 & AR_KeyMiss)
529 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 529 rxs->rs_status |= ATH9K_RXERR_KEYMISS;
530 } 530 }
531 531
532 return 0; 532 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 609acb2b504f..0c462c904cbe 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -19,7 +19,6 @@
19 19
20void ar9003_paprd_enable(struct ath_hw *ah, bool val) 20void ar9003_paprd_enable(struct ath_hw *ah, bool val)
21{ 21{
22 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
23 struct ath9k_channel *chan = ah->curchan; 22 struct ath9k_channel *chan = ah->curchan;
24 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 23 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
25 24
@@ -54,13 +53,7 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val)
54 53
55 if (val) { 54 if (val) {
56 ah->paprd_table_write_done = true; 55 ah->paprd_table_write_done = true;
57 56 ath9k_hw_apply_txpower(ah, chan);
58 ah->eep_ops->set_txpower(ah, chan,
59 ath9k_regd_get_ctl(regulatory, chan),
60 chan->chan->max_antenna_gain * 2,
61 chan->chan->max_power * 2,
62 min((u32) MAX_RATE_POWER,
63 (u32) regulatory->power_limit), false);
64 } 57 }
65 58
66 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0, 59 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
@@ -207,7 +200,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
207 AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28); 200 AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28);
208 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1, 201 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
209 AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1); 202 AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1);
210 val = AR_SREV_9480(ah) ? 0x91 : 147; 203 val = AR_SREV_9462(ah) ? 0x91 : 147;
211 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2, 204 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
212 AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val); 205 AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val);
213 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 206 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
@@ -218,7 +211,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
218 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); 211 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
219 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 212 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
220 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); 213 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
221 if (AR_SREV_9485(ah) || AR_SREV_9480(ah)) 214 if (AR_SREV_9485(ah) || AR_SREV_9462(ah))
222 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 215 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
223 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, 216 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
224 -3); 217 -3);
@@ -226,7 +219,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
226 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 219 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
227 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, 220 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
228 -6); 221 -6);
229 val = AR_SREV_9480(ah) ? -10 : -15; 222 val = AR_SREV_9462(ah) ? -10 : -15;
230 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 223 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
231 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, 224 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
232 val); 225 val);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 7db6e8647a01..fe96997921d3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -559,7 +559,7 @@ static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
559 559
560 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 560 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
561 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 561 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
562 else if (AR_SREV_9480(ah)) 562 else if (AR_SREV_9462(ah))
563 /* xxx only when MCI support is enabled */ 563 /* xxx only when MCI support is enabled */
564 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 564 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
565 else 565 else
@@ -631,9 +631,7 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
631static int ar9003_hw_process_ini(struct ath_hw *ah, 631static int ar9003_hw_process_ini(struct ath_hw *ah,
632 struct ath9k_channel *chan) 632 struct ath9k_channel *chan)
633{ 633{
634 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
635 unsigned int regWrites = 0, i; 634 unsigned int regWrites = 0, i;
636 struct ieee80211_channel *channel = chan->chan;
637 u32 modesIndex; 635 u32 modesIndex;
638 636
639 switch (chan->chanmode) { 637 switch (chan->chanmode) {
@@ -664,7 +662,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
664 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); 662 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
665 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); 663 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
666 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); 664 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
667 if (i == ATH_INI_POST && AR_SREV_9480_20(ah)) 665 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
668 ar9003_hw_prog_ini(ah, 666 ar9003_hw_prog_ini(ah,
669 &ah->ini_radio_post_sys2ant, 667 &ah->ini_radio_post_sys2ant,
670 modesIndex); 668 modesIndex);
@@ -687,20 +685,27 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
687 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 685 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
688 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 686 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
689 687
690 if (AR_SREV_9480(ah)) 688 if (AR_SREV_9462(ah))
691 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1); 689 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
692 690
691 ah->modes_index = modesIndex;
693 ar9003_hw_override_ini(ah); 692 ar9003_hw_override_ini(ah);
694 ar9003_hw_set_channel_regs(ah, chan); 693 ar9003_hw_set_channel_regs(ah, chan);
695 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 694 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
695 ath9k_hw_apply_txpower(ah, chan);
696 696
697 /* Set TX power */ 697 if (AR_SREV_9462(ah)) {
698 ah->eep_ops->set_txpower(ah, chan, 698 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
699 ath9k_regd_get_ctl(regulatory, chan), 699 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
700 channel->max_antenna_gain * 2, 700 ah->enabled_cals |= TX_IQ_CAL;
701 channel->max_power * 2, 701 else
702 min((u32) MAX_RATE_POWER, 702 ah->enabled_cals &= ~TX_IQ_CAL;
703 (u32) regulatory->power_limit), false); 703
704 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
705 ah->enabled_cals |= TX_CL_CAL;
706 else
707 ah->enabled_cals &= ~TX_CL_CAL;
708 }
704 709
705 return 0; 710 return 0;
706} 711}
@@ -1256,6 +1261,73 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1256 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1261 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1257} 1262}
1258 1263
1264static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1265 struct ath9k_channel *chan,
1266 u8 *ini_reloaded)
1267{
1268 unsigned int regWrites = 0;
1269 u32 modesIndex;
1270
1271 switch (chan->chanmode) {
1272 case CHANNEL_A:
1273 case CHANNEL_A_HT20:
1274 modesIndex = 1;
1275 break;
1276 case CHANNEL_A_HT40PLUS:
1277 case CHANNEL_A_HT40MINUS:
1278 modesIndex = 2;
1279 break;
1280 case CHANNEL_G:
1281 case CHANNEL_G_HT20:
1282 case CHANNEL_B:
1283 modesIndex = 4;
1284 break;
1285 case CHANNEL_G_HT40PLUS:
1286 case CHANNEL_G_HT40MINUS:
1287 modesIndex = 3;
1288 break;
1289
1290 default:
1291 return -EINVAL;
1292 }
1293
1294 if (modesIndex == ah->modes_index) {
1295 *ini_reloaded = false;
1296 goto set_rfmode;
1297 }
1298
1299 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1300 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1301 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1302 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1303 if (AR_SREV_9462_20(ah))
1304 ar9003_hw_prog_ini(ah,
1305 &ah->ini_radio_post_sys2ant,
1306 modesIndex);
1307
1308 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1309
1310 /*
1311 * For 5GHz channels requiring Fast Clock, apply
1312 * different modal values.
1313 */
1314 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1315 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites);
1316
1317 if (AR_SREV_9330(ah))
1318 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
1319
1320 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
1321 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
1322
1323 ah->modes_index = modesIndex;
1324 *ini_reloaded = true;
1325
1326set_rfmode:
1327 ar9003_hw_set_rfmode(ah, chan);
1328 return 0;
1329}
1330
1259void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 1331void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1260{ 1332{
1261 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1333 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
@@ -1284,6 +1356,7 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1284 priv_ops->do_getnf = ar9003_hw_do_getnf; 1356 priv_ops->do_getnf = ar9003_hw_do_getnf;
1285 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; 1357 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1286 priv_ops->set_radar_params = ar9003_hw_set_radar_params; 1358 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1359 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1287 1360
1288 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; 1361 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1289 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; 1362 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 6cea546a1507..2f4023e66081 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -325,10 +325,10 @@
325 325
326#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200) 326#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
327 327
328#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110 328#define AR_PHY_CCA_NOM_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -110)
329#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115 329#define AR_PHY_CCA_NOM_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -115)
330#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125 330#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -125)
331#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125 331#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -125)
332#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 332#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
333#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 333#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
334 334
@@ -572,6 +572,8 @@
572 572
573#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300) 573#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
574 574
575#define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + AR_SREV_9485(ah) ? \
576 0x3c4 : 0x444)
575#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + AR_SREV_9485(ah) ? \ 577#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + AR_SREV_9485(ah) ? \
576 0x3c8 : 0x448) 578 0x3c8 : 0x448)
577#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + AR_SREV_9485(ah) ? \ 579#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + AR_SREV_9485(ah) ? \
@@ -582,8 +584,6 @@
582 (AR_SREV_9485(ah) ? \ 584 (AR_SREV_9485(ah) ? \
583 0x3d0 : 0x450) + ((_i) << 2)) 585 0x3d0 : 0x450) + ((_i) << 2))
584#define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380) 586#define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380)
585#define AR_PHY_RTT_TABLE_SW_INTF_B (AR_SM_BASE + 0x384)
586#define AR_PHY_RTT_TABLE_SW_INTF_1_B0 (AR_SM_BASE + 0x388)
587 587
588#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0) 588#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
589#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4) 589#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
@@ -608,9 +608,9 @@
608#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) 608#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
609#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) 609#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
610#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) 610#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
611#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ 611#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
612 0x4c0 : 0x4c4)) 612 0x4c0 : 0x4c4))
613#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ 613#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
614 0x4c4 : 0x4c8)) 614 0x4c4 : 0x4c8))
615#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) 615#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
616#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc) 616#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
@@ -625,7 +625,7 @@
625#define AR_PHY_65NM_CH0_RXTX4 0x1610c 625#define AR_PHY_65NM_CH0_RXTX4 0x1610c
626 626
627#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ 627#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
628 ((AR_SREV_9480(ah) ? 0x1628c : 0x16280))) 628 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
629#define AR_CH0_TOP_XPABIASLVL (0x300) 629#define AR_CH0_TOP_XPABIASLVL (0x300)
630#define AR_CH0_TOP_XPABIASLVL_S (8) 630#define AR_CH0_TOP_XPABIASLVL_S (8)
631 631
@@ -638,8 +638,8 @@
638 638
639#define AR_SWITCH_TABLE_COM_ALL (0xffff) 639#define AR_SWITCH_TABLE_COM_ALL (0xffff)
640#define AR_SWITCH_TABLE_COM_ALL_S (0) 640#define AR_SWITCH_TABLE_COM_ALL_S (0)
641#define AR_SWITCH_TABLE_COM_AR9480_ALL (0xffffff) 641#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
642#define AR_SWITCH_TABLE_COM_AR9480_ALL_S (0) 642#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
643#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000) 643#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
644#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0) 644#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
645#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4) 645#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
@@ -679,11 +679,11 @@
679#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 679#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
680#define AR_CH0_XTAL_CAPOUTDAC_S 17 680#define AR_CH0_XTAL_CAPOUTDAC_S 17
681 681
682#define AR_PHY_PMU1 (AR_SREV_9480(ah) ? 0x16340 : 0x16c40) 682#define AR_PHY_PMU1 (AR_SREV_9462(ah) ? 0x16340 : 0x16c40)
683#define AR_PHY_PMU1_PWD 0x1 683#define AR_PHY_PMU1_PWD 0x1
684#define AR_PHY_PMU1_PWD_S 0 684#define AR_PHY_PMU1_PWD_S 0
685 685
686#define AR_PHY_PMU2 (AR_SREV_9480(ah) ? 0x16344 : 0x16c44) 686#define AR_PHY_PMU2 (AR_SREV_9462(ah) ? 0x16344 : 0x16c44)
687#define AR_PHY_PMU2_PGM 0x00200000 687#define AR_PHY_PMU2_PGM 0x00200000
688#define AR_PHY_PMU2_PGM_S 21 688#define AR_PHY_PMU2_PGM_S 21
689 689
@@ -823,6 +823,22 @@
823#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 823#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
824#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 824#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
825#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 825#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
826#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001
827#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0
828#define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E
829#define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1
830#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080
831#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7
832#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS 0x00000001
833#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S 0
834#define AR_PHY_RTT_SW_RTT_TABLE_WRITE 0x00000002
835#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S 1
836#define AR_PHY_RTT_SW_RTT_TABLE_ADDR 0x0000001C
837#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S 2
838#define AR_PHY_RTT_SW_RTT_TABLE_DATA 0xFFFFFFF0
839#define AR_PHY_RTT_SW_RTT_TABLE_DATA_S 4
840#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000
841#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31
826#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000 842#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
827#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 843#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
828#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 844#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
@@ -905,9 +921,9 @@
905#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0) 921#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
906#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4) 922#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
907#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8) 923#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8)
908#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ 924#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
909 0x4c0 : 0x4c4)) 925 0x4c0 : 0x4c4))
910#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ 926#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
911 0x4c4 : 0x4c8)) 927 0x4c4 : 0x4c8))
912#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0) 928#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)
913#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc) 929#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)
@@ -915,6 +931,10 @@
915#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0) 931#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
916#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4) 932#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
917 933
934#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + (i) ? \
935 AR_SM1_BASE : AR_SM_BASE)
936#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + (i) ? \
937 AR_SM1_BASE : AR_SM_BASE)
918/* 938/*
919 * Channel 2 Register Map 939 * Channel 2 Register Map
920 */ 940 */
@@ -981,7 +1001,7 @@
981#define AR_GLB_BASE 0x20000 1001#define AR_GLB_BASE 0x20000
982#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44) 1002#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)
983#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \ 1003#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \
984 (AR_SREV_9480_20(_ah) ? 0x4c : 0x50)) 1004 (AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
985#define AR_GLB_STATUS (AR_GLB_BASE + 0x48) 1005#define AR_GLB_STATUS (AR_GLB_BASE + 0x48)
986 1006
987/* 1007/*
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_rtt.c b/drivers/net/wireless/ath/ath9k/ar9003_rtt.c
new file mode 100644
index 000000000000..48803ee9c0d6
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_rtt.c
@@ -0,0 +1,153 @@
1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_phy.h"
19
20#define RTT_RESTORE_TIMEOUT 1000
21#define RTT_ACCESS_TIMEOUT 100
22#define RTT_BAD_VALUE 0x0bad0bad
23
24/*
25 * RTT (Radio Retention Table) hardware implementation information
26 *
27 * There is an internal table (i.e. the rtt) for each chain (or bank).
28 * Each table contains 6 entries and each entry is corresponding to
29 * a specific calibration parameter as depicted below.
30 * 0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
31 * 3 - Filter cal (filterfc)
32 * 4 - RX gain settings
33 * 5 - Peak detector offset calibration (agc_caldac)
34 */
35
36void ar9003_hw_rtt_enable(struct ath_hw *ah)
37{
38 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
39}
40
41void ar9003_hw_rtt_disable(struct ath_hw *ah)
42{
43 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
44}
45
46void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask)
47{
48 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
49 AR_PHY_RTT_CTRL_RESTORE_MASK, rtt_mask);
50}
51
52bool ar9003_hw_rtt_force_restore(struct ath_hw *ah)
53{
54 if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
55 AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
56 0, RTT_RESTORE_TIMEOUT))
57 return false;
58
59 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
60 AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE, 1);
61
62 if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
63 AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
64 0, RTT_RESTORE_TIMEOUT))
65 return false;
66
67 return true;
68}
69
70static void ar9003_hw_rtt_load_hist_entry(struct ath_hw *ah, u8 chain,
71 u32 index, u32 data28)
72{
73 u32 val;
74
75 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
76 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
77
78 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
79 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
80 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
81 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
82 udelay(1);
83
84 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
85 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
86 udelay(1);
87
88 if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
89 AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
90 RTT_ACCESS_TIMEOUT))
91 return;
92
93 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
94 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
95 udelay(1);
96
97 ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
98 AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
99 RTT_ACCESS_TIMEOUT);
100}
101
102void ar9003_hw_rtt_load_hist(struct ath_hw *ah, u8 chain, u32 *table)
103{
104 int i;
105
106 for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
107 ar9003_hw_rtt_load_hist_entry(ah, chain, i, table[i]);
108}
109
110static int ar9003_hw_rtt_fill_hist_entry(struct ath_hw *ah, u8 chain, u32 index)
111{
112 u32 val;
113
114 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
115 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
116 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
117
118 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
119 udelay(1);
120
121 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
122 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
123 udelay(1);
124
125 if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
126 AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
127 RTT_ACCESS_TIMEOUT))
128 return RTT_BAD_VALUE;
129
130 val = REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain));
131
132 return val;
133}
134
135void ar9003_hw_rtt_fill_hist(struct ath_hw *ah, u8 chain, u32 *table)
136{
137 int i;
138
139 for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
140 table[i] = ar9003_hw_rtt_fill_hist_entry(ah, chain, i);
141}
142
143void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
144{
145 int i, j;
146
147 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
148 if (!(ah->rxchainmask & (1 << i)))
149 continue;
150 for (j = 0; j < MAX_RTT_TABLE_ENTRY; j++)
151 ar9003_hw_rtt_load_hist_entry(ah, i, j, 0);
152 }
153}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_rtt.h b/drivers/net/wireless/ath/ath9k/ar9003_rtt.h
new file mode 100644
index 000000000000..030758d087d6
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_rtt.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef AR9003_RTT_H
18#define AR9003_RTT_H
19
20void ar9003_hw_rtt_enable(struct ath_hw *ah);
21void ar9003_hw_rtt_disable(struct ath_hw *ah);
22void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask);
23bool ar9003_hw_rtt_force_restore(struct ath_hw *ah);
24void ar9003_hw_rtt_load_hist(struct ath_hw *ah, u8 chain, u32 *table);
25void ar9003_hw_rtt_fill_hist(struct ath_hw *ah, u8 chain, u32 *table);
26void ar9003_hw_rtt_clear_hist(struct ath_hw *ah);
27
28#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9480_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h
index 4071bd2bd03f..5c55ae389adb 100644
--- a/drivers/net/wireless/ath/ath9k/ar9480_1p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h
@@ -14,12 +14,12 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#ifndef INITVALS_9480_1P0_H 17#ifndef INITVALS_9462_1P0_H
18#define INITVALS_9480_1P0_H 18#define INITVALS_9462_1P0_H
19 19
20/* AR9480 1.0 */ 20/* AR9462 1.0 */
21 21
22static const u32 ar9480_1p0_mac_core[][2] = { 22static const u32 ar9462_1p0_mac_core[][2] = {
23 /* Addr allmodes */ 23 /* Addr allmodes */
24 {0x00000008, 0x00000000}, 24 {0x00000008, 0x00000000},
25 {0x00000030, 0x00060085}, 25 {0x00000030, 0x00060085},
@@ -183,27 +183,27 @@ static const u32 ar9480_1p0_mac_core[][2] = {
183 {0x000083d0, 0x000301ff}, 183 {0x000083d0, 0x000301ff},
184}; 184};
185 185
186static const u32 ar9480_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { 186static const u32 ar9462_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
187 /* Addr allmodes */ 187 /* Addr allmodes */
188 {0x0000a398, 0x00000000}, 188 {0x0000a398, 0x00000000},
189 {0x0000a39c, 0x6f7f0301}, 189 {0x0000a39c, 0x6f7f0301},
190 {0x0000a3a0, 0xca9228ee}, 190 {0x0000a3a0, 0xca9228ee},
191}; 191};
192 192
193static const u32 ar9480_1p0_sys3ant[][2] = { 193static const u32 ar9462_1p0_sys3ant[][2] = {
194 /* Addr allmodes */ 194 /* Addr allmodes */
195 {0x00063280, 0x00040807}, 195 {0x00063280, 0x00040807},
196 {0x00063284, 0x104ccccc}, 196 {0x00063284, 0x104ccccc},
197}; 197};
198 198
199static const u32 ar9480_pcie_phy_clkreq_enable_L1_1p0[][2] = { 199static const u32 ar9462_pcie_phy_clkreq_enable_L1_1p0[][2] = {
200 /* Addr allmodes */ 200 /* Addr allmodes */
201 {0x00018c00, 0x10053e5e}, 201 {0x00018c00, 0x10053e5e},
202 {0x00018c04, 0x000801d8}, 202 {0x00018c04, 0x000801d8},
203 {0x00018c08, 0x0000580c}, 203 {0x00018c08, 0x0000580c},
204}; 204};
205 205
206static const u32 ar9480_1p0_mac_core_emulation[][2] = { 206static const u32 ar9462_1p0_mac_core_emulation[][2] = {
207 /* Addr allmodes */ 207 /* Addr allmodes */
208 {0x00000030, 0x00060085}, 208 {0x00000030, 0x00060085},
209 {0x00000044, 0x00000008}, 209 {0x00000044, 0x00000008},
@@ -211,7 +211,7 @@ static const u32 ar9480_1p0_mac_core_emulation[][2] = {
211 {0x00008344, 0xaa4a105b}, 211 {0x00008344, 0xaa4a105b},
212}; 212};
213 213
214static const u32 ar9480_common_rx_gain_table_ar9280_2p0_1p0[][2] = { 214static const u32 ar9462_common_rx_gain_table_ar9280_2p0_1p0[][2] = {
215 /* Addr allmodes */ 215 /* Addr allmodes */
216 {0x0000a000, 0x02000101}, 216 {0x0000a000, 0x02000101},
217 {0x0000a004, 0x02000102}, 217 {0x0000a004, 0x02000102},
@@ -513,7 +513,7 @@ static const u32 ar9200_ar9280_2p0_radio_core_1p0[][2] = {
513 {0x00007894, 0x5a108000}, 513 {0x00007894, 0x5a108000},
514}; 514};
515 515
516static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = { 516static const u32 ar9462_1p0_baseband_postamble_emulation[][5] = {
517 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 517 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
518 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 518 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
519 {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221}, 519 {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221},
@@ -535,14 +535,14 @@ static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = {
535 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 535 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
536}; 536};
537 537
538static const u32 ar9480_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = { 538static const u32 ar9462_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = {
539 /* Addr allmodes */ 539 /* Addr allmodes */
540 {0x00018c00, 0x10012e5e}, 540 {0x00018c00, 0x10012e5e},
541 {0x00018c04, 0x000801d8}, 541 {0x00018c04, 0x000801d8},
542 {0x00018c08, 0x0000580c}, 542 {0x00018c08, 0x0000580c},
543}; 543};
544 544
545static const u32 ar9480_common_rx_gain_table_1p0[][2] = { 545static const u32 ar9462_common_rx_gain_table_1p0[][2] = {
546 /* Addr allmodes */ 546 /* Addr allmodes */
547 {0x0000a000, 0x00010000}, 547 {0x0000a000, 0x00010000},
548 {0x0000a004, 0x00030002}, 548 {0x0000a004, 0x00030002},
@@ -802,7 +802,7 @@ static const u32 ar9480_common_rx_gain_table_1p0[][2] = {
802 {0x0000b1fc, 0x00000196}, 802 {0x0000b1fc, 0x00000196},
803}; 803};
804 804
805static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = { 805static const u32 ar9462_modes_high_ob_db_tx_gain_table_1p0[][5] = {
806 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 806 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
807 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, 807 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
808 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, 808 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
@@ -867,7 +867,7 @@ static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = {
867 {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, 867 {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
868}; 868};
869 869
870static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = { 870static const u32 ar9462_common_wo_xlna_rx_gain_table_1p0[][2] = {
871 /* Addr allmodes */ 871 /* Addr allmodes */
872 {0x0000a000, 0x00010000}, 872 {0x0000a000, 0x00010000},
873 {0x0000a004, 0x00030002}, 873 {0x0000a004, 0x00030002},
@@ -1127,7 +1127,7 @@ static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = {
1127 {0x0000b1fc, 0x00000196}, 1127 {0x0000b1fc, 0x00000196},
1128}; 1128};
1129 1129
1130static const u32 ar9480_1p0_mac_postamble[][5] = { 1130static const u32 ar9462_1p0_mac_postamble[][5] = {
1131 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1131 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1132 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, 1132 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
1133 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, 1133 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
@@ -1139,13 +1139,13 @@ static const u32 ar9480_1p0_mac_postamble[][5] = {
1139 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, 1139 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
1140}; 1140};
1141 1141
1142static const u32 ar9480_1p0_mac_postamble_emulation[][5] = { 1142static const u32 ar9462_1p0_mac_postamble_emulation[][5] = {
1143 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1143 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1144 {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8}, 1144 {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8},
1145 {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017}, 1145 {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017},
1146}; 1146};
1147 1147
1148static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { 1148static const u32 ar9462_1p0_tx_gain_table_baseband_postamble_emulation[][5] = {
1149 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1149 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1150 {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5}, 1150 {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5},
1151 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 1151 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -1163,7 +1163,7 @@ static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = {
1163 {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a}, 1163 {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a},
1164}; 1164};
1165 1165
1166static const u32 ar9480_1p0_radio_postamble[][5] = { 1166static const u32 ar9462_1p0_radio_postamble[][5] = {
1167 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1167 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1168 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, 1168 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
1169 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24646c08, 0x24646c08}, 1169 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24646c08, 0x24646c08},
@@ -1174,12 +1174,12 @@ static const u32 ar9480_1p0_radio_postamble[][5] = {
1174 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, 1174 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
1175}; 1175};
1176 1176
1177static const u32 ar9480_1p0_soc_postamble_emulation[][5] = { 1177static const u32 ar9462_1p0_soc_postamble_emulation[][5] = {
1178 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1178 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1179 {0x00007010, 0x00001133, 0x00001133, 0x00001133, 0x00001133}, 1179 {0x00007010, 0x00001133, 0x00001133, 0x00001133, 0x00001133},
1180}; 1180};
1181 1181
1182static const u32 ar9480_1p0_baseband_core[][2] = { 1182static const u32 ar9462_1p0_baseband_core[][2] = {
1183 /* Addr allmodes */ 1183 /* Addr allmodes */
1184 {0x00009800, 0xafe68e30}, 1184 {0x00009800, 0xafe68e30},
1185 {0x00009804, 0xfd14e000}, 1185 {0x00009804, 0xfd14e000},
@@ -1336,7 +1336,7 @@ static const u32 ar9480_1p0_baseband_core[][2] = {
1336 {0x0000b6b4, 0x00c00001}, 1336 {0x0000b6b4, 0x00c00001},
1337}; 1337};
1338 1338
1339static const u32 ar9480_1p0_baseband_postamble[][5] = { 1339static const u32 ar9462_1p0_baseband_postamble[][5] = {
1340 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1340 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1341 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, 1341 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
1342 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, 1342 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
@@ -1386,7 +1386,7 @@ static const u32 ar9480_1p0_baseband_postamble[][5] = {
1386 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, 1386 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
1387}; 1387};
1388 1388
1389static const u32 ar9480_modes_fast_clock_1p0[][3] = { 1389static const u32 ar9462_modes_fast_clock_1p0[][3] = {
1390 /* Addr 5G_HT20 5G_HT40 */ 1390 /* Addr 5G_HT20 5G_HT40 */
1391 {0x00001030, 0x00000268, 0x000004d0}, 1391 {0x00001030, 0x00000268, 0x000004d0},
1392 {0x00001070, 0x0000018c, 0x00000318}, 1392 {0x00001070, 0x0000018c, 0x00000318},
@@ -1399,7 +1399,7 @@ static const u32 ar9480_modes_fast_clock_1p0[][3] = {
1399 {0x0000a254, 0x00000898, 0x00001130}, 1399 {0x0000a254, 0x00000898, 0x00001130},
1400}; 1400};
1401 1401
1402static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = { 1402static const u32 ar9462_modes_low_ob_db_tx_gain_table_1p0[][5] = {
1403 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1403 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1404 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, 1404 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
1405 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, 1405 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
@@ -1464,12 +1464,12 @@ static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = {
1464 {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, 1464 {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
1465}; 1465};
1466 1466
1467static const u32 ar9480_1p0_soc_postamble[][5] = { 1467static const u32 ar9462_1p0_soc_postamble[][5] = {
1468 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1468 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1469 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233}, 1469 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233},
1470}; 1470};
1471 1471
1472static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = { 1472static const u32 ar9462_common_mixed_rx_gain_table_1p0[][2] = {
1473 /* Addr allmodes */ 1473 /* Addr allmodes */
1474 {0x0000a000, 0x00010000}, 1474 {0x0000a000, 0x00010000},
1475 {0x0000a004, 0x00030002}, 1475 {0x0000a004, 0x00030002},
@@ -1729,14 +1729,14 @@ static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = {
1729 {0x0000b1fc, 0x00000196}, 1729 {0x0000b1fc, 0x00000196},
1730}; 1730};
1731 1731
1732static const u32 ar9480_pcie_phy_clkreq_disable_L1_1p0[][2] = { 1732static const u32 ar9462_pcie_phy_clkreq_disable_L1_1p0[][2] = {
1733 /* Addr allmodes */ 1733 /* Addr allmodes */
1734 {0x00018c00, 0x10013e5e}, 1734 {0x00018c00, 0x10013e5e},
1735 {0x00018c04, 0x000801d8}, 1735 {0x00018c04, 0x000801d8},
1736 {0x00018c08, 0x0000580c}, 1736 {0x00018c08, 0x0000580c},
1737}; 1737};
1738 1738
1739static const u32 ar9480_1p0_baseband_core_emulation[][2] = { 1739static const u32 ar9462_1p0_baseband_core_emulation[][2] = {
1740 /* Addr allmodes */ 1740 /* Addr allmodes */
1741 {0x00009800, 0xafa68e30}, 1741 {0x00009800, 0xafa68e30},
1742 {0x00009884, 0x00002842}, 1742 {0x00009884, 0x00002842},
@@ -1758,7 +1758,7 @@ static const u32 ar9480_1p0_baseband_core_emulation[][2] = {
1758 {0x0000a690, 0x00000038}, 1758 {0x0000a690, 0x00000038},
1759}; 1759};
1760 1760
1761static const u32 ar9480_1p0_radio_core[][2] = { 1761static const u32 ar9462_1p0_radio_core[][2] = {
1762 /* Addr allmodes */ 1762 /* Addr allmodes */
1763 {0x00016000, 0x36db6db6}, 1763 {0x00016000, 0x36db6db6},
1764 {0x00016004, 0x6db6db40}, 1764 {0x00016004, 0x6db6db40},
@@ -1818,16 +1818,16 @@ static const u32 ar9480_1p0_radio_core[][2] = {
1818 {0x00016548, 0x000080c0}, 1818 {0x00016548, 0x000080c0},
1819}; 1819};
1820 1820
1821static const u32 ar9480_1p0_soc_preamble[][2] = { 1821static const u32 ar9462_1p0_soc_preamble[][2] = {
1822 /* Addr allmodes */ 1822 /* Addr allmodes */
1823 {0x00007020, 0x00000000}, 1823 {0x00007020, 0x00000000},
1824 {0x00007034, 0x00000002}, 1824 {0x00007034, 0x00000002},
1825 {0x00007038, 0x000004c2}, 1825 {0x00007038, 0x000004c2},
1826}; 1826};
1827 1827
1828static const u32 ar9480_1p0_sys2ant[][2] = { 1828static const u32 ar9462_1p0_sys2ant[][2] = {
1829 /* Addr allmodes */ 1829 /* Addr allmodes */
1830 {0x00063120, 0x00801980}, 1830 {0x00063120, 0x00801980},
1831}; 1831};
1832 1832
1833#endif /* INITVALS_9480_1P0_H */ 1833#endif /* INITVALS_9462_1P0_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9480_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
index d54163d8d69f..9c51b395b4ff 100644
--- a/drivers/net/wireless/ath/ath9k/ar9480_2p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
@@ -14,12 +14,12 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#ifndef INITVALS_9480_2P0_H 17#ifndef INITVALS_9462_2P0_H
18#define INITVALS_9480_2P0_H 18#define INITVALS_9462_2P0_H
19 19
20/* AR9480 2.0 */ 20/* AR9462 2.0 */
21 21
22static const u32 ar9480_modes_fast_clock_2p0[][3] = { 22static const u32 ar9462_modes_fast_clock_2p0[][3] = {
23 /* Addr 5G_HT20 5G_HT40 */ 23 /* Addr 5G_HT20 5G_HT40 */
24 {0x00001030, 0x00000268, 0x000004d0}, 24 {0x00001030, 0x00000268, 0x000004d0},
25 {0x00001070, 0x0000018c, 0x00000318}, 25 {0x00001070, 0x0000018c, 0x00000318},
@@ -32,14 +32,14 @@ static const u32 ar9480_modes_fast_clock_2p0[][3] = {
32 {0x0000a254, 0x00000898, 0x00001130}, 32 {0x0000a254, 0x00000898, 0x00001130},
33}; 33};
34 34
35static const u32 ar9480_pciephy_clkreq_enable_L1_2p0[][2] = { 35static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
36 /* Addr allmodes */ 36 /* Addr allmodes */
37 {0x00018c00, 0x18253ede}, 37 {0x00018c00, 0x18253ede},
38 {0x00018c04, 0x000801d8}, 38 {0x00018c04, 0x000801d8},
39 {0x00018c08, 0x0003580c}, 39 {0x00018c08, 0x0003580c},
40}; 40};
41 41
42static const u32 ar9480_2p0_baseband_postamble[][5] = { 42static const u32 ar9462_2p0_baseband_postamble[][5] = {
43 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 43 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
44 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, 44 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
45 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, 45 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
@@ -89,7 +89,7 @@ static const u32 ar9480_2p0_baseband_postamble[][5] = {
89 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, 89 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
90}; 90};
91 91
92static const u32 ar9480_2p0_mac_core_emulation[][2] = { 92static const u32 ar9462_2p0_mac_core_emulation[][2] = {
93 /* Addr allmodes */ 93 /* Addr allmodes */
94 {0x00000030, 0x000e0085}, 94 {0x00000030, 0x000e0085},
95 {0x00000044, 0x00000008}, 95 {0x00000044, 0x00000008},
@@ -97,7 +97,7 @@ static const u32 ar9480_2p0_mac_core_emulation[][2] = {
97 {0x00008344, 0xaa4a105b}, 97 {0x00008344, 0xaa4a105b},
98}; 98};
99 99
100static const u32 ar9480_common_rx_gain_table_2p0[][2] = { 100static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
101 /* Addr allmodes */ 101 /* Addr allmodes */
102 {0x0000a000, 0x00010000}, 102 {0x0000a000, 0x00010000},
103 {0x0000a004, 0x00030002}, 103 {0x0000a004, 0x00030002},
@@ -357,27 +357,27 @@ static const u32 ar9480_common_rx_gain_table_2p0[][2] = {
357 {0x0000b1fc, 0x00000196}, 357 {0x0000b1fc, 0x00000196},
358}; 358};
359 359
360static const u32 ar9480_pciephy_clkreq_disable_L1_2p0[][2] = { 360static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
361 /* Addr allmodes */ 361 /* Addr allmodes */
362 {0x00018c00, 0x18213ede}, 362 {0x00018c00, 0x18213ede},
363 {0x00018c04, 0x000801d8}, 363 {0x00018c04, 0x000801d8},
364 {0x00018c08, 0x0003580c}, 364 {0x00018c08, 0x0003580c},
365}; 365};
366 366
367static const u32 ar9480_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = { 367static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
368 /* Addr allmodes */ 368 /* Addr allmodes */
369 {0x00018c00, 0x18212ede}, 369 {0x00018c00, 0x18212ede},
370 {0x00018c04, 0x000801d8}, 370 {0x00018c04, 0x000801d8},
371 {0x00018c08, 0x0003580c}, 371 {0x00018c08, 0x0003580c},
372}; 372};
373 373
374static const u32 ar9480_2p0_sys3ant[][2] = { 374static const u32 ar9462_2p0_sys3ant[][2] = {
375 /* Addr allmodes */ 375 /* Addr allmodes */
376 {0x00063280, 0x00040807}, 376 {0x00063280, 0x00040807},
377 {0x00063284, 0x104ccccc}, 377 {0x00063284, 0x104ccccc},
378}; 378};
379 379
380static const u32 ar9480_common_rx_gain_table_ar9280_2p0[][2] = { 380static const u32 ar9462_common_rx_gain_table_ar9280_2p0[][2] = {
381 /* Addr allmodes */ 381 /* Addr allmodes */
382 {0x0000a000, 0x02000101}, 382 {0x0000a000, 0x02000101},
383 {0x0000a004, 0x02000102}, 383 {0x0000a004, 0x02000102},
@@ -679,20 +679,20 @@ static const u32 ar9200_ar9280_2p0_radio_core[][2] = {
679 {0x00007894, 0x5a108000}, 679 {0x00007894, 0x5a108000},
680}; 680};
681 681
682static const u32 ar9480_2p0_mac_postamble_emulation[][5] = { 682static const u32 ar9462_2p0_mac_postamble_emulation[][5] = {
683 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 683 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
684 {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8}, 684 {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8},
685 {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017}, 685 {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017},
686}; 686};
687 687
688static const u32 ar9480_2p0_radio_postamble_sys3ant[][5] = { 688static const u32 ar9462_2p0_radio_postamble_sys3ant[][5] = {
689 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 689 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
690 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, 690 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
691 {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, 691 {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
692 {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, 692 {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
693}; 693};
694 694
695static const u32 ar9480_2p0_baseband_postamble_emulation[][5] = { 695static const u32 ar9462_2p0_baseband_postamble_emulation[][5] = {
696 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 696 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
697 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 697 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
698 {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221}, 698 {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221},
@@ -714,14 +714,14 @@ static const u32 ar9480_2p0_baseband_postamble_emulation[][5] = {
714 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 714 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
715}; 715};
716 716
717static const u32 ar9480_2p0_radio_postamble_sys2ant[][5] = { 717static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
718 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 718 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
719 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, 719 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
720 {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, 720 {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
721 {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, 721 {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
722}; 722};
723 723
724static const u32 ar9480_common_wo_xlna_rx_gain_table_2p0[][2] = { 724static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
725 /* Addr allmodes */ 725 /* Addr allmodes */
726 {0x0000a000, 0x00010000}, 726 {0x0000a000, 0x00010000},
727 {0x0000a004, 0x00030002}, 727 {0x0000a004, 0x00030002},
@@ -981,14 +981,14 @@ static const u32 ar9480_common_wo_xlna_rx_gain_table_2p0[][2] = {
981 {0x0000b1fc, 0x00000196}, 981 {0x0000b1fc, 0x00000196},
982}; 982};
983 983
984static const u32 ar9480_2p0_baseband_core_txfir_coeff_japan_2484[][2] = { 984static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
985 /* Addr allmodes */ 985 /* Addr allmodes */
986 {0x0000a398, 0x00000000}, 986 {0x0000a398, 0x00000000},
987 {0x0000a39c, 0x6f7f0301}, 987 {0x0000a39c, 0x6f7f0301},
988 {0x0000a3a0, 0xca9228ee}, 988 {0x0000a3a0, 0xca9228ee},
989}; 989};
990 990
991static const u32 ar9480_modes_low_ob_db_tx_gain_table_2p0[][5] = { 991static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
992 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 992 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
993 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, 993 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
994 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, 994 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
@@ -1057,12 +1057,12 @@ static const u32 ar9480_modes_low_ob_db_tx_gain_table_2p0[][5] = {
1057 {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, 1057 {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
1058}; 1058};
1059 1059
1060static const u32 ar9480_2p0_soc_postamble[][5] = { 1060static const u32 ar9462_2p0_soc_postamble[][5] = {
1061 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1061 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1062 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233}, 1062 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233},
1063}; 1063};
1064 1064
1065static const u32 ar9480_2p0_baseband_core[][2] = { 1065static const u32 ar9462_2p0_baseband_core[][2] = {
1066 /* Addr allmodes */ 1066 /* Addr allmodes */
1067 {0x00009800, 0xafe68e30}, 1067 {0x00009800, 0xafe68e30},
1068 {0x00009804, 0xfd14e000}, 1068 {0x00009804, 0xfd14e000},
@@ -1221,7 +1221,7 @@ static const u32 ar9480_2p0_baseband_core[][2] = {
1221 {0x0000b6b4, 0x00000001}, 1221 {0x0000b6b4, 0x00000001},
1222}; 1222};
1223 1223
1224static const u32 ar9480_2p0_radio_postamble[][5] = { 1224static const u32 ar9462_2p0_radio_postamble[][5] = {
1225 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1225 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1226 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, 1226 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
1227 {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70}, 1227 {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
@@ -1229,7 +1229,7 @@ static const u32 ar9480_2p0_radio_postamble[][5] = {
1229 {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, 1229 {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
1230}; 1230};
1231 1231
1232static const u32 ar9480_modes_high_ob_db_tx_gain_table_2p0[][5] = { 1232static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
1233 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1233 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1234 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, 1234 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
1235 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, 1235 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
@@ -1298,7 +1298,7 @@ static const u32 ar9480_modes_high_ob_db_tx_gain_table_2p0[][5] = {
1298 {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, 1298 {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
1299}; 1299};
1300 1300
1301static const u32 ar9480_2p0_radio_core[][2] = { 1301static const u32 ar9462_2p0_radio_core[][2] = {
1302 /* Addr allmodes */ 1302 /* Addr allmodes */
1303 {0x00016000, 0x36db6db6}, 1303 {0x00016000, 0x36db6db6},
1304 {0x00016004, 0x6db6db40}, 1304 {0x00016004, 0x6db6db40},
@@ -1356,7 +1356,7 @@ static const u32 ar9480_2p0_radio_core[][2] = {
1356 {0x00016548, 0x000080c0}, 1356 {0x00016548, 0x000080c0},
1357}; 1357};
1358 1358
1359static const u32 ar9480_2p0_tx_gain_table_baseband_postamble_emulation[][5] = { 1359static const u32 ar9462_2p0_tx_gain_table_baseband_postamble_emulation[][5] = {
1360 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1360 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1361 {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5}, 1361 {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5},
1362 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 1362 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -1374,19 +1374,19 @@ static const u32 ar9480_2p0_tx_gain_table_baseband_postamble_emulation[][5] = {
1374 {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a}, 1374 {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a},
1375}; 1375};
1376 1376
1377static const u32 ar9480_2p0_soc_preamble[][2] = { 1377static const u32 ar9462_2p0_soc_preamble[][2] = {
1378 /* Addr allmodes */ 1378 /* Addr allmodes */
1379 {0x00007020, 0x00000000}, 1379 {0x00007020, 0x00000000},
1380 {0x00007034, 0x00000002}, 1380 {0x00007034, 0x00000002},
1381 {0x00007038, 0x000004c2}, 1381 {0x00007038, 0x000004c2},
1382}; 1382};
1383 1383
1384static const u32 ar9480_2p0_sys2ant[][2] = { 1384static const u32 ar9462_2p0_sys2ant[][2] = {
1385 /* Addr allmodes */ 1385 /* Addr allmodes */
1386 {0x00063120, 0x00801980}, 1386 {0x00063120, 0x00801980},
1387}; 1387};
1388 1388
1389static const u32 ar9480_2p0_mac_core[][2] = { 1389static const u32 ar9462_2p0_mac_core[][2] = {
1390 /* Addr allmodes */ 1390 /* Addr allmodes */
1391 {0x00000008, 0x00000000}, 1391 {0x00000008, 0x00000000},
1392 {0x00000030, 0x000e0085}, 1392 {0x00000030, 0x000e0085},
@@ -1550,7 +1550,7 @@ static const u32 ar9480_2p0_mac_core[][2] = {
1550 {0x000083d0, 0x000301ff}, 1550 {0x000083d0, 0x000301ff},
1551}; 1551};
1552 1552
1553static const u32 ar9480_2p0_mac_postamble[][5] = { 1553static const u32 ar9462_2p0_mac_postamble[][5] = {
1554 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1554 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1555 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, 1555 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
1556 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, 1556 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
@@ -1562,7 +1562,7 @@ static const u32 ar9480_2p0_mac_postamble[][5] = {
1562 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, 1562 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
1563}; 1563};
1564 1564
1565static const u32 ar9480_common_mixed_rx_gain_table_2p0[][2] = { 1565static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
1566 /* Addr allmodes */ 1566 /* Addr allmodes */
1567 {0x0000a000, 0x00010000}, 1567 {0x0000a000, 0x00010000},
1568 {0x0000a004, 0x00030002}, 1568 {0x0000a004, 0x00030002},
@@ -1822,7 +1822,7 @@ static const u32 ar9480_common_mixed_rx_gain_table_2p0[][2] = {
1822 {0x0000b1fc, 0x00000196}, 1822 {0x0000b1fc, 0x00000196},
1823}; 1823};
1824 1824
1825static const u32 ar9480_modes_green_ob_db_tx_gain_table_2p0[][5] = { 1825static const u32 ar9462_modes_green_ob_db_tx_gain_table_2p0[][5] = {
1826 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1826 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1827 {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003}, 1827 {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
1828 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, 1828 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
@@ -1891,7 +1891,7 @@ static const u32 ar9480_modes_green_ob_db_tx_gain_table_2p0[][5] = {
1891 {0x00016454, 0x6db60180, 0x6db60180, 0x6db60180, 0x6db60180}, 1891 {0x00016454, 0x6db60180, 0x6db60180, 0x6db60180, 0x6db60180},
1892}; 1892};
1893 1893
1894static const u32 ar9480_2p0_BTCOEX_MAX_TXPWR_table[][2] = { 1894static const u32 ar9462_2p0_BTCOEX_MAX_TXPWR_table[][2] = {
1895 /* Addr allmodes */ 1895 /* Addr allmodes */
1896 {0x000018c0, 0x10101010}, 1896 {0x000018c0, 0x10101010},
1897 {0x000018c4, 0x10101010}, 1897 {0x000018c4, 0x10101010},
@@ -1903,7 +1903,7 @@ static const u32 ar9480_2p0_BTCOEX_MAX_TXPWR_table[][2] = {
1903 {0x000018dc, 0x10101010}, 1903 {0x000018dc, 0x10101010},
1904}; 1904};
1905 1905
1906static const u32 ar9480_2p0_baseband_core_emulation[][2] = { 1906static const u32 ar9462_2p0_baseband_core_emulation[][2] = {
1907 /* Addr allmodes */ 1907 /* Addr allmodes */
1908 {0x00009800, 0xafa68e30}, 1908 {0x00009800, 0xafa68e30},
1909 {0x00009884, 0x00002842}, 1909 {0x00009884, 0x00002842},
@@ -1925,4 +1925,4 @@ static const u32 ar9480_2p0_baseband_core_emulation[][2] = {
1925 {0x0000a690, 0x00000038}, 1925 {0x0000a690, 0x00000038},
1926}; 1926};
1927 1927
1928#endif /* INITVALS_9480_2P0_H */ 1928#endif /* INITVALS_9462_2P0_H */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 1e8614783181..1c269f50822b 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -458,7 +458,7 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc);
458#define ATH_LED_PIN_9287 8 458#define ATH_LED_PIN_9287 8
459#define ATH_LED_PIN_9300 10 459#define ATH_LED_PIN_9300 10
460#define ATH_LED_PIN_9485 6 460#define ATH_LED_PIN_9485 6
461#define ATH_LED_PIN_9480 0 461#define ATH_LED_PIN_9462 0
462 462
463#ifdef CONFIG_MAC80211_LEDS 463#ifdef CONFIG_MAC80211_LEDS
464void ath_init_leds(struct ath_softc *sc); 464void ath_init_leds(struct ath_softc *sc);
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 9cdeaebc844f..a13cabb95435 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -515,7 +515,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
515 sc->sc_flags |= SC_OP_TSF_RESET; 515 sc->sc_flags |= SC_OP_TSF_RESET;
516 ath9k_beacon_init(sc, nexttbtt, intval); 516 ath9k_beacon_init(sc, nexttbtt, intval);
517 sc->beacon.bmisscnt = 0; 517 sc->beacon.bmisscnt = 0;
518 ath9k_hw_set_interrupts(ah, ah->imask); 518 ath9k_hw_set_interrupts(ah);
519 ath9k_hw_enable_interrupts(ah); 519 ath9k_hw_enable_interrupts(ah);
520} 520}
521 521
@@ -643,7 +643,7 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
643 ath9k_hw_set_sta_beacon_timers(ah, &bs); 643 ath9k_hw_set_sta_beacon_timers(ah, &bs);
644 ah->imask |= ATH9K_INT_BMISS; 644 ah->imask |= ATH9K_INT_BMISS;
645 645
646 ath9k_hw_set_interrupts(ah, ah->imask); 646 ath9k_hw_set_interrupts(ah);
647 ath9k_hw_enable_interrupts(ah); 647 ath9k_hw_enable_interrupts(ah);
648} 648}
649 649
@@ -679,7 +679,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
679 ath9k_beacon_init(sc, nexttbtt, intval); 679 ath9k_beacon_init(sc, nexttbtt, intval);
680 sc->beacon.bmisscnt = 0; 680 sc->beacon.bmisscnt = 0;
681 681
682 ath9k_hw_set_interrupts(ah, ah->imask); 682 ath9k_hw_set_interrupts(ah);
683 ath9k_hw_enable_interrupts(ah); 683 ath9k_hw_enable_interrupts(ah);
684} 684}
685 685
@@ -821,11 +821,11 @@ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
821 if (status) { 821 if (status) {
822 /* Re-enable beaconing */ 822 /* Re-enable beaconing */
823 ah->imask |= ATH9K_INT_SWBA; 823 ah->imask |= ATH9K_INT_SWBA;
824 ath9k_hw_set_interrupts(ah, ah->imask); 824 ath9k_hw_set_interrupts(ah);
825 } else { 825 } else {
826 /* Disable SWBA interrupt */ 826 /* Disable SWBA interrupt */
827 ah->imask &= ~ATH9K_INT_SWBA; 827 ah->imask &= ~ATH9K_INT_SWBA;
828 ath9k_hw_set_interrupts(ah, ah->imask); 828 ath9k_hw_set_interrupts(ah);
829 tasklet_kill(&sc->bcon_tasklet); 829 tasklet_kill(&sc->bcon_tasklet);
830 ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq); 830 ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
831 } 831 }
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c
index dc705a224952..905f1b313961 100644
--- a/drivers/net/wireless/ath/ath9k/common.c
+++ b/drivers/net/wireless/ath/ath9k/common.c
@@ -161,10 +161,12 @@ EXPORT_SYMBOL(ath9k_cmn_count_streams);
161void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow, 161void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
162 u16 new_txpow, u16 *txpower) 162 u16 new_txpow, u16 *txpower)
163{ 163{
164 if (cur_txpow != new_txpow) { 164 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
165
166 if (reg->power_limit != new_txpow) {
165 ath9k_hw_set_txpowerlimit(ah, new_txpow, false); 167 ath9k_hw_set_txpowerlimit(ah, new_txpow, false);
166 /* read back in case value is clamped */ 168 /* read back in case value is clamped */
167 *txpower = ath9k_hw_regulatory(ah)->power_limit; 169 *txpower = reg->max_power_level;
168 } 170 }
169} 171}
170EXPORT_SYMBOL(ath9k_cmn_update_txpow); 172EXPORT_SYMBOL(ath9k_cmn_update_txpow);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index a5329c98f9ea..327aa28f6030 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -523,9 +523,22 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
523 if (tmp & ATH9K_RX_FILTER_PHYRADAR) 523 if (tmp & ATH9K_RX_FILTER_PHYRADAR)
524 len += snprintf(buf + len, sizeof(buf) - len, " PHYRADAR"); 524 len += snprintf(buf + len, sizeof(buf) - len, " PHYRADAR");
525 if (tmp & ATH9K_RX_FILTER_MCAST_BCAST_ALL) 525 if (tmp & ATH9K_RX_FILTER_MCAST_BCAST_ALL)
526 len += snprintf(buf + len, sizeof(buf) - len, " MCAST_BCAST_ALL\n"); 526 len += snprintf(buf + len, sizeof(buf) - len, " MCAST_BCAST_ALL");
527 else 527
528 len += snprintf(buf + len, sizeof(buf) - len, "\n"); 528 len += snprintf(buf + len, sizeof(buf) - len,
529 "\n\nReset causes:\n"
530 " baseband hang: %d\n"
531 " baseband watchdog: %d\n"
532 " fatal hardware error interrupt: %d\n"
533 " tx hardware error: %d\n"
534 " tx path hang: %d\n"
535 " pll rx hang: %d\n",
536 sc->debug.stats.reset[RESET_TYPE_BB_HANG],
537 sc->debug.stats.reset[RESET_TYPE_BB_WATCHDOG],
538 sc->debug.stats.reset[RESET_TYPE_FATAL_INT],
539 sc->debug.stats.reset[RESET_TYPE_TX_ERROR],
540 sc->debug.stats.reset[RESET_TYPE_TX_HANG],
541 sc->debug.stats.reset[RESET_TYPE_PLL_HANG]);
529 542
530 if (len > sizeof(buf)) 543 if (len > sizeof(buf))
531 len = sizeof(buf); 544 len = sizeof(buf);
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index b93e88bd8c58..356352ac2d6e 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -25,8 +25,10 @@ struct ath_buf;
25 25
26#ifdef CONFIG_ATH9K_DEBUGFS 26#ifdef CONFIG_ATH9K_DEBUGFS
27#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 27#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
28#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
28#else 29#else
29#define TX_STAT_INC(q, c) do { } while (0) 30#define TX_STAT_INC(q, c) do { } while (0)
31#define RESET_STAT_INC(sc, type) do { } while (0)
30#endif 32#endif
31 33
32#ifdef CONFIG_ATH9K_DEBUGFS 34#ifdef CONFIG_ATH9K_DEBUGFS
@@ -171,10 +173,21 @@ struct ath_rx_stats {
171 u8 rs_antenna; 173 u8 rs_antenna;
172}; 174};
173 175
176enum ath_reset_type {
177 RESET_TYPE_BB_HANG,
178 RESET_TYPE_BB_WATCHDOG,
179 RESET_TYPE_FATAL_INT,
180 RESET_TYPE_TX_ERROR,
181 RESET_TYPE_TX_HANG,
182 RESET_TYPE_PLL_HANG,
183 __RESET_TYPE_MAX
184};
185
174struct ath_stats { 186struct ath_stats {
175 struct ath_interrupt_stats istats; 187 struct ath_interrupt_stats istats;
176 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 188 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
177 struct ath_rx_stats rxstats; 189 struct ath_rx_stats rxstats;
190 u32 reset[__RESET_TYPE_MAX];
178}; 191};
179 192
180#define ATH_DBG_MAX_SAMPLES 10 193#define ATH_DBG_MAX_SAMPLES 10
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 5d92f96980e6..49abd34be741 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -108,7 +108,7 @@
108#define EEP_RFSILENT_ENABLED_S 0 108#define EEP_RFSILENT_ENABLED_S 0
109#define EEP_RFSILENT_POLARITY 0x0002 109#define EEP_RFSILENT_POLARITY 0x0002
110#define EEP_RFSILENT_POLARITY_S 1 110#define EEP_RFSILENT_POLARITY_S 1
111#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9480(ah) ? 0x00fc : 0x001c) 111#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9462(ah) ? 0x00fc : 0x001c)
112#define EEP_RFSILENT_GPIO_SEL_S 2 112#define EEP_RFSILENT_GPIO_SEL_S 2
113 113
114#define AR5416_OPFLAGS_11A 0x01 114#define AR5416_OPFLAGS_11A 0x01
@@ -220,7 +220,6 @@ enum eeprom_param {
220 EEP_MAC_MID, 220 EEP_MAC_MID,
221 EEP_MAC_LSW, 221 EEP_MAC_LSW,
222 EEP_REG_0, 222 EEP_REG_0,
223 EEP_REG_1,
224 EEP_OP_CAP, 223 EEP_OP_CAP,
225 EEP_OP_MODE, 224 EEP_OP_MODE,
226 EEP_RF_SILENT, 225 EEP_RF_SILENT,
@@ -248,7 +247,9 @@ enum eeprom_param {
248 EEP_PAPRD, 247 EEP_PAPRD,
249 EEP_MODAL_VER, 248 EEP_MODAL_VER,
250 EEP_ANT_DIV_CTL1, 249 EEP_ANT_DIV_CTL1,
251 EEP_CHAIN_MASK_REDUCE 250 EEP_CHAIN_MASK_REDUCE,
251 EEP_ANTENNA_GAIN_2G,
252 EEP_ANTENNA_GAIN_5G
252}; 253};
253 254
254enum ar5416_rates { 255enum ar5416_rates {
@@ -652,8 +653,7 @@ struct eeprom_ops {
652 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 653 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
653 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 654 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
654 u16 cfgCtl, u8 twiceAntennaReduction, 655 u16 cfgCtl, u8 twiceAntennaReduction,
655 u8 twiceMaxRegulatoryPower, u8 powerLimit, 656 u8 powerLimit, bool test);
656 bool test);
657 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 657 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
658}; 658};
659 659
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 303560e49ac8..9a7520f987f0 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -322,8 +322,6 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
322 return get_unaligned_be16(pBase->macAddr + 4); 322 return get_unaligned_be16(pBase->macAddr + 4);
323 case EEP_REG_0: 323 case EEP_REG_0:
324 return pBase->regDmn[0]; 324 return pBase->regDmn[0];
325 case EEP_REG_1:
326 return pBase->regDmn[1];
327 case EEP_OP_CAP: 325 case EEP_OP_CAP:
328 return pBase->deviceCap; 326 return pBase->deviceCap;
329 case EEP_OP_MODE: 327 case EEP_OP_MODE:
@@ -350,6 +348,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
350 return pModal->antdiv_ctl1; 348 return pModal->antdiv_ctl1;
351 case EEP_TXGAIN_TYPE: 349 case EEP_TXGAIN_TYPE:
352 return pBase->txGainType; 350 return pBase->txGainType;
351 case EEP_ANTENNA_GAIN_2G:
352 return pModal->antennaGainCh[0];
353 default: 353 default:
354 return 0; 354 return 0;
355 } 355 }
@@ -462,8 +462,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
462 struct ath9k_channel *chan, 462 struct ath9k_channel *chan,
463 int16_t *ratesArray, 463 int16_t *ratesArray,
464 u16 cfgCtl, 464 u16 cfgCtl,
465 u16 AntennaReduction, 465 u16 antenna_reduction,
466 u16 twiceMaxRegulatoryPower,
467 u16 powerLimit) 466 u16 powerLimit)
468{ 467{
469#define CMP_TEST_GRP \ 468#define CMP_TEST_GRP \
@@ -472,20 +471,16 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
472 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 471 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
473 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) 472 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
474 473
475 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
476 int i; 474 int i;
477 int16_t twiceLargestAntenna;
478 u16 twiceMinEdgePower; 475 u16 twiceMinEdgePower;
479 u16 twiceMaxEdgePower = MAX_RATE_POWER; 476 u16 twiceMaxEdgePower = MAX_RATE_POWER;
480 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 477 u16 scaledPower = 0, minCtlPower;
481 u16 numCtlModes; 478 u16 numCtlModes;
482 const u16 *pCtlMode; 479 const u16 *pCtlMode;
483 u16 ctlMode, freq; 480 u16 ctlMode, freq;
484 struct chan_centers centers; 481 struct chan_centers centers;
485 struct cal_ctl_data_4k *rep; 482 struct cal_ctl_data_4k *rep;
486 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 483 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
487 static const u16 tpScaleReductionTable[5] =
488 { 0, 3, 6, 9, MAX_RATE_POWER };
489 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 484 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
490 0, { 0, 0, 0, 0} 485 0, { 0, 0, 0, 0}
491 }; 486 };
@@ -503,19 +498,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
503 498
504 ath9k_hw_get_channel_centers(ah, chan, &centers); 499 ath9k_hw_get_channel_centers(ah, chan, &centers);
505 500
506 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 501 scaledPower = powerLimit - antenna_reduction;
507 twiceLargestAntenna = (int16_t)min(AntennaReduction -
508 twiceLargestAntenna, 0);
509
510 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
511 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
512 maxRegAllowedPower -=
513 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
514 }
515
516 scaledPower = min(powerLimit, maxRegAllowedPower);
517 scaledPower = max((u16)0, scaledPower);
518
519 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; 502 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
520 pCtlMode = ctlModesFor11g; 503 pCtlMode = ctlModesFor11g;
521 504
@@ -671,7 +654,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
671 struct ath9k_channel *chan, 654 struct ath9k_channel *chan,
672 u16 cfgCtl, 655 u16 cfgCtl,
673 u8 twiceAntennaReduction, 656 u8 twiceAntennaReduction,
674 u8 twiceMaxRegulatoryPower,
675 u8 powerLimit, bool test) 657 u8 powerLimit, bool test)
676{ 658{
677 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 659 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
@@ -691,7 +673,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
691 ath9k_hw_set_4k_power_per_rate_table(ah, chan, 673 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
692 &ratesArray[0], cfgCtl, 674 &ratesArray[0], cfgCtl,
693 twiceAntennaReduction, 675 twiceAntennaReduction,
694 twiceMaxRegulatoryPower,
695 powerLimit); 676 powerLimit);
696 677
697 ath9k_hw_set_4k_power_cal_table(ah, chan); 678 ath9k_hw_set_4k_power_cal_table(ah, chan);
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index 6698b722b604..4f5c50a87ce3 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -308,8 +308,6 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
308 return get_unaligned_be16(pBase->macAddr + 4); 308 return get_unaligned_be16(pBase->macAddr + 4);
309 case EEP_REG_0: 309 case EEP_REG_0:
310 return pBase->regDmn[0]; 310 return pBase->regDmn[0];
311 case EEP_REG_1:
312 return pBase->regDmn[1];
313 case EEP_OP_CAP: 311 case EEP_OP_CAP:
314 return pBase->deviceCap; 312 return pBase->deviceCap;
315 case EEP_OP_MODE: 313 case EEP_OP_MODE:
@@ -336,6 +334,9 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
336 return pBase->tempSensSlopePalOn; 334 return pBase->tempSensSlopePalOn;
337 else 335 else
338 return 0; 336 return 0;
337 case EEP_ANTENNA_GAIN_2G:
338 return max_t(u8, pModal->antennaGainCh[0],
339 pModal->antennaGainCh[1]);
339 default: 340 default:
340 return 0; 341 return 0;
341 } 342 }
@@ -554,8 +555,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
554 struct ath9k_channel *chan, 555 struct ath9k_channel *chan,
555 int16_t *ratesArray, 556 int16_t *ratesArray,
556 u16 cfgCtl, 557 u16 cfgCtl,
557 u16 AntennaReduction, 558 u16 antenna_reduction,
558 u16 twiceMaxRegulatoryPower,
559 u16 powerLimit) 559 u16 powerLimit)
560{ 560{
561#define CMP_CTL \ 561#define CMP_CTL \
@@ -569,12 +569,8 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
569#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 569#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
570#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 570#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
571 571
572 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
573 u16 twiceMaxEdgePower = MAX_RATE_POWER; 572 u16 twiceMaxEdgePower = MAX_RATE_POWER;
574 static const u16 tpScaleReductionTable[5] =
575 { 0, 3, 6, 9, MAX_RATE_POWER };
576 int i; 573 int i;
577 int16_t twiceLargestAntenna;
578 struct cal_ctl_data_ar9287 *rep; 574 struct cal_ctl_data_ar9287 *rep;
579 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} }, 575 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
580 targetPowerCck = {0, {0, 0, 0, 0} }; 576 targetPowerCck = {0, {0, 0, 0, 0} };
@@ -582,7 +578,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
582 targetPowerCckExt = {0, {0, 0, 0, 0} }; 578 targetPowerCckExt = {0, {0, 0, 0, 0} };
583 struct cal_target_power_ht targetPowerHt20, 579 struct cal_target_power_ht targetPowerHt20,
584 targetPowerHt40 = {0, {0, 0, 0, 0} }; 580 targetPowerHt40 = {0, {0, 0, 0, 0} };
585 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 581 u16 scaledPower = 0, minCtlPower;
586 static const u16 ctlModesFor11g[] = { 582 static const u16 ctlModesFor11g[] = {
587 CTL_11B, CTL_11G, CTL_2GHT20, 583 CTL_11B, CTL_11G, CTL_2GHT20,
588 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 584 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
@@ -597,24 +593,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
597 tx_chainmask = ah->txchainmask; 593 tx_chainmask = ah->txchainmask;
598 594
599 ath9k_hw_get_channel_centers(ah, chan, &centers); 595 ath9k_hw_get_channel_centers(ah, chan, &centers);
600 596 scaledPower = powerLimit - antenna_reduction;
601 /* Compute TxPower reduction due to Antenna Gain */
602 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
603 pEepData->modalHeader.antennaGainCh[1]);
604 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
605 twiceLargestAntenna, 0);
606
607 /*
608 * scaledPower is the minimum of the user input power level
609 * and the regulatory allowed power level.
610 */
611 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
612
613 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
614 maxRegAllowedPower -=
615 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
616
617 scaledPower = min(powerLimit, maxRegAllowedPower);
618 597
619 /* 598 /*
620 * Reduce scaled Power by number of chains active 599 * Reduce scaled Power by number of chains active
@@ -815,7 +794,6 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
815static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, 794static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
816 struct ath9k_channel *chan, u16 cfgCtl, 795 struct ath9k_channel *chan, u16 cfgCtl,
817 u8 twiceAntennaReduction, 796 u8 twiceAntennaReduction,
818 u8 twiceMaxRegulatoryPower,
819 u8 powerLimit, bool test) 797 u8 powerLimit, bool test)
820{ 798{
821 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 799 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
@@ -834,7 +812,6 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
834 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan, 812 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
835 &ratesArray[0], cfgCtl, 813 &ratesArray[0], cfgCtl,
836 twiceAntennaReduction, 814 twiceAntennaReduction,
837 twiceMaxRegulatoryPower,
838 powerLimit); 815 powerLimit);
839 816
840 ath9k_hw_set_ar9287_power_cal_table(ah, chan); 817 ath9k_hw_set_ar9287_power_cal_table(ah, chan);
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index eda681fc7ba6..81e629671679 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -400,6 +400,7 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
400 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 400 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
401 struct modal_eep_header *pModal = eep->modalHeader; 401 struct modal_eep_header *pModal = eep->modalHeader;
402 struct base_eep_header *pBase = &eep->baseEepHeader; 402 struct base_eep_header *pBase = &eep->baseEepHeader;
403 int band = 0;
403 404
404 switch (param) { 405 switch (param) {
405 case EEP_NFTHRESH_5: 406 case EEP_NFTHRESH_5:
@@ -414,8 +415,6 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
414 return get_unaligned_be16(pBase->macAddr + 4); 415 return get_unaligned_be16(pBase->macAddr + 4);
415 case EEP_REG_0: 416 case EEP_REG_0:
416 return pBase->regDmn[0]; 417 return pBase->regDmn[0];
417 case EEP_REG_1:
418 return pBase->regDmn[1];
419 case EEP_OP_CAP: 418 case EEP_OP_CAP:
420 return pBase->deviceCap; 419 return pBase->deviceCap;
421 case EEP_OP_MODE: 420 case EEP_OP_MODE:
@@ -467,6 +466,14 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
467 return pBase->pwr_table_offset; 466 return pBase->pwr_table_offset;
468 else 467 else
469 return AR5416_PWR_TABLE_OFFSET_DB; 468 return AR5416_PWR_TABLE_OFFSET_DB;
469 case EEP_ANTENNA_GAIN_2G:
470 band = 1;
471 /* fall through */
472 case EEP_ANTENNA_GAIN_5G:
473 return max_t(u8, max_t(u8,
474 pModal[band].antennaGainCh[0],
475 pModal[band].antennaGainCh[1]),
476 pModal[band].antennaGainCh[2]);
470 default: 477 default:
471 return 0; 478 return 0;
472 } 479 }
@@ -986,21 +993,15 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
986 struct ath9k_channel *chan, 993 struct ath9k_channel *chan,
987 int16_t *ratesArray, 994 int16_t *ratesArray,
988 u16 cfgCtl, 995 u16 cfgCtl,
989 u16 AntennaReduction, 996 u16 antenna_reduction,
990 u16 twiceMaxRegulatoryPower,
991 u16 powerLimit) 997 u16 powerLimit)
992{ 998{
993#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ 999#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
994#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */ 1000#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
995 1001
996 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
997 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; 1002 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
998 u16 twiceMaxEdgePower = MAX_RATE_POWER; 1003 u16 twiceMaxEdgePower = MAX_RATE_POWER;
999 static const u16 tpScaleReductionTable[5] =
1000 { 0, 3, 6, 9, MAX_RATE_POWER };
1001
1002 int i; 1004 int i;
1003 int16_t twiceLargestAntenna;
1004 struct cal_ctl_data *rep; 1005 struct cal_ctl_data *rep;
1005 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 1006 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1006 0, { 0, 0, 0, 0} 1007 0, { 0, 0, 0, 0}
@@ -1012,7 +1013,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
1012 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 1013 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1013 0, {0, 0, 0, 0} 1014 0, {0, 0, 0, 0}
1014 }; 1015 };
1015 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 1016 u16 scaledPower = 0, minCtlPower;
1016 static const u16 ctlModesFor11a[] = { 1017 static const u16 ctlModesFor11a[] = {
1017 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 1018 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1018 }; 1019 };
@@ -1031,27 +1032,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
1031 1032
1032 ath9k_hw_get_channel_centers(ah, chan, &centers); 1033 ath9k_hw_get_channel_centers(ah, chan, &centers);
1033 1034
1034 twiceLargestAntenna = max( 1035 scaledPower = powerLimit - antenna_reduction;
1035 pEepData->modalHeader
1036 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1037 pEepData->modalHeader
1038 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1039
1040 twiceLargestAntenna = max((u8)twiceLargestAntenna,
1041 pEepData->modalHeader
1042 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1043
1044 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1045 twiceLargestAntenna, 0);
1046
1047 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1048
1049 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
1050 maxRegAllowedPower -=
1051 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
1052 }
1053
1054 scaledPower = min(powerLimit, maxRegAllowedPower);
1055 1036
1056 switch (ar5416_get_ntxchains(tx_chainmask)) { 1037 switch (ar5416_get_ntxchains(tx_chainmask)) {
1057 case 1: 1038 case 1:
@@ -1256,7 +1237,6 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1256 struct ath9k_channel *chan, 1237 struct ath9k_channel *chan,
1257 u16 cfgCtl, 1238 u16 cfgCtl,
1258 u8 twiceAntennaReduction, 1239 u8 twiceAntennaReduction,
1259 u8 twiceMaxRegulatoryPower,
1260 u8 powerLimit, bool test) 1240 u8 powerLimit, bool test)
1261{ 1241{
1262#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta) 1242#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
@@ -1278,7 +1258,6 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1278 ath9k_hw_set_def_power_per_rate_table(ah, chan, 1258 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1279 &ratesArray[0], cfgCtl, 1259 &ratesArray[0], cfgCtl,
1280 twiceAntennaReduction, 1260 twiceAntennaReduction,
1281 twiceMaxRegulatoryPower,
1282 powerLimit); 1261 powerLimit);
1283 1262
1284 ath9k_hw_set_def_power_cal_table(ah, chan); 1263 ath9k_hw_set_def_power_cal_table(ah, chan);
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index fd0f84ebdb51..655576c8fdab 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -48,8 +48,8 @@ void ath_init_leds(struct ath_softc *sc)
48 sc->sc_ah->led_pin = ATH_LED_PIN_9485; 48 sc->sc_ah->led_pin = ATH_LED_PIN_9485;
49 else if (AR_SREV_9300(sc->sc_ah)) 49 else if (AR_SREV_9300(sc->sc_ah))
50 sc->sc_ah->led_pin = ATH_LED_PIN_9300; 50 sc->sc_ah->led_pin = ATH_LED_PIN_9300;
51 else if (AR_SREV_9480(sc->sc_ah)) 51 else if (AR_SREV_9462(sc->sc_ah))
52 sc->sc_ah->led_pin = ATH_LED_PIN_9480; 52 sc->sc_ah->led_pin = ATH_LED_PIN_9462;
53 else 53 else
54 sc->sc_ah->led_pin = ATH_LED_PIN_DEF; 54 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
55 } 55 }
@@ -155,7 +155,7 @@ static void ath9k_gen_timer_start(struct ath_hw *ah,
155 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 155 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
156 ath9k_hw_disable_interrupts(ah); 156 ath9k_hw_disable_interrupts(ah);
157 ah->imask |= ATH9K_INT_GENTIMER; 157 ah->imask |= ATH9K_INT_GENTIMER;
158 ath9k_hw_set_interrupts(ah, ah->imask); 158 ath9k_hw_set_interrupts(ah);
159 ath9k_hw_enable_interrupts(ah); 159 ath9k_hw_enable_interrupts(ah);
160 } 160 }
161} 161}
@@ -170,7 +170,7 @@ static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
170 if (timer_table->timer_mask.val == 0) { 170 if (timer_table->timer_mask.val == 0) {
171 ath9k_hw_disable_interrupts(ah); 171 ath9k_hw_disable_interrupts(ah);
172 ah->imask &= ~ATH9K_INT_GENTIMER; 172 ah->imask &= ~ATH9K_INT_GENTIMER;
173 ath9k_hw_set_interrupts(ah, ah->imask); 173 ath9k_hw_set_interrupts(ah);
174 ath9k_hw_enable_interrupts(ah); 174 ath9k_hw_enable_interrupts(ah);
175 } 175 }
176} 176}
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index e9782d164962..e74c233757a2 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -205,4 +205,11 @@ static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
205 ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal); 205 ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
206} 206}
207 207
208static inline int ath9k_hw_fast_chan_change(struct ath_hw *ah,
209 struct ath9k_channel *chan,
210 u8 *ini_reloaded)
211{
212 return ath9k_hw_private_ops(ah)->fast_chan_change(ah, chan,
213 ini_reloaded);
214}
208#endif /* ATH9K_HW_OPS_H */ 215#endif /* ATH9K_HW_OPS_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 42ebe8fb053a..f16d2033081f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -285,7 +285,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
287 287
288 if (AR_SREV_9480(ah)) 288 if (AR_SREV_9462(ah))
289 ah->is_pciexpress = true; 289 ah->is_pciexpress = true;
290 else 290 else
291 ah->is_pciexpress = (val & 291 ah->is_pciexpress = (val &
@@ -433,7 +433,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
433 433
434 regulatory->country_code = CTRY_DEFAULT; 434 regulatory->country_code = CTRY_DEFAULT;
435 regulatory->power_limit = MAX_RATE_POWER; 435 regulatory->power_limit = MAX_RATE_POWER;
436 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
437 436
438 ah->hw_version.magic = AR5416_MAGIC; 437 ah->hw_version.magic = AR5416_MAGIC;
439 ah->hw_version.subvendorid = 0; 438 ah->hw_version.subvendorid = 0;
@@ -542,6 +541,9 @@ static int __ath9k_hw_init(struct ath_hw *ah)
542 return -EIO; 541 return -EIO;
543 } 542 }
544 543
544 if (AR_SREV_9462(ah))
545 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
546
545 ath9k_hw_init_defaults(ah); 547 ath9k_hw_init_defaults(ah);
546 ath9k_hw_init_config(ah); 548 ath9k_hw_init_config(ah);
547 549
@@ -585,7 +587,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
585 case AR_SREV_VERSION_9330: 587 case AR_SREV_VERSION_9330:
586 case AR_SREV_VERSION_9485: 588 case AR_SREV_VERSION_9485:
587 case AR_SREV_VERSION_9340: 589 case AR_SREV_VERSION_9340:
588 case AR_SREV_VERSION_9480: 590 case AR_SREV_VERSION_9462:
589 break; 591 break;
590 default: 592 default:
591 ath_err(common, 593 ath_err(common,
@@ -670,7 +672,7 @@ int ath9k_hw_init(struct ath_hw *ah)
670 case AR9300_DEVID_AR9330: 672 case AR9300_DEVID_AR9330:
671 case AR9300_DEVID_AR9340: 673 case AR9300_DEVID_AR9340:
672 case AR9300_DEVID_AR9580: 674 case AR9300_DEVID_AR9580:
673 case AR9300_DEVID_AR9480: 675 case AR9300_DEVID_AR9462:
674 break; 676 break;
675 default: 677 default:
676 if (common->bus_ops->ath_bus_type == ATH_USB) 678 if (common->bus_ops->ath_bus_type == ATH_USB)
@@ -1389,11 +1391,17 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1389static bool ath9k_hw_channel_change(struct ath_hw *ah, 1391static bool ath9k_hw_channel_change(struct ath_hw *ah,
1390 struct ath9k_channel *chan) 1392 struct ath9k_channel *chan)
1391{ 1393{
1392 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1393 struct ath_common *common = ath9k_hw_common(ah); 1394 struct ath_common *common = ath9k_hw_common(ah);
1394 struct ieee80211_channel *channel = chan->chan;
1395 u32 qnum; 1395 u32 qnum;
1396 int r; 1396 int r;
1397 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1398 bool band_switch, mode_diff;
1399 u8 ini_reloaded;
1400
1401 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1402 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1403 CHANNEL_5GHZ));
1404 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1397 1405
1398 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1406 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1399 if (ath9k_hw_numtxpending(ah, qnum)) { 1407 if (ath9k_hw_numtxpending(ah, qnum)) {
@@ -1408,6 +1416,18 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1408 return false; 1416 return false;
1409 } 1417 }
1410 1418
1419 if (edma && (band_switch || mode_diff)) {
1420 ath9k_hw_mark_phy_inactive(ah);
1421 udelay(5);
1422
1423 ath9k_hw_init_pll(ah, NULL);
1424
1425 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1426 ath_err(common, "Failed to do fast channel change\n");
1427 return false;
1428 }
1429 }
1430
1411 ath9k_hw_set_channel_regs(ah, chan); 1431 ath9k_hw_set_channel_regs(ah, chan);
1412 1432
1413 r = ath9k_hw_rf_set_freq(ah, chan); 1433 r = ath9k_hw_rf_set_freq(ah, chan);
@@ -1416,14 +1436,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1416 return false; 1436 return false;
1417 } 1437 }
1418 ath9k_hw_set_clockrate(ah); 1438 ath9k_hw_set_clockrate(ah);
1419 1439 ath9k_hw_apply_txpower(ah, chan);
1420 ah->eep_ops->set_txpower(ah, chan,
1421 ath9k_regd_get_ctl(regulatory, chan),
1422 channel->max_antenna_gain * 2,
1423 channel->max_power * 2,
1424 min((u32) MAX_RATE_POWER,
1425 (u32) regulatory->power_limit), false);
1426
1427 ath9k_hw_rfbus_done(ah); 1440 ath9k_hw_rfbus_done(ah);
1428 1441
1429 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1442 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
@@ -1431,6 +1444,18 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1431 1444
1432 ath9k_hw_spur_mitigate_freq(ah, chan); 1445 ath9k_hw_spur_mitigate_freq(ah, chan);
1433 1446
1447 if (edma && (band_switch || mode_diff)) {
1448 ah->ah_flags |= AH_FASTCC;
1449 if (band_switch || ini_reloaded)
1450 ah->eep_ops->set_board_values(ah, chan);
1451
1452 ath9k_hw_init_bb(ah, chan);
1453
1454 if (band_switch || ini_reloaded)
1455 ath9k_hw_init_cal(ah, chan);
1456 ah->ah_flags &= ~AH_FASTCC;
1457 }
1458
1434 return true; 1459 return true;
1435} 1460}
1436 1461
@@ -1486,6 +1511,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1486 u32 macStaId1; 1511 u32 macStaId1;
1487 u64 tsf = 0; 1512 u64 tsf = 0;
1488 int i, r; 1513 int i, r;
1514 bool allow_fbs = false;
1489 1515
1490 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1516 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1491 return -EIO; 1517 return -EIO;
@@ -1504,16 +1530,22 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1504 } 1530 }
1505 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1531 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1506 1532
1507 if ((AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) || 1533 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1508 (AR_SREV_9300_20_OR_LATER(ah) && IS_CHAN_5GHZ(chan)))
1509 bChannelChange = false; 1534 bChannelChange = false;
1510 1535
1536 if (caldata &&
1537 caldata->done_txiqcal_once &&
1538 caldata->done_txclcal_once &&
1539 caldata->rtt_hist.num_readings)
1540 allow_fbs = true;
1541
1511 if (bChannelChange && 1542 if (bChannelChange &&
1512 (ah->chip_fullsleep != true) && 1543 (ah->chip_fullsleep != true) &&
1513 (ah->curchan != NULL) && 1544 (ah->curchan != NULL) &&
1514 (chan->channel != ah->curchan->channel) && 1545 (chan->channel != ah->curchan->channel) &&
1515 ((chan->channelFlags & CHANNEL_ALL) == 1546 (allow_fbs ||
1516 (ah->curchan->channelFlags & CHANNEL_ALL))) { 1547 ((chan->channelFlags & CHANNEL_ALL) ==
1548 (ah->curchan->channelFlags & CHANNEL_ALL)))) {
1517 if (ath9k_hw_channel_change(ah, chan)) { 1549 if (ath9k_hw_channel_change(ah, chan)) {
1518 ath9k_hw_loadnf(ah, ah->curchan); 1550 ath9k_hw_loadnf(ah, ah->curchan);
1519 ath9k_hw_start_nfcal(ah, true); 1551 ath9k_hw_start_nfcal(ah, true);
@@ -1684,6 +1716,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1684 1716
1685 ath9k_hw_init_bb(ah, chan); 1717 ath9k_hw_init_bb(ah, chan);
1686 1718
1719 if (caldata) {
1720 caldata->done_txiqcal_once = false;
1721 caldata->done_txclcal_once = false;
1722 caldata->rtt_hist.num_readings = 0;
1723 }
1687 if (!ath9k_hw_init_cal(ah, chan)) 1724 if (!ath9k_hw_init_cal(ah, chan))
1688 return -EIO; 1725 return -EIO;
1689 1726
@@ -1753,7 +1790,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1753{ 1790{
1754 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1791 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1755 if (setChip) { 1792 if (setChip) {
1756 if (AR_SREV_9480(ah)) { 1793 if (AR_SREV_9462(ah)) {
1757 REG_WRITE(ah, AR_TIMER_MODE, 1794 REG_WRITE(ah, AR_TIMER_MODE,
1758 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); 1795 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1759 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, 1796 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
@@ -1771,7 +1808,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1771 */ 1808 */
1772 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1809 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1773 1810
1774 if (AR_SREV_9480(ah)) 1811 if (AR_SREV_9462(ah))
1775 udelay(100); 1812 udelay(100);
1776 1813
1777 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1814 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
@@ -1779,15 +1816,14 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1779 1816
1780 /* Shutdown chip. Active low */ 1817 /* Shutdown chip. Active low */
1781 if (!AR_SREV_5416(ah) && 1818 if (!AR_SREV_5416(ah) &&
1782 !AR_SREV_9271(ah) && !AR_SREV_9480_10(ah)) { 1819 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) {
1783 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 1820 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1784 udelay(2); 1821 udelay(2);
1785 } 1822 }
1786 } 1823 }
1787 1824
1788 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1825 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1789 if (!AR_SREV_9480(ah)) 1826 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1790 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1791} 1827}
1792 1828
1793/* 1829/*
@@ -1818,7 +1854,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1818 * SYS_WAKING and SYS_SLEEPING messages which will make 1854 * SYS_WAKING and SYS_SLEEPING messages which will make
1819 * BT CPU to busy to process. 1855 * BT CPU to busy to process.
1820 */ 1856 */
1821 if (AR_SREV_9480(ah)) { 1857 if (AR_SREV_9462(ah)) {
1822 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 1858 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
1823 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 1859 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
1824 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 1860 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
@@ -1830,7 +1866,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1830 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1866 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1831 AR_RTC_FORCE_WAKE_EN); 1867 AR_RTC_FORCE_WAKE_EN);
1832 1868
1833 if (AR_SREV_9480(ah)) 1869 if (AR_SREV_9462(ah))
1834 udelay(30); 1870 udelay(30);
1835 } 1871 }
1836 } 1872 }
@@ -2082,11 +2118,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2082 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2118 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2083 regulatory->current_rd = eeval; 2119 regulatory->current_rd = eeval;
2084 2120
2085 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2086 if (AR_SREV_9285_12_OR_LATER(ah))
2087 eeval |= AR9285_RDEXT_DEFAULT;
2088 regulatory->current_rd_ext = eeval;
2089
2090 if (ah->opmode != NL80211_IFTYPE_AP && 2121 if (ah->opmode != NL80211_IFTYPE_AP &&
2091 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2122 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2092 if (regulatory->current_rd == 0x64 || 2123 if (regulatory->current_rd == 0x64 ||
@@ -2294,6 +2325,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2294 rx_chainmask >>= 1; 2325 rx_chainmask >>= 1;
2295 } 2326 }
2296 2327
2328 if (AR_SREV_9300_20_OR_LATER(ah)) {
2329 ah->enabled_cals |= TX_IQ_CAL;
2330 if (!AR_SREV_9330(ah))
2331 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2332 }
2333 if (AR_SREV_9462(ah))
2334 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2335
2297 return 0; 2336 return 0;
2298} 2337}
2299 2338
@@ -2454,7 +2493,7 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2454 2493
2455 ENABLE_REGWRITE_BUFFER(ah); 2494 ENABLE_REGWRITE_BUFFER(ah);
2456 2495
2457 if (AR_SREV_9480(ah)) 2496 if (AR_SREV_9462(ah))
2458 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2497 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2459 2498
2460 REG_WRITE(ah, AR_RX_FILTER, bits); 2499 REG_WRITE(ah, AR_RX_FILTER, bits);
@@ -2498,23 +2537,56 @@ bool ath9k_hw_disable(struct ath_hw *ah)
2498} 2537}
2499EXPORT_SYMBOL(ath9k_hw_disable); 2538EXPORT_SYMBOL(ath9k_hw_disable);
2500 2539
2540static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2541{
2542 enum eeprom_param gain_param;
2543
2544 if (IS_CHAN_2GHZ(chan))
2545 gain_param = EEP_ANTENNA_GAIN_2G;
2546 else
2547 gain_param = EEP_ANTENNA_GAIN_5G;
2548
2549 return ah->eep_ops->get_eeprom(ah, gain_param);
2550}
2551
2552void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2553{
2554 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2555 struct ieee80211_channel *channel;
2556 int chan_pwr, new_pwr, max_gain;
2557 int ant_gain, ant_reduction = 0;
2558
2559 if (!chan)
2560 return;
2561
2562 channel = chan->chan;
2563 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2564 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2565 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2566
2567 ant_gain = get_antenna_gain(ah, chan);
2568 if (ant_gain > max_gain)
2569 ant_reduction = ant_gain - max_gain;
2570
2571 ah->eep_ops->set_txpower(ah, chan,
2572 ath9k_regd_get_ctl(reg, chan),
2573 ant_reduction, new_pwr, false);
2574}
2575
2501void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2576void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2502{ 2577{
2503 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2578 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2504 struct ath9k_channel *chan = ah->curchan; 2579 struct ath9k_channel *chan = ah->curchan;
2505 struct ieee80211_channel *channel = chan->chan; 2580 struct ieee80211_channel *channel = chan->chan;
2506 int reg_pwr = min_t(int, MAX_RATE_POWER, limit);
2507 int chan_pwr = channel->max_power * 2;
2508 2581
2582 reg->power_limit = min_t(int, limit, MAX_RATE_POWER);
2509 if (test) 2583 if (test)
2510 reg_pwr = chan_pwr = MAX_RATE_POWER; 2584 channel->max_power = MAX_RATE_POWER / 2;
2511 2585
2512 regulatory->power_limit = reg_pwr; 2586 ath9k_hw_apply_txpower(ah, chan);
2513 2587
2514 ah->eep_ops->set_txpower(ah, chan, 2588 if (test)
2515 ath9k_regd_get_ctl(regulatory, chan), 2589 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2516 channel->max_antenna_gain * 2,
2517 chan_pwr, reg_pwr, test);
2518} 2590}
2519EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2591EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2520 2592
@@ -2713,9 +2785,9 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2713 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2785 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2714 gen_tmr_configuration[timer->index].mode_mask); 2786 gen_tmr_configuration[timer->index].mode_mask);
2715 2787
2716 if (AR_SREV_9480(ah)) { 2788 if (AR_SREV_9462(ah)) {
2717 /* 2789 /*
2718 * Starting from AR9480, each generic timer can select which tsf 2790 * Starting from AR9462, each generic timer can select which tsf
2719 * to use. But we still follow the old rule, 0 - 7 use tsf and 2791 * to use. But we still follow the old rule, 0 - 7 use tsf and
2720 * 8 - 15 use tsf2. 2792 * 8 - 15 use tsf2.
2721 */ 2793 */
@@ -2832,7 +2904,7 @@ static struct {
2832 { AR_SREV_VERSION_9330, "9330" }, 2904 { AR_SREV_VERSION_9330, "9330" },
2833 { AR_SREV_VERSION_9340, "9340" }, 2905 { AR_SREV_VERSION_9340, "9340" },
2834 { AR_SREV_VERSION_9485, "9485" }, 2906 { AR_SREV_VERSION_9485, "9485" },
2835 { AR_SREV_VERSION_9480, "9480" }, 2907 { AR_SREV_VERSION_9462, "9462" },
2836}; 2908};
2837 2909
2838/* For devices with external radios */ 2910/* For devices with external radios */
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 24889f78a053..f389b3c93cf3 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -46,7 +46,7 @@
46#define AR9300_DEVID_AR9340 0x0031 46#define AR9300_DEVID_AR9340 0x0031
47#define AR9300_DEVID_AR9485_PCIE 0x0032 47#define AR9300_DEVID_AR9485_PCIE 0x0032
48#define AR9300_DEVID_AR9580 0x0033 48#define AR9300_DEVID_AR9580 0x0033
49#define AR9300_DEVID_AR9480 0x0034 49#define AR9300_DEVID_AR9462 0x0034
50#define AR9300_DEVID_AR9330 0x0035 50#define AR9300_DEVID_AR9330 0x0035
51 51
52#define AR5416_AR9100_DEVID 0x000b 52#define AR5416_AR9100_DEVID 0x000b
@@ -202,6 +202,7 @@ enum ath9k_hw_caps {
202 ATH9K_HW_CAP_2GHZ = BIT(13), 202 ATH9K_HW_CAP_2GHZ = BIT(13),
203 ATH9K_HW_CAP_5GHZ = BIT(14), 203 ATH9K_HW_CAP_5GHZ = BIT(14),
204 ATH9K_HW_CAP_APM = BIT(15), 204 ATH9K_HW_CAP_APM = BIT(15),
205 ATH9K_HW_CAP_RTT = BIT(16),
205}; 206};
206 207
207struct ath9k_hw_capabilities { 208struct ath9k_hw_capabilities {
@@ -337,6 +338,16 @@ enum ath9k_int {
337 CHANNEL_HT40PLUS | \ 338 CHANNEL_HT40PLUS | \
338 CHANNEL_HT40MINUS) 339 CHANNEL_HT40MINUS)
339 340
341#define MAX_RTT_TABLE_ENTRY 6
342#define RTT_HIST_MAX 3
343struct ath9k_rtt_hist {
344 u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
345 u8 num_readings;
346};
347
348#define MAX_IQCAL_MEASUREMENT 8
349#define MAX_CL_TAB_ENTRY 16
350
340struct ath9k_hw_cal_data { 351struct ath9k_hw_cal_data {
341 u16 channel; 352 u16 channel;
342 u32 channelFlags; 353 u32 channelFlags;
@@ -346,9 +357,15 @@ struct ath9k_hw_cal_data {
346 bool paprd_done; 357 bool paprd_done;
347 bool nfcal_pending; 358 bool nfcal_pending;
348 bool nfcal_interference; 359 bool nfcal_interference;
360 bool done_txiqcal_once;
361 bool done_txclcal_once;
349 u16 small_signal_gain[AR9300_MAX_CHAINS]; 362 u16 small_signal_gain[AR9300_MAX_CHAINS];
350 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 363 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
364 u32 num_measures[AR9300_MAX_CHAINS];
365 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
366 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
351 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 367 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
368 struct ath9k_rtt_hist rtt_hist;
352}; 369};
353 370
354struct ath9k_channel { 371struct ath9k_channel {
@@ -390,14 +407,6 @@ enum ath9k_power_mode {
390 ATH9K_PM_UNDEFINED 407 ATH9K_PM_UNDEFINED
391}; 408};
392 409
393enum ath9k_tp_scale {
394 ATH9K_TP_SCALE_MAX = 0,
395 ATH9K_TP_SCALE_50,
396 ATH9K_TP_SCALE_25,
397 ATH9K_TP_SCALE_12,
398 ATH9K_TP_SCALE_MIN
399};
400
401enum ser_reg_mode { 410enum ser_reg_mode {
402 SER_REG_MODE_OFF = 0, 411 SER_REG_MODE_OFF = 0,
403 SER_REG_MODE_ON = 1, 412 SER_REG_MODE_ON = 1,
@@ -591,6 +600,8 @@ struct ath_hw_private_ops {
591 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 600 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
592 void (*set_radar_params)(struct ath_hw *ah, 601 void (*set_radar_params)(struct ath_hw *ah,
593 struct ath_hw_radar_conf *conf); 602 struct ath_hw_radar_conf *conf);
603 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
604 u8 *ini_reloaded);
594 605
595 /* ANI */ 606 /* ANI */
596 void (*ani_cache_ini_regs)(struct ath_hw *ah); 607 void (*ani_cache_ini_regs)(struct ath_hw *ah);
@@ -632,9 +643,16 @@ struct ath_nf_limits {
632 s16 nominal; 643 s16 nominal;
633}; 644};
634 645
646enum ath_cal_list {
647 TX_IQ_CAL = BIT(0),
648 TX_IQ_ON_AGC_CAL = BIT(1),
649 TX_CL_CAL = BIT(2),
650};
651
635/* ah_flags */ 652/* ah_flags */
636#define AH_USE_EEPROM 0x1 653#define AH_USE_EEPROM 0x1
637#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 654#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
655#define AH_FASTCC 0x4
638 656
639struct ath_hw { 657struct ath_hw {
640 struct ath_ops reg_ops; 658 struct ath_ops reg_ops;
@@ -692,6 +710,7 @@ struct ath_hw {
692 atomic_t intr_ref_cnt; 710 atomic_t intr_ref_cnt;
693 bool chip_fullsleep; 711 bool chip_fullsleep;
694 u32 atim_window; 712 u32 atim_window;
713 u32 modes_index;
695 714
696 /* Calibration */ 715 /* Calibration */
697 u32 supp_cals; 716 u32 supp_cals;
@@ -730,6 +749,7 @@ struct ath_hw {
730 int32_t sign[AR5416_MAX_CHAINS]; 749 int32_t sign[AR5416_MAX_CHAINS];
731 } meas3; 750 } meas3;
732 u16 cal_samples; 751 u16 cal_samples;
752 u8 enabled_cals;
733 753
734 u32 sta_id1_defaults; 754 u32 sta_id1_defaults;
735 u32 misc_mode; 755 u32 misc_mode;
@@ -968,6 +988,7 @@ void ath9k_hw_htc_resetinit(struct ath_hw *ah);
968/* PHY */ 988/* PHY */
969void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 989void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
970 u32 *coef_mantissa, u32 *coef_exponent); 990 u32 *coef_mantissa, u32 *coef_exponent);
991void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
971 992
972/* 993/*
973 * Code Specific to AR5008, AR9001 or AR9002, 994 * Code Specific to AR5008, AR9001 or AR9002,
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 39514de044ef..af1b32549531 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -626,7 +626,6 @@ static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
626 struct ieee80211_supported_band *sband; 626 struct ieee80211_supported_band *sband;
627 struct ieee80211_channel *chan; 627 struct ieee80211_channel *chan;
628 struct ath_hw *ah = sc->sc_ah; 628 struct ath_hw *ah = sc->sc_ah;
629 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
630 int i; 629 int i;
631 630
632 sband = &sc->sbands[band]; 631 sband = &sc->sbands[band];
@@ -635,7 +634,6 @@ static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
635 ah->curchan = &ah->channels[chan->hw_value]; 634 ah->curchan = &ah->channels[chan->hw_value];
636 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); 635 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
637 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 636 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
638 chan->max_power = reg->max_power_level / 2;
639 } 637 }
640} 638}
641 639
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 22f23eafe8ba..6a8fdf33a527 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -620,8 +620,8 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
620 rs->rs_status |= ATH9K_RXERR_DECRYPT; 620 rs->rs_status |= ATH9K_RXERR_DECRYPT;
621 else if (ads.ds_rxstatus8 & AR_MichaelErr) 621 else if (ads.ds_rxstatus8 & AR_MichaelErr)
622 rs->rs_status |= ATH9K_RXERR_MIC; 622 rs->rs_status |= ATH9K_RXERR_MIC;
623 else if (ads.ds_rxstatus8 & AR_KeyMiss) 623 if (ads.ds_rxstatus8 & AR_KeyMiss)
624 rs->rs_status |= ATH9K_RXERR_DECRYPT; 624 rs->rs_status |= ATH9K_RXERR_KEYMISS;
625 } 625 }
626 626
627 return 0; 627 return 0;
@@ -827,9 +827,9 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
827} 827}
828EXPORT_SYMBOL(ath9k_hw_enable_interrupts); 828EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
829 829
830void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) 830void ath9k_hw_set_interrupts(struct ath_hw *ah)
831{ 831{
832 enum ath9k_int omask = ah->imask; 832 enum ath9k_int ints = ah->imask;
833 u32 mask, mask2; 833 u32 mask, mask2;
834 struct ath9k_hw_capabilities *pCap = &ah->caps; 834 struct ath9k_hw_capabilities *pCap = &ah->caps;
835 struct ath_common *common = ath9k_hw_common(ah); 835 struct ath_common *common = ath9k_hw_common(ah);
@@ -837,7 +837,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
837 if (!(ints & ATH9K_INT_GLOBAL)) 837 if (!(ints & ATH9K_INT_GLOBAL))
838 ath9k_hw_disable_interrupts(ah); 838 ath9k_hw_disable_interrupts(ah);
839 839
840 ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 840 ath_dbg(common, ATH_DBG_INTERRUPT, "New interrupt mask 0x%x\n", ints);
841 841
842 mask = ints & ATH9K_INT_COMMON; 842 mask = ints & ATH9K_INT_COMMON;
843 mask2 = 0; 843 mask2 = 0;
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 91c96546c0cd..11dbd1473a13 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -75,9 +75,10 @@
75#define ATH9K_TXERR_XTXOP 0x08 75#define ATH9K_TXERR_XTXOP 0x08
76#define ATH9K_TXERR_TIMER_EXPIRED 0x10 76#define ATH9K_TXERR_TIMER_EXPIRED 0x10
77#define ATH9K_TX_ACKED 0x20 77#define ATH9K_TX_ACKED 0x20
78#define ATH9K_TX_FLUSH 0x40
78#define ATH9K_TXERR_MASK \ 79#define ATH9K_TXERR_MASK \
79 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \ 80 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
80 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED) 81 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED | ATH9K_TX_FLUSH)
81 82
82#define ATH9K_TX_BA 0x01 83#define ATH9K_TX_BA 0x01
83#define ATH9K_TX_PWRMGMT 0x02 84#define ATH9K_TX_PWRMGMT 0x02
@@ -181,6 +182,7 @@ struct ath_htc_rx_status {
181#define ATH9K_RXERR_FIFO 0x04 182#define ATH9K_RXERR_FIFO 0x04
182#define ATH9K_RXERR_DECRYPT 0x08 183#define ATH9K_RXERR_DECRYPT 0x08
183#define ATH9K_RXERR_MIC 0x10 184#define ATH9K_RXERR_MIC 0x10
185#define ATH9K_RXERR_KEYMISS 0x20
184 186
185#define ATH9K_RX_MORE 0x01 187#define ATH9K_RX_MORE 0x01
186#define ATH9K_RX_MORE_AGGR 0x02 188#define ATH9K_RX_MORE_AGGR 0x02
@@ -734,7 +736,7 @@ int ath9k_hw_beaconq_setup(struct ath_hw *ah);
734 736
735/* Interrupt Handling */ 737/* Interrupt Handling */
736bool ath9k_hw_intrpend(struct ath_hw *ah); 738bool ath9k_hw_intrpend(struct ath_hw *ah);
737void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints); 739void ath9k_hw_set_interrupts(struct ath_hw *ah);
738void ath9k_hw_enable_interrupts(struct ath_hw *ah); 740void ath9k_hw_enable_interrupts(struct ath_hw *ah);
739void ath9k_hw_disable_interrupts(struct ath_hw *ah); 741void ath9k_hw_disable_interrupts(struct ath_hw *ah);
740 742
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 988318665758..93fbe6f40898 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -273,7 +273,7 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start)
273 273
274 ath9k_cmn_update_txpow(ah, sc->curtxpow, 274 ath9k_cmn_update_txpow(ah, sc->curtxpow,
275 sc->config.txpowlimit, &sc->curtxpow); 275 sc->config.txpowlimit, &sc->curtxpow);
276 ath9k_hw_set_interrupts(ah, ah->imask); 276 ath9k_hw_set_interrupts(ah);
277 ath9k_hw_enable_interrupts(ah); 277 ath9k_hw_enable_interrupts(ah);
278 278
279 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) { 279 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
@@ -679,6 +679,16 @@ void ath9k_tasklet(unsigned long data)
679 679
680 if ((status & ATH9K_INT_FATAL) || 680 if ((status & ATH9K_INT_FATAL) ||
681 (status & ATH9K_INT_BB_WATCHDOG)) { 681 (status & ATH9K_INT_BB_WATCHDOG)) {
682#ifdef CONFIG_ATH9K_DEBUGFS
683 enum ath_reset_type type;
684
685 if (status & ATH9K_INT_FATAL)
686 type = RESET_TYPE_FATAL_INT;
687 else
688 type = RESET_TYPE_BB_WATCHDOG;
689
690 RESET_STAT_INC(sc, type);
691#endif
682 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 692 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
683 goto out; 693 goto out;
684 } 694 }
@@ -823,7 +833,7 @@ irqreturn_t ath_isr(int irq, void *dev)
823 833
824 if (status & ATH9K_INT_RXEOL) { 834 if (status & ATH9K_INT_RXEOL) {
825 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 835 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
826 ath9k_hw_set_interrupts(ah, ah->imask); 836 ath9k_hw_set_interrupts(ah);
827 } 837 }
828 838
829 if (status & ATH9K_INT_MIB) { 839 if (status & ATH9K_INT_MIB) {
@@ -995,8 +1005,10 @@ void ath_hw_check(struct work_struct *work)
995 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " 1005 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
996 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); 1006 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
997 if (busy >= 99) { 1007 if (busy >= 99) {
998 if (++sc->hw_busy_count >= 3) 1008 if (++sc->hw_busy_count >= 3) {
1009 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
999 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 1010 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
1011 }
1000 1012
1001 } else if (busy >= 0) 1013 } else if (busy >= 0)
1002 sc->hw_busy_count = 0; 1014 sc->hw_busy_count = 0;
@@ -1016,6 +1028,7 @@ static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
1016 /* Rx is hung for more than 500ms. Reset it */ 1028 /* Rx is hung for more than 500ms. Reset it */
1017 ath_dbg(common, ATH_DBG_RESET, 1029 ath_dbg(common, ATH_DBG_RESET,
1018 "Possible RX hang, resetting"); 1030 "Possible RX hang, resetting");
1031 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
1019 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 1032 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
1020 count = 0; 1033 count = 0;
1021 } 1034 }
@@ -1396,7 +1409,7 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1396 ah->imask &= ~ATH9K_INT_TSFOOR; 1409 ah->imask &= ~ATH9K_INT_TSFOOR;
1397 } 1410 }
1398 1411
1399 ath9k_hw_set_interrupts(ah, ah->imask); 1412 ath9k_hw_set_interrupts(ah);
1400 1413
1401 /* Set up ANI */ 1414 /* Set up ANI */
1402 if (iter_data.naps > 0) { 1415 if (iter_data.naps > 0) {
@@ -1571,7 +1584,7 @@ static void ath9k_enable_ps(struct ath_softc *sc)
1571 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1584 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1572 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1585 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1573 ah->imask |= ATH9K_INT_TIM_TIMER; 1586 ah->imask |= ATH9K_INT_TIM_TIMER;
1574 ath9k_hw_set_interrupts(ah, ah->imask); 1587 ath9k_hw_set_interrupts(ah);
1575 } 1588 }
1576 ath9k_hw_setrxabort(ah, 1); 1589 ath9k_hw_setrxabort(ah, 1);
1577 } 1590 }
@@ -1591,7 +1604,7 @@ static void ath9k_disable_ps(struct ath_softc *sc)
1591 PS_WAIT_FOR_TX_ACK); 1604 PS_WAIT_FOR_TX_ACK);
1592 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1605 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1593 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1606 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1594 ath9k_hw_set_interrupts(ah, ah->imask); 1607 ath9k_hw_set_interrupts(ah);
1595 } 1608 }
1596 } 1609 }
1597 1610
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index d67d6eee3954..edb0b4b3da3a 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -33,7 +33,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
33 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 33 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
34 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 34 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
35 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 35 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
36 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9480 */ 36 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
37 { 0 } 37 { 0 }
38}; 38};
39 39
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index f658ec60b510..67b862cdae6d 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -433,12 +433,9 @@ void ath_rx_cleanup(struct ath_softc *sc)
433 433
434u32 ath_calcrxfilter(struct ath_softc *sc) 434u32 ath_calcrxfilter(struct ath_softc *sc)
435{ 435{
436#define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
437
438 u32 rfilt; 436 u32 rfilt;
439 437
440 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) 438 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
441 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
442 | ATH9K_RX_FILTER_MCAST; 439 | ATH9K_RX_FILTER_MCAST;
443 440
444 if (sc->rx.rxfilter & FIF_PROBE_REQ) 441 if (sc->rx.rxfilter & FIF_PROBE_REQ)
@@ -811,6 +808,7 @@ static bool ath9k_rx_accept(struct ath_common *common,
811 struct ath_rx_status *rx_stats, 808 struct ath_rx_status *rx_stats,
812 bool *decrypt_error) 809 bool *decrypt_error)
813{ 810{
811 struct ath_softc *sc = (struct ath_softc *) common->priv;
814 bool is_mc, is_valid_tkip, strip_mic, mic_error; 812 bool is_mc, is_valid_tkip, strip_mic, mic_error;
815 struct ath_hw *ah = common->ah; 813 struct ath_hw *ah = common->ah;
816 __le16 fc; 814 __le16 fc;
@@ -823,7 +821,8 @@ static bool ath9k_rx_accept(struct ath_common *common,
823 test_bit(rx_stats->rs_keyix, common->tkip_keymap); 821 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
824 strip_mic = is_valid_tkip && ieee80211_is_data(fc) && 822 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
825 !(rx_stats->rs_status & 823 !(rx_stats->rs_status &
826 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC)); 824 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
825 ATH9K_RXERR_KEYMISS));
827 826
828 if (!rx_stats->rs_datalen) 827 if (!rx_stats->rs_datalen)
829 return false; 828 return false;
@@ -851,6 +850,8 @@ static bool ath9k_rx_accept(struct ath_common *common,
851 * descriptors. 850 * descriptors.
852 */ 851 */
853 if (rx_stats->rs_status != 0) { 852 if (rx_stats->rs_status != 0) {
853 u8 status_mask;
854
854 if (rx_stats->rs_status & ATH9K_RXERR_CRC) { 855 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
855 rxs->flag |= RX_FLAG_FAILED_FCS_CRC; 856 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
856 mic_error = false; 857 mic_error = false;
@@ -858,7 +859,8 @@ static bool ath9k_rx_accept(struct ath_common *common,
858 if (rx_stats->rs_status & ATH9K_RXERR_PHY) 859 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
859 return false; 860 return false;
860 861
861 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { 862 if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
863 (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
862 *decrypt_error = true; 864 *decrypt_error = true;
863 mic_error = false; 865 mic_error = false;
864 } 866 }
@@ -868,17 +870,14 @@ static bool ath9k_rx_accept(struct ath_common *common,
868 * decryption and MIC failures. For monitor mode, 870 * decryption and MIC failures. For monitor mode,
869 * we also ignore the CRC error. 871 * we also ignore the CRC error.
870 */ 872 */
871 if (ah->is_monitoring) { 873 status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
872 if (rx_stats->rs_status & 874 ATH9K_RXERR_KEYMISS;
873 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | 875
874 ATH9K_RXERR_CRC)) 876 if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
875 return false; 877 status_mask |= ATH9K_RXERR_CRC;
876 } else { 878
877 if (rx_stats->rs_status & 879 if (rx_stats->rs_status & ~status_mask)
878 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { 880 return false;
879 return false;
880 }
881 }
882 } 881 }
883 882
884 /* 883 /*
@@ -1973,7 +1972,7 @@ requeue:
1973 1972
1974 if (!(ah->imask & ATH9K_INT_RXEOL)) { 1973 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1975 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 1974 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1976 ath9k_hw_set_interrupts(ah, ah->imask); 1975 ath9k_hw_set_interrupts(ah);
1977 } 1976 }
1978 1977
1979 return 0; 1978 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index b76c49d9c503..8fcb7e9e8399 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -796,9 +796,9 @@
796#define AR_SREV_VERSION_9340 0x300 796#define AR_SREV_VERSION_9340 0x300
797#define AR_SREV_VERSION_9580 0x1C0 797#define AR_SREV_VERSION_9580 0x1C0
798#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ 798#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
799#define AR_SREV_VERSION_9480 0x280 799#define AR_SREV_VERSION_9462 0x280
800#define AR_SREV_REVISION_9480_10 0 800#define AR_SREV_REVISION_9462_10 0
801#define AR_SREV_REVISION_9480_20 2 801#define AR_SREV_REVISION_9462_20 2
802 802
803#define AR_SREV_5416(_ah) \ 803#define AR_SREV_5416(_ah) \
804 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 804 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -895,20 +895,20 @@
895 (AR_SREV_9285_12_OR_LATER(_ah) && \ 895 (AR_SREV_9285_12_OR_LATER(_ah) && \
896 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 896 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
897 897
898#define AR_SREV_9480(_ah) \ 898#define AR_SREV_9462(_ah) \
899 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480)) 899 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462))
900 900
901#define AR_SREV_9480_10(_ah) \ 901#define AR_SREV_9462_10(_ah) \
902 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ 902 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
903 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_10)) 903 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_10))
904 904
905#define AR_SREV_9480_20(_ah) \ 905#define AR_SREV_9462_20(_ah) \
906 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ 906 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
907 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_20)) 907 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_20))
908 908
909#define AR_SREV_9480_20_OR_LATER(_ah) \ 909#define AR_SREV_9462_20_OR_LATER(_ah) \
910 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ 910 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
911 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9480_20)) 911 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20))
912 912
913#define AR_SREV_9580(_ah) \ 913#define AR_SREV_9580(_ah) \
914 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ 914 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
@@ -1933,6 +1933,7 @@ enum {
1933#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ 1933#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
1934#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ 1934#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
1935#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ 1935#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
1936#define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000
1936#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 1937#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
1937#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 1938#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
1938 1939
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index c2bfc57958d8..03b0a651a591 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -373,7 +373,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
373 struct ath_frame_info *fi; 373 struct ath_frame_info *fi;
374 int nframes; 374 int nframes;
375 u8 tidno; 375 u8 tidno;
376 bool clear_filter; 376 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
377 377
378 skb = bf->bf_mpdu; 378 skb = bf->bf_mpdu;
379 hdr = (struct ieee80211_hdr *)skb->data; 379 hdr = (struct ieee80211_hdr *)skb->data;
@@ -462,12 +462,12 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
462 * the un-acked sub-frames 462 * the un-acked sub-frames
463 */ 463 */
464 txfail = 1; 464 txfail = 1;
465 } else if (flush) {
466 txpending = 1;
465 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 467 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
466 if (!(ts->ts_status & ATH9K_TXERR_FILT) || 468 if (txok || !an->sleeping)
467 !an->sleeping)
468 ath_tx_set_retry(sc, txq, bf->bf_mpdu); 469 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
469 470
470 clear_filter = true;
471 txpending = 1; 471 txpending = 1;
472 } else { 472 } else {
473 txfail = 1; 473 txfail = 1;
@@ -521,7 +521,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
521 521
522 ath_tx_complete_buf(sc, bf, txq, 522 ath_tx_complete_buf(sc, bf, txq,
523 &bf_head, 523 &bf_head,
524 ts, 0, 1); 524 ts, 0,
525 !flush);
525 break; 526 break;
526 } 527 }
527 528
@@ -545,11 +546,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
545 ieee80211_sta_set_buffered(sta, tid->tidno, true); 546 ieee80211_sta_set_buffered(sta, tid->tidno, true);
546 547
547 spin_lock_bh(&txq->axq_lock); 548 spin_lock_bh(&txq->axq_lock);
548 if (clear_filter)
549 tid->ac->clear_ps_filter = true;
550 skb_queue_splice(&bf_pending, &tid->buf_q); 549 skb_queue_splice(&bf_pending, &tid->buf_q);
551 if (!an->sleeping) 550 if (!an->sleeping) {
552 ath_tx_queue_tid(txq, tid); 551 ath_tx_queue_tid(txq, tid);
552
553 if (ts->ts_status & ATH9K_TXERR_FILT)
554 tid->ac->clear_ps_filter = true;
555 }
553 spin_unlock_bh(&txq->axq_lock); 556 spin_unlock_bh(&txq->axq_lock);
554 } 557 }
555 558
@@ -564,8 +567,10 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
564 567
565 rcu_read_unlock(); 568 rcu_read_unlock();
566 569
567 if (needreset) 570 if (needreset) {
571 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
568 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 572 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
573 }
569} 574}
570 575
571static bool ath_lookup_legacy(struct ath_buf *bf) 576static bool ath_lookup_legacy(struct ath_buf *bf)
@@ -1255,7 +1260,6 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1255struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1260struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1256{ 1261{
1257 struct ath_hw *ah = sc->sc_ah; 1262 struct ath_hw *ah = sc->sc_ah;
1258 struct ath_common *common = ath9k_hw_common(ah);
1259 struct ath9k_tx_queue_info qi; 1263 struct ath9k_tx_queue_info qi;
1260 static const int subtype_txq_to_hwq[] = { 1264 static const int subtype_txq_to_hwq[] = {
1261 [WME_AC_BE] = ATH_TXQ_AC_BE, 1265 [WME_AC_BE] = ATH_TXQ_AC_BE,
@@ -1305,12 +1309,6 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1305 */ 1309 */
1306 return NULL; 1310 return NULL;
1307 } 1311 }
1308 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1309 ath_err(common, "qnum %u out of range, max %zu!\n",
1310 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1311 ath9k_hw_releasetxqueue(ah, axq_qnum);
1312 return NULL;
1313 }
1314 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1312 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1315 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1313 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1316 1314
@@ -1407,6 +1405,7 @@ static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1407 struct ath_tx_status ts; 1405 struct ath_tx_status ts;
1408 1406
1409 memset(&ts, 0, sizeof(ts)); 1407 memset(&ts, 0, sizeof(ts));
1408 ts.ts_status = ATH9K_TX_FLUSH;
1410 INIT_LIST_HEAD(&bf_head); 1409 INIT_LIST_HEAD(&bf_head);
1411 1410
1412 while (!list_empty(list)) { 1411 while (!list_empty(list)) {
@@ -1473,7 +1472,8 @@ bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1473 struct ath_hw *ah = sc->sc_ah; 1472 struct ath_hw *ah = sc->sc_ah;
1474 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1473 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1475 struct ath_txq *txq; 1474 struct ath_txq *txq;
1476 int i, npend = 0; 1475 int i;
1476 u32 npend = 0;
1477 1477
1478 if (sc->sc_flags & SC_OP_INVALID) 1478 if (sc->sc_flags & SC_OP_INVALID)
1479 return true; 1479 return true;
@@ -1485,11 +1485,12 @@ bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1485 if (!ATH_TXQ_SETUP(sc, i)) 1485 if (!ATH_TXQ_SETUP(sc, i))
1486 continue; 1486 continue;
1487 1487
1488 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum); 1488 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1489 npend |= BIT(i);
1489 } 1490 }
1490 1491
1491 if (npend) 1492 if (npend)
1492 ath_err(common, "Failed to stop TX DMA!\n"); 1493 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1493 1494
1494 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1495 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1495 if (!ATH_TXQ_SETUP(sc, i)) 1496 if (!ATH_TXQ_SETUP(sc, i))
@@ -2211,6 +2212,7 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2211 if (needreset) { 2212 if (needreset) {
2212 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, 2213 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2213 "tx hung, resetting the chip\n"); 2214 "tx hung, resetting the chip\n");
2215 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2214 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 2216 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2215 } 2217 }
2216 2218
diff --git a/drivers/net/wireless/ath/carl9170/main.c b/drivers/net/wireless/ath/carl9170/main.c
index beca71073e9b..f06e0695d412 100644
--- a/drivers/net/wireless/ath/carl9170/main.c
+++ b/drivers/net/wireless/ath/carl9170/main.c
@@ -1896,7 +1896,6 @@ static int carl9170_parse_eeprom(struct ar9170 *ar)
1896 ar->hw->channel_change_time = 80 * 1000; 1896 ar->hw->channel_change_time = 80 * 1000;
1897 1897
1898 regulatory->current_rd = le16_to_cpu(ar->eeprom.reg_domain[0]); 1898 regulatory->current_rd = le16_to_cpu(ar->eeprom.reg_domain[0]);
1899 regulatory->current_rd_ext = le16_to_cpu(ar->eeprom.reg_domain[1]);
1900 1899
1901 /* second part of wiphy init */ 1900 /* second part of wiphy init */
1902 SET_IEEE80211_PERM_ADDR(ar->hw, ar->eeprom.mac_address); 1901 SET_IEEE80211_PERM_ADDR(ar->hw, ar->eeprom.mac_address);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-05 06:09:21 -0500