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path: root/drivers/net/wireless/ath9k/ani.c
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Diffstat (limited to 'drivers/net/wireless/ath9k/ani.c')
-rw-r--r--drivers/net/wireless/ath9k/ani.c263
1 files changed, 120 insertions, 143 deletions
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c
index 42197fff2a47..d4df7e611df5 100644
--- a/drivers/net/wireless/ath9k/ani.c
+++ b/drivers/net/wireless/ath9k/ani.c
@@ -14,23 +14,19 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21 18
22static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, 19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
23 struct ath9k_channel *chan) 20 struct ath9k_channel *chan)
24{ 21{
25 struct ath_hal_5416 *ahp = AH5416(ah);
26 int i; 22 int i;
27 23
28 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { 24 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
29 if (ahp->ah_ani[i].c.channel == chan->channel) 25 if (ah->ani[i].c &&
26 ah->ani[i].c->channel == chan->channel)
30 return i; 27 return i;
31 if (ahp->ah_ani[i].c.channel == 0) { 28 if (ah->ani[i].c == NULL) {
32 ahp->ah_ani[i].c.channel = chan->channel; 29 ah->ani[i].c = chan;
33 ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
34 return i; 30 return i;
35 } 31 }
36 } 32 }
@@ -41,41 +37,40 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
41 return 0; 37 return 0;
42} 38}
43 39
44static bool ath9k_hw_ani_control(struct ath_hal *ah, 40static bool ath9k_hw_ani_control(struct ath_hw *ah,
45 enum ath9k_ani_cmd cmd, int param) 41 enum ath9k_ani_cmd cmd, int param)
46{ 42{
47 struct ath_hal_5416 *ahp = AH5416(ah); 43 struct ar5416AniState *aniState = ah->curani;
48 struct ar5416AniState *aniState = ahp->ah_curani;
49 44
50 switch (cmd & ahp->ah_ani_function) { 45 switch (cmd & ah->ani_function) {
51 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 46 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
52 u32 level = param; 47 u32 level = param;
53 48
54 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { 49 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
55 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 50 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
56 "level out of range (%u > %u)\n", 51 "level out of range (%u > %u)\n",
57 level, 52 level,
58 (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); 53 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
59 return false; 54 return false;
60 } 55 }
61 56
62 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 57 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
63 AR_PHY_DESIRED_SZ_TOT_DES, 58 AR_PHY_DESIRED_SZ_TOT_DES,
64 ahp->ah_totalSizeDesired[level]); 59 ah->totalSizeDesired[level]);
65 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 60 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
66 AR_PHY_AGC_CTL1_COARSE_LOW, 61 AR_PHY_AGC_CTL1_COARSE_LOW,
67 ahp->ah_coarseLow[level]); 62 ah->coarse_low[level]);
68 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 63 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
69 AR_PHY_AGC_CTL1_COARSE_HIGH, 64 AR_PHY_AGC_CTL1_COARSE_HIGH,
70 ahp->ah_coarseHigh[level]); 65 ah->coarse_high[level]);
71 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 66 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
72 AR_PHY_FIND_SIG_FIRPWR, 67 AR_PHY_FIND_SIG_FIRPWR,
73 ahp->ah_firpwr[level]); 68 ah->firpwr[level]);
74 69
75 if (level > aniState->noiseImmunityLevel) 70 if (level > aniState->noiseImmunityLevel)
76 ahp->ah_stats.ast_ani_niup++; 71 ah->stats.ast_ani_niup++;
77 else if (level < aniState->noiseImmunityLevel) 72 else if (level < aniState->noiseImmunityLevel)
78 ahp->ah_stats.ast_ani_nidown++; 73 ah->stats.ast_ani_nidown++;
79 aniState->noiseImmunityLevel = level; 74 aniState->noiseImmunityLevel = level;
80 break; 75 break;
81 } 76 }
@@ -129,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
129 124
130 if (!on != aniState->ofdmWeakSigDetectOff) { 125 if (!on != aniState->ofdmWeakSigDetectOff) {
131 if (on) 126 if (on)
132 ahp->ah_stats.ast_ani_ofdmon++; 127 ah->stats.ast_ani_ofdmon++;
133 else 128 else
134 ahp->ah_stats.ast_ani_ofdmoff++; 129 ah->stats.ast_ani_ofdmoff++;
135 aniState->ofdmWeakSigDetectOff = !on; 130 aniState->ofdmWeakSigDetectOff = !on;
136 } 131 }
137 break; 132 break;
@@ -145,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
145 weakSigThrCck[high]); 140 weakSigThrCck[high]);
146 if (high != aniState->cckWeakSigThreshold) { 141 if (high != aniState->cckWeakSigThreshold) {
147 if (high) 142 if (high)
148 ahp->ah_stats.ast_ani_cckhigh++; 143 ah->stats.ast_ani_cckhigh++;
149 else 144 else
150 ahp->ah_stats.ast_ani_ccklow++; 145 ah->stats.ast_ani_ccklow++;
151 aniState->cckWeakSigThreshold = high; 146 aniState->cckWeakSigThreshold = high;
152 } 147 }
153 break; 148 break;
@@ -167,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
167 AR_PHY_FIND_SIG_FIRSTEP, 162 AR_PHY_FIND_SIG_FIRSTEP,
168 firstep[level]); 163 firstep[level]);
169 if (level > aniState->firstepLevel) 164 if (level > aniState->firstepLevel)
170 ahp->ah_stats.ast_ani_stepup++; 165 ah->stats.ast_ani_stepup++;
171 else if (level < aniState->firstepLevel) 166 else if (level < aniState->firstepLevel)
172 ahp->ah_stats.ast_ani_stepdown++; 167 ah->stats.ast_ani_stepdown++;
173 aniState->firstepLevel = level; 168 aniState->firstepLevel = level;
174 break; 169 break;
175 } 170 }
@@ -190,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
190 AR_PHY_TIMING5_CYCPWR_THR1, 185 AR_PHY_TIMING5_CYCPWR_THR1,
191 cycpwrThr1[level]); 186 cycpwrThr1[level]);
192 if (level > aniState->spurImmunityLevel) 187 if (level > aniState->spurImmunityLevel)
193 ahp->ah_stats.ast_ani_spurup++; 188 ah->stats.ast_ani_spurup++;
194 else if (level < aniState->spurImmunityLevel) 189 else if (level < aniState->spurImmunityLevel)
195 ahp->ah_stats.ast_ani_spurdown++; 190 ah->stats.ast_ani_spurdown++;
196 aniState->spurImmunityLevel = level; 191 aniState->spurImmunityLevel = level;
197 break; 192 break;
198 } 193 }
@@ -223,7 +218,7 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
223 return true; 218 return true;
224} 219}
225 220
226static void ath9k_hw_update_mibstats(struct ath_hal *ah, 221static void ath9k_hw_update_mibstats(struct ath_hw *ah,
227 struct ath9k_mib_stats *stats) 222 struct ath9k_mib_stats *stats)
228{ 223{
229 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); 224 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
@@ -233,18 +228,17 @@ static void ath9k_hw_update_mibstats(struct ath_hal *ah,
233 stats->beacons += REG_READ(ah, AR_BEACON_CNT); 228 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
234} 229}
235 230
236static void ath9k_ani_restart(struct ath_hal *ah) 231static void ath9k_ani_restart(struct ath_hw *ah)
237{ 232{
238 struct ath_hal_5416 *ahp = AH5416(ah);
239 struct ar5416AniState *aniState; 233 struct ar5416AniState *aniState;
240 234
241 if (!DO_ANI(ah)) 235 if (!DO_ANI(ah))
242 return; 236 return;
243 237
244 aniState = ahp->ah_curani; 238 aniState = ah->curani;
245 239
246 aniState->listenTime = 0; 240 aniState->listenTime = 0;
247 if (ahp->ah_hasHwPhyCounters) { 241 if (ah->has_hw_phycounters) {
248 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { 242 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
249 aniState->ofdmPhyErrBase = 0; 243 aniState->ofdmPhyErrBase = 0;
250 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 244 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -270,15 +264,14 @@ static void ath9k_ani_restart(struct ath_hal *ah)
270 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 264 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
271 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 265 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
272 266
273 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 267 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
274 } 268 }
275 aniState->ofdmPhyErrCount = 0; 269 aniState->ofdmPhyErrCount = 0;
276 aniState->cckPhyErrCount = 0; 270 aniState->cckPhyErrCount = 0;
277} 271}
278 272
279static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) 273static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
280{ 274{
281 struct ath_hal_5416 *ahp = AH5416(ah);
282 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 275 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
283 struct ar5416AniState *aniState; 276 struct ar5416AniState *aniState;
284 int32_t rssi; 277 int32_t rssi;
@@ -286,7 +279,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
286 if (!DO_ANI(ah)) 279 if (!DO_ANI(ah))
287 return; 280 return;
288 281
289 aniState = ahp->ah_curani; 282 aniState = ah->curani;
290 283
291 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 284 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
292 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 285 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
@@ -302,14 +295,14 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
302 } 295 }
303 } 296 }
304 297
305 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 298 if (ah->opmode == NL80211_IFTYPE_AP) {
306 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 299 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
307 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 300 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
308 aniState->firstepLevel + 1); 301 aniState->firstepLevel + 1);
309 } 302 }
310 return; 303 return;
311 } 304 }
312 rssi = BEACON_RSSI(ahp); 305 rssi = BEACON_RSSI(ah);
313 if (rssi > aniState->rssiThrHigh) { 306 if (rssi > aniState->rssiThrHigh) {
314 if (!aniState->ofdmWeakSigDetectOff) { 307 if (!aniState->ofdmWeakSigDetectOff) {
315 if (ath9k_hw_ani_control(ah, 308 if (ath9k_hw_ani_control(ah,
@@ -348,9 +341,8 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
348 } 341 }
349} 342}
350 343
351static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) 344static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
352{ 345{
353 struct ath_hal_5416 *ahp = AH5416(ah);
354 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 346 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
355 struct ar5416AniState *aniState; 347 struct ar5416AniState *aniState;
356 int32_t rssi; 348 int32_t rssi;
@@ -358,21 +350,21 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
358 if (!DO_ANI(ah)) 350 if (!DO_ANI(ah))
359 return; 351 return;
360 352
361 aniState = ahp->ah_curani; 353 aniState = ah->curani;
362 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 354 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
363 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 355 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
364 aniState->noiseImmunityLevel + 1)) { 356 aniState->noiseImmunityLevel + 1)) {
365 return; 357 return;
366 } 358 }
367 } 359 }
368 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 360 if (ah->opmode == NL80211_IFTYPE_AP) {
369 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 361 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
370 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 362 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
371 aniState->firstepLevel + 1); 363 aniState->firstepLevel + 1);
372 } 364 }
373 return; 365 return;
374 } 366 }
375 rssi = BEACON_RSSI(ahp); 367 rssi = BEACON_RSSI(ah);
376 if (rssi > aniState->rssiThrLow) { 368 if (rssi > aniState->rssiThrLow) {
377 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) 369 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
378 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 370 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
@@ -386,22 +378,21 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
386 } 378 }
387} 379}
388 380
389static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) 381static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
390{ 382{
391 struct ath_hal_5416 *ahp = AH5416(ah);
392 struct ar5416AniState *aniState; 383 struct ar5416AniState *aniState;
393 int32_t rssi; 384 int32_t rssi;
394 385
395 aniState = ahp->ah_curani; 386 aniState = ah->curani;
396 387
397 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 388 if (ah->opmode == NL80211_IFTYPE_AP) {
398 if (aniState->firstepLevel > 0) { 389 if (aniState->firstepLevel > 0) {
399 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 390 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
400 aniState->firstepLevel - 1)) 391 aniState->firstepLevel - 1))
401 return; 392 return;
402 } 393 }
403 } else { 394 } else {
404 rssi = BEACON_RSSI(ahp); 395 rssi = BEACON_RSSI(ah);
405 if (rssi > aniState->rssiThrHigh) { 396 if (rssi > aniState->rssiThrHigh) {
406 /* XXX: Handle me */ 397 /* XXX: Handle me */
407 } else if (rssi > aniState->rssiThrLow) { 398 } else if (rssi > aniState->rssiThrLow) {
@@ -440,9 +431,8 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
440 } 431 }
441} 432}
442 433
443static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) 434static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
444{ 435{
445 struct ath_hal_5416 *ahp = AH5416(ah);
446 struct ar5416AniState *aniState; 436 struct ar5416AniState *aniState;
447 u32 txFrameCount, rxFrameCount, cycleCount; 437 u32 txFrameCount, rxFrameCount, cycleCount;
448 int32_t listenTime; 438 int32_t listenTime;
@@ -451,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
451 rxFrameCount = REG_READ(ah, AR_RFCNT); 441 rxFrameCount = REG_READ(ah, AR_RFCNT);
452 cycleCount = REG_READ(ah, AR_CCCNT); 442 cycleCount = REG_READ(ah, AR_CCCNT);
453 443
454 aniState = ahp->ah_curani; 444 aniState = ah->curani;
455 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { 445 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
456 446
457 listenTime = 0; 447 listenTime = 0;
458 ahp->ah_stats.ast_ani_lzero++; 448 ah->stats.ast_ani_lzero++;
459 } else { 449 } else {
460 int32_t ccdelta = cycleCount - aniState->cycleCount; 450 int32_t ccdelta = cycleCount - aniState->cycleCount;
461 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; 451 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
@@ -469,25 +459,24 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
469 return listenTime; 459 return listenTime;
470} 460}
471 461
472void ath9k_ani_reset(struct ath_hal *ah) 462void ath9k_ani_reset(struct ath_hw *ah)
473{ 463{
474 struct ath_hal_5416 *ahp = AH5416(ah);
475 struct ar5416AniState *aniState; 464 struct ar5416AniState *aniState;
476 struct ath9k_channel *chan = ah->ah_curchan; 465 struct ath9k_channel *chan = ah->curchan;
477 int index; 466 int index;
478 467
479 if (!DO_ANI(ah)) 468 if (!DO_ANI(ah))
480 return; 469 return;
481 470
482 index = ath9k_hw_get_ani_channel_idx(ah, chan); 471 index = ath9k_hw_get_ani_channel_idx(ah, chan);
483 aniState = &ahp->ah_ani[index]; 472 aniState = &ah->ani[index];
484 ahp->ah_curani = aniState; 473 ah->curani = aniState;
485 474
486 if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION 475 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
487 && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { 476 && ah->opmode != NL80211_IFTYPE_ADHOC) {
488 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 477 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
489 "Reset ANI state opmode %u\n", ah->ah_opmode); 478 "Reset ANI state opmode %u\n", ah->opmode);
490 ahp->ah_stats.ast_ani_reset++; 479 ah->stats.ast_ani_reset++;
491 480
492 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); 481 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
493 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); 482 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
@@ -500,15 +489,15 @@ void ath9k_ani_reset(struct ath_hal *ah)
500 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | 489 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
501 ATH9K_RX_FILTER_PHYERR); 490 ATH9K_RX_FILTER_PHYERR);
502 491
503 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 492 if (ah->opmode == NL80211_IFTYPE_AP) {
504 ahp->ah_curani->ofdmTrigHigh = 493 ah->curani->ofdmTrigHigh =
505 ah->ah_config.ofdm_trig_high; 494 ah->config.ofdm_trig_high;
506 ahp->ah_curani->ofdmTrigLow = 495 ah->curani->ofdmTrigLow =
507 ah->ah_config.ofdm_trig_low; 496 ah->config.ofdm_trig_low;
508 ahp->ah_curani->cckTrigHigh = 497 ah->curani->cckTrigHigh =
509 ah->ah_config.cck_trig_high; 498 ah->config.cck_trig_high;
510 ahp->ah_curani->cckTrigLow = 499 ah->curani->cckTrigLow =
511 ah->ah_config.cck_trig_low; 500 ah->config.cck_trig_low;
512 } 501 }
513 ath9k_ani_restart(ah); 502 ath9k_ani_restart(ah);
514 return; 503 return;
@@ -529,7 +518,7 @@ void ath9k_ani_reset(struct ath_hal *ah)
529 if (aniState->firstepLevel != 0) 518 if (aniState->firstepLevel != 0)
530 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 519 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
531 aniState->firstepLevel); 520 aniState->firstepLevel);
532 if (ahp->ah_hasHwPhyCounters) { 521 if (ah->has_hw_phycounters) {
533 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & 522 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
534 ~ATH9K_RX_FILTER_PHYERR); 523 ~ATH9K_RX_FILTER_PHYERR);
535 ath9k_ani_restart(ah); 524 ath9k_ani_restart(ah);
@@ -543,34 +532,33 @@ void ath9k_ani_reset(struct ath_hal *ah)
543 } 532 }
544} 533}
545 534
546void ath9k_hw_ani_monitor(struct ath_hal *ah, 535void ath9k_hw_ani_monitor(struct ath_hw *ah,
547 const struct ath9k_node_stats *stats, 536 const struct ath9k_node_stats *stats,
548 struct ath9k_channel *chan) 537 struct ath9k_channel *chan)
549{ 538{
550 struct ath_hal_5416 *ahp = AH5416(ah);
551 struct ar5416AniState *aniState; 539 struct ar5416AniState *aniState;
552 int32_t listenTime; 540 int32_t listenTime;
553 541
554 if (!DO_ANI(ah)) 542 if (!DO_ANI(ah))
555 return; 543 return;
556 544
557 aniState = ahp->ah_curani; 545 aniState = ah->curani;
558 ahp->ah_stats.ast_nodestats = *stats; 546 ah->stats.ast_nodestats = *stats;
559 547
560 listenTime = ath9k_hw_ani_get_listen_time(ah); 548 listenTime = ath9k_hw_ani_get_listen_time(ah);
561 if (listenTime < 0) { 549 if (listenTime < 0) {
562 ahp->ah_stats.ast_ani_lneg++; 550 ah->stats.ast_ani_lneg++;
563 ath9k_ani_restart(ah); 551 ath9k_ani_restart(ah);
564 return; 552 return;
565 } 553 }
566 554
567 aniState->listenTime += listenTime; 555 aniState->listenTime += listenTime;
568 556
569 if (ahp->ah_hasHwPhyCounters) { 557 if (ah->has_hw_phycounters) {
570 u32 phyCnt1, phyCnt2; 558 u32 phyCnt1, phyCnt2;
571 u32 ofdmPhyErrCnt, cckPhyErrCnt; 559 u32 ofdmPhyErrCnt, cckPhyErrCnt;
572 560
573 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 561 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
574 562
575 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 563 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
576 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 564 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
@@ -603,24 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
603 } 591 }
604 592
605 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; 593 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
606 ahp->ah_stats.ast_ani_ofdmerrs += 594 ah->stats.ast_ani_ofdmerrs +=
607 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 595 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
608 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 596 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
609 597
610 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; 598 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
611 ahp->ah_stats.ast_ani_cckerrs += 599 ah->stats.ast_ani_cckerrs +=
612 cckPhyErrCnt - aniState->cckPhyErrCount; 600 cckPhyErrCnt - aniState->cckPhyErrCount;
613 aniState->cckPhyErrCount = cckPhyErrCnt; 601 aniState->cckPhyErrCount = cckPhyErrCnt;
614 } 602 }
615 603
616 if (aniState->listenTime > 5 * ahp->ah_aniPeriod) { 604 if (aniState->listenTime > 5 * ah->aniperiod) {
617 if (aniState->ofdmPhyErrCount <= aniState->listenTime * 605 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
618 aniState->ofdmTrigLow / 1000 && 606 aniState->ofdmTrigLow / 1000 &&
619 aniState->cckPhyErrCount <= aniState->listenTime * 607 aniState->cckPhyErrCount <= aniState->listenTime *
620 aniState->cckTrigLow / 1000) 608 aniState->cckTrigLow / 1000)
621 ath9k_hw_ani_lower_immunity(ah); 609 ath9k_hw_ani_lower_immunity(ah);
622 ath9k_ani_restart(ah); 610 ath9k_ani_restart(ah);
623 } else if (aniState->listenTime > ahp->ah_aniPeriod) { 611 } else if (aniState->listenTime > ah->aniperiod) {
624 if (aniState->ofdmPhyErrCount > aniState->listenTime * 612 if (aniState->ofdmPhyErrCount > aniState->listenTime *
625 aniState->ofdmTrigHigh / 1000) { 613 aniState->ofdmTrigHigh / 1000) {
626 ath9k_hw_ani_ofdm_err_trigger(ah); 614 ath9k_hw_ani_ofdm_err_trigger(ah);
@@ -634,20 +622,16 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
634 } 622 }
635} 623}
636 624
637bool ath9k_hw_phycounters(struct ath_hal *ah) 625bool ath9k_hw_phycounters(struct ath_hw *ah)
638{ 626{
639 struct ath_hal_5416 *ahp = AH5416(ah); 627 return ah->has_hw_phycounters ? true : false;
640
641 return ahp->ah_hasHwPhyCounters ? true : false;
642} 628}
643 629
644void ath9k_enable_mib_counters(struct ath_hal *ah) 630void ath9k_enable_mib_counters(struct ath_hw *ah)
645{ 631{
646 struct ath_hal_5416 *ahp = AH5416(ah);
647
648 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); 632 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");
649 633
650 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 634 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
651 635
652 REG_WRITE(ah, AR_FILT_OFDM, 0); 636 REG_WRITE(ah, AR_FILT_OFDM, 0);
653 REG_WRITE(ah, AR_FILT_CCK, 0); 637 REG_WRITE(ah, AR_FILT_CCK, 0);
@@ -658,21 +642,19 @@ void ath9k_enable_mib_counters(struct ath_hal *ah)
658 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 642 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
659} 643}
660 644
661void ath9k_hw_disable_mib_counters(struct ath_hal *ah) 645void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
662{ 646{
663 struct ath_hal_5416 *ahp = AH5416(ah);
664
665 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); 647 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n");
666 648
667 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); 649 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
668 650
669 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 651 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
670 652
671 REG_WRITE(ah, AR_FILT_OFDM, 0); 653 REG_WRITE(ah, AR_FILT_OFDM, 0);
672 REG_WRITE(ah, AR_FILT_CCK, 0); 654 REG_WRITE(ah, AR_FILT_CCK, 0);
673} 655}
674 656
675u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, 657u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
676 u32 *rxc_pcnt, 658 u32 *rxc_pcnt,
677 u32 *rxf_pcnt, 659 u32 *rxf_pcnt,
678 u32 *txf_pcnt) 660 u32 *txf_pcnt)
@@ -717,10 +699,9 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
717 * any of the MIB counters overflow/trigger so don't assume we're 699 * any of the MIB counters overflow/trigger so don't assume we're
718 * here because a PHY error counter triggered. 700 * here because a PHY error counter triggered.
719 */ 701 */
720void ath9k_hw_procmibevent(struct ath_hal *ah, 702void ath9k_hw_procmibevent(struct ath_hw *ah,
721 const struct ath9k_node_stats *stats) 703 const struct ath9k_node_stats *stats)
722{ 704{
723 struct ath_hal_5416 *ahp = AH5416(ah);
724 u32 phyCnt1, phyCnt2; 705 u32 phyCnt1, phyCnt2;
725 706
726 /* Reset these counters regardless */ 707 /* Reset these counters regardless */
@@ -730,8 +711,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
730 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); 711 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
731 712
732 /* Clear the mib counters and save them in the stats */ 713 /* Clear the mib counters and save them in the stats */
733 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 714 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
734 ahp->ah_stats.ast_nodestats = *stats; 715 ah->stats.ast_nodestats = *stats;
735 716
736 if (!DO_ANI(ah)) 717 if (!DO_ANI(ah))
737 return; 718 return;
@@ -741,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
741 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 722 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
742 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 723 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
743 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { 724 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
744 struct ar5416AniState *aniState = ahp->ah_curani; 725 struct ar5416AniState *aniState = ah->curani;
745 u32 ofdmPhyErrCnt, cckPhyErrCnt; 726 u32 ofdmPhyErrCnt, cckPhyErrCnt;
746 727
747 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ 728 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
748 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; 729 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
749 ahp->ah_stats.ast_ani_ofdmerrs += 730 ah->stats.ast_ani_ofdmerrs +=
750 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 731 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
751 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 732 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
752 733
753 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; 734 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
754 ahp->ah_stats.ast_ani_cckerrs += 735 ah->stats.ast_ani_cckerrs +=
755 cckPhyErrCnt - aniState->cckPhyErrCount; 736 cckPhyErrCnt - aniState->cckPhyErrCount;
756 aniState->cckPhyErrCount = cckPhyErrCnt; 737 aniState->cckPhyErrCount = cckPhyErrCnt;
757 738
@@ -770,9 +751,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
770 } 751 }
771} 752}
772 753
773void ath9k_hw_ani_setup(struct ath_hal *ah) 754void ath9k_hw_ani_setup(struct ath_hw *ah)
774{ 755{
775 struct ath_hal_5416 *ahp = AH5416(ah);
776 int i; 756 int i;
777 757
778 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; 758 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
@@ -781,66 +761,63 @@ void ath9k_hw_ani_setup(struct ath_hal *ah)
781 const int firpwr[] = { -78, -78, -78, -78, -80 }; 761 const int firpwr[] = { -78, -78, -78, -78, -80 };
782 762
783 for (i = 0; i < 5; i++) { 763 for (i = 0; i < 5; i++) {
784 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i]; 764 ah->totalSizeDesired[i] = totalSizeDesired[i];
785 ahp->ah_coarseHigh[i] = coarseHigh[i]; 765 ah->coarse_high[i] = coarseHigh[i];
786 ahp->ah_coarseLow[i] = coarseLow[i]; 766 ah->coarse_low[i] = coarseLow[i];
787 ahp->ah_firpwr[i] = firpwr[i]; 767 ah->firpwr[i] = firpwr[i];
788 } 768 }
789} 769}
790 770
791void ath9k_hw_ani_attach(struct ath_hal *ah) 771void ath9k_hw_ani_attach(struct ath_hw *ah)
792{ 772{
793 struct ath_hal_5416 *ahp = AH5416(ah);
794 int i; 773 int i;
795 774
796 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); 775 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n");
797 776
798 ahp->ah_hasHwPhyCounters = 1; 777 ah->has_hw_phycounters = 1;
799 778
800 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani)); 779 memset(ah->ani, 0, sizeof(ah->ani));
801 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { 780 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
802 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; 781 ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
803 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; 782 ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
804 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; 783 ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
805 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; 784 ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
806 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; 785 ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
807 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; 786 ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
808 ahp->ah_ani[i].ofdmWeakSigDetectOff = 787 ah->ani[i].ofdmWeakSigDetectOff =
809 !ATH9K_ANI_USE_OFDM_WEAK_SIG; 788 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
810 ahp->ah_ani[i].cckWeakSigThreshold = 789 ah->ani[i].cckWeakSigThreshold =
811 ATH9K_ANI_CCK_WEAK_SIG_THR; 790 ATH9K_ANI_CCK_WEAK_SIG_THR;
812 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 791 ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
813 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 792 ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
814 if (ahp->ah_hasHwPhyCounters) { 793 if (ah->has_hw_phycounters) {
815 ahp->ah_ani[i].ofdmPhyErrBase = 794 ah->ani[i].ofdmPhyErrBase =
816 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; 795 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
817 ahp->ah_ani[i].cckPhyErrBase = 796 ah->ani[i].cckPhyErrBase =
818 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; 797 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
819 } 798 }
820 } 799 }
821 if (ahp->ah_hasHwPhyCounters) { 800 if (ah->has_hw_phycounters) {
822 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 801 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
823 "Setting OfdmErrBase = 0x%08x\n", 802 "Setting OfdmErrBase = 0x%08x\n",
824 ahp->ah_ani[0].ofdmPhyErrBase); 803 ah->ani[0].ofdmPhyErrBase);
825 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 804 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
826 ahp->ah_ani[0].cckPhyErrBase); 805 ah->ani[0].cckPhyErrBase);
827 806
828 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase); 807 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
829 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase); 808 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
830 ath9k_enable_mib_counters(ah); 809 ath9k_enable_mib_counters(ah);
831 } 810 }
832 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD; 811 ah->aniperiod = ATH9K_ANI_PERIOD;
833 if (ah->ah_config.enable_ani) 812 if (ah->config.enable_ani)
834 ahp->ah_procPhyErr |= HAL_PROCESS_ANI; 813 ah->proc_phyerr |= HAL_PROCESS_ANI;
835} 814}
836 815
837void ath9k_hw_ani_detach(struct ath_hal *ah) 816void ath9k_hw_ani_detach(struct ath_hw *ah)
838{ 817{
839 struct ath_hal_5416 *ahp = AH5416(ah);
840
841 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); 818 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n");
842 819
843 if (ahp->ah_hasHwPhyCounters) { 820 if (ah->has_hw_phycounters) {
844 ath9k_hw_disable_mib_counters(ah); 821 ath9k_hw_disable_mib_counters(ah);
845 REG_WRITE(ah, AR_PHY_ERR_1, 0); 822 REG_WRITE(ah, AR_PHY_ERR_1, 0);
846 REG_WRITE(ah, AR_PHY_ERR_2, 0); 823 REG_WRITE(ah, AR_PHY_ERR_2, 0);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 11:21:27 -0500