diff options
Diffstat (limited to 'drivers/net/wireless/ath5k/reg.h')
| -rw-r--r-- | drivers/net/wireless/ath5k/reg.h | 1987 |
1 files changed, 1987 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath5k/reg.h b/drivers/net/wireless/ath5k/reg.h new file mode 100644 index 000000000000..2f41c8398602 --- /dev/null +++ b/drivers/net/wireless/ath5k/reg.h | |||
| @@ -0,0 +1,1987 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2007 Nick Kossifidis <mickflemm@gmail.com> | ||
| 3 | * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> | ||
| 4 | * Copyright (c) 2007 Michael Taylor <mike.taylor@apprion.com> | ||
| 5 | * | ||
| 6 | * Permission to use, copy, modify, and distribute this software for any | ||
| 7 | * purpose with or without fee is hereby granted, provided that the above | ||
| 8 | * copyright notice and this permission notice appear in all copies. | ||
| 9 | * | ||
| 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k | ||
| 22 | * maintained by Reyk Floeter | ||
| 23 | * | ||
| 24 | * I tried to document those registers by looking at ar5k code, some | ||
| 25 | * 802.11 (802.11e mostly) papers and by reading various public available | ||
| 26 | * Atheros presentations and papers like these: | ||
| 27 | * | ||
| 28 | * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf | ||
| 29 | * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf | ||
| 30 | * | ||
| 31 | * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf | ||
| 32 | */ | ||
| 33 | |||
| 34 | |||
| 35 | |||
| 36 | /*====MAC DMA REGISTERS====*/ | ||
| 37 | |||
| 38 | /* | ||
| 39 | * AR5210-Specific TXDP registers | ||
| 40 | * 5210 has only 2 transmit queues so no DCU/QCU, just | ||
| 41 | * 2 transmit descriptor pointers... | ||
| 42 | */ | ||
| 43 | #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ | ||
| 44 | #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ | ||
| 45 | |||
| 46 | /* | ||
| 47 | * Mac Control Register | ||
| 48 | */ | ||
| 49 | #define AR5K_CR 0x0008 /* Register Address */ | ||
| 50 | #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ | ||
| 51 | #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */ | ||
| 52 | #define AR5K_CR_RXE 0x00000004 /* RX Enable */ | ||
| 53 | #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ | ||
| 54 | #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ | ||
| 55 | #define AR5K_CR_RXD 0x00000020 /* RX Disable */ | ||
| 56 | #define AR5K_CR_SWI 0x00000040 | ||
| 57 | |||
| 58 | /* | ||
| 59 | * RX Descriptor Pointer register | ||
| 60 | */ | ||
| 61 | #define AR5K_RXDP 0x000c | ||
| 62 | |||
| 63 | /* | ||
| 64 | * Configuration and status register | ||
| 65 | */ | ||
| 66 | #define AR5K_CFG 0x0014 /* Register Address */ | ||
| 67 | #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ | ||
| 68 | #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer (?) */ | ||
| 69 | #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ | ||
| 70 | #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer (?) */ | ||
| 71 | #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register values (?) */ | ||
| 72 | #define AR5K_CFG_ADHOC 0x00000020 /* [5211+] */ | ||
| 73 | #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ | ||
| 74 | #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ | ||
| 75 | #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (?) */ | ||
| 76 | #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ | ||
| 77 | #define AR5K_CFG_TXCNT_S 11 | ||
| 78 | #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ | ||
| 79 | #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ | ||
| 80 | #define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ | ||
| 81 | #define AR5K_CFG_PCI_THRES_S 17 | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Interrupt enable register | ||
| 85 | */ | ||
| 86 | #define AR5K_IER 0x0024 /* Register Address */ | ||
| 87 | #define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */ | ||
| 88 | #define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */ | ||
| 89 | |||
| 90 | |||
| 91 | /* | ||
| 92 | * 0x0028 is Beacon Control Register on 5210 | ||
| 93 | * and first RTS duration register on 5211 | ||
| 94 | */ | ||
| 95 | |||
| 96 | /* | ||
| 97 | * Beacon control register [5210] | ||
| 98 | */ | ||
| 99 | #define AR5K_BCR 0x0028 /* Register Address */ | ||
| 100 | #define AR5K_BCR_AP 0x00000000 /* AP mode */ | ||
| 101 | #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */ | ||
| 102 | #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ | ||
| 103 | #define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ | ||
| 104 | #define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ | ||
| 105 | #define AR5K_BCR_BCGET 0x00000010 | ||
| 106 | |||
| 107 | /* | ||
| 108 | * First RTS duration register [5211] | ||
| 109 | */ | ||
| 110 | #define AR5K_RTSD0 0x0028 /* Register Address */ | ||
| 111 | #define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */ | ||
| 112 | #define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */ | ||
| 113 | #define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/ | ||
| 114 | #define AR5K_RTSD0_9_S 8 | ||
| 115 | #define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/ | ||
| 116 | #define AR5K_RTSD0_12_S 16 | ||
| 117 | #define AR5K_RTSD0_18 0xff000000 /* 16Mb*/ | ||
| 118 | #define AR5K_RTSD0_18_S 24 | ||
| 119 | |||
| 120 | |||
| 121 | /* | ||
| 122 | * 0x002c is Beacon Status Register on 5210 | ||
| 123 | * and second RTS duration register on 5211 | ||
| 124 | */ | ||
| 125 | |||
| 126 | /* | ||
| 127 | * Beacon status register [5210] | ||
| 128 | * | ||
| 129 | * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR | ||
| 130 | * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning | ||
| 131 | * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). | ||
| 132 | * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i | ||
| 133 | * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what | ||
| 134 | * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. | ||
| 135 | */ | ||
| 136 | #define AR5K_BSR 0x002c /* Register Address */ | ||
| 137 | #define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */ | ||
| 138 | #define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */ | ||
| 139 | #define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */ | ||
| 140 | #define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */ | ||
| 141 | #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */ | ||
| 142 | #define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */ | ||
| 143 | #define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ | ||
| 144 | #define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ | ||
| 145 | #define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ | ||
| 146 | #define AR5K_BSR_SWBA_CNT 0x00ff0000 | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Second RTS duration register [5211] | ||
| 150 | */ | ||
| 151 | #define AR5K_RTSD1 0x002c /* Register Address */ | ||
| 152 | #define AR5K_RTSD1_24 0x000000ff /* 24Mb */ | ||
| 153 | #define AR5K_RTSD1_24_S 0 | ||
| 154 | #define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */ | ||
| 155 | #define AR5K_RTSD1_36_S 8 | ||
| 156 | #define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */ | ||
| 157 | #define AR5K_RTSD1_48_S 16 | ||
| 158 | #define AR5K_RTSD1_54 0xff000000 /* 54Mb */ | ||
| 159 | #define AR5K_RTSD1_54_S 24 | ||
| 160 | |||
| 161 | |||
| 162 | /* | ||
| 163 | * Transmit configuration register | ||
| 164 | */ | ||
| 165 | #define AR5K_TXCFG 0x0030 /* Register Address */ | ||
| 166 | #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size */ | ||
| 167 | #define AR5K_TXCFG_SDMAMR_S 0 | ||
| 168 | #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ | ||
| 169 | #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ | ||
| 170 | #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ | ||
| 171 | #define AR5K_TXCFG_TXFULL_S 4 | ||
| 172 | #define AR5K_TXCFG_TXFULL_0B 0x00000000 | ||
| 173 | #define AR5K_TXCFG_TXFULL_64B 0x00000010 | ||
| 174 | #define AR5K_TXCFG_TXFULL_128B 0x00000020 | ||
| 175 | #define AR5K_TXCFG_TXFULL_192B 0x00000030 | ||
| 176 | #define AR5K_TXCFG_TXFULL_256B 0x00000040 | ||
| 177 | #define AR5K_TXCFG_TXCONT_EN 0x00000080 | ||
| 178 | #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ | ||
| 179 | #define AR5K_TXCFG_JUMBO_TXE 0x00000400 /* Enable jumbo frames transmition (?) [5211+] */ | ||
| 180 | #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ | ||
| 181 | #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ | ||
| 182 | #define AR5K_TXCFG_RDY_DIS 0x00004000 /* [5211+] */ | ||
| 183 | |||
| 184 | /* | ||
| 185 | * Receive configuration register | ||
| 186 | */ | ||
| 187 | #define AR5K_RXCFG 0x0034 /* Register Address */ | ||
| 188 | #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size */ | ||
| 189 | #define AR5K_RXCFG_SDMAMW_S 0 | ||
| 190 | #define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /* Default antenna */ | ||
| 191 | #define AR5K_RXCFG_ZLFDMA 0x00000010 /* Zero-length DMA */ | ||
| 192 | #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo frames reception (?) [5211+] */ | ||
| 193 | #define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames (?) [5211+] */ | ||
| 194 | |||
| 195 | /* | ||
| 196 | * Receive jumbo descriptor last address register | ||
| 197 | * Only found in 5211 (?) | ||
| 198 | */ | ||
| 199 | #define AR5K_RXJLA 0x0038 | ||
| 200 | |||
| 201 | /* | ||
| 202 | * MIB control register | ||
| 203 | */ | ||
| 204 | #define AR5K_MIBC 0x0040 /* Register Address */ | ||
| 205 | #define AR5K_MIBC_COW 0x00000001 | ||
| 206 | #define AR5K_MIBC_FMC 0x00000002 /* Freeze Mib Counters (?) */ | ||
| 207 | #define AR5K_MIBC_CMC 0x00000004 /* Clean Mib Counters (?) */ | ||
| 208 | #define AR5K_MIBC_MCS 0x00000008 | ||
| 209 | |||
| 210 | /* | ||
| 211 | * Timeout prescale register | ||
| 212 | */ | ||
| 213 | #define AR5K_TOPS 0x0044 | ||
| 214 | #define AR5K_TOPS_M 0x0000ffff /* [5211+] (?) */ | ||
| 215 | |||
| 216 | /* | ||
| 217 | * Receive timeout register (no frame received) | ||
| 218 | */ | ||
| 219 | #define AR5K_RXNOFRM 0x0048 | ||
| 220 | #define AR5K_RXNOFRM_M 0x000003ff /* [5211+] (?) */ | ||
| 221 | |||
| 222 | /* | ||
| 223 | * Transmit timeout register (no frame sent) | ||
| 224 | */ | ||
| 225 | #define AR5K_TXNOFRM 0x004c | ||
| 226 | #define AR5K_TXNOFRM_M 0x000003ff /* [5211+] (?) */ | ||
| 227 | #define AR5K_TXNOFRM_QCU 0x000ffc00 /* [5211+] (?) */ | ||
| 228 | |||
| 229 | /* | ||
| 230 | * Receive frame gap timeout register | ||
| 231 | */ | ||
| 232 | #define AR5K_RPGTO 0x0050 | ||
| 233 | #define AR5K_RPGTO_M 0x000003ff /* [5211+] (?) */ | ||
| 234 | |||
| 235 | /* | ||
| 236 | * Receive frame count limit register | ||
| 237 | */ | ||
| 238 | #define AR5K_RFCNT 0x0054 | ||
| 239 | #define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */ | ||
| 240 | #define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */ | ||
| 241 | |||
| 242 | /* | ||
| 243 | * Misc settings register | ||
| 244 | */ | ||
| 245 | #define AR5K_MISC 0x0058 /* Register Address */ | ||
| 246 | #define AR5K_MISC_DMA_OBS_M 0x000001e0 | ||
| 247 | #define AR5K_MISC_DMA_OBS_S 5 | ||
| 248 | #define AR5K_MISC_MISC_OBS_M 0x00000e00 | ||
| 249 | #define AR5K_MISC_MISC_OBS_S 9 | ||
| 250 | #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 | ||
| 251 | #define AR5K_MISC_MAC_OBS_LSB_S 12 | ||
| 252 | #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 | ||
| 253 | #define AR5K_MISC_MAC_OBS_MSB_S 15 | ||
| 254 | #define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ | ||
| 255 | #define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ | ||
| 256 | |||
| 257 | /* | ||
| 258 | * QCU/DCU clock gating register (5311) | ||
| 259 | */ | ||
| 260 | #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ | ||
| 261 | #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ | ||
| 262 | #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */ | ||
| 263 | |||
| 264 | /* | ||
| 265 | * Interrupt Status Registers | ||
| 266 | * | ||
| 267 | * For 5210 there is only one status register but for | ||
| 268 | * 5211/5212 we have one primary and 4 secondary registers. | ||
| 269 | * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. | ||
| 270 | * Most of these bits are common for all chipsets. | ||
| 271 | */ | ||
| 272 | #define AR5K_ISR 0x001c /* Register Address [5210] */ | ||
| 273 | #define AR5K_PISR 0x0080 /* Register Address [5211+] */ | ||
| 274 | #define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly recieved */ | ||
| 275 | #define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ | ||
| 276 | #define AR5K_ISR_RXERR 0x00000004 /* Receive error */ | ||
| 277 | #define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ | ||
| 278 | #define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ | ||
| 279 | #define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ | ||
| 280 | #define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ | ||
| 281 | #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ | ||
| 282 | #define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ | ||
| 283 | #define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ | ||
| 284 | #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ | ||
| 285 | #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ | ||
| 286 | #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ | ||
| 287 | #define AR5K_ISR_SWI 0x00002000 /* Software interrupt (?) */ | ||
| 288 | #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ | ||
| 289 | #define AR5K_ISR_RXKCM 0x00008000 | ||
| 290 | #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ | ||
| 291 | #define AR5K_ISR_BRSSI 0x00020000 | ||
| 292 | #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ | ||
| 293 | #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ | ||
| 294 | #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ | ||
| 295 | #define AR5K_ISR_MCABT 0x00100000 /* [5210] */ | ||
| 296 | #define AR5K_ISR_RXCHIRP 0x00200000 /* [5212+] */ | ||
| 297 | #define AR5K_ISR_SSERR 0x00200000 /* [5210] */ | ||
| 298 | #define AR5K_ISR_DPERR 0x00400000 /* [5210] */ | ||
| 299 | #define AR5K_ISR_TIM 0x00800000 /* [5210] */ | ||
| 300 | #define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ | ||
| 301 | #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ | ||
| 302 | #define AR5K_ISR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ | ||
| 303 | #define AR5K_ISR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ | ||
| 304 | #define AR5K_ISR_QTRIG 0x08000000 /* [5211+] */ | ||
| 305 | |||
| 306 | /* | ||
| 307 | * Secondary status registers [5211+] (0 - 4) | ||
| 308 | * | ||
| 309 | * I guess from the names that these give the status for each | ||
| 310 | * queue, that's why only masks are defined here, haven't got | ||
| 311 | * any info about them (couldn't find them anywhere in ar5k code). | ||
| 312 | */ | ||
| 313 | #define AR5K_SISR0 0x0084 /* Register Address [5211+] */ | ||
| 314 | #define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ | ||
| 315 | #define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ | ||
| 316 | |||
| 317 | #define AR5K_SISR1 0x0088 /* Register Address [5211+] */ | ||
| 318 | #define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ | ||
| 319 | #define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ | ||
| 320 | |||
| 321 | #define AR5K_SISR2 0x008c /* Register Address [5211+] */ | ||
| 322 | #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ | ||
| 323 | #define AR5K_SISR2_MCABT 0x00100000 | ||
| 324 | #define AR5K_SISR2_SSERR 0x00200000 | ||
| 325 | #define AR5K_SISR2_DPERR 0x00400000 | ||
| 326 | #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ | ||
| 327 | #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ | ||
| 328 | #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* [5212+] */ | ||
| 329 | #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ | ||
| 330 | #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ | ||
| 331 | #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ | ||
| 332 | |||
| 333 | #define AR5K_SISR3 0x0090 /* Register Address [5211+] */ | ||
| 334 | #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ | ||
| 335 | #define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ | ||
| 336 | |||
| 337 | #define AR5K_SISR4 0x0094 /* Register Address [5211+] */ | ||
| 338 | #define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ | ||
| 339 | |||
| 340 | /* | ||
| 341 | * Shadow read-and-clear interrupt status registers [5211+] | ||
| 342 | */ | ||
| 343 | #define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */ | ||
| 344 | #define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */ | ||
| 345 | #define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */ | ||
| 346 | #define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */ | ||
| 347 | #define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */ | ||
| 348 | #define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */ | ||
| 349 | |||
| 350 | /* | ||
| 351 | * Interrupt Mask Registers | ||
| 352 | * | ||
| 353 | * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary | ||
| 354 | * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. | ||
| 355 | */ | ||
| 356 | #define AR5K_IMR 0x0020 /* Register Address [5210] */ | ||
| 357 | #define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ | ||
| 358 | #define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly recieved*/ | ||
| 359 | #define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ | ||
| 360 | #define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ | ||
| 361 | #define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ | ||
| 362 | #define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ | ||
| 363 | #define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ | ||
| 364 | #define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ | ||
| 365 | #define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ | ||
| 366 | #define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ | ||
| 367 | #define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ | ||
| 368 | #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ | ||
| 369 | #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ | ||
| 370 | #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ | ||
| 371 | #define AR5K_IMR_SWI 0x00002000 | ||
| 372 | #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ | ||
| 373 | #define AR5K_IMR_RXKCM 0x00008000 | ||
| 374 | #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ | ||
| 375 | #define AR5K_IMR_BRSSI 0x00020000 | ||
| 376 | #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ | ||
| 377 | #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ | ||
| 378 | #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ | ||
| 379 | #define AR5K_IMR_MCABT 0x00100000 /* [5210] */ | ||
| 380 | #define AR5K_IMR_RXCHIRP 0x00200000 /* [5212+]*/ | ||
| 381 | #define AR5K_IMR_SSERR 0x00200000 /* [5210] */ | ||
| 382 | #define AR5K_IMR_DPERR 0x00400000 /* [5210] */ | ||
| 383 | #define AR5K_IMR_TIM 0x00800000 /* [5211+] */ | ||
| 384 | #define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ | ||
| 385 | #define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ | ||
| 386 | #define AR5K_IMR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ | ||
| 387 | #define AR5K_IMR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ | ||
| 388 | #define AR5K_IMR_QTRIG 0x08000000 /* [5211+] */ | ||
| 389 | |||
| 390 | /* | ||
| 391 | * Secondary interrupt mask registers [5211+] (0 - 4) | ||
| 392 | */ | ||
| 393 | #define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */ | ||
| 394 | #define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ | ||
| 395 | #define AR5K_SIMR0_QCU_TXOK_S 0 | ||
| 396 | #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ | ||
| 397 | #define AR5K_SIMR0_QCU_TXDESC_S 16 | ||
| 398 | |||
| 399 | #define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */ | ||
| 400 | #define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ | ||
| 401 | #define AR5K_SIMR1_QCU_TXERR_S 0 | ||
| 402 | #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ | ||
| 403 | #define AR5K_SIMR1_QCU_TXEOL_S 16 | ||
| 404 | |||
| 405 | #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ | ||
| 406 | #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ | ||
| 407 | #define AR5K_SIMR2_QCU_TXURN_S 0 | ||
| 408 | #define AR5K_SIMR2_MCABT 0x00100000 | ||
| 409 | #define AR5K_SIMR2_SSERR 0x00200000 | ||
| 410 | #define AR5K_SIMR2_DPERR 0x00400000 | ||
| 411 | #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ | ||
| 412 | #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ | ||
| 413 | #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* [5212+] */ | ||
| 414 | #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ | ||
| 415 | #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ | ||
| 416 | #define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ | ||
| 417 | |||
| 418 | #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ | ||
| 419 | #define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ | ||
| 420 | #define AR5K_SIMR3_QCBRORN_S 0 | ||
| 421 | #define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ | ||
| 422 | #define AR5K_SIMR3_QCBRURN_S 16 | ||
| 423 | |||
| 424 | #define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */ | ||
| 425 | #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ | ||
| 426 | #define AR5K_SIMR4_QTRIG_S 0 | ||
| 427 | |||
| 428 | |||
| 429 | /* | ||
| 430 | * Decompression mask registers [5212+] | ||
| 431 | */ | ||
| 432 | #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (?)*/ | ||
| 433 | #define AR5K_DCM_DATA 0x0404 /*Decompression mask data (?)*/ | ||
| 434 | |||
| 435 | /* | ||
| 436 | * Decompression configuration registers [5212+] | ||
| 437 | */ | ||
| 438 | #define AR5K_DCCFG 0x0420 | ||
| 439 | |||
| 440 | /* | ||
| 441 | * Compression configuration registers [5212+] | ||
| 442 | */ | ||
| 443 | #define AR5K_CCFG 0x0600 | ||
| 444 | #define AR5K_CCFG_CUP 0x0604 | ||
| 445 | |||
| 446 | /* | ||
| 447 | * Compression performance counter registers [5212+] | ||
| 448 | */ | ||
| 449 | #define AR5K_CPC0 0x0610 /* Compression performance counter 0 */ | ||
| 450 | #define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ | ||
| 451 | #define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ | ||
| 452 | #define AR5K_CPC3 0x061c /* Compression performance counter 3 */ | ||
| 453 | #define AR5K_CPCORN 0x0620 /* Compression performance overrun (?) */ | ||
| 454 | |||
| 455 | |||
| 456 | /* | ||
| 457 | * Queue control unit (QCU) registers [5211+] | ||
| 458 | * | ||
| 459 | * Card has 12 TX Queues but i see that only 0-9 are used (?) | ||
| 460 | * both in binary HAL (see ah.h) and ar5k. Each queue has it's own | ||
| 461 | * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) | ||
| 462 | * configuration register (0x08c0 - 0x08ec), a ready time configuration | ||
| 463 | * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - | ||
| 464 | * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some | ||
| 465 | * global registers, QCU transmit enable/disable and "one shot arm (?)" | ||
| 466 | * set/clear, which contain status for all queues (we shift by 1 for each | ||
| 467 | * queue). To access these registers easily we define some macros here | ||
| 468 | * that are used inside HAL. For more infos check out *_tx_queue functs. | ||
| 469 | * | ||
| 470 | * TODO: Boundary checking on macros (here?) | ||
| 471 | */ | ||
| 472 | |||
| 473 | /* | ||
| 474 | * Generic QCU Register access macros | ||
| 475 | */ | ||
| 476 | #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) | ||
| 477 | #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) | ||
| 478 | #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) | ||
| 479 | |||
| 480 | /* | ||
| 481 | * QCU Transmit descriptor pointer registers | ||
| 482 | */ | ||
| 483 | #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */ | ||
| 484 | #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) | ||
| 485 | |||
| 486 | /* | ||
| 487 | * QCU Transmit enable register | ||
| 488 | */ | ||
| 489 | #define AR5K_QCU_TXE 0x0840 | ||
| 490 | #define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q) | ||
| 491 | #define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q) | ||
| 492 | |||
| 493 | /* | ||
| 494 | * QCU Transmit disable register | ||
| 495 | */ | ||
| 496 | #define AR5K_QCU_TXD 0x0880 | ||
| 497 | #define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q) | ||
| 498 | #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q) | ||
| 499 | |||
| 500 | /* | ||
| 501 | * QCU Constant Bit Rate configuration registers | ||
| 502 | */ | ||
| 503 | #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */ | ||
| 504 | #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */ | ||
| 505 | #define AR5K_QCU_CBRCFG_INTVAL_S 0 | ||
| 506 | #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */ | ||
| 507 | #define AR5K_QCU_CBRCFG_ORN_THRES_S 24 | ||
| 508 | #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) | ||
| 509 | |||
| 510 | /* | ||
| 511 | * QCU Ready time configuration registers | ||
| 512 | */ | ||
| 513 | #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ | ||
| 514 | #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ | ||
| 515 | #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 | ||
| 516 | #define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /* Ready time duration mask */ | ||
| 517 | #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ | ||
| 518 | #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) | ||
| 519 | |||
| 520 | /* | ||
| 521 | * QCU one shot arm set registers | ||
| 522 | */ | ||
| 523 | #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */ | ||
| 524 | #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff | ||
| 525 | |||
| 526 | /* | ||
| 527 | * QCU one shot arm clear registers | ||
| 528 | */ | ||
| 529 | #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */ | ||
| 530 | #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff | ||
| 531 | |||
| 532 | /* | ||
| 533 | * QCU misc registers | ||
| 534 | */ | ||
| 535 | #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ | ||
| 536 | #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ | ||
| 537 | #define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ | ||
| 538 | #define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ | ||
| 539 | #define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ | ||
| 540 | #define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ | ||
| 541 | #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ | ||
| 542 | #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ | ||
| 543 | #define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ | ||
| 544 | #define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ | ||
| 545 | #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Beacons enabled */ | ||
| 546 | #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled (?) */ | ||
| 547 | #define AR5K_QCU_MISC_TXE 0x00000200 /* TXE reset when RDYTIME enalbed (?) */ | ||
| 548 | #define AR5K_QCU_MISC_CBR 0x00000400 /* CBR threshold reset (?) */ | ||
| 549 | #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU reset (?) */ | ||
| 550 | #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) | ||
| 551 | |||
| 552 | |||
| 553 | /* | ||
| 554 | * QCU status registers | ||
| 555 | */ | ||
| 556 | #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ | ||
| 557 | #define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ | ||
| 558 | #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter (?) */ | ||
| 559 | #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) | ||
| 560 | |||
| 561 | /* | ||
| 562 | * QCU ready time shutdown register | ||
| 563 | */ | ||
| 564 | #define AR5K_QCU_RDYTIMESHDN 0x0a40 | ||
| 565 | #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff | ||
| 566 | |||
| 567 | /* | ||
| 568 | * QCU compression buffer base registers [5212+] | ||
| 569 | */ | ||
| 570 | #define AR5K_QCU_CBB_SELECT 0x0b00 | ||
| 571 | #define AR5K_QCU_CBB_ADDR 0x0b04 | ||
| 572 | |||
| 573 | /* | ||
| 574 | * QCU compression buffer configuration register [5212+] | ||
| 575 | */ | ||
| 576 | #define AR5K_QCU_CBCFG 0x0b08 | ||
| 577 | |||
| 578 | |||
| 579 | |||
| 580 | /* | ||
| 581 | * Distributed Coordination Function (DCF) control unit (DCU) | ||
| 582 | * registers [5211+] | ||
| 583 | * | ||
| 584 | * These registers control the various characteristics of each queue | ||
| 585 | * for 802.11e (WME) combatibility so they go together with | ||
| 586 | * QCU registers in pairs. For each queue we have a QCU mask register, | ||
| 587 | * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), | ||
| 588 | * a retry limit register (0x1080 - 0x10ac), a channel time register | ||
| 589 | * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and | ||
| 590 | * a sequence number register (0x1140 - 0x116c). It seems that "global" | ||
| 591 | * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). | ||
| 592 | * We use the same macros here for easier register access. | ||
| 593 | * | ||
| 594 | */ | ||
| 595 | |||
| 596 | /* | ||
| 597 | * DCU QCU mask registers | ||
| 598 | */ | ||
| 599 | #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */ | ||
| 600 | #define AR5K_DCU_QCUMASK_M 0x000003ff | ||
| 601 | #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) | ||
| 602 | |||
| 603 | /* | ||
| 604 | * DCU local Inter Frame Space settings register | ||
| 605 | */ | ||
| 606 | #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */ | ||
| 607 | #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */ | ||
| 608 | #define AR5K_DCU_LCL_IFS_CW_MIN_S 0 | ||
| 609 | #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */ | ||
| 610 | #define AR5K_DCU_LCL_IFS_CW_MAX_S 10 | ||
| 611 | #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ | ||
| 612 | #define AR5K_DCU_LCL_IFS_AIFS_S 20 | ||
| 613 | #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) | ||
| 614 | |||
| 615 | /* | ||
| 616 | * DCU retry limit registers | ||
| 617 | */ | ||
| 618 | #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */ | ||
| 619 | #define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ | ||
| 620 | #define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 | ||
| 621 | #define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry limit mask */ | ||
| 622 | #define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 | ||
| 623 | #define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask (?) */ | ||
| 624 | #define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 | ||
| 625 | #define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask (?) */ | ||
| 626 | #define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 | ||
| 627 | #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) | ||
| 628 | |||
| 629 | /* | ||
| 630 | * DCU channel time registers | ||
| 631 | */ | ||
| 632 | #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */ | ||
| 633 | #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */ | ||
| 634 | #define AR5K_DCU_CHAN_TIME_DUR_S 0 | ||
| 635 | #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */ | ||
| 636 | #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) | ||
| 637 | |||
| 638 | /* | ||
| 639 | * DCU misc registers [5211+] | ||
| 640 | * | ||
| 641 | * For some of the registers i couldn't find in the code | ||
| 642 | * (only backoff stuff is there realy) i tried to match the | ||
| 643 | * names with 802.11e parameters etc, so i guess VIRTCOL here | ||
| 644 | * means Virtual Collision and HCFPOLL means Hybrid Coordination | ||
| 645 | * factor Poll (CF- Poll). Arbiter lockout control controls the | ||
| 646 | * behaviour on low priority queues when we have multiple queues | ||
| 647 | * with pending frames. Intra-frame lockout means we wait until | ||
| 648 | * the queue's current frame transmits (with post frame backoff and bursting) | ||
| 649 | * before we transmit anything else and global lockout means we | ||
| 650 | * wait for the whole queue to finish before higher priority queues | ||
| 651 | * can transmit (this is used on beacon and CAB queues). | ||
| 652 | * No lockout means there is no special handling. | ||
| 653 | */ | ||
| 654 | #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ | ||
| 655 | #define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff setting (?) */ | ||
| 656 | #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ | ||
| 657 | #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll (?) */ | ||
| 658 | #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff (?) */ | ||
| 659 | #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch (?) */ | ||
| 660 | #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ | ||
| 661 | #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 | ||
| 662 | #define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 | ||
| 663 | #define AR5K_DCU_MISC_VIRTCOL_IGNORE 2 | ||
| 664 | #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Beacon enable (?) */ | ||
| 665 | #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ | ||
| 666 | #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 | ||
| 667 | #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ | ||
| 668 | #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ | ||
| 669 | #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ | ||
| 670 | #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 | ||
| 671 | #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment (?) */ | ||
| 672 | #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff (?) */ | ||
| 673 | #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision policy (?) */ | ||
| 674 | #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 | ||
| 675 | #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ | ||
| 676 | #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) | ||
| 677 | |||
| 678 | /* | ||
| 679 | * DCU frame sequence number registers | ||
| 680 | */ | ||
| 681 | #define AR5K_DCU_SEQNUM_BASE 0x1140 | ||
| 682 | #define AR5K_DCU_SEQNUM_M 0x00000fff | ||
| 683 | #define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) | ||
| 684 | |||
| 685 | /* | ||
| 686 | * DCU global IFS SIFS registers | ||
| 687 | */ | ||
| 688 | #define AR5K_DCU_GBL_IFS_SIFS 0x1030 | ||
| 689 | #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff | ||
| 690 | |||
| 691 | /* | ||
| 692 | * DCU global IFS slot interval registers | ||
| 693 | */ | ||
| 694 | #define AR5K_DCU_GBL_IFS_SLOT 0x1070 | ||
| 695 | #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff | ||
| 696 | |||
| 697 | /* | ||
| 698 | * DCU global IFS EIFS registers | ||
| 699 | */ | ||
| 700 | #define AR5K_DCU_GBL_IFS_EIFS 0x10b0 | ||
| 701 | #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff | ||
| 702 | |||
| 703 | /* | ||
| 704 | * DCU global IFS misc registers | ||
| 705 | */ | ||
| 706 | #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ | ||
| 707 | #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 | ||
| 708 | #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode (?) */ | ||
| 709 | #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask (?) */ | ||
| 710 | #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 | ||
| 711 | #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 | ||
| 712 | |||
| 713 | /* | ||
| 714 | * DCU frame prefetch control register | ||
| 715 | */ | ||
| 716 | #define AR5K_DCU_FP 0x1230 | ||
| 717 | |||
| 718 | /* | ||
| 719 | * DCU transmit pause control/status register | ||
| 720 | */ | ||
| 721 | #define AR5K_DCU_TXP 0x1270 /* Register Address */ | ||
| 722 | #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask (?) */ | ||
| 723 | #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status (?) */ | ||
| 724 | |||
| 725 | /* | ||
| 726 | * DCU transmit filter register | ||
| 727 | */ | ||
| 728 | #define AR5K_DCU_TX_FILTER 0x1038 | ||
| 729 | |||
| 730 | /* | ||
| 731 | * DCU clear transmit filter register | ||
| 732 | */ | ||
| 733 | #define AR5K_DCU_TX_FILTER_CLR 0x143c | ||
| 734 | |||
| 735 | /* | ||
| 736 | * DCU set transmit filter register | ||
| 737 | */ | ||
| 738 | #define AR5K_DCU_TX_FILTER_SET 0x147c | ||
| 739 | |||
| 740 | /* | ||
| 741 | * Reset control register | ||
| 742 | * | ||
| 743 | * 4 and 8 are not used in 5211/5212 and | ||
| 744 | * 2 means "baseband reset" on 5211/5212. | ||
| 745 | */ | ||
| 746 | #define AR5K_RESET_CTL 0x4000 /* Register Address */ | ||
| 747 | #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ | ||
| 748 | #define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */ | ||
| 749 | #define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */ | ||
| 750 | #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ | ||
| 751 | #define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ | ||
| 752 | #define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ | ||
| 753 | #define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA | \ | ||
| 754 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY) | ||
| 755 | |||
| 756 | /* | ||
| 757 | * Sleep control register | ||
| 758 | */ | ||
| 759 | #define AR5K_SLEEP_CTL 0x4004 /* Register Address */ | ||
| 760 | #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */ | ||
| 761 | #define AR5K_SLEEP_CTL_SLDUR_S 0 | ||
| 762 | #define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */ | ||
| 763 | #define AR5K_SLEEP_CTL_SLE_S 16 | ||
| 764 | #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ | ||
| 765 | #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ | ||
| 766 | #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 | ||
| 767 | #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ | ||
| 768 | |||
| 769 | /* | ||
| 770 | * Interrupt pending register | ||
| 771 | */ | ||
| 772 | #define AR5K_INTPEND 0x4008 | ||
| 773 | #define AR5K_INTPEND_M 0x00000001 | ||
| 774 | |||
| 775 | /* | ||
| 776 | * Sleep force register | ||
| 777 | */ | ||
| 778 | #define AR5K_SFR 0x400c | ||
| 779 | #define AR5K_SFR_M 0x00000001 | ||
| 780 | |||
| 781 | /* | ||
| 782 | * PCI configuration register | ||
| 783 | */ | ||
| 784 | #define AR5K_PCICFG 0x4010 /* Register Address */ | ||
| 785 | #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ | ||
| 786 | #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ | ||
| 787 | #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ | ||
| 788 | #define AR5K_PCICFG_EESIZE_S 3 | ||
| 789 | #define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ | ||
| 790 | #define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ | ||
| 791 | #define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ | ||
| 792 | #define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size (?) [5211+] */ | ||
| 793 | #define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ | ||
| 794 | #define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ | ||
| 795 | #define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ | ||
| 796 | #define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ | ||
| 797 | #define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ | ||
| 798 | #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ | ||
| 799 | #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ | ||
| 800 | #define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ | ||
| 801 | #define AR5K_PCICFG_SL_INPEN 0x00002800 /* Sleep even whith pending interrupts (?) */ | ||
| 802 | #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ | ||
| 803 | #define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ | ||
| 804 | #define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ | ||
| 805 | #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ | ||
| 806 | #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ | ||
| 807 | #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ | ||
| 808 | #define AR5K_PCICFG_LEDBLINK 0x00700000 | ||
| 809 | #define AR5K_PCICFG_LEDBLINK_S 20 | ||
| 810 | #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slow led blink rate (?) [5211+] */ | ||
| 811 | #define AR5K_PCICFG_LEDSTATE \ | ||
| 812 | (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ | ||
| 813 | AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) | ||
| 814 | |||
| 815 | /* | ||
| 816 | * "General Purpose Input/Output" (GPIO) control register | ||
| 817 | * | ||
| 818 | * I'm not sure about this but after looking at the code | ||
| 819 | * for all chipsets here is what i got. | ||
| 820 | * | ||
| 821 | * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) | ||
| 822 | * Mode 0 -> always input | ||
| 823 | * Mode 1 -> output when GPIODO for this GPIO is set to 0 | ||
| 824 | * Mode 2 -> output when GPIODO for this GPIO is set to 1 | ||
| 825 | * Mode 3 -> always output | ||
| 826 | * | ||
| 827 | * For more infos check out get_gpio/set_gpio and | ||
| 828 | * set_gpio_input/set_gpio_output functs. | ||
| 829 | * For more infos on gpio interrupt check out set_gpio_intr. | ||
| 830 | */ | ||
| 831 | #define AR5K_NUM_GPIO 6 | ||
| 832 | |||
| 833 | #define AR5K_GPIOCR 0x4014 /* Register Address */ | ||
| 834 | #define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ | ||
| 835 | #define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is off (?) */ | ||
| 836 | #define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is on */ | ||
| 837 | #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ | ||
| 838 | #define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ | ||
| 839 | #define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ | ||
| 840 | #define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */ | ||
| 841 | #define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */ | ||
| 842 | |||
| 843 | /* | ||
| 844 | * "General Purpose Input/Output" (GPIO) data output register | ||
| 845 | */ | ||
| 846 | #define AR5K_GPIODO 0x4018 | ||
| 847 | |||
| 848 | /* | ||
| 849 | * "General Purpose Input/Output" (GPIO) data input register | ||
| 850 | */ | ||
| 851 | #define AR5K_GPIODI 0x401c | ||
| 852 | #define AR5K_GPIODI_M 0x0000002f | ||
| 853 | |||
| 854 | |||
| 855 | /* | ||
| 856 | * Silicon revision register | ||
| 857 | */ | ||
| 858 | #define AR5K_SREV 0x4020 /* Register Address */ | ||
| 859 | #define AR5K_SREV_REV 0x0000000f /* Mask for revision */ | ||
| 860 | #define AR5K_SREV_REV_S 0 | ||
| 861 | #define AR5K_SREV_VER 0x000000ff /* Mask for version */ | ||
| 862 | #define AR5K_SREV_VER_S 4 | ||
| 863 | |||
| 864 | |||
| 865 | |||
| 866 | /*====EEPROM REGISTERS====*/ | ||
| 867 | |||
| 868 | /* | ||
| 869 | * EEPROM access registers | ||
| 870 | * | ||
| 871 | * Here we got a difference between 5210/5211-12 | ||
| 872 | * read data register for 5210 is at 0x6800 and | ||
| 873 | * status register is at 0x6c00. There is also | ||
| 874 | * no eeprom command register on 5210 and the | ||
| 875 | * offsets are different. | ||
| 876 | * | ||
| 877 | * To read eeprom data for a specific offset: | ||
| 878 | * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) | ||
| 879 | * read AR5K_EEPROM_BASE +(4 * offset) | ||
| 880 | * check the eeprom status register | ||
| 881 | * and read eeprom data register. | ||
| 882 | * | ||
| 883 | * 5211 - write offset to AR5K_EEPROM_BASE | ||
| 884 | * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD | ||
| 885 | * check the eeprom status register | ||
| 886 | * and read eeprom data register. | ||
| 887 | * | ||
| 888 | * To write eeprom data for a specific offset: | ||
| 889 | * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) | ||
| 890 | * write data to AR5K_EEPROM_BASE +(4 * offset) | ||
| 891 | * check the eeprom status register | ||
| 892 | * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD | ||
| 893 | * 5212 write offset to AR5K_EEPROM_BASE | ||
| 894 | * write data to data register | ||
| 895 | * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD | ||
| 896 | * check the eeprom status register | ||
| 897 | * | ||
| 898 | * For more infos check eeprom_* functs and the ar5k.c | ||
| 899 | * file posted in madwifi-devel mailing list. | ||
| 900 | * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 | ||
| 901 | * | ||
| 902 | */ | ||
| 903 | #define AR5K_EEPROM_BASE 0x6000 | ||
| 904 | |||
| 905 | /* | ||
| 906 | * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE) | ||
| 907 | */ | ||
| 908 | #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ | ||
| 909 | #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ | ||
| 910 | #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ | ||
| 911 | #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ | ||
| 912 | #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ | ||
| 913 | |||
| 914 | #define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */ | ||
| 915 | #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */ | ||
| 916 | #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */ | ||
| 917 | #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */ | ||
| 918 | #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 | ||
| 919 | #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */ | ||
| 920 | #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 | ||
| 921 | #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */ | ||
| 922 | #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 | ||
| 923 | #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */ | ||
| 924 | #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 | ||
| 925 | #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */ | ||
| 926 | #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 | ||
| 927 | #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */ | ||
| 928 | #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 | ||
| 929 | #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */ | ||
| 930 | #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 | ||
| 931 | #define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */ | ||
| 932 | #define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */ | ||
| 933 | #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) | ||
| 934 | #define AR5K_EEPROM_INFO_CKSUM 0xffff | ||
| 935 | #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) | ||
| 936 | |||
| 937 | #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */ | ||
| 938 | #define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */ | ||
| 939 | #define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */ | ||
| 940 | #define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */ | ||
| 941 | #define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */ | ||
| 942 | #define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain ee_cck_ofdm_power_delta (eeprom_read_modes) */ | ||
| 943 | #define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc*, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */ | ||
| 944 | #define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */ | ||
| 945 | #define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */ | ||
| 946 | #define AR5K_EEPROM_VERSION_4_3 0x4003 | ||
| 947 | #define AR5K_EEPROM_VERSION_4_4 0x4004 | ||
| 948 | #define AR5K_EEPROM_VERSION_4_5 0x4005 | ||
| 949 | #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ | ||
| 950 | #define AR5K_EEPROM_VERSION_4_7 0x3007 | ||
| 951 | |||
| 952 | #define AR5K_EEPROM_MODE_11A 0 | ||
| 953 | #define AR5K_EEPROM_MODE_11B 1 | ||
| 954 | #define AR5K_EEPROM_MODE_11G 2 | ||
| 955 | |||
| 956 | #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */ | ||
| 957 | #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) | ||
| 958 | #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) | ||
| 959 | #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) | ||
| 960 | #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ | ||
| 961 | #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ | ||
| 962 | #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) | ||
| 963 | #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz (?) */ | ||
| 964 | #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ | ||
| 965 | |||
| 966 | #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c | ||
| 967 | #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 | ||
| 968 | #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 | ||
| 969 | #define AR5K_EEPROM_RFKILL_POLARITY_S 1 | ||
| 970 | |||
| 971 | /* Newer EEPROMs are using a different offset */ | ||
| 972 | #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ | ||
| 973 | (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) | ||
| 974 | |||
| 975 | #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) | ||
| 976 | #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) | ||
| 977 | #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) | ||
| 978 | |||
| 979 | /* calibration settings */ | ||
| 980 | #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) | ||
| 981 | #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) | ||
| 982 | #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) | ||
| 983 | #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */ | ||
| 984 | |||
| 985 | /* [3.1 - 3.3] */ | ||
| 986 | #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec | ||
| 987 | #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed | ||
| 988 | |||
| 989 | /* Misc values available since EEPROM 4.0 */ | ||
| 990 | #define AR5K_EEPROM_MISC0 0x00c4 | ||
| 991 | #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) | ||
| 992 | #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) | ||
| 993 | #define AR5K_EEPROM_MISC1 0x00c5 | ||
| 994 | #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) | ||
| 995 | #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) | ||
| 996 | |||
| 997 | /* | ||
| 998 | * EEPROM data register | ||
| 999 | */ | ||
| 1000 | #define AR5K_EEPROM_DATA_5211 0x6004 | ||
| 1001 | #define AR5K_EEPROM_DATA_5210 0x6800 | ||
| 1002 | #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1003 | AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) | ||
| 1004 | |||
| 1005 | /* | ||
| 1006 | * EEPROM command register | ||
| 1007 | */ | ||
| 1008 | #define AR5K_EEPROM_CMD 0x6008 /* Register Addres */ | ||
| 1009 | #define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */ | ||
| 1010 | #define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */ | ||
| 1011 | #define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */ | ||
| 1012 | |||
| 1013 | /* | ||
| 1014 | * EEPROM status register | ||
| 1015 | */ | ||
| 1016 | #define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */ | ||
| 1017 | #define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */ | ||
| 1018 | #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1019 | AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) | ||
| 1020 | #define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */ | ||
| 1021 | #define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */ | ||
| 1022 | #define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */ | ||
| 1023 | #define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ | ||
| 1024 | |||
| 1025 | /* | ||
| 1026 | * EEPROM config register (?) | ||
| 1027 | */ | ||
| 1028 | #define AR5K_EEPROM_CFG 0x6010 | ||
| 1029 | |||
| 1030 | |||
| 1031 | |||
| 1032 | /* | ||
| 1033 | * Protocol Control Unit (PCU) registers | ||
| 1034 | */ | ||
| 1035 | /* | ||
| 1036 | * Used for checking initial register writes | ||
| 1037 | * during channel reset (see reset func) | ||
| 1038 | */ | ||
| 1039 | #define AR5K_PCU_MIN 0x8000 | ||
| 1040 | #define AR5K_PCU_MAX 0x8fff | ||
| 1041 | |||
| 1042 | /* | ||
| 1043 | * First station id register (MAC address in lower 32 bits) | ||
| 1044 | */ | ||
| 1045 | #define AR5K_STA_ID0 0x8000 | ||
| 1046 | |||
| 1047 | /* | ||
| 1048 | * Second station id register (MAC address in upper 16 bits) | ||
| 1049 | */ | ||
| 1050 | #define AR5K_STA_ID1 0x8004 /* Register Address */ | ||
| 1051 | #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ | ||
| 1052 | #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ | ||
| 1053 | #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting (?) */ | ||
| 1054 | #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ | ||
| 1055 | #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ | ||
| 1056 | #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ | ||
| 1057 | #define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/ | ||
| 1058 | #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1059 | AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) | ||
| 1060 | #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ | ||
| 1061 | #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ | ||
| 1062 | #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS (?) */ | ||
| 1063 | #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS (?) */ | ||
| 1064 | #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ | ||
| 1065 | |||
| 1066 | /* | ||
| 1067 | * First BSSID register (MAC address, lower 32bits) | ||
| 1068 | */ | ||
| 1069 | #define AR5K_BSS_ID0 0x8008 | ||
| 1070 | |||
| 1071 | /* | ||
| 1072 | * Second BSSID register (MAC address in upper 16 bits) | ||
| 1073 | * | ||
| 1074 | * AID: Association ID | ||
| 1075 | */ | ||
| 1076 | #define AR5K_BSS_ID1 0x800c | ||
| 1077 | #define AR5K_BSS_ID1_AID 0xffff0000 | ||
| 1078 | #define AR5K_BSS_ID1_AID_S 16 | ||
| 1079 | |||
| 1080 | /* | ||
| 1081 | * Backoff slot time register | ||
| 1082 | */ | ||
| 1083 | #define AR5K_SLOT_TIME 0x8010 | ||
| 1084 | |||
| 1085 | /* | ||
| 1086 | * ACK/CTS timeout register | ||
| 1087 | */ | ||
| 1088 | #define AR5K_TIME_OUT 0x8014 /* Register Address */ | ||
| 1089 | #define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */ | ||
| 1090 | #define AR5K_TIME_OUT_ACK_S 0 | ||
| 1091 | #define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */ | ||
| 1092 | #define AR5K_TIME_OUT_CTS_S 16 | ||
| 1093 | |||
| 1094 | /* | ||
| 1095 | * RSSI threshold register | ||
| 1096 | */ | ||
| 1097 | #define AR5K_RSSI_THR 0x8018 /* Register Address */ | ||
| 1098 | #define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */ | ||
| 1099 | #define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */ | ||
| 1100 | #define AR5K_RSSI_THR_BMISS_5210_S 8 | ||
| 1101 | #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */ | ||
| 1102 | #define AR5K_RSSI_THR_BMISS_5211_S 8 | ||
| 1103 | #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1104 | AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) | ||
| 1105 | #define AR5K_RSSI_THR_BMISS_S 8 | ||
| 1106 | |||
| 1107 | /* | ||
| 1108 | * 5210 has more PCU registers because there is no QCU/DCU | ||
| 1109 | * so queue parameters are set here, this way a lot common | ||
| 1110 | * registers have different address for 5210. To make things | ||
| 1111 | * easier we define a macro based on ah->ah_version for common | ||
| 1112 | * registers with different addresses and common flags. | ||
| 1113 | */ | ||
| 1114 | |||
| 1115 | /* | ||
| 1116 | * Retry limit register | ||
| 1117 | * | ||
| 1118 | * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) | ||
| 1119 | */ | ||
| 1120 | #define AR5K_NODCU_RETRY_LMT 0x801c /*Register Address */ | ||
| 1121 | #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ | ||
| 1122 | #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 | ||
| 1123 | #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ | ||
| 1124 | #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 | ||
| 1125 | #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */ | ||
| 1126 | #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 | ||
| 1127 | #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */ | ||
| 1128 | #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 | ||
| 1129 | #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */ | ||
| 1130 | #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 | ||
| 1131 | |||
| 1132 | /* | ||
| 1133 | * Transmit latency register | ||
| 1134 | */ | ||
| 1135 | #define AR5K_USEC_5210 0x8020 /* Register Address [5210] */ | ||
| 1136 | #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ | ||
| 1137 | #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1138 | AR5K_USEC_5210 : AR5K_USEC_5211) | ||
| 1139 | #define AR5K_USEC_1 0x0000007f | ||
| 1140 | #define AR5K_USEC_1_S 0 | ||
| 1141 | #define AR5K_USEC_32 0x00003f80 | ||
| 1142 | #define AR5K_USEC_32_S 7 | ||
| 1143 | #define AR5K_USEC_TX_LATENCY_5211 0x007fc000 | ||
| 1144 | #define AR5K_USEC_TX_LATENCY_5211_S 14 | ||
| 1145 | #define AR5K_USEC_RX_LATENCY_5211 0x1f800000 | ||
| 1146 | #define AR5K_USEC_RX_LATENCY_5211_S 23 | ||
| 1147 | #define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */ | ||
| 1148 | #define AR5K_USEC_TX_LATENCY_5210_S 14 | ||
| 1149 | #define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */ | ||
| 1150 | #define AR5K_USEC_RX_LATENCY_5210_S 20 | ||
| 1151 | |||
| 1152 | /* | ||
| 1153 | * PCU beacon control register | ||
| 1154 | */ | ||
| 1155 | #define AR5K_BEACON_5210 0x8024 | ||
| 1156 | #define AR5K_BEACON_5211 0x8020 | ||
| 1157 | #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1158 | AR5K_BEACON_5210 : AR5K_BEACON_5211) | ||
| 1159 | #define AR5K_BEACON_PERIOD 0x0000ffff | ||
| 1160 | #define AR5K_BEACON_PERIOD_S 0 | ||
| 1161 | #define AR5K_BEACON_TIM 0x007f0000 | ||
| 1162 | #define AR5K_BEACON_TIM_S 16 | ||
| 1163 | #define AR5K_BEACON_ENABLE 0x00800000 | ||
| 1164 | #define AR5K_BEACON_RESET_TSF 0x01000000 | ||
| 1165 | |||
| 1166 | /* | ||
| 1167 | * CFP period register | ||
| 1168 | */ | ||
| 1169 | #define AR5K_CFP_PERIOD_5210 0x8028 | ||
| 1170 | #define AR5K_CFP_PERIOD_5211 0x8024 | ||
| 1171 | #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1172 | AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) | ||
| 1173 | |||
| 1174 | /* | ||
| 1175 | * Next beacon time register | ||
| 1176 | */ | ||
| 1177 | #define AR5K_TIMER0_5210 0x802c | ||
| 1178 | #define AR5K_TIMER0_5211 0x8028 | ||
| 1179 | #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1180 | AR5K_TIMER0_5210 : AR5K_TIMER0_5211) | ||
| 1181 | |||
| 1182 | /* | ||
| 1183 | * Next DMA beacon alert register | ||
| 1184 | */ | ||
| 1185 | #define AR5K_TIMER1_5210 0x8030 | ||
| 1186 | #define AR5K_TIMER1_5211 0x802c | ||
| 1187 | #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1188 | AR5K_TIMER1_5210 : AR5K_TIMER1_5211) | ||
| 1189 | |||
| 1190 | /* | ||
| 1191 | * Next software beacon alert register | ||
| 1192 | */ | ||
| 1193 | #define AR5K_TIMER2_5210 0x8034 | ||
| 1194 | #define AR5K_TIMER2_5211 0x8030 | ||
| 1195 | #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1196 | AR5K_TIMER2_5210 : AR5K_TIMER2_5211) | ||
| 1197 | |||
| 1198 | /* | ||
| 1199 | * Next ATIM window time register | ||
| 1200 | */ | ||
| 1201 | #define AR5K_TIMER3_5210 0x8038 | ||
| 1202 | #define AR5K_TIMER3_5211 0x8034 | ||
| 1203 | #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1204 | AR5K_TIMER3_5210 : AR5K_TIMER3_5211) | ||
| 1205 | |||
| 1206 | |||
| 1207 | /* | ||
| 1208 | * 5210 First inter frame spacing register (IFS) | ||
| 1209 | */ | ||
| 1210 | #define AR5K_IFS0 0x8040 | ||
| 1211 | #define AR5K_IFS0_SIFS 0x000007ff | ||
| 1212 | #define AR5K_IFS0_SIFS_S 0 | ||
| 1213 | #define AR5K_IFS0_DIFS 0x007ff800 | ||
| 1214 | #define AR5K_IFS0_DIFS_S 11 | ||
| 1215 | |||
| 1216 | /* | ||
| 1217 | * 5210 Second inter frame spacing register (IFS) | ||
| 1218 | */ | ||
| 1219 | #define AR5K_IFS1 0x8044 | ||
| 1220 | #define AR5K_IFS1_PIFS 0x00000fff | ||
| 1221 | #define AR5K_IFS1_PIFS_S 0 | ||
| 1222 | #define AR5K_IFS1_EIFS 0x03fff000 | ||
| 1223 | #define AR5K_IFS1_EIFS_S 12 | ||
| 1224 | #define AR5K_IFS1_CS_EN 0x04000000 | ||
| 1225 | |||
| 1226 | |||
| 1227 | /* | ||
| 1228 | * CFP duration register | ||
| 1229 | */ | ||
| 1230 | #define AR5K_CFP_DUR_5210 0x8048 | ||
| 1231 | #define AR5K_CFP_DUR_5211 0x8038 | ||
| 1232 | #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1233 | AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) | ||
| 1234 | |||
| 1235 | /* | ||
| 1236 | * Receive filter register | ||
| 1237 | * TODO: Get these out of ar5xxx.h on ath5k | ||
| 1238 | */ | ||
| 1239 | #define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ | ||
| 1240 | #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ | ||
| 1241 | #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1242 | AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) | ||
| 1243 | #define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ | ||
| 1244 | #define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ | ||
| 1245 | #define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ | ||
| 1246 | #define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ | ||
| 1247 | #define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ | ||
| 1248 | #define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ | ||
| 1249 | #define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ | ||
| 1250 | #define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ | ||
| 1251 | #define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ | ||
| 1252 | #define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ | ||
| 1253 | #define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ | ||
| 1254 | #define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ | ||
| 1255 | #define AR5K_RX_FILTER_PHYERR \ | ||
| 1256 | ((ah->ah_version == AR5K_AR5211 ? \ | ||
| 1257 | AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212)) | ||
| 1258 | #define AR5K_RX_FILTER_RADARERR \ | ||
| 1259 | ((ah->ah_version == AR5K_AR5211 ? \ | ||
| 1260 | AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212)) | ||
| 1261 | |||
| 1262 | /* | ||
| 1263 | * Multicast filter register (lower 32 bits) | ||
| 1264 | */ | ||
| 1265 | #define AR5K_MCAST_FILTER0_5210 0x8050 | ||
| 1266 | #define AR5K_MCAST_FILTER0_5211 0x8040 | ||
| 1267 | #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1268 | AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) | ||
| 1269 | |||
| 1270 | /* | ||
| 1271 | * Multicast filter register (higher 16 bits) | ||
| 1272 | */ | ||
| 1273 | #define AR5K_MCAST_FILTER1_5210 0x8054 | ||
| 1274 | #define AR5K_MCAST_FILTER1_5211 0x8044 | ||
| 1275 | #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1276 | AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) | ||
| 1277 | |||
| 1278 | |||
| 1279 | /* | ||
| 1280 | * Transmit mask register (lower 32 bits) [5210] | ||
| 1281 | */ | ||
| 1282 | #define AR5K_TX_MASK0 0x8058 | ||
| 1283 | |||
| 1284 | /* | ||
| 1285 | * Transmit mask register (higher 16 bits) [5210] | ||
| 1286 | */ | ||
| 1287 | #define AR5K_TX_MASK1 0x805c | ||
| 1288 | |||
| 1289 | /* | ||
| 1290 | * Clear transmit mask [5210] | ||
| 1291 | */ | ||
| 1292 | #define AR5K_CLR_TMASK 0x8060 | ||
| 1293 | |||
| 1294 | /* | ||
| 1295 | * Trigger level register (before transmission) [5210] | ||
| 1296 | */ | ||
| 1297 | #define AR5K_TRIG_LVL 0x8064 | ||
| 1298 | |||
| 1299 | |||
| 1300 | /* | ||
| 1301 | * PCU control register | ||
| 1302 | * | ||
| 1303 | * Only DIS_RX is used in the code, the rest i guess are | ||
| 1304 | * for tweaking/diagnostics. | ||
| 1305 | */ | ||
| 1306 | #define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ | ||
| 1307 | #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ | ||
| 1308 | #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1309 | AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) | ||
| 1310 | #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 | ||
| 1311 | #define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs (?) */ | ||
| 1312 | #define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs (?) */ | ||
| 1313 | #define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption (?) */ | ||
| 1314 | #define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption (?) */ | ||
| 1315 | #define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ | ||
| 1316 | #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ | ||
| 1317 | #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 | ||
| 1318 | #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1319 | AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) | ||
| 1320 | #define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */ | ||
| 1321 | #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 | ||
| 1322 | #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1323 | AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) | ||
| 1324 | #define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 | ||
| 1325 | #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 | ||
| 1326 | #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1327 | AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) | ||
| 1328 | #define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 | ||
| 1329 | #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 | ||
| 1330 | #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1331 | AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) | ||
| 1332 | #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Scrambler seed (?) */ | ||
| 1333 | #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 | ||
| 1334 | #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1335 | AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) | ||
| 1336 | #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ | ||
| 1337 | #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ | ||
| 1338 | #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask (?) */ | ||
| 1339 | #define AR5K_DIAG_SW_SCRAM_SEED_S 10 | ||
| 1340 | #define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ | ||
| 1341 | #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 | ||
| 1342 | #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 | ||
| 1343 | #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1344 | AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) | ||
| 1345 | #define AR5K_DIAG_SW_OBSPT_M 0x000c0000 | ||
| 1346 | #define AR5K_DIAG_SW_OBSPT_S 18 | ||
| 1347 | |||
| 1348 | /* | ||
| 1349 | * TSF (clock) register (lower 32 bits) | ||
| 1350 | */ | ||
| 1351 | #define AR5K_TSF_L32_5210 0x806c | ||
| 1352 | #define AR5K_TSF_L32_5211 0x804c | ||
| 1353 | #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1354 | AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) | ||
| 1355 | |||
| 1356 | /* | ||
| 1357 | * TSF (clock) register (higher 32 bits) | ||
| 1358 | */ | ||
| 1359 | #define AR5K_TSF_U32_5210 0x8070 | ||
| 1360 | #define AR5K_TSF_U32_5211 0x8050 | ||
| 1361 | #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1362 | AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) | ||
| 1363 | |||
| 1364 | /* | ||
| 1365 | * Last beacon timestamp register | ||
| 1366 | */ | ||
| 1367 | #define AR5K_LAST_TSTP 0x8080 | ||
| 1368 | |||
| 1369 | /* | ||
| 1370 | * ADDAC test register [5211+] | ||
| 1371 | */ | ||
| 1372 | #define AR5K_ADDAC_TEST 0x8054 | ||
| 1373 | #define AR5K_ADDAC_TEST_TXCONT 0x00000001 | ||
| 1374 | |||
| 1375 | /* | ||
| 1376 | * Default antenna register [5211+] | ||
| 1377 | */ | ||
| 1378 | #define AR5K_DEFAULT_ANTENNA 0x8058 | ||
| 1379 | |||
| 1380 | |||
| 1381 | |||
| 1382 | /* | ||
| 1383 | * Retry count register [5210] | ||
| 1384 | */ | ||
| 1385 | #define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */ | ||
| 1386 | #define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */ | ||
| 1387 | #define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */ | ||
| 1388 | |||
| 1389 | /* | ||
| 1390 | * Back-off status register [5210] | ||
| 1391 | */ | ||
| 1392 | #define AR5K_BACKOFF 0x8088 /* Register Address [5210] */ | ||
| 1393 | #define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */ | ||
| 1394 | #define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */ | ||
| 1395 | |||
| 1396 | |||
| 1397 | |||
| 1398 | /* | ||
| 1399 | * NAV register (current) | ||
| 1400 | */ | ||
| 1401 | #define AR5K_NAV_5210 0x808c | ||
| 1402 | #define AR5K_NAV_5211 0x8084 | ||
| 1403 | #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1404 | AR5K_NAV_5210 : AR5K_NAV_5211) | ||
| 1405 | |||
| 1406 | /* | ||
| 1407 | * RTS success register | ||
| 1408 | */ | ||
| 1409 | #define AR5K_RTS_OK_5210 0x8090 | ||
| 1410 | #define AR5K_RTS_OK_5211 0x8088 | ||
| 1411 | #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1412 | AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) | ||
| 1413 | |||
| 1414 | /* | ||
| 1415 | * RTS failure register | ||
| 1416 | */ | ||
| 1417 | #define AR5K_RTS_FAIL_5210 0x8094 | ||
| 1418 | #define AR5K_RTS_FAIL_5211 0x808c | ||
| 1419 | #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1420 | AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) | ||
| 1421 | |||
| 1422 | /* | ||
| 1423 | * ACK failure register | ||
| 1424 | */ | ||
| 1425 | #define AR5K_ACK_FAIL_5210 0x8098 | ||
| 1426 | #define AR5K_ACK_FAIL_5211 0x8090 | ||
| 1427 | #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1428 | AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) | ||
| 1429 | |||
| 1430 | /* | ||
| 1431 | * FCS failure register | ||
| 1432 | */ | ||
| 1433 | #define AR5K_FCS_FAIL_5210 0x809c | ||
| 1434 | #define AR5K_FCS_FAIL_5211 0x8094 | ||
| 1435 | #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1436 | AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) | ||
| 1437 | |||
| 1438 | /* | ||
| 1439 | * Beacon count register | ||
| 1440 | */ | ||
| 1441 | #define AR5K_BEACON_CNT_5210 0x80a0 | ||
| 1442 | #define AR5K_BEACON_CNT_5211 0x8098 | ||
| 1443 | #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1444 | AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) | ||
| 1445 | |||
| 1446 | |||
| 1447 | /*===5212 Specific PCU registers===*/ | ||
| 1448 | |||
| 1449 | /* | ||
| 1450 | * XR (eXtended Range) mode register | ||
| 1451 | */ | ||
| 1452 | #define AR5K_XRMODE 0x80c0 | ||
| 1453 | #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f | ||
| 1454 | #define AR5K_XRMODE_POLL_TYPE_S 0 | ||
| 1455 | #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c | ||
| 1456 | #define AR5K_XRMODE_POLL_SUBTYPE_S 2 | ||
| 1457 | #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 | ||
| 1458 | #define AR5K_XRMODE_SIFS_DELAY 0x000fff00 | ||
| 1459 | #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 | ||
| 1460 | #define AR5K_XRMODE_FRAME_HOLD_S 20 | ||
| 1461 | |||
| 1462 | /* | ||
| 1463 | * XR delay register | ||
| 1464 | */ | ||
| 1465 | #define AR5K_XRDELAY 0x80c4 | ||
| 1466 | #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff | ||
| 1467 | #define AR5K_XRDELAY_SLOT_DELAY_S 0 | ||
| 1468 | #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 | ||
| 1469 | #define AR5K_XRDELAY_CHIRP_DELAY_S 16 | ||
| 1470 | |||
| 1471 | /* | ||
| 1472 | * XR timeout register | ||
| 1473 | */ | ||
| 1474 | #define AR5K_XRTIMEOUT 0x80c8 | ||
| 1475 | #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff | ||
| 1476 | #define AR5K_XRTIMEOUT_CHIRP_S 0 | ||
| 1477 | #define AR5K_XRTIMEOUT_POLL_M 0xffff0000 | ||
| 1478 | #define AR5K_XRTIMEOUT_POLL_S 16 | ||
| 1479 | |||
| 1480 | /* | ||
| 1481 | * XR chirp register | ||
| 1482 | */ | ||
| 1483 | #define AR5K_XRCHIRP 0x80cc | ||
| 1484 | #define AR5K_XRCHIRP_SEND 0x00000001 | ||
| 1485 | #define AR5K_XRCHIRP_GAP 0xffff0000 | ||
| 1486 | |||
| 1487 | /* | ||
| 1488 | * XR stomp register | ||
| 1489 | */ | ||
| 1490 | #define AR5K_XRSTOMP 0x80d0 | ||
| 1491 | #define AR5K_XRSTOMP_TX 0x00000001 | ||
| 1492 | #define AR5K_XRSTOMP_RX_ABORT 0x00000002 | ||
| 1493 | #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 | ||
| 1494 | |||
| 1495 | /* | ||
| 1496 | * First enhanced sleep register | ||
| 1497 | */ | ||
| 1498 | #define AR5K_SLEEP0 0x80d4 | ||
| 1499 | #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff | ||
| 1500 | #define AR5K_SLEEP0_NEXT_DTIM_S 0 | ||
| 1501 | #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 | ||
| 1502 | #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 | ||
| 1503 | #define AR5K_SLEEP0_CABTO 0xff000000 | ||
| 1504 | #define AR5K_SLEEP0_CABTO_S 24 | ||
| 1505 | |||
| 1506 | /* | ||
| 1507 | * Second enhanced sleep register | ||
| 1508 | */ | ||
| 1509 | #define AR5K_SLEEP1 0x80d8 | ||
| 1510 | #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff | ||
| 1511 | #define AR5K_SLEEP1_NEXT_TIM_S 0 | ||
| 1512 | #define AR5K_SLEEP1_BEACON_TO 0xff000000 | ||
| 1513 | #define AR5K_SLEEP1_BEACON_TO_S 24 | ||
| 1514 | |||
| 1515 | /* | ||
| 1516 | * Third enhanced sleep register | ||
| 1517 | */ | ||
| 1518 | #define AR5K_SLEEP2 0x80dc | ||
| 1519 | #define AR5K_SLEEP2_TIM_PER 0x0000ffff | ||
| 1520 | #define AR5K_SLEEP2_TIM_PER_S 0 | ||
| 1521 | #define AR5K_SLEEP2_DTIM_PER 0xffff0000 | ||
| 1522 | #define AR5K_SLEEP2_DTIM_PER_S 16 | ||
| 1523 | |||
| 1524 | /* | ||
| 1525 | * BSSID mask registers | ||
| 1526 | */ | ||
| 1527 | #define AR5K_BSS_IDM0 0x80e0 | ||
| 1528 | #define AR5K_BSS_IDM1 0x80e4 | ||
| 1529 | |||
| 1530 | /* | ||
| 1531 | * TX power control (TPC) register | ||
| 1532 | */ | ||
| 1533 | #define AR5K_TXPC 0x80e8 | ||
| 1534 | #define AR5K_TXPC_ACK_M 0x0000003f | ||
| 1535 | #define AR5K_TXPC_ACK_S 0 | ||
| 1536 | #define AR5K_TXPC_CTS_M 0x00003f00 | ||
| 1537 | #define AR5K_TXPC_CTS_S 8 | ||
| 1538 | #define AR5K_TXPC_CHIRP_M 0x003f0000 | ||
| 1539 | #define AR5K_TXPC_CHIRP_S 22 | ||
| 1540 | |||
| 1541 | /* | ||
| 1542 | * Profile count registers | ||
| 1543 | */ | ||
| 1544 | #define AR5K_PROFCNT_TX 0x80ec | ||
| 1545 | #define AR5K_PROFCNT_RX 0x80f0 | ||
| 1546 | #define AR5K_PROFCNT_RXCLR 0x80f4 | ||
| 1547 | #define AR5K_PROFCNT_CYCLE 0x80f8 | ||
| 1548 | |||
| 1549 | /* | ||
| 1550 | * TSF parameter register | ||
| 1551 | */ | ||
| 1552 | #define AR5K_TSF_PARM 0x8104 | ||
| 1553 | #define AR5K_TSF_PARM_INC_M 0x000000ff | ||
| 1554 | #define AR5K_TSF_PARM_INC_S 0 | ||
| 1555 | |||
| 1556 | /* | ||
| 1557 | * PHY error filter register | ||
| 1558 | */ | ||
| 1559 | #define AR5K_PHY_ERR_FIL 0x810c | ||
| 1560 | #define AR5K_PHY_ERR_FIL_RADAR 0x00000020 | ||
| 1561 | #define AR5K_PHY_ERR_FIL_OFDM 0x00020000 | ||
| 1562 | #define AR5K_PHY_ERR_FIL_CCK 0x02000000 | ||
| 1563 | |||
| 1564 | /* | ||
| 1565 | * Rate duration register | ||
| 1566 | */ | ||
| 1567 | #define AR5K_RATE_DUR_BASE 0x8700 | ||
| 1568 | #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) | ||
| 1569 | |||
| 1570 | /*===5212 end===*/ | ||
| 1571 | |||
| 1572 | /* | ||
| 1573 | * Key table (WEP) register | ||
| 1574 | */ | ||
| 1575 | #define AR5K_KEYTABLE_0_5210 0x9000 | ||
| 1576 | #define AR5K_KEYTABLE_0_5211 0x8800 | ||
| 1577 | #define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5)) | ||
| 1578 | #define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) << 5)) | ||
| 1579 | #define AR5K_KEYTABLE(_n) (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1580 | AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n)) | ||
| 1581 | #define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2)) | ||
| 1582 | #define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5) | ||
| 1583 | #define AR5K_KEYTABLE_TYPE_40 0x00000000 | ||
| 1584 | #define AR5K_KEYTABLE_TYPE_104 0x00000001 | ||
| 1585 | #define AR5K_KEYTABLE_TYPE_128 0x00000003 | ||
| 1586 | #define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /* [5212+] */ | ||
| 1587 | #define AR5K_KEYTABLE_TYPE_AES 0x00000005 /* [5211+] */ | ||
| 1588 | #define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /* [5212+] */ | ||
| 1589 | #define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /* [5211+] */ | ||
| 1590 | #define AR5K_KEYTABLE_ANTENNA 0x00000008 /* [5212+] */ | ||
| 1591 | #define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6) | ||
| 1592 | #define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7) | ||
| 1593 | #define AR5K_KEYTABLE_VALID 0x00008000 | ||
| 1594 | |||
| 1595 | /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit | ||
| 1596 | * WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit | ||
| 1597 | * WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit | ||
| 1598 | * | ||
| 1599 | * Some vendors have introduced bigger WEP keys to address | ||
| 1600 | * security vulnerabilities in WEP. This includes: | ||
| 1601 | * | ||
| 1602 | * WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit | ||
| 1603 | * | ||
| 1604 | * We can expand this if we find ar5k Atheros cards with a larger | ||
| 1605 | * key table size. | ||
| 1606 | */ | ||
| 1607 | #define AR5K_KEYTABLE_SIZE_5210 64 | ||
| 1608 | #define AR5K_KEYTABLE_SIZE_5211 128 | ||
| 1609 | #define AR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1610 | AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) | ||
| 1611 | |||
| 1612 | |||
| 1613 | /*===PHY REGISTERS===*/ | ||
| 1614 | |||
| 1615 | /* | ||
| 1616 | * PHY register | ||
| 1617 | */ | ||
| 1618 | #define AR5K_PHY_BASE 0x9800 | ||
| 1619 | #define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) | ||
| 1620 | #define AR5K_PHY_SHIFT_2GHZ 0x00004007 | ||
| 1621 | #define AR5K_PHY_SHIFT_5GHZ 0x00000007 | ||
| 1622 | |||
| 1623 | /* | ||
| 1624 | * PHY frame control register [5110] /turbo mode register [5111+] | ||
| 1625 | * | ||
| 1626 | * There is another frame control register for [5111+] | ||
| 1627 | * at address 0x9944 (see below) but the 2 first flags | ||
| 1628 | * are common here between 5110 frame control register | ||
| 1629 | * and [5111+] turbo mode register, so this also works as | ||
| 1630 | * a "turbo mode register" for 5110. We treat this one as | ||
| 1631 | * a frame control register for 5110 below. | ||
| 1632 | */ | ||
| 1633 | #define AR5K_PHY_TURBO 0x9804 | ||
| 1634 | #define AR5K_PHY_TURBO_MODE 0x00000001 | ||
| 1635 | #define AR5K_PHY_TURBO_SHORT 0x00000002 | ||
| 1636 | |||
| 1637 | /* | ||
| 1638 | * PHY agility command register | ||
| 1639 | */ | ||
| 1640 | #define AR5K_PHY_AGC 0x9808 | ||
| 1641 | #define AR5K_PHY_AGC_DISABLE 0x08000000 | ||
| 1642 | |||
| 1643 | /* | ||
| 1644 | * PHY timing register [5112+] | ||
| 1645 | */ | ||
| 1646 | #define AR5K_PHY_TIMING_3 0x9814 | ||
| 1647 | #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 | ||
| 1648 | #define AR5K_PHY_TIMING_3_DSC_MAN_S 17 | ||
| 1649 | #define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 | ||
| 1650 | #define AR5K_PHY_TIMING_3_DSC_EXP_S 13 | ||
| 1651 | |||
| 1652 | /* | ||
| 1653 | * PHY chip revision register | ||
| 1654 | */ | ||
| 1655 | #define AR5K_PHY_CHIP_ID 0x9818 | ||
| 1656 | |||
| 1657 | /* | ||
| 1658 | * PHY activation register | ||
| 1659 | */ | ||
| 1660 | #define AR5K_PHY_ACT 0x981c | ||
| 1661 | #define AR5K_PHY_ACT_ENABLE 0x00000001 | ||
| 1662 | #define AR5K_PHY_ACT_DISABLE 0x00000002 | ||
| 1663 | |||
| 1664 | /* | ||
| 1665 | * PHY signal register | ||
| 1666 | */ | ||
| 1667 | #define AR5K_PHY_SIG 0x9858 | ||
| 1668 | #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 | ||
| 1669 | #define AR5K_PHY_SIG_FIRSTEP_S 12 | ||
| 1670 | #define AR5K_PHY_SIG_FIRPWR 0x03fc0000 | ||
| 1671 | #define AR5K_PHY_SIG_FIRPWR_S 18 | ||
| 1672 | |||
| 1673 | /* | ||
| 1674 | * PHY coarse agility control register | ||
| 1675 | */ | ||
| 1676 | #define AR5K_PHY_AGCCOARSE 0x985c | ||
| 1677 | #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 | ||
| 1678 | #define AR5K_PHY_AGCCOARSE_LO_S 7 | ||
| 1679 | #define AR5K_PHY_AGCCOARSE_HI 0x003f8000 | ||
| 1680 | #define AR5K_PHY_AGCCOARSE_HI_S 15 | ||
| 1681 | |||
| 1682 | /* | ||
| 1683 | * PHY agility control register | ||
| 1684 | */ | ||
| 1685 | #define AR5K_PHY_AGCCTL 0x9860 /* Register address */ | ||
| 1686 | #define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ | ||
| 1687 | #define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ | ||
| 1688 | |||
| 1689 | /* | ||
| 1690 | * PHY noise floor status register | ||
| 1691 | */ | ||
| 1692 | #define AR5K_PHY_NF 0x9864 | ||
| 1693 | #define AR5K_PHY_NF_M 0x000001ff | ||
| 1694 | #define AR5K_PHY_NF_ACTIVE 0x00000100 | ||
| 1695 | #define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) | ||
| 1696 | #define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) | ||
| 1697 | #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) | ||
| 1698 | |||
| 1699 | /* | ||
| 1700 | * PHY ADC saturation register [5110] | ||
| 1701 | */ | ||
| 1702 | #define AR5K_PHY_ADCSAT 0x9868 | ||
| 1703 | #define AR5K_PHY_ADCSAT_ICNT 0x0001f800 | ||
| 1704 | #define AR5K_PHY_ADCSAT_ICNT_S 11 | ||
| 1705 | #define AR5K_PHY_ADCSAT_THR 0x000007e0 | ||
| 1706 | #define AR5K_PHY_ADCSAT_THR_S 5 | ||
| 1707 | |||
| 1708 | /* | ||
| 1709 | * PHY sleep registers [5112+] | ||
| 1710 | */ | ||
| 1711 | #define AR5K_PHY_SCR 0x9870 | ||
| 1712 | #define AR5K_PHY_SCR_32MHZ 0x0000001f | ||
| 1713 | #define AR5K_PHY_SLMT 0x9874 | ||
| 1714 | #define AR5K_PHY_SLMT_32MHZ 0x0000007f | ||
| 1715 | #define AR5K_PHY_SCAL 0x9878 | ||
| 1716 | #define AR5K_PHY_SCAL_32MHZ 0x0000000e | ||
| 1717 | |||
| 1718 | /* | ||
| 1719 | * PHY PLL (Phase Locked Loop) control register | ||
| 1720 | */ | ||
| 1721 | #define AR5K_PHY_PLL 0x987c | ||
| 1722 | #define AR5K_PHY_PLL_20MHZ 0x13 /* For half rate (?) [5111+] */ | ||
| 1723 | #define AR5K_PHY_PLL_40MHZ_5211 0x18 /* For 802.11a */ | ||
| 1724 | #define AR5K_PHY_PLL_40MHZ_5212 0x000000aa | ||
| 1725 | #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ | ||
| 1726 | AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) | ||
| 1727 | #define AR5K_PHY_PLL_44MHZ_5211 0x19 /* For 802.11b/g */ | ||
| 1728 | #define AR5K_PHY_PLL_44MHZ_5212 0x000000ab | ||
| 1729 | #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ | ||
| 1730 | AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) | ||
| 1731 | #define AR5K_PHY_PLL_RF5111 0x00000000 | ||
| 1732 | #define AR5K_PHY_PLL_RF5112 0x00000040 | ||
| 1733 | |||
| 1734 | /* | ||
| 1735 | * RF Buffer register | ||
| 1736 | * | ||
| 1737 | * There are some special control registers on the RF chip | ||
| 1738 | * that hold various operation settings related mostly to | ||
| 1739 | * the analog parts (channel, gain adjustment etc). | ||
| 1740 | * | ||
| 1741 | * We don't write on those registers directly but | ||
| 1742 | * we send a data packet on the buffer register and | ||
| 1743 | * then write on another special register to notify hw | ||
| 1744 | * to apply the settings. This is done so that control registers | ||
| 1745 | * can be dynamicaly programmed during operation and the settings | ||
| 1746 | * are applied faster on the hw. | ||
| 1747 | * | ||
| 1748 | * We sent such data packets during rf initialization and channel change | ||
| 1749 | * through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions. | ||
| 1750 | * | ||
| 1751 | * The data packets we send during initializadion are inside ath5k_ini_rf | ||
| 1752 | * struct (see ath5k_hw.h) and each one is related to an "rf register bank". | ||
| 1753 | * We use *rfregs functions to modify them acording to current operation | ||
| 1754 | * mode and eeprom values and pass them all together to the chip. | ||
| 1755 | * | ||
| 1756 | * It's obvious from the code that 0x989c is the buffer register but | ||
| 1757 | * for the other special registers that we write to after sending each | ||
| 1758 | * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers | ||
| 1759 | * for now. It's interesting that they are also used for some other operations. | ||
| 1760 | * | ||
| 1761 | * Also check out hw.h and U.S. Patent 6677779 B1 (about buffer | ||
| 1762 | * registers and control registers): | ||
| 1763 | * | ||
| 1764 | * http://www.google.com/patents?id=qNURAAAAEBAJ | ||
| 1765 | */ | ||
| 1766 | |||
| 1767 | #define AR5K_RF_BUFFER 0x989c | ||
| 1768 | #define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */ | ||
| 1769 | #define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */ | ||
| 1770 | #define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */ | ||
| 1771 | |||
| 1772 | #define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 */ | ||
| 1773 | /* Channel set on 5111 */ | ||
| 1774 | /* Used to read radio revision*/ | ||
| 1775 | |||
| 1776 | #define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 */ | ||
| 1777 | /* Bank 0,1,2,6 on 5111 */ | ||
| 1778 | /* Bank 1 on 5112 */ | ||
| 1779 | /* Used during activation on 5111 */ | ||
| 1780 | |||
| 1781 | #define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 */ | ||
| 1782 | /* Used during activation on 5111 */ | ||
| 1783 | /* Channel on 5112 */ | ||
| 1784 | /* Bank 6 on 5112 */ | ||
| 1785 | |||
| 1786 | #define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */ | ||
| 1787 | |||
| 1788 | /* | ||
| 1789 | * PHY RF stage register [5210] | ||
| 1790 | */ | ||
| 1791 | #define AR5K_PHY_RFSTG 0x98d4 | ||
| 1792 | #define AR5K_PHY_RFSTG_DISABLE 0x00000021 | ||
| 1793 | |||
| 1794 | /* | ||
| 1795 | * PHY receiver delay register [5111+] | ||
| 1796 | */ | ||
| 1797 | #define AR5K_PHY_RX_DELAY 0x9914 | ||
| 1798 | #define AR5K_PHY_RX_DELAY_M 0x00003fff | ||
| 1799 | |||
| 1800 | /* | ||
| 1801 | * PHY timing I(nphase) Q(adrature) control register [5111+] | ||
| 1802 | */ | ||
| 1803 | #define AR5K_PHY_IQ 0x9920 /* Register address */ | ||
| 1804 | #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ | ||
| 1805 | #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ | ||
| 1806 | #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 | ||
| 1807 | #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ | ||
| 1808 | #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 | ||
| 1809 | #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 | ||
| 1810 | #define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ | ||
| 1811 | |||
| 1812 | |||
| 1813 | /* | ||
| 1814 | * PHY PAPD probe register [5111+ (?)] | ||
| 1815 | * Is this only present in 5212 ? | ||
| 1816 | * Because it's always 0 in 5211 initialization code | ||
| 1817 | */ | ||
| 1818 | #define AR5K_PHY_PAPD_PROBE 0x9930 | ||
| 1819 | #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 | ||
| 1820 | #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 | ||
| 1821 | #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 | ||
| 1822 | #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ | ||
| 1823 | #define AR5K_PHY_PAPD_PROBE_TYPE_S 23 | ||
| 1824 | #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 | ||
| 1825 | #define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 | ||
| 1826 | #define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 | ||
| 1827 | #define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 | ||
| 1828 | #define AR5K_PHY_PAPD_PROBE_GAINF_S 25 | ||
| 1829 | #define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */ | ||
| 1830 | #define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */ | ||
| 1831 | |||
| 1832 | |||
| 1833 | /* | ||
| 1834 | * PHY TX rate power registers [5112+] | ||
| 1835 | */ | ||
| 1836 | #define AR5K_PHY_TXPOWER_RATE1 0x9934 | ||
| 1837 | #define AR5K_PHY_TXPOWER_RATE2 0x9938 | ||
| 1838 | #define AR5K_PHY_TXPOWER_RATE_MAX 0x993c | ||
| 1839 | #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 | ||
| 1840 | #define AR5K_PHY_TXPOWER_RATE3 0xa234 | ||
| 1841 | #define AR5K_PHY_TXPOWER_RATE4 0xa238 | ||
| 1842 | |||
| 1843 | /* | ||
| 1844 | * PHY frame control register [5111+] | ||
| 1845 | */ | ||
| 1846 | #define AR5K_PHY_FRAME_CTL_5210 0x9804 | ||
| 1847 | #define AR5K_PHY_FRAME_CTL_5211 0x9944 | ||
| 1848 | #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ | ||
| 1849 | AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) | ||
| 1850 | /*---[5111+]---*/ | ||
| 1851 | #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 | ||
| 1852 | #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 | ||
| 1853 | /*---[5110/5111]---*/ | ||
| 1854 | #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 | ||
| 1855 | #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 | ||
| 1856 | #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* illegal rate */ | ||
| 1857 | #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* illegal length */ | ||
| 1858 | #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 | ||
| 1859 | #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* tx underrun */ | ||
| 1860 | #define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ | ||
| 1861 | AR5K_PHY_FRAME_CTL_TXURN_ERR | \ | ||
| 1862 | AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ | ||
| 1863 | AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ | ||
| 1864 | AR5K_PHY_FRAME_CTL_PARITY_ERR | \ | ||
| 1865 | AR5K_PHY_FRAME_CTL_TIMING_ERR | ||
| 1866 | |||
| 1867 | /* | ||
| 1868 | * PHY radar detection register [5111+] | ||
| 1869 | */ | ||
| 1870 | #define AR5K_PHY_RADAR 0x9954 | ||
| 1871 | |||
| 1872 | /* Radar enable ........ ........ ........ .......1 */ | ||
| 1873 | #define AR5K_PHY_RADAR_ENABLE 0x00000001 | ||
| 1874 | #define AR5K_PHY_RADAR_DISABLE 0x00000000 | ||
| 1875 | #define AR5K_PHY_RADAR_ENABLE_S 0 | ||
| 1876 | |||
| 1877 | /* This is the value found on the card .1.111.1 .1.1.... 111....1 1...1... | ||
| 1878 | at power on. */ | ||
| 1879 | #define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188 | ||
| 1880 | |||
| 1881 | /* This is the value found on the card .1.1.111 ..11...1 .1...1.1 1...11.1 | ||
| 1882 | after DFS is enabled */ | ||
| 1883 | #define AR5K_PHY_RADAR_ENABLED_AR5213 0x5731458d | ||
| 1884 | |||
| 1885 | /* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........ | ||
| 1886 | * power out threshold. | ||
| 1887 | * 7-bits, standard power range {0..127} in 1/2 dBm units. */ | ||
| 1888 | #define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000 | ||
| 1889 | #define AR5K_PHY_RADAR_FIRPWROUTTHR_S 24 | ||
| 1890 | |||
| 1891 | /* Radar RSSI/SNR threshold. ........ 111111.. ........ ........ | ||
| 1892 | * 6-bits, dBm range {0..63} in dBm units. */ | ||
| 1893 | #define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000 | ||
| 1894 | #define AR5K_PHY_RADAR_RADARRSSITHR_S 18 | ||
| 1895 | |||
| 1896 | /* Pulse height threshold ........ ......11 1111.... ........ | ||
| 1897 | * 6-bits, dBm range {0..63} in dBm units. */ | ||
| 1898 | #define AR5K_PHY_RADAR_PULSEHEIGHTTHR 0x0003f000 | ||
| 1899 | #define AR5K_PHY_RADAR_PULSEHEIGHTTHR_S 12 | ||
| 1900 | |||
| 1901 | /* Pulse RSSI/SNR threshold ........ ........ ....1111 11...... | ||
| 1902 | * 6-bits, dBm range {0..63} in dBm units. */ | ||
| 1903 | #define AR5K_PHY_RADAR_PULSERSSITHR 0x00000fc0 | ||
| 1904 | #define AR5K_PHY_RADAR_PULSERSSITHR_S 6 | ||
| 1905 | |||
| 1906 | /* Inband threshold ........ ........ ........ ..11111. | ||
| 1907 | * 5-bits, units unknown {0..31} (? MHz ?) */ | ||
| 1908 | #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e | ||
| 1909 | #define AR5K_PHY_RADAR_INBANDTHR_S 1 | ||
| 1910 | |||
| 1911 | /* | ||
| 1912 | * PHY antenna switch table registers [5110] | ||
| 1913 | */ | ||
| 1914 | #define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 | ||
| 1915 | #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 | ||
| 1916 | |||
| 1917 | /* | ||
| 1918 | * PHY clock sleep registers [5112+] | ||
| 1919 | */ | ||
| 1920 | #define AR5K_PHY_SCLOCK 0x99f0 | ||
| 1921 | #define AR5K_PHY_SCLOCK_32MHZ 0x0000000c | ||
| 1922 | #define AR5K_PHY_SDELAY 0x99f4 | ||
| 1923 | #define AR5K_PHY_SDELAY_32MHZ 0x000000ff | ||
| 1924 | #define AR5K_PHY_SPENDING 0x99f8 | ||
| 1925 | #define AR5K_PHY_SPENDING_RF5111 0x00000018 | ||
| 1926 | #define AR5K_PHY_SPENDING_RF5112 0x00000014 | ||
| 1927 | |||
| 1928 | /* | ||
| 1929 | * Misc PHY/radio registers [5110 - 5111] | ||
| 1930 | */ | ||
| 1931 | #define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ | ||
| 1932 | #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) | ||
| 1933 | #define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ | ||
| 1934 | #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) | ||
| 1935 | |||
| 1936 | /* | ||
| 1937 | * PHY timing IQ calibration result register [5111+] | ||
| 1938 | */ | ||
| 1939 | #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ | ||
| 1940 | #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ | ||
| 1941 | #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */ | ||
| 1942 | |||
| 1943 | /* | ||
| 1944 | * PHY current RSSI register [5111+] | ||
| 1945 | */ | ||
| 1946 | #define AR5K_PHY_CURRENT_RSSI 0x9c1c | ||
| 1947 | |||
| 1948 | /* | ||
| 1949 | * PHY PCDAC TX power table | ||
| 1950 | */ | ||
| 1951 | #define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180 | ||
| 1952 | #define AR5K_PHY_PCDAC_TXPOWER_BASE_5413 0xa280 | ||
| 1953 | #define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF5413 ? \ | ||
| 1954 | AR5K_PHY_PCDAC_TXPOWER_BASE_5413 :\ | ||
| 1955 | AR5K_PHY_PCDAC_TXPOWER_BASE_5211) | ||
| 1956 | #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) | ||
| 1957 | |||
| 1958 | /* | ||
| 1959 | * PHY mode register [5111+] | ||
| 1960 | */ | ||
| 1961 | #define AR5K_PHY_MODE 0x0a200 /* Register address */ | ||
| 1962 | #define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation mask*/ | ||
| 1963 | #define AR5K_PHY_MODE_MOD_OFDM 0 | ||
| 1964 | #define AR5K_PHY_MODE_MOD_CCK 1 | ||
| 1965 | #define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode mask */ | ||
| 1966 | #define AR5K_PHY_MODE_FREQ_5GHZ 0 | ||
| 1967 | #define AR5K_PHY_MODE_FREQ_2GHZ 2 | ||
| 1968 | #define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Dynamic OFDM/CCK mode mask [5112+] */ | ||
| 1969 | #define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ | ||
| 1970 | #define AR5K_PHY_MODE_RAD_RF5111 0 | ||
| 1971 | #define AR5K_PHY_MODE_RAD_RF5112 8 | ||
| 1972 | #define AR5K_PHY_MODE_XR 0x00000010 /* [5112+] */ | ||
| 1973 | |||
| 1974 | /* | ||
| 1975 | * PHY CCK transmit control register [5111+ (?)] | ||
| 1976 | */ | ||
| 1977 | #define AR5K_PHY_CCKTXCTL 0xa204 | ||
| 1978 | #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 | ||
| 1979 | #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 | ||
| 1980 | |||
| 1981 | /* | ||
| 1982 | * PHY 2GHz gain register [5111+] | ||
| 1983 | */ | ||
| 1984 | #define AR5K_PHY_GAIN_2GHZ 0xa20c | ||
| 1985 | #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 | ||
| 1986 | #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 | ||
| 1987 | #define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c | ||