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-rw-r--r--drivers/net/wireless/ath5k/reg.h679
1 files changed, 409 insertions, 270 deletions
diff --git a/drivers/net/wireless/ath5k/reg.h b/drivers/net/wireless/ath5k/reg.h
index 7562bf173d3e..e557fe178bbf 100644
--- a/drivers/net/wireless/ath5k/reg.h
+++ b/drivers/net/wireless/ath5k/reg.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright (c) 2007 Nick Kossifidis <mickflemm@gmail.com> 2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007 Michael Taylor <mike.taylor@apprion.com> 4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
5 * 5 *
6 * Permission to use, copy, modify, and distribute this software for any 6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above 7 * purpose with or without fee is hereby granted, provided that the above
@@ -29,6 +29,10 @@
29 * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf 29 * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf
30 * 30 *
31 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf 31 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
32 *
33 * This file also contains register values found on a memory dump of
34 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
35 * released by Atheros and on various debug messages found on the net.
32 */ 36 */
33 37
34 38
@@ -295,7 +299,7 @@
295#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ 299#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */
296#define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */ 300#define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */
297#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ 301#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */
298#define AR5K_ISR_BRSSI 0x00020000 302#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
299#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ 303#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */
300#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 304#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
301#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ 305#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */
@@ -303,46 +307,56 @@
303#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ 307#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */
304#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ 308#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */
305#define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 309#define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */
306#define AR5K_ISR_TIM 0x00800000 /* [5210] */ 310#define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
307#define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ 311#define AR5K_ISR_TIM 0x00800000 /* [5211+] */
308#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ 312#define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
309#define AR5K_ISR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ 313 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
310#define AR5K_ISR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ 314#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */
311#define AR5K_ISR_QTRIG 0x08000000 /* [5211+] */ 315#define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
316#define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
317#define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
312 318
313/* 319/*
314 * Secondary status registers [5211+] (0 - 4) 320 * Secondary status registers [5211+] (0 - 4)
315 * 321 *
316 * I guess from the names that these give the status for each 322 * These give the status for each QCU, only QCUs 0-9 are
317 * queue, that's why only masks are defined here, haven't got 323 * represented.
318 * any info about them (couldn't find them anywhere in ar5k code).
319 */ 324 */
320#define AR5K_SISR0 0x0084 /* Register Address [5211+] */ 325#define AR5K_SISR0 0x0084 /* Register Address [5211+] */
321#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ 326#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
327#define AR5K_SISR0_QCU_TXOK_S 0
322#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ 328#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
329#define AR5K_SISR0_QCU_TXDESC_S 16
323 330
324#define AR5K_SISR1 0x0088 /* Register Address [5211+] */ 331#define AR5K_SISR1 0x0088 /* Register Address [5211+] */
325#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ 332#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
333#define AR5K_SISR1_QCU_TXERR_S 0
326#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ 334#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
335#define AR5K_SISR1_QCU_TXEOL_S 16
327 336
328#define AR5K_SISR2 0x008c /* Register Address [5211+] */ 337#define AR5K_SISR2 0x008c /* Register Address [5211+] */
329#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ 338#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
339#define AR5K_SISR2_QCU_TXURN_S 0
330#define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */ 340#define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */
331#define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */ 341#define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */
332#define AR5K_SISR2_DPERR 0x00400000 /* Det par Error (?) */ 342#define AR5K_SISR2_DPERR 0x00400000 /* Bus parity error */
333#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ 343#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */
334#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ 344#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */
335#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */ 345#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */
336#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 346#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
337#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 347#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
338#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ 348#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */
349#define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */
339 350
340#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ 351#define AR5K_SISR3 0x0090 /* Register Address [5211+] */
341#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 352#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
353#define AR5K_SISR3_QCBORN_S 0
342#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ 354#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
355#define AR5K_SISR3_QCBRURN_S 16
343 356
344#define AR5K_SISR4 0x0094 /* Register Address [5211+] */ 357#define AR5K_SISR4 0x0094 /* Register Address [5211+] */
345#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ 358#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */
359#define AR5K_SISR4_QTRIG_S 0
346 360
347/* 361/*
348 * Shadow read-and-clear interrupt status registers [5211+] 362 * Shadow read-and-clear interrupt status registers [5211+]
@@ -379,7 +393,7 @@
379#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ 393#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/
380#define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */ 394#define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */
381#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ 395#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/
382#define AR5K_IMR_BRSSI 0x00020000 396#define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
383#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ 397#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/
384#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 398#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
385#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ 399#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */
@@ -387,12 +401,14 @@
387#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ 401#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/
388#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ 402#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */
389#define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 403#define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */
404#define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
390#define AR5K_IMR_TIM 0x00800000 /* [5211+] */ 405#define AR5K_IMR_TIM 0x00800000 /* [5211+] */
391#define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ 406#define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
407 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
392#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ 408#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/
393#define AR5K_IMR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ 409#define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */
394#define AR5K_IMR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ 410#define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */
395#define AR5K_IMR_QTRIG 0x08000000 /* [5211+] */ 411#define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
396 412
397/* 413/*
398 * Secondary interrupt mask registers [5211+] (0 - 4) 414 * Secondary interrupt mask registers [5211+] (0 - 4)
@@ -414,13 +430,14 @@
414#define AR5K_SIMR2_QCU_TXURN_S 0 430#define AR5K_SIMR2_QCU_TXURN_S 0
415#define AR5K_SIMR2_MCABT 0x00100000 /* Master Cycle Abort */ 431#define AR5K_SIMR2_MCABT 0x00100000 /* Master Cycle Abort */
416#define AR5K_SIMR2_SSERR 0x00200000 /* Signaled System Error */ 432#define AR5K_SIMR2_SSERR 0x00200000 /* Signaled System Error */
417#define AR5K_SIMR2_DPERR 0x00400000 /* Det par Error (?) */ 433#define AR5K_SIMR2_DPERR 0x00400000 /* Bus parity error */
418#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ 434#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */
419#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ 435#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */
420#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */ 436#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */
421#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 437#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
422#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 438#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
423#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ 439#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */
440#define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */
424 441
425#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ 442#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */
426#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 443#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
@@ -586,15 +603,15 @@
586#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ 603#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */
587#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ 604#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */
588#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ 605#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */
589#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ 606#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */
590#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ 607#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */
591#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ 608#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */
592#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ 609#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */
593#define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ 610#define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */
594#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ 611#define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */
595#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */ 612#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */
596#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled */ 613#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */
597#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME enalbed */ 614#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */
598#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */ 615#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */
599#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */ 616#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */
600#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */ 617#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */
@@ -663,6 +680,7 @@
663#define AR5K_DCU_LCL_IFS_CW_MAX_S 10 680#define AR5K_DCU_LCL_IFS_CW_MAX_S 10
664#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ 681#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */
665#define AR5K_DCU_LCL_IFS_AIFS_S 20 682#define AR5K_DCU_LCL_IFS_AIFS_S 20
683#define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */
666#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) 684#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
667 685
668/* 686/*
@@ -691,11 +709,7 @@
691/* 709/*
692 * DCU misc registers [5211+] 710 * DCU misc registers [5211+]
693 * 711 *
694 * For some of the registers i couldn't find in the code 712 * Note: Arbiter lockout control controls the
695 * (only backoff stuff is there realy) i tried to match the
696 * names with 802.11e parameters etc, so i guess VIRTCOL here
697 * means Virtual Collision and HCFPOLL means Hybrid Coordination
698 * factor Poll (CF- Poll). Arbiter lockout control controls the
699 * behaviour on low priority queues when we have multiple queues 713 * behaviour on low priority queues when we have multiple queues
700 * with pending frames. Intra-frame lockout means we wait until 714 * with pending frames. Intra-frame lockout means we wait until
701 * the queue's current frame transmits (with post frame backoff and bursting) 715 * the queue's current frame transmits (with post frame backoff and bursting)
@@ -705,15 +719,20 @@
705 * No lockout means there is no special handling. 719 * No lockout means there is no special handling.
706 */ 720 */
707#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ 721#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
708#define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff threshold */ 722#define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */
723#define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series
724 station RTS/data failure count
725 reset policy (?) */
726#define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series
727 CW reset policy */
728#define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */
709#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ 729#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */
710#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */ 730#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
711#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */ 731#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */
712#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */ 732#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
713#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ 733#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */
714#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 734#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
715#define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 735#define AR5K_DCU_MISC_VIRTCOL_IGNORE 1
716#define AR5K_DCU_MISC_VIRTCOL_IGNORE 2
717#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */ 736#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */
718#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ 737#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */
719#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 738#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
@@ -768,8 +787,9 @@
768#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */ 787#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */
769#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */ 788#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */
770#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */ 789#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */
790#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10
771#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */ 791#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */
772#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFC cnt reset policy (?) */ 792#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */
773#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */ 793#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */
774#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */ 794#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */
775 795
@@ -820,8 +840,6 @@
820#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ 840#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */
821#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ 841#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */
822#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ 842#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */
823#define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA | \
824 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY)
825 843
826/* 844/*
827 * Sleep control register 845 * Sleep control register
@@ -833,9 +851,11 @@
833#define AR5K_SLEEP_CTL_SLE_S 16 851#define AR5K_SLEEP_CTL_SLE_S 16
834#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ 852#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */
835#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ 853#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */
836#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 854#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */
837#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ 855#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */
838/* more bits */ 856#define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */
857#define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */
858#define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */
839 859
840/* 860/*
841 * Interrupt pending register 861 * Interrupt pending register
@@ -851,27 +871,28 @@
851 871
852/* 872/*
853 * PCI configuration register 873 * PCI configuration register
874 * TODO: Fix LED stuff
854 */ 875 */
855#define AR5K_PCICFG 0x4010 /* Register Address */ 876#define AR5K_PCICFG 0x4010 /* Register Address */
856#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ 877#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */
857#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock (?) */ 878#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */
858#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ 879#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */
859#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ 880#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */
860#define AR5K_PCICFG_EESIZE_S 3 881#define AR5K_PCICFG_EESIZE_S 3
861#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ 882#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */
862#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ 883#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */
863#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ 884#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */
864#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size (?) [5211+] */ 885#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */
865#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ 886#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */
866#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ 887#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */
867#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ 888#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */
868#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ 889#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */
869#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ 890#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */
870#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ 891#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */
871#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ 892#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */
872#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ 893#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */
873#define AR5K_PCICFG_UNK 0x00001000 /* Passed on some parts durring attach (?) */ 894#define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */
874#define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts (?) */ 895#define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts*/
875#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ 896#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */
876#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ 897#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */
877#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ 898#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */
@@ -884,7 +905,8 @@
884#define AR5K_PCICFG_LEDSTATE \ 905#define AR5K_PCICFG_LEDSTATE \
885 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ 906 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
886 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) 907 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
887#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate (field) */ 908#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */
909#define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24
888 910
889/* 911/*
890 * "General Purpose Input/Output" (GPIO) control register 912 * "General Purpose Input/Output" (GPIO) control register
@@ -906,8 +928,8 @@
906 928
907#define AR5K_GPIOCR 0x4014 /* Register Address */ 929#define AR5K_GPIOCR 0x4014 /* Register Address */
908#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ 930#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */
909#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is off (?) */ 931#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */
910#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is on */ 932#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */
911#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ 933#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */
912#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ 934#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */
913#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ 935#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */
@@ -925,7 +947,6 @@
925#define AR5K_GPIODI 0x401c 947#define AR5K_GPIODI 0x401c
926#define AR5K_GPIODI_M 0x0000002f 948#define AR5K_GPIODI_M 0x0000002f
927 949
928
929/* 950/*
930 * Silicon revision register 951 * Silicon revision register
931 */ 952 */
@@ -935,7 +956,59 @@
935#define AR5K_SREV_VER 0x000000ff /* Mask for version */ 956#define AR5K_SREV_VER 0x000000ff /* Mask for version */
936#define AR5K_SREV_VER_S 4 957#define AR5K_SREV_VER_S 4
937 958
959/*
960 * TXE write posting register
961 */
962#define AR5K_TXEPOST 0x4028
963
964/*
965 * QCU sleep mask
966 */
967#define AR5K_QCU_SLEEP_MASK 0x402c
968
969/* 0x4068 is compression buffer configuration
970 * register on 5414 and pm configuration register
971 * on 5424 and newer pci-e chips. */
972
973/*
974 * Compression buffer configuration
975 * register (enable/disable) [5414]
976 */
977#define AR5K_5414_CBCFG 0x4068
978#define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */
979
980/*
981 * PCI-E Power managment configuration
982 * and status register [5424+]
983 */
984#define AR5K_PCIE_PM_CTL 0x4068 /* Register address */
985/* Only 5424 */
986#define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1
987 when d2_sleep_en is asserted */
988#define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */
989#define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */
990#define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes
991 down */
992/* Wake On Wireless */
993#define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */
994#define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */
995#define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */
996#define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
997#define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
998#define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
999#define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
1000
1001/*
1002 * PCI-E Workaround enable register
1003 */
1004#define AR5K_PCIE_WAEN 0x407c
938 1005
1006/*
1007 * PCI-E Serializer/Desirializer
1008 * registers
1009 */
1010#define AR5K_PCIE_SERDES 0x4080
1011#define AR5K_PCIE_SERDES_RESET 0x4084
939 1012
940/*====EEPROM REGISTERS====*/ 1013/*====EEPROM REGISTERS====*/
941 1014
@@ -977,98 +1050,6 @@
977#define AR5K_EEPROM_BASE 0x6000 1050#define AR5K_EEPROM_BASE 0x6000
978 1051
979/* 1052/*
980 * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
981 */
982#define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */
983#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */
984#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */
985#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
986#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
987
988#define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */
989#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */
990#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */
991#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */
992#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
993#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */
994#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
995#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */
996#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
997#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */
998#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
999#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */
1000#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
1001#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */
1002#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
1003#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */
1004#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
1005#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
1006#define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
1007#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE)
1008#define AR5K_EEPROM_INFO_CKSUM 0xffff
1009#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
1010
1011#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */
1012#define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */
1013#define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */
1014#define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */
1015#define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
1016#define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain ee_cck_ofdm_power_delta (eeprom_read_modes) */
1017#define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc*, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
1018#define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */
1019#define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */
1020#define AR5K_EEPROM_VERSION_4_3 0x4003
1021#define AR5K_EEPROM_VERSION_4_4 0x4004
1022#define AR5K_EEPROM_VERSION_4_5 0x4005
1023#define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */
1024#define AR5K_EEPROM_VERSION_4_7 0x4007
1025
1026#define AR5K_EEPROM_MODE_11A 0
1027#define AR5K_EEPROM_MODE_11B 1
1028#define AR5K_EEPROM_MODE_11G 2
1029
1030#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */
1031#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
1032#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
1033#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
1034#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */
1035#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */
1036#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
1037#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz (?) */
1038#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */
1039
1040#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
1041#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
1042#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
1043#define AR5K_EEPROM_RFKILL_POLARITY_S 1
1044
1045/* Newer EEPROMs are using a different offset */
1046#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
1047 (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
1048
1049#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
1050#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff))
1051#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff))
1052
1053/* calibration settings */
1054#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
1055#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
1056#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
1057#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */
1058
1059/* [3.1 - 3.3] */
1060#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
1061#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
1062
1063/* Misc values available since EEPROM 4.0 */
1064#define AR5K_EEPROM_MISC0 0x00c4
1065#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
1066#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
1067#define AR5K_EEPROM_MISC1 0x00c5
1068#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
1069#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
1070
1071/*
1072 * EEPROM data register 1053 * EEPROM data register
1073 */ 1054 */
1074#define AR5K_EEPROM_DATA_5211 0x6004 1055#define AR5K_EEPROM_DATA_5211 0x6004
@@ -1100,14 +1081,28 @@
1100 * EEPROM config register 1081 * EEPROM config register
1101 */ 1082 */
1102#define AR5K_EEPROM_CFG 0x6010 /* Register Addres */ 1083#define AR5K_EEPROM_CFG 0x6010 /* Register Addres */
1103#define AR5K_EEPROM_CFG_SIZE_OVR 0x00000001 1084#define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */
1085#define AR5K_EEPROM_CFG_SIZE_AUTO 0
1086#define AR5K_EEPROM_CFG_SIZE_4KBIT 1
1087#define AR5K_EEPROM_CFG_SIZE_8KBIT 2
1088#define AR5K_EEPROM_CFG_SIZE_16KBIT 3
1104#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */ 1089#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */
1105#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */ 1090#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */
1106#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protectio key */ 1091#define AR5K_EEPROM_CFG_CLK_RATE_S 3
1092#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
1093#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
1094#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
1095#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */
1096#define AR5K_EEPROM_CFG_PROT_KEY_S 8
1107#define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */ 1097#define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */
1108 1098
1109 1099
1110/* 1100/*
1101 * TODO: Wake On Wireless registers
1102 * Range 0x7000 - 0x7ce0
1103 */
1104
1105/*
1111 * Protocol Control Unit (PCU) registers 1106 * Protocol Control Unit (PCU) registers
1112 */ 1107 */
1113/* 1108/*
@@ -1139,11 +1134,13 @@
1139#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ 1134#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */
1140#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */ 1135#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */
1141#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */ 1136#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */
1142#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ 1137#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate for ACK/CTS [5211+] */
1143#define AR5K_STA_ID1_SELF_GEN_SECTORE 0x04000000 /* Self generate sectore (?) */ 1138#define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */
1144#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */ 1139#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */
1145#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Keysearch mode (?) */ 1140#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */
1146#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */ 1141#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */
1142#define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */
1143#define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */
1147 1144
1148/* 1145/*
1149 * First BSSID register (MAC address, lower 32bits) 1146 * First BSSID register (MAC address, lower 32bits)
@@ -1402,16 +1399,16 @@
1402#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 1399#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
1403#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ 1400#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
1404 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) 1401 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
1405#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 1402#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Corrupted FCS */
1406#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 1403#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
1407#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ 1404#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
1408 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) 1405 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
1409#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 1406#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Dump channel info */
1410#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 1407#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
1411#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ 1408#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1412 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) 1409 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
1413#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Enable scrambler seed */ 1410#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */
1414#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 1411#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200
1415#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ 1412#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
1416 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) 1413 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
1417#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ 1414#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */
@@ -1420,12 +1417,15 @@
1420#define AR5K_DIAG_SW_SCRAM_SEED_S 10 1417#define AR5K_DIAG_SW_SCRAM_SEED_S 10
1421#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ 1418#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */
1422#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 1419#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
1423#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 1420#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */
1424#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ 1421#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
1425 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) 1422 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
1426#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 1423#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */
1427#define AR5K_DIAG_SW_OBSPT_S 18 1424#define AR5K_DIAG_SW_OBSPT_S 18
1428/* more bits */ 1425#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 /* Force RX Clear high */
1426#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 /* Ignore virtual carrier sense */
1427#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 /* Force channel idle high */
1428#define AR5K_DIAG_SW_PHEAR_ME 0x0080000 /* ??? */
1429 1429
1430/* 1430/*
1431 * TSF (clock) register (lower 32 bits) 1431 * TSF (clock) register (lower 32 bits)
@@ -1636,16 +1636,16 @@
1636 * 1636 *
1637 * XXX: PCDAC steps (0.5dbm) or DBM ? 1637 * XXX: PCDAC steps (0.5dbm) or DBM ?
1638 * 1638 *
1639 * XXX: Mask changes for newer chips to 7f
1640 * like tx power table ?
1641 */ 1639 */
1642#define AR5K_TXPC 0x80e8 /* Register Address */ 1640#define AR5K_TXPC 0x80e8 /* Register Address */
1643#define AR5K_TXPC_ACK_M 0x0000003f /* Mask for ACK tx power */ 1641#define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */
1644#define AR5K_TXPC_ACK_S 0 1642#define AR5K_TXPC_ACK_S 0
1645#define AR5K_TXPC_CTS_M 0x00003f00 /* Mask for CTS tx power */ 1643#define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */
1646#define AR5K_TXPC_CTS_S 8 1644#define AR5K_TXPC_CTS_S 8
1647#define AR5K_TXPC_CHIRP_M 0x003f0000 /* Mask for CHIRP tx power */ 1645#define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */
1648#define AR5K_TXPC_CHIRP_S 22 1646#define AR5K_TXPC_CHIRP_S 16
1647#define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */
1648#define AR5K_TXPC_DOPPLER_S 24
1649 1649
1650/* 1650/*
1651 * Profile count registers 1651 * Profile count registers
@@ -1656,14 +1656,19 @@
1656#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */ 1656#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */
1657 1657
1658/* 1658/*
1659 * Quiet (period) control registers (?) 1659 * Quiet period control registers
1660 */ 1660 */
1661#define AR5K_QUIET_CTL1 0x80fc /* Register Address */ 1661#define AR5K_QUIET_CTL1 0x80fc /* Register Address */
1662#define AR5K_QUIET_CTL1_NEXT_QT 0x0000ffff /* Mask for next quiet (period?) (?) */ 1662#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */
1663#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet (period?) */ 1663#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0
1664#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */
1665#define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 /* Send ACK/CTS during quiet period */
1666
1664#define AR5K_QUIET_CTL2 0x8100 /* Register Address */ 1667#define AR5K_QUIET_CTL2 0x8100 /* Register Address */
1665#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period (?) */ 1668#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */
1666#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet duration (?) */ 1669#define AR5K_QUIET_CTL2_QT_PER_S 0
1670#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */
1671#define AR5K_QUIET_CTL2_QT_DUR_S 16
1667 1672
1668/* 1673/*
1669 * TSF parameter register 1674 * TSF parameter register
@@ -1673,12 +1678,15 @@
1673#define AR5K_TSF_PARM_INC_S 0 1678#define AR5K_TSF_PARM_INC_S 0
1674 1679
1675/* 1680/*
1676 * QoS register (?) 1681 * QoS NOACK policy
1677 */ 1682 */
1678#define AR5K_QOS 0x8108 /* Register Address */ 1683#define AR5K_QOS_NOACK 0x8108 /* Register Address */
1679#define AR5K_QOS_NOACK_2BIT_VALUES 0x00000000 /* (field) */ 1684#define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f /* ??? */
1680#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000020 /* (field) */ 1685#define AR5K_QOS_NOACK_2BIT_VALUES_S 0
1681#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000080 /* (field) */ 1686#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */
1687#define AR5K_QOS_NOACK_BIT_OFFSET_S 4
1688#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */
1689#define AR5K_QOS_NOACK_BYTE_OFFSET_S 8
1682 1690
1683/* 1691/*
1684 * PHY error filter register 1692 * PHY error filter register
@@ -1702,29 +1710,15 @@
1702/* 1710/*
1703 * MIC QoS control register (?) 1711 * MIC QoS control register (?)
1704 */ 1712 */
1705#define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */ 1713#define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */
1706#define AR5K_MIC_QOS_CTL_0 0x00000001 /* MIC QoS control 0 (?) */ 1714#define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2))
1707#define AR5K_MIC_QOS_CTL_1 0x00000004 /* MIC QoS control 1 (?) */ 1715#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */
1708#define AR5K_MIC_QOS_CTL_2 0x00000010 /* MIC QoS control 2 (?) */
1709#define AR5K_MIC_QOS_CTL_3 0x00000040 /* MIC QoS control 3 (?) */
1710#define AR5K_MIC_QOS_CTL_4 0x00000100 /* MIC QoS control 4 (?) */
1711#define AR5K_MIC_QOS_CTL_5 0x00000400 /* MIC QoS control 5 (?) */
1712#define AR5K_MIC_QOS_CTL_6 0x00001000 /* MIC QoS control 6 (?) */
1713#define AR5K_MIC_QOS_CTL_7 0x00004000 /* MIC QoS control 7 (?) */
1714#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */
1715 1716
1716/* 1717/*
1717 * MIC QoS select register (?) 1718 * MIC QoS select register (?)
1718 */ 1719 */
1719#define AR5K_MIC_QOS_SEL 0x811c 1720#define AR5K_MIC_QOS_SEL 0x811c
1720#define AR5K_MIC_QOS_SEL_0 0x00000001 1721#define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4))
1721#define AR5K_MIC_QOS_SEL_1 0x00000010
1722#define AR5K_MIC_QOS_SEL_2 0x00000100
1723#define AR5K_MIC_QOS_SEL_3 0x00001000
1724#define AR5K_MIC_QOS_SEL_4 0x00010000
1725#define AR5K_MIC_QOS_SEL_5 0x00100000
1726#define AR5K_MIC_QOS_SEL_6 0x01000000
1727#define AR5K_MIC_QOS_SEL_7 0x10000000
1728 1722
1729/* 1723/*
1730 * Misc mode control register (?) 1724 * Misc mode control register (?)
@@ -1759,6 +1753,11 @@
1759#define AR5K_TSF_THRES 0x813c 1753#define AR5K_TSF_THRES 0x813c
1760 1754
1761/* 1755/*
1756 * TODO: Wake On Wireless registers
1757 * Range: 0x8147 - 0x818c
1758 */
1759
1760/*
1762 * Rate -> ACK SIFS mapping table (32 entries) 1761 * Rate -> ACK SIFS mapping table (32 entries)
1763 */ 1762 */
1764#define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */ 1763#define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */
@@ -1873,7 +1872,8 @@
1873 */ 1872 */
1874#define AR5K_PHY_TURBO 0x9804 /* Register Address */ 1873#define AR5K_PHY_TURBO 0x9804 /* Register Address */
1875#define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */ 1874#define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */
1876#define AR5K_PHY_TURBO_SHORT 0x00000002 /* Short mode (20Mhz channels) (?) */ 1875#define AR5K_PHY_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode */
1876#define AR5K_PHY_TURBO_MIMO 0x00000004 /* Set turbo for mimo mimo */
1877 1877
1878/* 1878/*
1879 * PHY agility command register 1879 * PHY agility command register
@@ -1883,6 +1883,11 @@
1883#define AR5K_PHY_TST1 0x9808 1883#define AR5K_PHY_TST1 0x9808
1884#define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/ 1884#define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/
1885#define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */ 1885#define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */
1886#define AR5K_PHY_TST1_TXSRC_SRC 0x00000002 /* Used with bit 7 (?) */
1887#define AR5K_PHY_TST1_TXSRC_SRC_S 1
1888#define AR5K_PHY_TST1_TXSRC_ALT 0x00000080 /* Set input to tsdac (?) */
1889#define AR5K_PHY_TST1_TXSRC_ALT_S 7
1890
1886 1891
1887/* 1892/*
1888 * PHY timing register 3 [5112+] 1893 * PHY timing register 3 [5112+]
@@ -1907,15 +1912,23 @@
1907 1912
1908/* 1913/*
1909 * PHY RF control registers 1914 * PHY RF control registers
1910 * (i think these are delay times,
1911 * these calibration values exist
1912 * in EEPROM)
1913 */ 1915 */
1914#define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */ 1916#define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */
1915#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* Mask for TX frame to TX d(esc?) start */ 1917#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */
1918#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
1916 1919
1917#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */ 1920#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */
1918#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* Mask for TX end to XLNA on */ 1921#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* TX end to XLNA on */
1922#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 0
1923
1924#define AR5K_PHY_ADC_CTL 0x982c
1925#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
1926#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0
1927#define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000
1928#define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000
1929#define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000
1930#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000
1931#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16
1919 1932
1920#define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */ 1933#define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */
1921#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */ 1934#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */
@@ -1937,35 +1950,43 @@
1937 * PHY settling register 1950 * PHY settling register
1938 */ 1951 */
1939#define AR5K_PHY_SETTLING 0x9844 /* Register Address */ 1952#define AR5K_PHY_SETTLING 0x9844 /* Register Address */
1940#define AR5K_PHY_SETTLING_AGC 0x0000007f /* Mask for AGC settling time */ 1953#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */
1941#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Mask for Switch settlig time */ 1954#define AR5K_PHY_SETTLING_AGC_S 0
1955#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */
1956#define AR5K_PHY_SETTLINK_SWITCH_S 7
1942 1957
1943/* 1958/*
1944 * PHY Gain registers 1959 * PHY Gain registers
1945 */ 1960 */
1946#define AR5K_PHY_GAIN 0x9848 /* Register Address */ 1961#define AR5K_PHY_GAIN 0x9848 /* Register Address */
1947#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* Mask for TX-RX Attenuation */ 1962#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */
1963#define AR5K_PHY_GAIN_TXRX_ATTEN_S 12
1964#define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000
1965#define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18
1948 1966
1949#define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */ 1967#define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */
1950#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ 1968#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */
1951 1969
1952/* 1970/*
1953 * Desired size register 1971 * Desired ADC/PGA size register
1954 * (for more infos read ANI patent) 1972 * (for more infos read ANI patent)
1955 */ 1973 */
1956#define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ 1974#define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */
1957#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* Mask for ADC desired size */ 1975#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* ADC desired size */
1958#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* Mask for PGA desired size */ 1976#define AR5K_PHY_DESIRED_SIZE_ADC_S 0
1959#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Mask for Total desired size (?) */ 1977#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* PGA desired size */
1978#define AR5K_PHY_DESIRED_SIZE_PGA_S 8
1979#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Total desired size */
1980#define AR5K_PHY_DESIRED_SIZE_TOT_S 20
1960 1981
1961/* 1982/*
1962 * PHY signal register 1983 * PHY signal register
1963 * (for more infos read ANI patent) 1984 * (for more infos read ANI patent)
1964 */ 1985 */
1965#define AR5K_PHY_SIG 0x9858 /* Register Address */ 1986#define AR5K_PHY_SIG 0x9858 /* Register Address */
1966#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* Mask for FIRSTEP */ 1987#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* FIRSTEP */
1967#define AR5K_PHY_SIG_FIRSTEP_S 12 1988#define AR5K_PHY_SIG_FIRSTEP_S 12
1968#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* Mask for FIPWR */ 1989#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* FIPWR */
1969#define AR5K_PHY_SIG_FIRPWR_S 18 1990#define AR5K_PHY_SIG_FIRPWR_S 18
1970 1991
1971/* 1992/*
@@ -1973,9 +1994,9 @@
1973 * (for more infos read ANI patent) 1994 * (for more infos read ANI patent)
1974 */ 1995 */
1975#define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */ 1996#define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */
1976#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* Mask for AGC Coarse low */ 1997#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* AGC Coarse low */
1977#define AR5K_PHY_AGCCOARSE_LO_S 7 1998#define AR5K_PHY_AGCCOARSE_LO_S 7
1978#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* Mask for AGC Coarse high */ 1999#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* AGC Coarse high */
1979#define AR5K_PHY_AGCCOARSE_HI_S 15 2000#define AR5K_PHY_AGCCOARSE_HI_S 15
1980 2001
1981/* 2002/*
@@ -1984,6 +2005,8 @@
1984#define AR5K_PHY_AGCCTL 0x9860 /* Register address */ 2005#define AR5K_PHY_AGCCTL 0x9860 /* Register address */
1985#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ 2006#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */
1986#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ 2007#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */
2008#define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */
2009#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automaticaly */
1987 2010
1988/* 2011/*
1989 * PHY noise floor status register 2012 * PHY noise floor status register
@@ -1994,7 +2017,10 @@
1994#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) 2017#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M)
1995#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) 2018#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1)
1996#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) 2019#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))
1997#define AR5K_PHY_NF_THRESH62 0x00001000 /* Thresh62 -check ANI patent- (field) */ 2020#define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */
2021#define AR5K_PHY_NF_THRESH62_S 12
2022#define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000 /* ??? */
2023#define AR5K_PHY_NF_MINCCA_PWR_S 19
1998 2024
1999/* 2025/*
2000 * PHY ADC saturation register [5110] 2026 * PHY ADC saturation register [5110]
@@ -2034,24 +2060,31 @@
2034 */ 2060 */
2035#define AR5K_PHY_SCR 0x9870 2061#define AR5K_PHY_SCR 0x9870
2036#define AR5K_PHY_SCR_32MHZ 0x0000001f 2062#define AR5K_PHY_SCR_32MHZ 0x0000001f
2063
2037#define AR5K_PHY_SLMT 0x9874 2064#define AR5K_PHY_SLMT 0x9874
2038#define AR5K_PHY_SLMT_32MHZ 0x0000007f 2065#define AR5K_PHY_SLMT_32MHZ 0x0000007f
2066
2039#define AR5K_PHY_SCAL 0x9878 2067#define AR5K_PHY_SCAL 0x9878
2040#define AR5K_PHY_SCAL_32MHZ 0x0000000e 2068#define AR5K_PHY_SCAL_32MHZ 0x0000000e
2041 2069
2070
2042/* 2071/*
2043 * PHY PLL (Phase Locked Loop) control register 2072 * PHY PLL (Phase Locked Loop) control register
2044 */ 2073 */
2045#define AR5K_PHY_PLL 0x987c 2074#define AR5K_PHY_PLL 0x987c
2046#define AR5K_PHY_PLL_20MHZ 0x13 /* For half rate (?) [5111+] */ 2075#define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */
2047#define AR5K_PHY_PLL_40MHZ_5211 0x18 /* For 802.11a */ 2076/* 40MHz -> 5GHz band */
2077#define AR5K_PHY_PLL_40MHZ_5211 0x00000018
2048#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa 2078#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa
2079#define AR5K_PHY_PLL_40MHZ_5413 0x00000004
2049#define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ 2080#define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
2050 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) 2081 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)
2051#define AR5K_PHY_PLL_44MHZ_5211 0x19 /* For 802.11b/g */ 2082/* 44MHz -> 2.4GHz band */
2083#define AR5K_PHY_PLL_44MHZ_5211 0x00000019
2052#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab 2084#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab
2053#define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ 2085#define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
2054 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) 2086 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
2087
2055#define AR5K_PHY_PLL_RF5111 0x00000000 2088#define AR5K_PHY_PLL_RF5111 0x00000000
2056#define AR5K_PHY_PLL_RF5112 0x00000040 2089#define AR5K_PHY_PLL_RF5112 0x00000040
2057#define AR5K_PHY_PLL_HALF_RATE 0x00000100 2090#define AR5K_PHY_PLL_HALF_RATE 0x00000100
@@ -2118,6 +2151,19 @@
2118#define AR5K_PHY_RFSTG_DISABLE 0x00000021 2151#define AR5K_PHY_RFSTG_DISABLE 0x00000021
2119 2152
2120/* 2153/*
2154 * BIN masks (?)
2155 */
2156#define AR5K_PHY_BIN_MASK_1 0x9900
2157#define AR5K_PHY_BIN_MASK_2 0x9904
2158#define AR5K_PHY_BIN_MASK_3 0x9908
2159
2160#define AR5K_PHY_BIN_MASK_CTL 0x990c
2161#define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff
2162#define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0
2163#define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000
2164#define AR5K_PHY_BIN_MASK_CTL_RATE_S 24
2165
2166/*
2121 * PHY Antenna control register 2167 * PHY Antenna control register
2122 */ 2168 */
2123#define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */ 2169#define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */
@@ -2164,6 +2210,7 @@
2164#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */ 2210#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */
2165#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */ 2211#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */
2166#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */ 2212#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */
2213#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 0
2167#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */ 2214#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */
2168#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */ 2215#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */
2169#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */ 2216#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */
@@ -2210,7 +2257,6 @@
2210#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */ 2257#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */
2211#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */ 2258#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */
2212 2259
2213
2214/* 2260/*
2215 * PHY TX rate power registers [5112+] 2261 * PHY TX rate power registers [5112+]
2216 */ 2262 */
@@ -2232,6 +2278,8 @@
2232#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */ 2278#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */
2233#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 2279#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
2234#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */ 2280#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */
2281#define AR5K_PHY_FRAME_CTL_EMU 0x80000000
2282#define AR5K_PHY_FRAME_CTL_EMU_S 31
2235/*---[5110/5111]---*/ 2283/*---[5110/5111]---*/
2236#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */ 2284#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */
2237#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */ 2285#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */
@@ -2250,48 +2298,36 @@
2250 * PHY radar detection register [5111+] 2298 * PHY radar detection register [5111+]
2251 */ 2299 */
2252#define AR5K_PHY_RADAR 0x9954 2300#define AR5K_PHY_RADAR 0x9954
2253
2254/* Radar enable ........ ........ ........ .......1 */
2255#define AR5K_PHY_RADAR_ENABLE 0x00000001 2301#define AR5K_PHY_RADAR_ENABLE 0x00000001
2256#define AR5K_PHY_RADAR_DISABLE 0x00000000 2302#define AR5K_PHY_RADAR_DISABLE 0x00000000
2257#define AR5K_PHY_RADAR_ENABLE_S 0 2303#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold
2258 2304 5-bits, units unknown {0..31}
2259/* This is the value found on the card .1.111.1 .1.1.... 111....1 1...1... 2305 (? MHz ?) */
2260at power on. */
2261#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188
2262
2263/* This is the value found on the card .1.1.111 ..11...1 .1...1.1 1...11.1
2264after DFS is enabled */
2265#define AR5K_PHY_RADAR_ENABLED_AR5213 0x5731458d
2266
2267/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........
2268 * power out threshold.
2269 * 7-bits, standard power range {0..127} in 1/2 dBm units. */
2270#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000
2271#define AR5K_PHY_RADAR_FIRPWROUTTHR_S 24
2272
2273/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........
2274 * 6-bits, dBm range {0..63} in dBm units. */
2275#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000
2276#define AR5K_PHY_RADAR_RADARRSSITHR_S 18
2277
2278/* Pulse height threshold ........ ......11 1111.... ........
2279 * 6-bits, dBm range {0..63} in dBm units. */
2280#define AR5K_PHY_RADAR_PULSEHEIGHTTHR 0x0003f000
2281#define AR5K_PHY_RADAR_PULSEHEIGHTTHR_S 12
2282
2283/* Pulse RSSI/SNR threshold ........ ........ ....1111 11......
2284 * 6-bits, dBm range {0..63} in dBm units. */
2285#define AR5K_PHY_RADAR_PULSERSSITHR 0x00000fc0
2286#define AR5K_PHY_RADAR_PULSERSSITHR_S 6
2287
2288/* Inband threshold ........ ........ ........ ..11111.
2289 * 5-bits, units unknown {0..31} (? MHz ?) */
2290#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e
2291#define AR5K_PHY_RADAR_INBANDTHR_S 1 2306#define AR5K_PHY_RADAR_INBANDTHR_S 1
2292 2307
2308#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold
2309 6-bits, dBm range {0..63}
2310 in dBm units. */
2311#define AR5K_PHY_RADAR_PRSSI_THR_S 6
2312
2313#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold
2314 6-bits, dBm range {0..63}
2315 in dBm units. */
2316#define AR5K_PHY_RADAR_PHEIGHT_THR_S 12
2317
2318#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold.
2319 6-bits, dBm range {0..63}
2320 in dBm units. */
2321#define AR5K_PHY_RADAR_RSSI_THR_S 18
2322
2323#define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 /* Finite Impulse Response
2324 filter power out threshold.
2325 7-bits, standard power range
2326 {0..127} in 1/2 dBm units. */
2327#define AR5K_PHY_RADAR_FIRPWR_THRS 24
2328
2293/* 2329/*
2294 * PHY antenna switch table registers [5110] 2330 * PHY antenna switch table registers
2295 */ 2331 */
2296#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 2332#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960
2297#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 2333#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
@@ -2302,25 +2338,65 @@ after DFS is enabled */
2302#define AR5K_PHY_NFTHRES 0x9968 2338#define AR5K_PHY_NFTHRES 0x9968
2303 2339
2304/* 2340/*
2305 * PHY clock sleep registers [5112+] 2341 * Sigma Delta register (?) [5213]
2306 */ 2342 */
2307#define AR5K_PHY_SCLOCK 0x99f0 2343#define AR5K_PHY_SIGMA_DELTA 0x996C
2308#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c 2344#define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
2309#define AR5K_PHY_SDELAY 0x99f4 2345#define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0
2310#define AR5K_PHY_SDELAY_32MHZ 0x000000ff 2346#define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8
2311#define AR5K_PHY_SPENDING 0x99f8 2347#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
2312#define AR5K_PHY_SPENDING_14 0x00000014 2348#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
2313#define AR5K_PHY_SPENDING_18 0x00000018 2349#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
2314#define AR5K_PHY_SPENDING_RF5111 0x00000018 2350#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ff3000
2315#define AR5K_PHY_SPENDING_RF5112 0x00000014 2351#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
2316/* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */ 2352
2317/* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */ 2353/*
2318#define AR5K_PHY_SPENDING_RF5413 0x00000014 2354 * RF restart register [5112+] (?)
2319#define AR5K_PHY_SPENDING_RF2413 0x00000014 2355 */
2320#define AR5K_PHY_SPENDING_RF2425 0x00000018 2356#define AR5K_PHY_RESTART 0x9970 /* restart */
2357#define AR5K_PHY_RESTART_DIV_GC 0x001c0000 /* Fast diversity gc_limit (?) */
2358#define AR5K_PHY_RESTART_DIV_GC_S 18
2359
2360/*
2361 * RF Bus access request register (for synth-oly channel switching)
2362 */
2363#define AR5K_PHY_RFBUS_REQ 0x997C
2364#define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001
2365
2366/*
2367 * Spur mitigation masks (?)
2368 */
2369#define AR5K_PHY_TIMING_7 0x9980
2370#define AR5K_PHY_TIMING_8 0x9984
2371#define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff
2372#define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0
2373
2374#define AR5K_PHY_BIN_MASK2_1 0x9988
2375#define AR5K_PHY_BIN_MASK2_2 0x998c
2376#define AR5K_PHY_BIN_MASK2_3 0x9990
2377
2378#define AR5K_PHY_BIN_MASK2_4 0x9994
2379#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
2380#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
2381
2382#define AR_PHY_TIMING_9 0x9998
2383#define AR_PHY_TIMING_10 0x999c
2384#define AR_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
2385#define AR_PHY_TIMING_10_PILOT_MASK_2_S 0
2386
2387/*
2388 * Spur mitigation control
2389 */
2390#define AR_PHY_TIMING_11 0x99a0 /* Register address */
2391#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
2392#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
2393#define AR_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
2394#define AR_PHY_TIMING_11_SPUR_FREQ_SD_S 20
2395#define AR_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
2396#define AR_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
2321 2397
2322/* 2398/*
2323 * Misc PHY/radio registers [5110 - 5111] 2399 * Gain tables
2324 */ 2400 */
2325#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ 2401#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */
2326#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) 2402#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
@@ -2340,9 +2416,10 @@ after DFS is enabled */
2340#define AR5K_PHY_CURRENT_RSSI 0x9c1c 2416#define AR5K_PHY_CURRENT_RSSI 0x9c1c
2341 2417
2342/* 2418/*
2343 * PHY RF Bus grant register (?) 2419 * PHY RF Bus grant register
2344 */ 2420 */
2345#define AR5K_PHY_RFBUS_GRANT 0x9c20 2421#define AR5K_PHY_RFBUS_GRANT 0x9c20
2422#define AR5K_PHY_RFBUS_GRANT_OK 0x00000001
2346 2423
2347/* 2424/*
2348 * PHY ADC test register 2425 * PHY ADC test register
@@ -2386,6 +2463,31 @@ after DFS is enabled */
2386#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 2463#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
2387 2464
2388/* 2465/*
2466 * Heavy clip enable register
2467 */
2468#define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0
2469
2470/*
2471 * PHY clock sleep registers [5112+]
2472 */
2473#define AR5K_PHY_SCLOCK 0x99f0
2474#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c
2475#define AR5K_PHY_SDELAY 0x99f4
2476#define AR5K_PHY_SDELAY_32MHZ 0x000000ff
2477#define AR5K_PHY_SPENDING 0x99f8
2478#define AR5K_PHY_SPENDING_14 0x00000014
2479#define AR5K_PHY_SPENDING_18 0x00000018
2480#define AR5K_PHY_SPENDING_RF5111 0x00000018
2481#define AR5K_PHY_SPENDING_RF5112 0x00000014
2482/* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */
2483/* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */
2484#define AR5K_PHY_SPENDING_RF5413 0x00000018
2485#define AR5K_PHY_SPENDING_RF2413 0x00000018
2486#define AR5K_PHY_SPENDING_RF2316 0x00000018
2487#define AR5K_PHY_SPENDING_RF2317 0x00000018
2488#define AR5K_PHY_SPENDING_RF2425 0x00000014
2489
2490/*
2389 * PHY PAPD I (power?) table (?) 2491 * PHY PAPD I (power?) table (?)
2390 * (92! entries) 2492 * (92! entries)
2391 */ 2493 */
@@ -2436,10 +2538,47 @@ after DFS is enabled */
2436#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f 2538#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f
2437#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0 2539#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0
2438 2540
2541/* Same address is used for antenna diversity activation */
2542#define AR5K_PHY_FAST_ANT_DIV 0xa208
2543#define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000
2544
2439/* 2545/*
2440 * PHY 2GHz gain register [5111+] 2546 * PHY 2GHz gain register [5111+]
2441 */ 2547 */
2442#define AR5K_PHY_GAIN_2GHZ 0xa20c 2548#define AR5K_PHY_GAIN_2GHZ 0xa20c
2443#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 2549#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
2444#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 2550#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
2445#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c 2551#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c
2552
2553#define AR5K_PHY_CCK_RX_CTL_4 0xa21c
2554#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000
2555#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19
2556
2557#define AR5K_PHY_DAG_CCK_CTL 0xa228
2558#define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200
2559#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00
2560#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10
2561
2562#define AR5K_PHY_FAST_ADC 0xa24c
2563
2564#define AR5K_PHY_BLUETOOTH 0xa254
2565
2566/*
2567 * Transmit Power Control register
2568 * [2413+]
2569 */
2570#define AR5K_PHY_TPC_RG1 0xa258
2571#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000
2572#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14
2573
2574#define AR5K_PHY_TPC_RG5 0xa26C
2575#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F
2576#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0
2577#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0
2578#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4
2579#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00
2580#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10
2581#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000
2582#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
2583#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
2584#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-28 11:26:16 -0400