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-rw-r--r--drivers/net/wireless/ath5k/hw.c4492
1 files changed, 0 insertions, 4492 deletions
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c
deleted file mode 100644
index b987aa1e0f77..000000000000
--- a/drivers/net/wireless/ath5k/hw.c
+++ /dev/null
@@ -1,4492 +0,0 @@
1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23/*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27#include <linux/pci.h>
28#include <linux/delay.h>
29
30#include "reg.h"
31#include "base.h"
32#include "debug.h"
33
34/* Prototypes */
35static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
36static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
37static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
38 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
39 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
40 unsigned int, unsigned int);
41static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
42 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
43 unsigned int);
44static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
45 struct ath5k_tx_status *);
46static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
47 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
48 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
49 unsigned int, unsigned int);
50static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
51 struct ath5k_tx_status *);
52static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *, struct ath5k_desc *,
53 struct ath5k_rx_status *);
54static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *, struct ath5k_desc *,
55 struct ath5k_rx_status *);
56static int ath5k_hw_get_capabilities(struct ath5k_hw *);
57
58static int ath5k_eeprom_init(struct ath5k_hw *);
59static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
60
61static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
62static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
63
64/*
65 * Enable to overwrite the country code (use "00" for debug)
66 */
67#if 0
68#define COUNTRYCODE "00"
69#endif
70
71/*******************\
72 General Functions
73\*******************/
74
75/*
76 * Functions used internaly
77 */
78
79static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
80{
81 return turbo ? (usec * 80) : (usec * 40);
82}
83
84static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
85{
86 return turbo ? (clock / 80) : (clock / 40);
87}
88
89/*
90 * Check if a register write has been completed
91 */
92int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
93 bool is_set)
94{
95 int i;
96 u32 data;
97
98 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
99 data = ath5k_hw_reg_read(ah, reg);
100 if (is_set && (data & flag))
101 break;
102 else if ((data & flag) == val)
103 break;
104 udelay(15);
105 }
106
107 return (i <= 0) ? -EAGAIN : 0;
108}
109
110
111/***************************************\
112 Attach/Detach Functions
113\***************************************/
114
115/*
116 * Power On Self Test helper function
117 */
118static int ath5k_hw_post(struct ath5k_hw *ah)
119{
120
121 int i, c;
122 u16 cur_reg;
123 u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
124 u32 var_pattern;
125 u32 static_pattern[4] = {
126 0x55555555, 0xaaaaaaaa,
127 0x66666666, 0x99999999
128 };
129 u32 init_val;
130 u32 cur_val;
131
132 for (c = 0; c < 2; c++) {
133
134 cur_reg = regs[c];
135
136 /* Save previous value */
137 init_val = ath5k_hw_reg_read(ah, cur_reg);
138
139 for (i = 0; i < 256; i++) {
140 var_pattern = i << 16 | i;
141 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
142 cur_val = ath5k_hw_reg_read(ah, cur_reg);
143
144 if (cur_val != var_pattern) {
145 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
146 return -EAGAIN;
147 }
148
149 /* Found on ndiswrapper dumps */
150 var_pattern = 0x0039080f;
151 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
152 }
153
154 for (i = 0; i < 4; i++) {
155 var_pattern = static_pattern[i];
156 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
157 cur_val = ath5k_hw_reg_read(ah, cur_reg);
158
159 if (cur_val != var_pattern) {
160 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
161 return -EAGAIN;
162 }
163
164 /* Found on ndiswrapper dumps */
165 var_pattern = 0x003b080f;
166 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
167 }
168
169 /* Restore previous value */
170 ath5k_hw_reg_write(ah, init_val, cur_reg);
171
172 }
173
174 return 0;
175
176}
177
178/*
179 * Check if the device is supported and initialize the needed structs
180 */
181struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
182{
183 struct ath5k_hw *ah;
184 struct pci_dev *pdev = sc->pdev;
185 u8 mac[ETH_ALEN];
186 int ret;
187 u32 srev;
188
189 /*If we passed the test malloc a ath5k_hw struct*/
190 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
191 if (ah == NULL) {
192 ret = -ENOMEM;
193 ATH5K_ERR(sc, "out of memory\n");
194 goto err;
195 }
196
197 ah->ah_sc = sc;
198 ah->ah_iobase = sc->iobase;
199
200 /*
201 * HW information
202 */
203
204 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
205 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
206 ah->ah_turbo = false;
207 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
208 ah->ah_imr = 0;
209 ah->ah_atim_window = 0;
210 ah->ah_aifs = AR5K_TUNE_AIFS;
211 ah->ah_cw_min = AR5K_TUNE_CWMIN;
212 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
213 ah->ah_software_retry = false;
214 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
215
216 /*
217 * Set the mac revision based on the pci id
218 */
219 ah->ah_version = mac_version;
220
221 /*Fill the ath5k_hw struct with the needed functions*/
222 if (ah->ah_version == AR5K_AR5212)
223 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
224 else if (ah->ah_version == AR5K_AR5211)
225 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
226
227 if (ah->ah_version == AR5K_AR5212) {
228 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
229 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
230 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
231 } else {
232 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
233 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
234 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
235 }
236
237 if (ah->ah_version == AR5K_AR5212)
238 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
239 else if (ah->ah_version <= AR5K_AR5211)
240 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
241
242 /* Bring device out of sleep and reset it's units */
243 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
244 if (ret)
245 goto err_free;
246
247 /* Get MAC, PHY and RADIO revisions */
248 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
249 ah->ah_mac_srev = srev;
250 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
251 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
252 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
253 0xffffffff;
254 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
255 CHANNEL_5GHZ);
256
257 if (ah->ah_version == AR5K_AR5210)
258 ah->ah_radio_2ghz_revision = 0;
259 else
260 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
261 CHANNEL_2GHZ);
262
263 /* Return on unsuported chips (unsupported eeprom etc) */
264 if ((srev >= AR5K_SREV_VER_AR5416) &&
265 (srev < AR5K_SREV_VER_AR2425)) {
266 ATH5K_ERR(sc, "Device not yet supported.\n");
267 ret = -ENODEV;
268 goto err_free;
269 } else if (srev == AR5K_SREV_VER_AR2425) {
270 ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
271 }
272
273 /* Identify single chip solutions */
274 if (((srev <= AR5K_SREV_VER_AR5414) &&
275 (srev >= AR5K_SREV_VER_AR2413)) ||
276 (srev == AR5K_SREV_VER_AR2425)) {
277 ah->ah_single_chip = true;
278 } else {
279 ah->ah_single_chip = false;
280 }
281
282 /* Single chip radio */
283 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
284 ah->ah_radio_2ghz_revision = 0;
285
286 /* Identify the radio chip*/
287 if (ah->ah_version == AR5K_AR5210) {
288 ah->ah_radio = AR5K_RF5110;
289 /*
290 * Register returns 0x0/0x04 for radio revision
291 * so ath5k_hw_radio_revision doesn't parse the value
292 * correctly. For now we are based on mac's srev to
293 * identify RF2425 radio.
294 */
295 } else if (srev == AR5K_SREV_VER_AR2425) {
296 ah->ah_radio = AR5K_RF2425;
297 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
298 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
299 ah->ah_radio = AR5K_RF5111;
300 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
301 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
302 ah->ah_radio = AR5K_RF5112;
303 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
304 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
305 ah->ah_radio = AR5K_RF2413;
306 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
307 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) {
308 ah->ah_radio = AR5K_RF5413;
309 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
310 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
311 /* AR5424 */
312 if (srev >= AR5K_SREV_VER_AR5424) {
313 ah->ah_radio = AR5K_RF5413;
314 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
315 /* AR2424 */
316 } else {
317 ah->ah_radio = AR5K_RF2413; /* For testing */
318 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
319 }
320 }
321 ah->ah_phy = AR5K_PHY(0);
322
323 /*
324 * Write PCI-E power save settings
325 */
326 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
327 ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
328 ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
329 ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
330 ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
331 ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
332 ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
333 ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
334 ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
335 ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
336 ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
337 }
338
339 /*
340 * POST
341 */
342 ret = ath5k_hw_post(ah);
343 if (ret)
344 goto err_free;
345
346 /* Write AR5K_PCICFG_UNK on 2112B and later chips */
347 if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B ||
348 srev > AR5K_SREV_VER_AR2413) {
349 ath5k_hw_reg_write(ah, AR5K_PCICFG_UNK, AR5K_PCICFG);
350 }
351
352 /*
353 * Get card capabilities, values, ...
354 */
355 ret = ath5k_eeprom_init(ah);
356 if (ret) {
357 ATH5K_ERR(sc, "unable to init EEPROM\n");
358 goto err_free;
359 }
360
361 /* Get misc capabilities */
362 ret = ath5k_hw_get_capabilities(ah);
363 if (ret) {
364 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
365 sc->pdev->device);
366 goto err_free;
367 }
368
369 /* Get MAC address */
370 ret = ath5k_eeprom_read_mac(ah, mac);
371 if (ret) {
372 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
373 sc->pdev->device);
374 goto err_free;
375 }
376
377 ath5k_hw_set_lladdr(ah, mac);
378 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
379 memset(ah->ah_bssid, 0xff, ETH_ALEN);
380 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
381 ath5k_hw_set_opmode(ah);
382
383 ath5k_hw_set_rfgain_opt(ah);
384
385 return ah;
386err_free:
387 kfree(ah);
388err:
389 return ERR_PTR(ret);
390}
391
392/*
393 * Bring up MAC + PHY Chips
394 */
395static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
396{
397 struct pci_dev *pdev = ah->ah_sc->pdev;
398 u32 turbo, mode, clock, bus_flags;
399 int ret;
400
401 turbo = 0;
402 mode = 0;
403 clock = 0;
404
405 ATH5K_TRACE(ah->ah_sc);
406
407 /* Wakeup the device */
408 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
409 if (ret) {
410 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
411 return ret;
412 }
413
414 if (ah->ah_version != AR5K_AR5210) {
415 /*
416 * Get channel mode flags
417 */
418
419 if (ah->ah_radio >= AR5K_RF5112) {
420 mode = AR5K_PHY_MODE_RAD_RF5112;
421 clock = AR5K_PHY_PLL_RF5112;
422 } else {
423 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
424 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
425 }
426
427 if (flags & CHANNEL_2GHZ) {
428 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
429 clock |= AR5K_PHY_PLL_44MHZ;
430
431 if (flags & CHANNEL_CCK) {
432 mode |= AR5K_PHY_MODE_MOD_CCK;
433 } else if (flags & CHANNEL_OFDM) {
434 /* XXX Dynamic OFDM/CCK is not supported by the
435 * AR5211 so we set MOD_OFDM for plain g (no
436 * CCK headers) operation. We need to test
437 * this, 5211 might support ofdm-only g after
438 * all, there are also initial register values
439 * in the code for g mode (see initvals.c). */
440 if (ah->ah_version == AR5K_AR5211)
441 mode |= AR5K_PHY_MODE_MOD_OFDM;
442 else
443 mode |= AR5K_PHY_MODE_MOD_DYN;
444 } else {
445 ATH5K_ERR(ah->ah_sc,
446 "invalid radio modulation mode\n");
447 return -EINVAL;
448 }
449 } else if (flags & CHANNEL_5GHZ) {
450 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
451 clock |= AR5K_PHY_PLL_40MHZ;
452
453 if (flags & CHANNEL_OFDM)
454 mode |= AR5K_PHY_MODE_MOD_OFDM;
455 else {
456 ATH5K_ERR(ah->ah_sc,
457 "invalid radio modulation mode\n");
458 return -EINVAL;
459 }
460 } else {
461 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
462 return -EINVAL;
463 }
464
465 if (flags & CHANNEL_TURBO)
466 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
467 } else { /* Reset the device */
468
469 /* ...enable Atheros turbo mode if requested */
470 if (flags & CHANNEL_TURBO)
471 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
472 AR5K_PHY_TURBO);
473 }
474
475 /* reseting PCI on PCI-E cards results card to hang
476 * and always return 0xffff... so we ingore that flag
477 * for PCI-E cards */
478 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
479
480 /* Reset chipset */
481 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
482 AR5K_RESET_CTL_BASEBAND | bus_flags);
483 if (ret) {
484 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
485 return -EIO;
486 }
487
488 if (ah->ah_version == AR5K_AR5210)
489 udelay(2300);
490
491 /* ...wakeup again!*/
492 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
493 if (ret) {
494 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
495 return ret;
496 }
497
498 /* ...final warm reset */
499 if (ath5k_hw_nic_reset(ah, 0)) {
500 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
501 return -EIO;
502 }
503
504 if (ah->ah_version != AR5K_AR5210) {
505 /* ...set the PHY operating mode */
506 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
507 udelay(300);
508
509 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
510 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
511 }
512
513 return 0;
514}
515
516/*
517 * Free the ath5k_hw struct
518 */
519void ath5k_hw_detach(struct ath5k_hw *ah)
520{
521 ATH5K_TRACE(ah->ah_sc);
522
523 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
524
525 if (ah->ah_rf_banks != NULL)
526 kfree(ah->ah_rf_banks);
527
528 /* assume interrupts are down */
529 kfree(ah);
530}
531
532/****************************\
533 Reset function and helpers
534\****************************/
535
536/**
537 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
538 *
539 * @ah: the &struct ath5k_hw
540 * @channel: the currently set channel upon reset
541 *
542 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
543 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
544 * depending on the bandwidth of the channel.
545 *
546 */
547static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
548 struct ieee80211_channel *channel)
549{
550 /* Get exponent and mantissa and set it */
551 u32 coef_scaled, coef_exp, coef_man,
552 ds_coef_exp, ds_coef_man, clock;
553
554 if (!(ah->ah_version == AR5K_AR5212) ||
555 !(channel->hw_value & CHANNEL_OFDM))
556 BUG();
557
558 /* Seems there are two PLLs, one for baseband sampling and one
559 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
560 * turbo. */
561 clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
562 coef_scaled = ((5 * (clock << 24)) / 2) /
563 channel->center_freq;
564
565 for (coef_exp = 31; coef_exp > 0; coef_exp--)
566 if ((coef_scaled >> coef_exp) & 0x1)
567 break;
568
569 if (!coef_exp)
570 return -EINVAL;
571
572 coef_exp = 14 - (coef_exp - 24);
573 coef_man = coef_scaled +
574 (1 << (24 - coef_exp - 1));
575 ds_coef_man = coef_man >> (24 - coef_exp);
576 ds_coef_exp = coef_exp - 16;
577
578 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
579 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
580 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
581 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
582
583 return 0;
584}
585
586
587/*
588 * index into rates for control rates, we can set it up like this because
589 * this is only used for AR5212 and we know it supports G mode
590 */
591static int control_rates[] =
592 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
593
594/**
595 * ath5k_hw_write_rate_duration - set rate duration during hw resets
596 *
597 * @ah: the &struct ath5k_hw
598 * @mode: one of enum ath5k_driver_mode
599 *
600 * Write the rate duration table upon hw reset. This is a helper for
601 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout for
602 * the hardware for the current mode for each rate. The rates which are capable
603 * of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have another
604 * register for the short preamble ACK timeout calculation.
605 */
606static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
607 unsigned int mode)
608{
609 struct ath5k_softc *sc = ah->ah_sc;
610 struct ieee80211_rate *rate;
611 unsigned int i;
612
613 /* Write rate duration table */
614 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) {
615 u32 reg;
616 u16 tx_time;
617
618 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]];
619
620 /* Set ACK timeout */
621 reg = AR5K_RATE_DUR(rate->hw_value);
622
623 /* An ACK frame consists of 10 bytes. If you add the FCS,
624 * which ieee80211_generic_frame_duration() adds,
625 * its 14 bytes. Note we use the control rate and not the
626 * actual rate for this rate. See mac80211 tx.c
627 * ieee80211_duration() for a brief description of
628 * what rate we should choose to TX ACKs. */
629 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
630 sc->vif, 10, rate));
631
632 ath5k_hw_reg_write(ah, tx_time, reg);
633
634 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
635 continue;
636
637 /*
638 * We're not distinguishing short preamble here,
639 * This is true, all we'll get is a longer value here
640 * which is not necessarilly bad. We could use
641 * export ieee80211_frame_duration() but that needs to be
642 * fixed first to be properly used by mac802111 drivers:
643 *
644 * - remove erp stuff and let the routine figure ofdm
645 * erp rates
646 * - remove passing argument ieee80211_local as
647 * drivers don't have access to it
648 * - move drivers using ieee80211_generic_frame_duration()
649 * to this
650 */
651 ath5k_hw_reg_write(ah, tx_time,
652 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
653 }
654}
655
656/*
657 * Main reset function
658 */
659int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
660 struct ieee80211_channel *channel, bool change_channel)
661{
662 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
663 struct pci_dev *pdev = ah->ah_sc->pdev;
664 u32 data, s_seq, s_ant, s_led[3], dma_size;
665 unsigned int i, mode, freq, ee_mode, ant[2];
666 int ret;
667
668 ATH5K_TRACE(ah->ah_sc);
669
670 s_seq = 0;
671 s_ant = 0;
672 ee_mode = 0;
673 freq = 0;
674 mode = 0;
675
676 /*
677 * Save some registers before a reset
678 */
679 /*DCU/Antenna selection not available on 5210*/
680 if (ah->ah_version != AR5K_AR5210) {
681 if (change_channel) {
682 /* Seq number for queue 0 -do this for all queues ? */
683 s_seq = ath5k_hw_reg_read(ah,
684 AR5K_QUEUE_DFS_SEQNUM(0));
685 /*Default antenna*/
686 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
687 }
688 }
689
690 /*GPIOs*/
691 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
692 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
693 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
694
695 if (change_channel && ah->ah_rf_banks != NULL)
696 ath5k_hw_get_rf_gain(ah);
697
698
699 /*Wakeup the device*/
700 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
701 if (ret)
702 return ret;
703
704 /*
705 * Initialize operating mode
706 */
707 ah->ah_op_mode = op_mode;
708
709 /*
710 * 5111/5112 Settings
711 * 5210 only comes with RF5110
712 */
713 if (ah->ah_version != AR5K_AR5210) {
714 if (ah->ah_radio != AR5K_RF5111 &&
715 ah->ah_radio != AR5K_RF5112 &&
716 ah->ah_radio != AR5K_RF5413 &&
717 ah->ah_radio != AR5K_RF2413 &&
718 ah->ah_radio != AR5K_RF2425) {
719 ATH5K_ERR(ah->ah_sc,
720 "invalid phy radio: %u\n", ah->ah_radio);
721 return -EINVAL;
722 }
723
724 switch (channel->hw_value & CHANNEL_MODES) {
725 case CHANNEL_A:
726 mode = AR5K_MODE_11A;
727 freq = AR5K_INI_RFGAIN_5GHZ;
728 ee_mode = AR5K_EEPROM_MODE_11A;
729 break;
730 case CHANNEL_G:
731 mode = AR5K_MODE_11G;
732 freq = AR5K_INI_RFGAIN_2GHZ;
733 ee_mode = AR5K_EEPROM_MODE_11G;
734 break;
735 case CHANNEL_B:
736 mode = AR5K_MODE_11B;
737 freq = AR5K_INI_RFGAIN_2GHZ;
738 ee_mode = AR5K_EEPROM_MODE_11B;
739 break;
740 case CHANNEL_T:
741 mode = AR5K_MODE_11A_TURBO;
742 freq = AR5K_INI_RFGAIN_5GHZ;
743 ee_mode = AR5K_EEPROM_MODE_11A;
744 break;
745 /*Is this ok on 5211 too ?*/
746 case CHANNEL_TG:
747 mode = AR5K_MODE_11G_TURBO;
748 freq = AR5K_INI_RFGAIN_2GHZ;
749 ee_mode = AR5K_EEPROM_MODE_11G;
750 break;
751 case CHANNEL_XR:
752 if (ah->ah_version == AR5K_AR5211) {
753 ATH5K_ERR(ah->ah_sc,
754 "XR mode not available on 5211");
755 return -EINVAL;
756 }
757 mode = AR5K_MODE_XR;
758 freq = AR5K_INI_RFGAIN_5GHZ;
759 ee_mode = AR5K_EEPROM_MODE_11A;
760 break;
761 default:
762 ATH5K_ERR(ah->ah_sc,
763 "invalid channel: %d\n", channel->center_freq);
764 return -EINVAL;
765 }
766
767 /* PHY access enable */
768 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
769
770 }
771
772 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
773 if (ret)
774 return ret;
775
776 /*
777 * 5211/5212 Specific
778 */
779 if (ah->ah_version != AR5K_AR5210) {
780 /*
781 * Write initial RF gain settings
782 * This should work for both 5111/5112
783 */
784 ret = ath5k_hw_rfgain(ah, freq);
785 if (ret)
786 return ret;
787
788 mdelay(1);
789
790 /*
791 * Write some more initial register settings
792 */
793 if (ah->ah_version == AR5K_AR5212) {
794 ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
795
796 if (channel->hw_value == CHANNEL_G)
797 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
798 ath5k_hw_reg_write(ah, 0x00f80d80,
799 0x994c);
800 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
801 ath5k_hw_reg_write(ah, 0x00380140,
802 0x994c);
803 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
804 ath5k_hw_reg_write(ah, 0x00fc0ec0,
805 0x994c);
806 else /* 2425 */
807 ath5k_hw_reg_write(ah, 0x00fc0fc0,
808 0x994c);
809 else
810 ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
811
812 /* Some bits are disabled here, we know nothing about
813 * register 0xa228 yet, most of the times this ends up
814 * with a value 0x9b5 -haven't seen any dump with
815 * a different value- */
816 /* Got this from decompiling binary HAL */
817 data = ath5k_hw_reg_read(ah, 0xa228);
818 data &= 0xfffffdff;
819 ath5k_hw_reg_write(ah, data, 0xa228);
820
821 data = ath5k_hw_reg_read(ah, 0xa228);
822 data &= 0xfffe03ff;
823 ath5k_hw_reg_write(ah, data, 0xa228);
824 data = 0;
825
826 /* Just write 0x9b5 ? */
827 /* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */
828 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
829 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
830 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
831 }
832
833 /* Fix for first revision of the RF5112 RF chipset */
834 if (ah->ah_radio >= AR5K_RF5112 &&
835 ah->ah_radio_5ghz_revision <
836 AR5K_SREV_RAD_5112A) {
837 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
838 AR5K_PHY_CCKTXCTL);
839 if (channel->hw_value & CHANNEL_5GHZ)
840 data = 0xffb81020;
841 else
842 data = 0xffb80d20;
843 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
844 data = 0;
845 }
846
847 /*
848 * Set TX power (FIXME)
849 */
850 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
851 if (ret)
852 return ret;
853
854 /* Write rate duration table only on AR5212 and if
855 * virtual interface has already been brought up
856 * XXX: rethink this after new mode changes to
857 * mac80211 are integrated */
858 if (ah->ah_version == AR5K_AR5212 &&
859 ah->ah_sc->vif != NULL)
860 ath5k_hw_write_rate_duration(ah, mode);
861
862 /*
863 * Write RF registers
864 */
865 ret = ath5k_hw_rfregs(ah, channel, mode);
866 if (ret)
867 return ret;
868
869 /*
870 * Configure additional registers
871 */
872
873 /* Write OFDM timings on 5212*/
874 if (ah->ah_version == AR5K_AR5212 &&
875 channel->hw_value & CHANNEL_OFDM) {
876 ret = ath5k_hw_write_ofdm_timings(ah, channel);
877 if (ret)
878 return ret;
879 }
880
881 /*Enable/disable 802.11b mode on 5111
882 (enable 2111 frequency converter + CCK)*/
883 if (ah->ah_radio == AR5K_RF5111) {
884 if (mode == AR5K_MODE_11B)
885 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
886 AR5K_TXCFG_B_MODE);
887 else
888 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
889 AR5K_TXCFG_B_MODE);
890 }
891
892 /*
893 * Set channel and calibrate the PHY
894 */
895 ret = ath5k_hw_channel(ah, channel);
896 if (ret)
897 return ret;
898
899 /* Set antenna mode */
900 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_ANT_CTL,
901 ah->ah_antenna[ee_mode][0], 0xfffffc06);
902
903 /*
904 * In case a fixed antenna was set as default
905 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
906 * registers.
907 */
908 if (s_ant != 0){
909 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
910 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
911 else /* 2 - Aux */
912 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
913 } else {
914 ant[0] = AR5K_ANT_FIXED_A;
915 ant[1] = AR5K_ANT_FIXED_B;
916 }
917
918 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
919 AR5K_PHY_ANT_SWITCH_TABLE_0);
920 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
921 AR5K_PHY_ANT_SWITCH_TABLE_1);
922
923 /* Commit values from EEPROM */
924 if (ah->ah_radio == AR5K_RF5111)
925 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
926 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
927
928 ath5k_hw_reg_write(ah,
929 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
930 AR5K_PHY_NFTHRES);
931
932 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_SETTLING,
933 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
934 0xffffc07f);
935 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_GAIN,
936 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
937 0xfffc0fff);
938 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_DESIRED_SIZE,
939 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
940 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
941 0xffff0000);
942
943 ath5k_hw_reg_write(ah,
944 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
945 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
946 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
947 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
948
949 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_RF_CTL3,
950 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
951 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_NF,
952 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
953 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 4, 0xffffff01);
954
955 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
956 AR5K_PHY_IQ_CORR_ENABLE |
957 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
958 ee->ee_q_cal[ee_mode]);
959
960 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
961 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
962 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
963 ee->ee_margin_tx_rx[ee_mode]);
964
965 } else {
966 mdelay(1);
967 /* Disable phy and wait */
968 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
969 mdelay(1);
970 }
971
972 /*
973 * Restore saved values
974 */
975 /*DCU/Antenna selection not available on 5210*/
976 if (ah->ah_version != AR5K_AR5210) {
977 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
978 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
979 }
980 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
981 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
982 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
983
984 /*
985 * Misc
986 */
987 /* XXX: add ah->aid once mac80211 gives this to us */
988 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
989
990 ath5k_hw_set_opmode(ah);
991 /*PISR/SISR Not available on 5210*/
992 if (ah->ah_version != AR5K_AR5210) {
993 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
994 /* If we later allow tuning for this, store into sc structure */
995 data = AR5K_TUNE_RSSI_THRES |
996 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
997 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
998 }
999
1000 /*
1001 * Set Rx/Tx DMA Configuration
1002 *
1003 * Set maximum DMA size (512) except for PCI-E cards since
1004 * it causes rx overruns and tx errors (tested on 5424 but since
1005 * rx overruns also occur on 5416/5418 with madwifi we set 128
1006 * for all PCI-E cards to be safe).
1007 *
1008 * In dumps this is 128 for allchips.
1009 *
1010 * XXX: need to check 5210 for this
1011 * TODO: Check out tx triger level, it's always 64 on dumps but I
1012 * guess we can tweak it and see how it goes ;-)
1013 */
1014 dma_size = (pdev->is_pcie) ? AR5K_DMASIZE_128B : AR5K_DMASIZE_512B;
1015 if (ah->ah_version != AR5K_AR5210) {
1016 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1017 AR5K_TXCFG_SDMAMR, dma_size);
1018 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1019 AR5K_RXCFG_SDMAMW, dma_size);
1020 }
1021
1022 /*
1023 * Enable the PHY and wait until completion
1024 */
1025 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1026
1027 /*
1028 * On 5211+ read activation -> rx delay
1029 * and use it.
1030 */
1031 if (ah->ah_version != AR5K_AR5210) {
1032 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1033 AR5K_PHY_RX_DELAY_M;
1034 data = (channel->hw_value & CHANNEL_CCK) ?
1035 ((data << 2) / 22) : (data / 10);
1036
1037 udelay(100 + (2 * data));
1038 data = 0;
1039 } else {
1040 mdelay(1);
1041 }
1042
1043 /*
1044 * Perform ADC test (?)
1045 */
1046 data = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1047 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1048 for (i = 0; i <= 20; i++) {
1049 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1050 break;
1051 udelay(200);
1052 }
1053 ath5k_hw_reg_write(ah, data, AR5K_PHY_TST1);
1054 data = 0;
1055
1056 /*
1057 * Start automatic gain calibration
1058 *
1059 * During AGC calibration RX path is re-routed to
1060 * a signal detector so we don't receive anything.
1061 *
1062 * This method is used to calibrate some static offsets
1063 * used together with on-the fly I/Q calibration (the
1064 * one performed via ath5k_hw_phy_calibrate), that doesn't
1065 * interrupt rx path.
1066 *
1067 * If we are in a noisy environment AGC calibration may time
1068 * out.
1069 */
1070 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1071 AR5K_PHY_AGCCTL_CAL);
1072
1073 /* At the same time start I/Q calibration for QAM constellation
1074 * -no need for CCK- */
1075 ah->ah_calibration = false;
1076 if (!(mode == AR5K_MODE_11B)) {
1077 ah->ah_calibration = true;
1078 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1079 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1080 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1081 AR5K_PHY_IQ_RUN);
1082 }
1083
1084 /* Wait for gain calibration to finish (we check for I/Q calibration
1085 * during ath5k_phy_calibrate) */
1086 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1087 AR5K_PHY_AGCCTL_CAL, 0, false)) {
1088 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
1089 channel->center_freq);
1090 return -EAGAIN;
1091 }
1092
1093 /*
1094 * Start noise floor calibration
1095 *
1096 * If we run NF calibration before AGC, it always times out.
1097 * Binary HAL starts NF and AGC calibration at the same time
1098 * and only waits for AGC to finish. I believe that's wrong because
1099 * during NF calibration, rx path is also routed to a detector, so if
1100 * it doesn't finish we won't have RX.
1101 *
1102 * XXX: Find an interval that's OK for all cards...
1103 */
1104 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
1105 if (ret)
1106 return ret;
1107
1108 /*
1109 * Reset queues and start beacon timers at the end of the reset routine
1110 */
1111 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1112 /*No QCU on 5210*/
1113 if (ah->ah_version != AR5K_AR5210)
1114 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
1115
1116 ret = ath5k_hw_reset_tx_queue(ah, i);
1117 if (ret) {
1118 ATH5K_ERR(ah->ah_sc,
1119 "failed to reset TX queue #%d\n", i);
1120 return ret;
1121 }
1122 }
1123
1124 /* Pre-enable interrupts on 5211/5212*/
1125 if (ah->ah_version != AR5K_AR5210)
1126 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
1127 AR5K_INT_FATAL);
1128
1129 /*
1130 * Set RF kill flags if supported by the device (read from the EEPROM)
1131 * Disable gpio_intr for now since it results system hang.
1132 * TODO: Handle this in ath5k_intr
1133 */
1134#if 0
1135 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
1136 ath5k_hw_set_gpio_input(ah, 0);
1137 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
1138 if (ah->ah_gpio[0] == 0)
1139 ath5k_hw_set_gpio_intr(ah, 0, 1);
1140 else
1141 ath5k_hw_set_gpio_intr(ah, 0, 0);
1142 }
1143#endif
1144
1145 /*
1146 * Set the 32MHz reference clock on 5212 phy clock sleep register
1147 *
1148 * TODO: Find out how to switch to external 32Khz clock to save power
1149 */
1150 if (ah->ah_version == AR5K_AR5212) {
1151 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
1152 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
1153 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
1154 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
1155 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
1156 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
1157
1158 data = ath5k_hw_reg_read(ah, AR5K_USEC_5211) & 0xffffc07f ;
1159 data |= (ah->ah_phy_spending == AR5K_PHY_SPENDING_18) ?
1160 0x00000f80 : 0x00001380 ;
1161 ath5k_hw_reg_write(ah, data, AR5K_USEC_5211);
1162 data = 0;
1163 }
1164
1165 if (ah->ah_version == AR5K_AR5212) {
1166 ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
1167 ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
1168 ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
1169 if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)
1170 ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
1171 }
1172
1173 /*
1174 * Disable beacons and reset the register
1175 */
1176 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1177 AR5K_BEACON_RESET_TSF);
1178
1179 return 0;
1180}
1181
1182/*
1183 * Reset chipset
1184 */
1185static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1186{
1187 int ret;
1188 u32 mask = val ? val : ~0U;
1189
1190 ATH5K_TRACE(ah->ah_sc);
1191
1192 /* Read-and-clear RX Descriptor Pointer*/
1193 ath5k_hw_reg_read(ah, AR5K_RXDP);
1194
1195 /*
1196 * Reset the device and wait until success
1197 */
1198 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1199
1200 /* Wait at least 128 PCI clocks */
1201 udelay(15);
1202
1203 if (ah->ah_version == AR5K_AR5210) {
1204 val &= AR5K_RESET_CTL_CHIP;
1205 mask &= AR5K_RESET_CTL_CHIP;
1206 } else {
1207 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1208 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1209 }
1210
1211 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1212
1213 /*
1214 * Reset configuration register (for hw byte-swap). Note that this
1215 * is only set for big endian. We do the necessary magic in
1216 * AR5K_INIT_CFG.
1217 */
1218 if ((val & AR5K_RESET_CTL_PCU) == 0)
1219 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1220
1221 return ret;
1222}
1223
1224/*
1225 * Power management functions
1226 */
1227
1228/*
1229 * Sleep control
1230 */
1231int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1232 bool set_chip, u16 sleep_duration)
1233{
1234 unsigned int i;
1235 u32 staid, data;
1236
1237 ATH5K_TRACE(ah->ah_sc);
1238 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1239
1240 switch (mode) {
1241 case AR5K_PM_AUTO:
1242 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1243 /* fallthrough */
1244 case AR5K_PM_NETWORK_SLEEP:
1245 if (set_chip)
1246 ath5k_hw_reg_write(ah,
1247 AR5K_SLEEP_CTL_SLE_ALLOW |
1248 sleep_duration,
1249 AR5K_SLEEP_CTL);
1250
1251 staid |= AR5K_STA_ID1_PWR_SV;
1252 break;
1253
1254 case AR5K_PM_FULL_SLEEP:
1255 if (set_chip)
1256 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1257 AR5K_SLEEP_CTL);
1258
1259 staid |= AR5K_STA_ID1_PWR_SV;
1260 break;
1261
1262 case AR5K_PM_AWAKE:
1263
1264 staid &= ~AR5K_STA_ID1_PWR_SV;
1265
1266 if (!set_chip)
1267 goto commit;
1268
1269 /* Preserve sleep duration */
1270 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
1271 if( data & 0xffc00000 ){
1272 data = 0;
1273 } else {
1274 data = data & 0xfffcffff;
1275 }
1276
1277 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
1278 udelay(15);
1279
1280 for (i = 50; i > 0; i--) {
1281 /* Check if the chip did wake up */
1282 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1283 AR5K_PCICFG_SPWR_DN) == 0)
1284 break;
1285
1286 /* Wait a bit and retry */
1287 udelay(200);
1288 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
1289 }
1290
1291 /* Fail if the chip didn't wake up */
1292 if (i <= 0)
1293 return -EIO;
1294
1295 break;
1296
1297 default:
1298 return -EINVAL;
1299 }
1300
1301commit:
1302 ah->ah_power_mode = mode;
1303 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1304
1305 return 0;
1306}
1307
1308/***********************\
1309 DMA Related Functions
1310\***********************/
1311
1312/*
1313 * Receive functions
1314 */
1315
1316/*
1317 * Start DMA receive
1318 */
1319void ath5k_hw_start_rx(struct ath5k_hw *ah)
1320{
1321 ATH5K_TRACE(ah->ah_sc);
1322 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
1323 ath5k_hw_reg_read(ah, AR5K_CR);
1324}
1325
1326/*
1327 * Stop DMA receive
1328 */
1329int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1330{
1331 unsigned int i;
1332
1333 ATH5K_TRACE(ah->ah_sc);
1334 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1335
1336 /*
1337 * It may take some time to disable the DMA receive unit
1338 */
1339 for (i = 2000; i > 0 &&
1340 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1341 i--)
1342 udelay(10);
1343
1344 return i ? 0 : -EBUSY;
1345}
1346
1347/*
1348 * Get the address of the RX Descriptor
1349 */
1350u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1351{
1352 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1353}
1354
1355/*
1356 * Set the address of the RX Descriptor
1357 */
1358void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1359{
1360 ATH5K_TRACE(ah->ah_sc);
1361
1362 /*TODO:Shouldn't we check if RX is enabled first ?*/
1363 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1364}
1365
1366/*
1367 * Transmit functions
1368 */
1369
1370/*
1371 * Start DMA transmit for a specific queue
1372 * (see also QCU/DCU functions)
1373 */
1374int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1375{
1376 u32 tx_queue;
1377
1378 ATH5K_TRACE(ah->ah_sc);
1379 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1380
1381 /* Return if queue is declared inactive */
1382 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1383 return -EIO;
1384
1385 if (ah->ah_version == AR5K_AR5210) {
1386 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1387
1388 /*
1389 * Set the queue by type on 5210
1390 */
1391 switch (ah->ah_txq[queue].tqi_type) {
1392 case AR5K_TX_QUEUE_DATA:
1393 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1394 break;
1395 case AR5K_TX_QUEUE_BEACON:
1396 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1397 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1398 AR5K_BSR);
1399 break;
1400 case AR5K_TX_QUEUE_CAB:
1401 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1402 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1403 AR5K_BCR_BDMAE, AR5K_BSR);
1404 break;
1405 default:
1406 return -EINVAL;
1407 }
1408 /* Start queue */
1409 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1410 ath5k_hw_reg_read(ah, AR5K_CR);
1411 } else {
1412 /* Return if queue is disabled */
1413 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1414 return -EIO;
1415
1416 /* Start queue */
1417 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1418 }
1419
1420 return 0;
1421}
1422
1423/*
1424 * Stop DMA transmit for a specific queue
1425 * (see also QCU/DCU functions)
1426 */
1427int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1428{
1429 unsigned int i = 100;
1430 u32 tx_queue, pending;
1431
1432 ATH5K_TRACE(ah->ah_sc);
1433 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1434
1435 /* Return if queue is declared inactive */
1436 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1437 return -EIO;
1438
1439 if (ah->ah_version == AR5K_AR5210) {
1440 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1441
1442 /*
1443 * Set by queue type
1444 */
1445 switch (ah->ah_txq[queue].tqi_type) {
1446 case AR5K_TX_QUEUE_DATA:
1447 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1448 break;
1449 case AR5K_TX_QUEUE_BEACON:
1450 case AR5K_TX_QUEUE_CAB:
1451 /* XXX Fix me... */
1452 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1453 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1454 break;
1455 default:
1456 return -EINVAL;
1457 }
1458
1459 /* Stop queue */
1460 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1461 ath5k_hw_reg_read(ah, AR5K_CR);
1462 } else {
1463 /*
1464 * Schedule TX disable and wait until queue is empty
1465 */
1466 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1467
1468 /*Check for pending frames*/
1469 do {
1470 pending = ath5k_hw_reg_read(ah,
1471 AR5K_QUEUE_STATUS(queue)) &
1472 AR5K_QCU_STS_FRMPENDCNT;
1473 udelay(100);
1474 } while (--i && pending);
1475
1476 /* Clear register */
1477 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
1478 if (pending)
1479 return -EBUSY;
1480 }
1481
1482 /* TODO: Check for success else return error */
1483 return 0;
1484}
1485
1486/*
1487 * Get the address of the TX Descriptor for a specific queue
1488 * (see also QCU/DCU functions)
1489 */
1490u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1491{
1492 u16 tx_reg;
1493
1494 ATH5K_TRACE(ah->ah_sc);
1495 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1496
1497 /*
1498 * Get the transmit queue descriptor pointer from the selected queue
1499 */
1500 /*5210 doesn't have QCU*/
1501 if (ah->ah_version == AR5K_AR5210) {
1502 switch (ah->ah_txq[queue].tqi_type) {
1503 case AR5K_TX_QUEUE_DATA:
1504 tx_reg = AR5K_NOQCU_TXDP0;
1505 break;
1506 case AR5K_TX_QUEUE_BEACON:
1507 case AR5K_TX_QUEUE_CAB:
1508 tx_reg = AR5K_NOQCU_TXDP1;
1509 break;
1510 default:
1511 return 0xffffffff;
1512 }
1513 } else {
1514 tx_reg = AR5K_QUEUE_TXDP(queue);
1515 }
1516
1517 return ath5k_hw_reg_read(ah, tx_reg);
1518}
1519
1520/*
1521 * Set the address of the TX Descriptor for a specific queue
1522 * (see also QCU/DCU functions)
1523 */
1524int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1525{
1526 u16 tx_reg;
1527
1528 ATH5K_TRACE(ah->ah_sc);
1529 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1530
1531 /*
1532 * Set the transmit queue descriptor pointer register by type
1533 * on 5210
1534 */
1535 if (ah->ah_version == AR5K_AR5210) {
1536 switch (ah->ah_txq[queue].tqi_type) {
1537 case AR5K_TX_QUEUE_DATA:
1538 tx_reg = AR5K_NOQCU_TXDP0;
1539 break;
1540 case AR5K_TX_QUEUE_BEACON:
1541 case AR5K_TX_QUEUE_CAB:
1542 tx_reg = AR5K_NOQCU_TXDP1;
1543 break;
1544 default:
1545 return -EINVAL;
1546 }
1547 } else {
1548 /*
1549 * Set the transmit queue descriptor pointer for
1550 * the selected queue on QCU for 5211+
1551 * (this won't work if the queue is still active)
1552 */
1553 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1554 return -EIO;
1555
1556 tx_reg = AR5K_QUEUE_TXDP(queue);
1557 }
1558
1559 /* Set descriptor pointer */
1560 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1561
1562 return 0;
1563}
1564
1565/*
1566 * Update tx trigger level
1567 */
1568int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1569{
1570 u32 trigger_level, imr;
1571 int ret = -EIO;
1572
1573 ATH5K_TRACE(ah->ah_sc);
1574
1575 /*
1576 * Disable interrupts by setting the mask
1577 */
1578 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1579
1580 /*TODO: Boundary check on trigger_level*/
1581 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1582 AR5K_TXCFG_TXFULL);
1583
1584 if (!increase) {
1585 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1586 goto done;
1587 } else
1588 trigger_level +=
1589 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1590
1591 /*
1592 * Update trigger level on success
1593 */
1594 if (ah->ah_version == AR5K_AR5210)
1595 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1596 else
1597 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1598 AR5K_TXCFG_TXFULL, trigger_level);
1599
1600 ret = 0;
1601
1602done:
1603 /*
1604 * Restore interrupt mask
1605 */
1606 ath5k_hw_set_intr(ah, imr);
1607
1608 return ret;
1609}
1610
1611/*
1612 * Interrupt handling
1613 */
1614
1615/*
1616 * Check if we have pending interrupts
1617 */
1618bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1619{
1620 ATH5K_TRACE(ah->ah_sc);
1621 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1622}
1623
1624/*
1625 * Get interrupt mask (ISR)
1626 */
1627int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1628{
1629 u32 data;
1630
1631 ATH5K_TRACE(ah->ah_sc);
1632
1633 /*
1634 * Read interrupt status from the Interrupt Status register
1635 * on 5210
1636 */
1637 if (ah->ah_version == AR5K_AR5210) {
1638 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1639 if (unlikely(data == AR5K_INT_NOCARD)) {
1640 *interrupt_mask = data;
1641 return -ENODEV;
1642 }
1643 } else {
1644 /*
1645 * Read interrupt status from the Read-And-Clear shadow register
1646 * Note: PISR/SISR Not available on 5210
1647 */
1648 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1649 }
1650
1651 /*
1652 * Get abstract interrupt mask (driver-compatible)
1653 */
1654 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1655
1656 if (unlikely(data == AR5K_INT_NOCARD))
1657 return -ENODEV;
1658
1659 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1660 *interrupt_mask |= AR5K_INT_RX;
1661
1662 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1663 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1664 *interrupt_mask |= AR5K_INT_TX;
1665
1666 if (ah->ah_version != AR5K_AR5210) {
1667 /*HIU = Host Interface Unit (PCI etc)*/
1668 if (unlikely(data & (AR5K_ISR_HIUERR)))
1669 *interrupt_mask |= AR5K_INT_FATAL;
1670
1671 /*Beacon Not Ready*/
1672 if (unlikely(data & (AR5K_ISR_BNR)))
1673 *interrupt_mask |= AR5K_INT_BNR;
1674 }
1675
1676 /*
1677 * XXX: BMISS interrupts may occur after association.
1678 * I found this on 5210 code but it needs testing. If this is
1679 * true we should disable them before assoc and re-enable them
1680 * after a successfull assoc + some jiffies.
1681 */
1682#if 0
1683 interrupt_mask &= ~AR5K_INT_BMISS;
1684#endif
1685
1686 /*
1687 * In case we didn't handle anything,
1688 * print the register value.
1689 */
1690 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1691 ATH5K_PRINTF("0x%08x\n", data);
1692
1693 return 0;
1694}
1695
1696/*
1697 * Set interrupt mask
1698 */
1699enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1700{
1701 enum ath5k_int old_mask, int_mask;
1702
1703 /*
1704 * Disable card interrupts to prevent any race conditions
1705 * (they will be re-enabled afterwards).
1706 */
1707 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
1708 ath5k_hw_reg_read(ah, AR5K_IER);
1709
1710 old_mask = ah->ah_imr;
1711
1712 /*
1713 * Add additional, chipset-dependent interrupt mask flags
1714 * and write them to the IMR (interrupt mask register).
1715 */
1716 int_mask = new_mask & AR5K_INT_COMMON;
1717
1718 if (new_mask & AR5K_INT_RX)
1719 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1720 AR5K_IMR_RXDESC;
1721
1722 if (new_mask & AR5K_INT_TX)
1723 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1724 AR5K_IMR_TXURN;
1725
1726 if (ah->ah_version != AR5K_AR5210) {
1727 if (new_mask & AR5K_INT_FATAL) {
1728 int_mask |= AR5K_IMR_HIUERR;
1729 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1730 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1731 }
1732 }
1733
1734 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1735
1736 /* Store new interrupt mask */
1737 ah->ah_imr = new_mask;
1738
1739 /* ..re-enable interrupts */
1740 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
1741 ath5k_hw_reg_read(ah, AR5K_IER);
1742
1743 return old_mask;
1744}
1745
1746
1747/*************************\
1748 EEPROM access functions
1749\*************************/
1750
1751/*
1752 * Read from eeprom
1753 */
1754static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1755{
1756 u32 status, timeout;
1757
1758 ATH5K_TRACE(ah->ah_sc);
1759 /*
1760 * Initialize EEPROM access
1761 */
1762 if (ah->ah_version == AR5K_AR5210) {
1763 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1764 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1765 } else {
1766 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1767 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1768 AR5K_EEPROM_CMD_READ);
1769 }
1770
1771 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1772 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1773 if (status & AR5K_EEPROM_STAT_RDDONE) {
1774 if (status & AR5K_EEPROM_STAT_RDERR)
1775 return -EIO;
1776 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1777 0xffff);
1778 return 0;
1779 }
1780 udelay(15);
1781 }
1782
1783 return -ETIMEDOUT;
1784}
1785
1786/*
1787 * Write to eeprom - currently disabled, use at your own risk
1788 */
1789#if 0
1790static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1791{
1792
1793 u32 status, timeout;
1794
1795 ATH5K_TRACE(ah->ah_sc);
1796
1797 /*
1798 * Initialize eeprom access
1799 */
1800
1801 if (ah->ah_version == AR5K_AR5210) {
1802 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1803 } else {
1804 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1805 AR5K_EEPROM_CMD_RESET);
1806 }
1807
1808 /*
1809 * Write data to data register
1810 */
1811
1812 if (ah->ah_version == AR5K_AR5210) {
1813 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1814 } else {
1815 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1816 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1817 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1818 AR5K_EEPROM_CMD_WRITE);
1819 }
1820
1821 /*
1822 * Check status
1823 */
1824
1825 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1826 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1827 if (status & AR5K_EEPROM_STAT_WRDONE) {
1828 if (status & AR5K_EEPROM_STAT_WRERR)
1829 return EIO;
1830 return 0;
1831 }
1832 udelay(15);
1833 }
1834
1835 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1836 return -EIO;
1837}
1838#endif
1839
1840/*
1841 * Translate binary channel representation in EEPROM to frequency
1842 */
1843static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1844{
1845 u16 val;
1846
1847 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1848 return bin;
1849
1850 if (mode == AR5K_EEPROM_MODE_11A) {
1851 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1852 val = (5 * bin) + 4800;
1853 else
1854 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1855 (bin * 10) + 5100;
1856 } else {
1857 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1858 val = bin + 2300;
1859 else
1860 val = bin + 2400;
1861 }
1862
1863 return val;
1864}
1865
1866/*
1867 * Read antenna infos from eeprom
1868 */
1869static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1870 unsigned int mode)
1871{
1872 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1873 u32 o = *offset;
1874 u16 val;
1875 int ret, i = 0;
1876
1877 AR5K_EEPROM_READ(o++, val);
1878 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1879 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1880 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1881
1882 AR5K_EEPROM_READ(o++, val);
1883 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1884 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1885 ee->ee_ant_control[mode][i++] = val & 0x3f;
1886
1887 AR5K_EEPROM_READ(o++, val);
1888 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1889 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1890 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1891
1892 AR5K_EEPROM_READ(o++, val);
1893 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1894 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1895 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1896 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1897
1898 AR5K_EEPROM_READ(o++, val);
1899 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1900 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1901 ee->ee_ant_control[mode][i++] = val & 0x3f;
1902
1903 /* Get antenna modes */
1904 ah->ah_antenna[mode][0] =
1905 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1906 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1907 ee->ee_ant_control[mode][1] |
1908 (ee->ee_ant_control[mode][2] << 6) |
1909 (ee->ee_ant_control[mode][3] << 12) |
1910 (ee->ee_ant_control[mode][4] << 18) |
1911 (ee->ee_ant_control[mode][5] << 24);
1912 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1913 ee->ee_ant_control[mode][6] |
1914 (ee->ee_ant_control[mode][7] << 6) |
1915 (ee->ee_ant_control[mode][8] << 12) |
1916 (ee->ee_ant_control[mode][9] << 18) |
1917 (ee->ee_ant_control[mode][10] << 24);
1918
1919 /* return new offset */
1920 *offset = o;
1921
1922 return 0;
1923}
1924
1925/*
1926 * Read supported modes from eeprom
1927 */
1928static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1929 unsigned int mode)
1930{
1931 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1932 u32 o = *offset;
1933 u16 val;
1934 int ret;
1935
1936 AR5K_EEPROM_READ(o++, val);
1937 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1938 ee->ee_thr_62[mode] = val & 0xff;
1939
1940 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1941 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1942
1943 AR5K_EEPROM_READ(o++, val);
1944 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1945 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1946
1947 AR5K_EEPROM_READ(o++, val);
1948 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1949
1950 if ((val & 0xff) & 0x80)
1951 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1952 else
1953 ee->ee_noise_floor_thr[mode] = val & 0xff;
1954
1955 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1956 ee->ee_noise_floor_thr[mode] =
1957 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1958
1959 AR5K_EEPROM_READ(o++, val);
1960 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1961 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
1962 ee->ee_xpd[mode] = val & 0x1;
1963
1964 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
1965 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
1966
1967 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
1968 AR5K_EEPROM_READ(o++, val);
1969 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
1970
1971 if (mode == AR5K_EEPROM_MODE_11A)
1972 ee->ee_xr_power[mode] = val & 0x3f;
1973 else {
1974 ee->ee_ob[mode][0] = val & 0x7;
1975 ee->ee_db[mode][0] = (val >> 3) & 0x7;
1976 }
1977 }
1978
1979 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
1980 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
1981 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
1982 } else {
1983 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
1984
1985 AR5K_EEPROM_READ(o++, val);
1986 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
1987
1988 if (mode == AR5K_EEPROM_MODE_11G)
1989 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1990 }
1991
1992 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
1993 mode == AR5K_EEPROM_MODE_11A) {
1994 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1995 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1996 }
1997
1998 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
1999 mode == AR5K_EEPROM_MODE_11G)
2000 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
2001
2002 /* return new offset */
2003 *offset = o;
2004
2005 return 0;
2006}
2007
2008/*
2009 * Initialize eeprom & capabilities structs
2010 */
2011static int ath5k_eeprom_init(struct ath5k_hw *ah)
2012{
2013 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2014 unsigned int mode, i;
2015 int ret;
2016 u32 offset;
2017 u16 val;
2018
2019 /* Initial TX thermal adjustment values */
2020 ee->ee_tx_clip = 4;
2021 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
2022 ee->ee_gain_select = 1;
2023
2024 /*
2025 * Read values from EEPROM and store them in the capability structure
2026 */
2027 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
2028 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
2029 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
2030 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
2031 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
2032
2033 /* Return if we have an old EEPROM */
2034 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
2035 return 0;
2036
2037#ifdef notyet
2038 /*
2039 * Validate the checksum of the EEPROM date. There are some
2040 * devices with invalid EEPROMs.
2041 */
2042 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
2043 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
2044 cksum ^= val;
2045 }
2046 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
2047 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
2048 return -EIO;
2049 }
2050#endif
2051
2052 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
2053 ee_ant_gain);
2054
2055 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2056 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
2057 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
2058 }
2059
2060 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
2061 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
2062 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
2063 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
2064
2065 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
2066 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
2067 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
2068 }
2069
2070 /*
2071 * Get conformance test limit values
2072 */
2073 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
2074 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
2075
2076 for (i = 0; i < ee->ee_ctls; i++) {
2077 AR5K_EEPROM_READ(offset++, val);
2078 ee->ee_ctl[i] = (val >> 8) & 0xff;
2079 ee->ee_ctl[i + 1] = val & 0xff;
2080 }
2081
2082 /*
2083 * Get values for 802.11a (5GHz)
2084 */
2085 mode = AR5K_EEPROM_MODE_11A;
2086
2087 ee->ee_turbo_max_power[mode] =
2088 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
2089
2090 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
2091
2092 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2093 if (ret)
2094 return ret;
2095
2096 AR5K_EEPROM_READ(offset++, val);
2097 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2098 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
2099 ee->ee_db[mode][3] = (val >> 2) & 0x7;
2100 ee->ee_ob[mode][2] = (val << 1) & 0x7;
2101
2102 AR5K_EEPROM_READ(offset++, val);
2103 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
2104 ee->ee_db[mode][2] = (val >> 12) & 0x7;
2105 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
2106 ee->ee_db[mode][1] = (val >> 6) & 0x7;
2107 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
2108 ee->ee_db[mode][0] = val & 0x7;
2109
2110 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2111 if (ret)
2112 return ret;
2113
2114 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
2115 AR5K_EEPROM_READ(offset++, val);
2116 ee->ee_margin_tx_rx[mode] = val & 0x3f;
2117 }
2118
2119 /*
2120 * Get values for 802.11b (2.4GHz)
2121 */
2122 mode = AR5K_EEPROM_MODE_11B;
2123 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
2124
2125 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2126 if (ret)
2127 return ret;
2128
2129 AR5K_EEPROM_READ(offset++, val);
2130 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2131 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2132 ee->ee_db[mode][1] = val & 0x7;
2133
2134 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2135 if (ret)
2136 return ret;
2137
2138 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2139 AR5K_EEPROM_READ(offset++, val);
2140 ee->ee_cal_pier[mode][0] =
2141 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2142 ee->ee_cal_pier[mode][1] =
2143 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2144
2145 AR5K_EEPROM_READ(offset++, val);
2146 ee->ee_cal_pier[mode][2] =
2147 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2148 }
2149
2150 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2151 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2152
2153 /*
2154 * Get values for 802.11g (2.4GHz)
2155 */
2156 mode = AR5K_EEPROM_MODE_11G;
2157 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
2158
2159 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2160 if (ret)
2161 return ret;
2162
2163 AR5K_EEPROM_READ(offset++, val);
2164 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2165 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2166 ee->ee_db[mode][1] = val & 0x7;
2167
2168 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2169 if (ret)
2170 return ret;
2171
2172 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2173 AR5K_EEPROM_READ(offset++, val);
2174 ee->ee_cal_pier[mode][0] =
2175 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2176 ee->ee_cal_pier[mode][1] =
2177 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2178
2179 AR5K_EEPROM_READ(offset++, val);
2180 ee->ee_turbo_max_power[mode] = val & 0x7f;
2181 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
2182
2183 AR5K_EEPROM_READ(offset++, val);
2184 ee->ee_cal_pier[mode][2] =
2185 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2186
2187 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2188 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2189
2190 AR5K_EEPROM_READ(offset++, val);
2191 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
2192 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
2193
2194 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
2195 AR5K_EEPROM_READ(offset++, val);
2196 ee->ee_cck_ofdm_gain_delta = val & 0xff;
2197 }
2198 }
2199
2200 /*
2201 * Read 5GHz EEPROM channels
2202 */
2203
2204 return 0;
2205}
2206
2207/*
2208 * Read the MAC address from eeprom
2209 */
2210static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2211{
2212 u8 mac_d[ETH_ALEN];
2213 u32 total, offset;
2214 u16 data;
2215 int octet, ret;
2216
2217 memset(mac, 0, ETH_ALEN);
2218 memset(mac_d, 0, ETH_ALEN);
2219
2220 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2221 if (ret)
2222 return ret;
2223
2224 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2225 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2226 if (ret)
2227 return ret;
2228
2229 total += data;
2230 mac_d[octet + 1] = data & 0xff;
2231 mac_d[octet] = data >> 8;
2232 octet += 2;
2233 }
2234
2235 memcpy(mac, mac_d, ETH_ALEN);
2236
2237 if (!total || total == 3 * 0xffff)
2238 return -EINVAL;
2239
2240 return 0;
2241}
2242
2243/*
2244 * Fill the capabilities struct
2245 */
2246static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2247{
2248 u16 ee_header;
2249
2250 ATH5K_TRACE(ah->ah_sc);
2251 /* Capabilities stored in the EEPROM */
2252 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2253
2254 if (ah->ah_version == AR5K_AR5210) {
2255 /*
2256 * Set radio capabilities
2257 * (The AR5110 only supports the middle 5GHz band)
2258 */
2259 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2260 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2261 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2262 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2263
2264 /* Set supported modes */
2265 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
2266 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
2267 } else {
2268 /*
2269 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2270 * XXX and from 2312 to 2732GHz. There are problems with the
2271 * XXX current ieee80211 implementation because the IEEE
2272 * XXX channel mapping does not support negative channel
2273 * XXX numbers (2312MHz is channel -19). Of course, this
2274 * XXX doesn't matter because these channels are out of range
2275 * XXX but some regulation domains like MKK (Japan) will
2276 * XXX support frequencies somewhere around 4.8GHz.
2277 */
2278
2279 /*
2280 * Set radio capabilities
2281 */
2282
2283 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2284 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2285 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2286
2287 /* Set supported modes */
2288 __set_bit(AR5K_MODE_11A,
2289 ah->ah_capabilities.cap_mode);
2290 __set_bit(AR5K_MODE_11A_TURBO,
2291 ah->ah_capabilities.cap_mode);
2292 if (ah->ah_version == AR5K_AR5212)
2293 __set_bit(AR5K_MODE_11G_TURBO,
2294 ah->ah_capabilities.cap_mode);
2295 }
2296
2297 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2298 * connected */
2299 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2300 AR5K_EEPROM_HDR_11G(ee_header)) {
2301 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2302 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2303
2304 if (AR5K_EEPROM_HDR_11B(ee_header))
2305 __set_bit(AR5K_MODE_11B,
2306 ah->ah_capabilities.cap_mode);
2307
2308 if (AR5K_EEPROM_HDR_11G(ee_header))
2309 __set_bit(AR5K_MODE_11G,
2310 ah->ah_capabilities.cap_mode);
2311 }
2312 }
2313
2314 /* GPIO */
2315 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2316
2317 /* Set number of supported TX queues */
2318 if (ah->ah_version == AR5K_AR5210)
2319 ah->ah_capabilities.cap_queues.q_tx_num =
2320 AR5K_NUM_TX_QUEUES_NOQCU;
2321 else
2322 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2323
2324 return 0;
2325}
2326
2327/*********************************\
2328 Protocol Control Unit Functions
2329\*********************************/
2330
2331/*
2332 * Set Operation mode
2333 */
2334int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2335{
2336 u32 pcu_reg, beacon_reg, low_id, high_id;
2337
2338 pcu_reg = 0;
2339 beacon_reg = 0;
2340
2341 ATH5K_TRACE(ah->ah_sc);
2342
2343 switch (ah->ah_op_mode) {
2344 case IEEE80211_IF_TYPE_IBSS:
2345 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2346 (ah->ah_version == AR5K_AR5210 ?
2347 AR5K_STA_ID1_NO_PSPOLL : 0);
2348 beacon_reg |= AR5K_BCR_ADHOC;
2349 break;
2350
2351 case IEEE80211_IF_TYPE_AP:
2352 case IEEE80211_IF_TYPE_MESH_POINT:
2353 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2354 (ah->ah_version == AR5K_AR5210 ?
2355 AR5K_STA_ID1_NO_PSPOLL : 0);
2356 beacon_reg |= AR5K_BCR_AP;
2357 break;
2358
2359 case IEEE80211_IF_TYPE_STA:
2360 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2361 (ah->ah_version == AR5K_AR5210 ?
2362 AR5K_STA_ID1_PWR_SV : 0);
2363 case IEEE80211_IF_TYPE_MNTR:
2364 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2365 (ah->ah_version == AR5K_AR5210 ?
2366 AR5K_STA_ID1_NO_PSPOLL : 0);
2367 break;
2368
2369 default:
2370 return -EINVAL;
2371 }
2372
2373 /*
2374 * Set PCU registers
2375 */
2376 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2377 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2378 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2379 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2380
2381 /*
2382 * Set Beacon Control Register on 5210
2383 */
2384 if (ah->ah_version == AR5K_AR5210)
2385 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2386
2387 return 0;
2388}
2389
2390/*
2391 * BSSID Functions
2392 */
2393
2394/*
2395 * Get station id
2396 */
2397void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2398{
2399 ATH5K_TRACE(ah->ah_sc);
2400 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2401}
2402
2403/*
2404 * Set station id
2405 */
2406int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2407{
2408 u32 low_id, high_id;
2409
2410 ATH5K_TRACE(ah->ah_sc);
2411 /* Set new station ID */
2412 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2413
2414 low_id = AR5K_LOW_ID(mac);
2415 high_id = AR5K_HIGH_ID(mac);
2416
2417 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2418 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2419
2420 return 0;
2421}
2422
2423/*
2424 * Set BSSID
2425 */
2426void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2427{
2428 u32 low_id, high_id;
2429 u16 tim_offset = 0;
2430
2431 /*
2432 * Set simple BSSID mask on 5212
2433 */
2434 if (ah->ah_version == AR5K_AR5212) {
2435 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM0);
2436 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM1);
2437 }
2438
2439 /*
2440 * Set BSSID which triggers the "SME Join" operation
2441 */
2442 low_id = AR5K_LOW_ID(bssid);
2443 high_id = AR5K_HIGH_ID(bssid);
2444 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2445 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2446 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2447
2448 if (assoc_id == 0) {
2449 ath5k_hw_disable_pspoll(ah);
2450 return;
2451 }
2452
2453 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2454 tim_offset ? tim_offset + 4 : 0);
2455
2456 ath5k_hw_enable_pspoll(ah, NULL, 0);
2457}
2458/**
2459 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2460 *
2461 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2462 * which bits of the interface's MAC address should be looked at when trying
2463 * to decide which packets to ACK. In station mode every bit matters. In AP
2464 * mode with a single BSS every bit matters as well. In AP mode with
2465 * multiple BSSes not every bit matters.
2466 *
2467 * @ah: the &struct ath5k_hw
2468 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2469 *
2470 * Note that this is a simple filter and *does* not filter out all
2471 * relevant frames. Some non-relevant frames will get through, probability
2472 * jocks are welcomed to compute.
2473 *
2474 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2475 * computing the set of:
2476 *
2477 * ~ ( MAC XOR BSSID )
2478 *
2479 * When you do this you are essentially computing the common bits. Later it
2480 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2481 * to obtain the relevant bits which should match on the destination frame.
2482 *
2483 * Simple example: on your card you have have two BSSes you have created with
2484 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2485 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2486 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2487 *
2488 * \
2489 * MAC: 0001 |
2490 * BSSID-01: 0100 | --> Belongs to us
2491 * BSSID-02: 1001 |
2492 * /
2493 * -------------------
2494 * BSSID-03: 0110 | --> External
2495 * -------------------
2496 *
2497 * Our bssid_mask would then be:
2498 *
2499 * On loop iteration for BSSID-01:
2500 * ~(0001 ^ 0100) -> ~(0101)
2501 * -> 1010
2502 * bssid_mask = 1010
2503 *
2504 * On loop iteration for BSSID-02:
2505 * bssid_mask &= ~(0001 ^ 1001)
2506 * bssid_mask = (1010) & ~(0001 ^ 1001)
2507 * bssid_mask = (1010) & ~(1001)
2508 * bssid_mask = (1010) & (0110)
2509 * bssid_mask = 0010
2510 *
2511 * A bssid_mask of 0010 means "only pay attention to the second least
2512 * significant bit". This is because its the only bit common
2513 * amongst the MAC and all BSSIDs we support. To findout what the real
2514 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2515 * or our MAC address (we assume the hardware uses the MAC address).
2516 *
2517 * Now, suppose there's an incoming frame for BSSID-03:
2518 *
2519 * IFRAME-01: 0110
2520 *
2521 * An easy eye-inspeciton of this already should tell you that this frame
2522 * will not pass our check. This is beacuse the bssid_mask tells the
2523 * hardware to only look at the second least significant bit and the
2524 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2525 * as 1, which does not match 0.
2526 *
2527 * So with IFRAME-01 we *assume* the hardware will do:
2528 *
2529 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2530 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2531 * --> allow = (0010) == 0000 ? 1 : 0;
2532 * --> allow = 0
2533 *
2534 * Lets now test a frame that should work:
2535 *
2536 * IFRAME-02: 0001 (we should allow)
2537 *
2538 * allow = (0001 & 1010) == 1010
2539 *
2540 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2541 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2542 * --> allow = (0010) == (0010)
2543 * --> allow = 1
2544 *
2545 * Other examples:
2546 *
2547 * IFRAME-03: 0100 --> allowed
2548 * IFRAME-04: 1001 --> allowed
2549 * IFRAME-05: 1101 --> allowed but its not for us!!!
2550 *
2551 */
2552int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2553{
2554 u32 low_id, high_id;
2555 ATH5K_TRACE(ah->ah_sc);
2556
2557 if (ah->ah_version == AR5K_AR5212) {
2558 low_id = AR5K_LOW_ID(mask);
2559 high_id = AR5K_HIGH_ID(mask);
2560
2561 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2562 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2563
2564 return 0;
2565 }
2566
2567 return -EIO;
2568}
2569
2570/*
2571 * Receive start/stop functions
2572 */
2573
2574/*
2575 * Start receive on PCU
2576 */
2577void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2578{
2579 ATH5K_TRACE(ah->ah_sc);
2580 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2581
2582 /* TODO: ANI Support */
2583}
2584
2585/*
2586 * Stop receive on PCU
2587 */
2588void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2589{
2590 ATH5K_TRACE(ah->ah_sc);
2591 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2592
2593 /* TODO: ANI Support */
2594}
2595
2596/*
2597 * RX Filter functions
2598 */
2599
2600/*
2601 * Set multicast filter
2602 */
2603void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2604{
2605 ATH5K_TRACE(ah->ah_sc);
2606 /* Set the multicat filter */
2607 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2608 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2609}
2610
2611/*
2612 * Set multicast filter by index
2613 */
2614int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2615{
2616
2617 ATH5K_TRACE(ah->ah_sc);
2618 if (index >= 64)
2619 return -EINVAL;
2620 else if (index >= 32)
2621 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2622 (1 << (index - 32)));
2623 else
2624 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2625
2626 return 0;
2627}
2628
2629/*
2630 * Clear Multicast filter by index
2631 */
2632int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2633{
2634
2635 ATH5K_TRACE(ah->ah_sc);
2636 if (index >= 64)
2637 return -EINVAL;
2638 else if (index >= 32)
2639 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2640 (1 << (index - 32)));
2641 else
2642 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2643
2644 return 0;
2645}
2646
2647/*
2648 * Get current rx filter
2649 */
2650u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2651{
2652 u32 data, filter = 0;
2653
2654 ATH5K_TRACE(ah->ah_sc);
2655 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2656
2657 /*Radar detection for 5212*/
2658 if (ah->ah_version == AR5K_AR5212) {
2659 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2660
2661 if (data & AR5K_PHY_ERR_FIL_RADAR)
2662 filter |= AR5K_RX_FILTER_RADARERR;
2663 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2664 filter |= AR5K_RX_FILTER_PHYERR;
2665 }
2666
2667 return filter;
2668}
2669
2670/*
2671 * Set rx filter
2672 */
2673void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2674{
2675 u32 data = 0;
2676
2677 ATH5K_TRACE(ah->ah_sc);
2678
2679 /* Set PHY error filter register on 5212*/
2680 if (ah->ah_version == AR5K_AR5212) {
2681 if (filter & AR5K_RX_FILTER_RADARERR)
2682 data |= AR5K_PHY_ERR_FIL_RADAR;
2683 if (filter & AR5K_RX_FILTER_PHYERR)
2684 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2685 }
2686
2687 /*
2688 * The AR5210 uses promiscous mode to detect radar activity
2689 */
2690 if (ah->ah_version == AR5K_AR5210 &&
2691 (filter & AR5K_RX_FILTER_RADARERR)) {
2692 filter &= ~AR5K_RX_FILTER_RADARERR;
2693 filter |= AR5K_RX_FILTER_PROM;
2694 }
2695
2696 /*Zero length DMA*/
2697 if (data)
2698 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2699 else
2700 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2701
2702 /*Write RX Filter register*/
2703 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2704
2705 /*Write PHY error filter register on 5212*/
2706 if (ah->ah_version == AR5K_AR5212)
2707 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2708
2709}
2710
2711/*
2712 * Beacon related functions
2713 */
2714
2715/*
2716 * Get a 32bit TSF
2717 */
2718u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2719{
2720 ATH5K_TRACE(ah->ah_sc);
2721 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2722}
2723
2724/*
2725 * Get the full 64bit TSF
2726 */
2727u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2728{
2729 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2730 ATH5K_TRACE(ah->ah_sc);
2731
2732 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2733}
2734
2735/*
2736 * Force a TSF reset
2737 */
2738void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2739{
2740 ATH5K_TRACE(ah->ah_sc);
2741 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2742}
2743
2744/*
2745 * Initialize beacon timers
2746 */
2747void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2748{
2749 u32 timer1, timer2, timer3;
2750
2751 ATH5K_TRACE(ah->ah_sc);
2752 /*
2753 * Set the additional timers by mode
2754 */
2755 switch (ah->ah_op_mode) {
2756 case IEEE80211_IF_TYPE_STA:
2757 if (ah->ah_version == AR5K_AR5210) {
2758 timer1 = 0xffffffff;
2759 timer2 = 0xffffffff;
2760 } else {
2761 timer1 = 0x0000ffff;
2762 timer2 = 0x0007ffff;
2763 }
2764 break;
2765
2766 default:
2767 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2768 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
2769 }
2770
2771 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2772
2773 /*
2774 * Set the beacon register and enable all timers.
2775 * (next beacon, DMA beacon, software beacon, ATIM window time)
2776 */
2777 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2778 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2779 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2780 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2781
2782 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2783 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2784 AR5K_BEACON);
2785}
2786
2787#if 0
2788/*
2789 * Set beacon timers
2790 */
2791int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2792 const struct ath5k_beacon_state *state)
2793{
2794 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2795
2796 /*
2797 * TODO: should be changed through *state
2798 * review struct ath5k_beacon_state struct
2799 *
2800 * XXX: These are used for cfp period bellow, are they
2801 * ok ? Is it O.K. for tsf here to be 0 or should we use
2802 * get_tsf ?
2803 */
2804 u32 dtim_count = 0; /* XXX */
2805 u32 cfp_count = 0; /* XXX */
2806 u32 tsf = 0; /* XXX */
2807
2808 ATH5K_TRACE(ah->ah_sc);
2809 /* Return on an invalid beacon state */
2810 if (state->bs_interval < 1)
2811 return -EINVAL;
2812
2813 interval = state->bs_interval;
2814 dtim = state->bs_dtim_period;
2815
2816 /*
2817 * PCF support?
2818 */
2819 if (state->bs_cfp_period > 0) {
2820 /*
2821 * Enable PCF mode and set the CFP
2822 * (Contention Free Period) and timer registers
2823 */
2824 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2825 state->bs_interval;
2826 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2827 state->bs_interval;
2828
2829 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2830 AR5K_STA_ID1_DEFAULT_ANTENNA |
2831 AR5K_STA_ID1_PCF);
2832 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2833 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2834 AR5K_CFP_DUR);
2835 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2836 next_cfp)) << 3, AR5K_TIMER2);
2837 } else {
2838 /* Disable PCF mode */
2839 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2840 AR5K_STA_ID1_DEFAULT_ANTENNA |
2841 AR5K_STA_ID1_PCF);
2842 }
2843
2844 /*
2845 * Enable the beacon timer register
2846 */
2847 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2848
2849 /*
2850 * Start the beacon timers
2851 */
2852 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2853 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2854 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2855 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2856 AR5K_BEACON_PERIOD), AR5K_BEACON);
2857
2858 /*
2859 * Write new beacon miss threshold, if it appears to be valid
2860 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2861 * and return if its not in range. We can test this by reading value and
2862 * setting value to a largest value and seeing which values register.
2863 */
2864
2865 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2866 state->bs_bmiss_threshold);
2867
2868 /*
2869 * Set sleep control register
2870 * XXX: Didn't find this in 5210 code but since this register
2871 * exists also in ar5k's 5210 headers i leave it as common code.
2872 */
2873 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2874 (state->bs_sleep_duration - 3) << 3);
2875
2876 /*
2877 * Set enhanced sleep registers on 5212
2878 */
2879 if (ah->ah_version == AR5K_AR5212) {
2880 if (state->bs_sleep_duration > state->bs_interval &&
2881 roundup(state->bs_sleep_duration, interval) ==
2882 state->bs_sleep_duration)
2883 interval = state->bs_sleep_duration;
2884
2885 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2886 roundup(state->bs_sleep_duration, dtim) ==
2887 state->bs_sleep_duration))
2888 dtim = state->bs_sleep_duration;
2889
2890 if (interval > dtim)
2891 return -EINVAL;
2892
2893 next_beacon = interval == dtim ? state->bs_next_dtim :
2894 state->bs_next_beacon;
2895
2896 ath5k_hw_reg_write(ah,
2897 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2898 AR5K_SLEEP0_NEXT_DTIM) |
2899 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2900 AR5K_SLEEP0_ENH_SLEEP_EN |
2901 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2902
2903 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2904 AR5K_SLEEP1_NEXT_TIM) |
2905 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2906
2907 ath5k_hw_reg_write(ah,
2908 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2909 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2910 }
2911
2912 return 0;
2913}
2914
2915/*
2916 * Reset beacon timers
2917 */
2918void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2919{
2920 ATH5K_TRACE(ah->ah_sc);
2921 /*
2922 * Disable beacon timer
2923 */
2924 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2925
2926 /*
2927 * Disable some beacon register values
2928 */
2929 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2930 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2931 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2932}
2933
2934/*
2935 * Wait for beacon queue to finish
2936 */
2937int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2938{
2939 unsigned int i;
2940 int ret;
2941
2942 ATH5K_TRACE(ah->ah_sc);
2943
2944 /* 5210 doesn't have QCU*/
2945 if (ah->ah_version == AR5K_AR5210) {
2946 /*
2947 * Wait for beaconn queue to finish by checking
2948 * Control Register and Beacon Status Register.
2949 */
2950 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2951 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2952 ||
2953 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2954 break;
2955 udelay(10);
2956 }
2957
2958 /* Timeout... */
2959 if (i <= 0) {
2960 /*
2961 * Re-schedule the beacon queue
2962 */
2963 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
2964 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
2965 AR5K_BCR);
2966
2967 return -EIO;
2968 }
2969 ret = 0;
2970 } else {
2971 /*5211/5212*/
2972 ret = ath5k_hw_register_timeout(ah,
2973 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
2974 AR5K_QCU_STS_FRMPENDCNT, 0, false);
2975
2976 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
2977 return -EIO;
2978 }
2979
2980 return ret;
2981}
2982#endif
2983
2984/*
2985 * Update mib counters (statistics)
2986 */
2987void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2988 struct ieee80211_low_level_stats *stats)
2989{
2990 ATH5K_TRACE(ah->ah_sc);
2991
2992 /* Read-And-Clear */
2993 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2994 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2995 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2996 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2997
2998 /* XXX: Should we use this to track beacon count ?
2999 * -we read it anyway to clear the register */
3000 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
3001
3002 /* Reset profile count registers on 5212*/
3003 if (ah->ah_version == AR5K_AR5212) {
3004 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
3005 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
3006 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
3007 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
3008 }
3009}
3010
3011/** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
3012 *
3013 * @ah: the &struct ath5k_hw
3014 * @high: determines if to use low bit rate or now
3015 */
3016void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
3017{
3018 if (ah->ah_version != AR5K_AR5212)
3019 return;
3020 else {
3021 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
3022 if (high)
3023 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
3024 else
3025 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
3026 }
3027}
3028
3029
3030/*
3031 * ACK/CTS Timeouts
3032 */
3033
3034/*
3035 * Set ACK timeout on PCU
3036 */
3037int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
3038{
3039 ATH5K_TRACE(ah->ah_sc);
3040 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
3041 ah->ah_turbo) <= timeout)
3042 return -EINVAL;
3043
3044 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
3045 ath5k_hw_htoclock(timeout, ah->ah_turbo));
3046
3047 return 0;
3048}
3049
3050/*
3051 * Read the ACK timeout from PCU
3052 */
3053unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
3054{
3055 ATH5K_TRACE(ah->ah_sc);
3056
3057 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
3058 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
3059}
3060
3061/*
3062 * Set CTS timeout on PCU
3063 */
3064int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
3065{
3066 ATH5K_TRACE(ah->ah_sc);
3067 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
3068 ah->ah_turbo) <= timeout)
3069 return -EINVAL;
3070
3071 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
3072 ath5k_hw_htoclock(timeout, ah->ah_turbo));
3073
3074 return 0;
3075}
3076
3077/*
3078 * Read CTS timeout from PCU
3079 */
3080unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
3081{
3082 ATH5K_TRACE(ah->ah_sc);
3083 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
3084 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
3085}
3086
3087/*
3088 * Key table (WEP) functions
3089 */
3090
3091int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
3092{
3093 unsigned int i;
3094
3095 ATH5K_TRACE(ah->ah_sc);
3096 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3097
3098 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
3099 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
3100
3101 /*
3102 * Set NULL encryption on AR5212+
3103 *
3104 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
3105 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
3106 *
3107 * Note2: Windows driver (ndiswrapper) sets this to
3108 * 0x00000714 instead of 0x00000007
3109 */
3110 if (ah->ah_version > AR5K_AR5211)
3111 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
3112 AR5K_KEYTABLE_TYPE(entry));
3113
3114 return 0;
3115}
3116
3117int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
3118{
3119 ATH5K_TRACE(ah->ah_sc);
3120 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3121
3122 /* Check the validation flag at the end of the entry */
3123 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
3124 AR5K_KEYTABLE_VALID;
3125}
3126
3127int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
3128 const struct ieee80211_key_conf *key, const u8 *mac)
3129{
3130 unsigned int i;
3131 __le32 key_v[5] = {};
3132 u32 keytype;
3133
3134 ATH5K_TRACE(ah->ah_sc);
3135
3136 /* key->keylen comes in from mac80211 in bytes */
3137
3138 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
3139 return -EOPNOTSUPP;
3140
3141 switch (key->keylen) {
3142 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
3143 case 40 / 8:
3144 memcpy(&key_v[0], key->key, 5);
3145 keytype = AR5K_KEYTABLE_TYPE_40;
3146 break;
3147
3148 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
3149 case 104 / 8:
3150 memcpy(&key_v[0], &key->key[0], 6);
3151 memcpy(&key_v[2], &key->key[6], 6);
3152 memcpy(&key_v[4], &key->key[12], 1);
3153 keytype = AR5K_KEYTABLE_TYPE_104;
3154 break;
3155 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
3156 case 128 / 8:
3157 memcpy(&key_v[0], &key->key[0], 6);
3158 memcpy(&key_v[2], &key->key[6], 6);
3159 memcpy(&key_v[4], &key->key[12], 4);
3160 keytype = AR5K_KEYTABLE_TYPE_128;
3161 break;
3162
3163 default:
3164 return -EINVAL; /* shouldn't happen */
3165 }
3166
3167 for (i = 0; i < ARRAY_SIZE(key_v); i++)
3168 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
3169 AR5K_KEYTABLE_OFF(entry, i));
3170
3171 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
3172
3173 return ath5k_hw_set_key_lladdr(ah, entry, mac);
3174}
3175
3176int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
3177{
3178 u32 low_id, high_id;
3179
3180 ATH5K_TRACE(ah->ah_sc);
3181 /* Invalid entry (key table overflow) */
3182 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3183
3184 /* MAC may be NULL if it's a broadcast key. In this case no need to
3185 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
3186 if (unlikely(mac == NULL)) {
3187 low_id = 0xffffffff;
3188 high_id = 0xffff | AR5K_KEYTABLE_VALID;
3189 } else {
3190 low_id = AR5K_LOW_ID(mac);
3191 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
3192 }
3193
3194 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
3195 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
3196
3197 return 0;
3198}
3199
3200
3201/********************************************\
3202Queue Control Unit, DFS Control Unit Functions
3203\********************************************/
3204
3205/*
3206 * Initialize a transmit queue
3207 */
3208int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
3209 struct ath5k_txq_info *queue_info)
3210{
3211 unsigned int queue;
3212 int ret;
3213
3214 ATH5K_TRACE(ah->ah_sc);
3215
3216 /*
3217 * Get queue by type
3218 */
3219 /*5210 only has 2 queues*/
3220 if (ah->ah_version == AR5K_AR5210) {
3221 switch (queue_type) {
3222 case AR5K_TX_QUEUE_DATA:
3223 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3224 break;
3225 case AR5K_TX_QUEUE_BEACON:
3226 case AR5K_TX_QUEUE_CAB:
3227 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3228 break;
3229 default:
3230 return -EINVAL;
3231 }
3232 } else {
3233 switch (queue_type) {
3234 case AR5K_TX_QUEUE_DATA:
3235 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3236 ah->ah_txq[queue].tqi_type !=
3237 AR5K_TX_QUEUE_INACTIVE; queue++) {
3238
3239 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3240 return -EINVAL;
3241 }
3242 break;
3243 case AR5K_TX_QUEUE_UAPSD:
3244 queue = AR5K_TX_QUEUE_ID_UAPSD;
3245 break;
3246 case AR5K_TX_QUEUE_BEACON:
3247 queue = AR5K_TX_QUEUE_ID_BEACON;
3248 break;
3249 case AR5K_TX_QUEUE_CAB:
3250 queue = AR5K_TX_QUEUE_ID_CAB;
3251 break;
3252 case AR5K_TX_QUEUE_XR_DATA:
3253 if (ah->ah_version != AR5K_AR5212)
3254 ATH5K_ERR(ah->ah_sc,
3255 "XR data queues only supported in"
3256 " 5212!\n");
3257 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3258 break;
3259 default:
3260 return -EINVAL;
3261 }
3262 }
3263
3264 /*
3265 * Setup internal queue structure
3266 */
3267 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3268 ah->ah_txq[queue].tqi_type = queue_type;
3269
3270 if (queue_info != NULL) {
3271 queue_info->tqi_type = queue_type;
3272 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3273 if (ret)
3274 return ret;
3275 }
3276 /*
3277 * We use ah_txq_status to hold a temp value for
3278 * the Secondary interrupt mask registers on 5211+
3279 * check out ath5k_hw_reset_tx_queue
3280 */
3281 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3282
3283 return queue;
3284}
3285
3286/*
3287 * Setup a transmit queue
3288 */
3289int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3290 const struct ath5k_txq_info *queue_info)
3291{
3292 ATH5K_TRACE(ah->ah_sc);
3293 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3294
3295 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3296 return -EIO;
3297
3298 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3299
3300 /*XXX: Is this supported on 5210 ?*/
3301 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3302 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3303 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3304 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3305 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3306
3307 return 0;
3308}
3309
3310/*
3311 * Get properties for a specific transmit queue
3312 */
3313int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3314 struct ath5k_txq_info *queue_info)
3315{
3316 ATH5K_TRACE(ah->ah_sc);
3317 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3318 return 0;
3319}
3320
3321/*
3322 * Set a transmit queue inactive
3323 */
3324void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3325{
3326 ATH5K_TRACE(ah->ah_sc);
3327 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3328 return;
3329
3330 /* This queue will be skipped in further operations */
3331 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3332 /*For SIMR setup*/
3333 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3334}
3335
3336/*
3337 * Set DFS params for a transmit queue
3338 */
3339int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3340{
3341 u32 cw_min, cw_max, retry_lg, retry_sh;
3342 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3343
3344 ATH5K_TRACE(ah->ah_sc);
3345 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3346
3347 tq = &ah->ah_txq[queue];
3348
3349 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3350 return 0;
3351
3352 if (ah->ah_version == AR5K_AR5210) {
3353 /* Only handle data queues, others will be ignored */
3354 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3355 return 0;
3356
3357 /* Set Slot time */
3358 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3359 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3360 AR5K_SLOT_TIME);
3361 /* Set ACK_CTS timeout */
3362 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3363 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3364 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3365 /* Set Transmit Latency */
3366 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3367 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3368 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3369 /* Set IFS0 */
3370 if (ah->ah_turbo)
3371 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3372 (ah->ah_aifs + tq->tqi_aifs) *
3373 AR5K_INIT_SLOT_TIME_TURBO) <<
3374 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3375 AR5K_IFS0);
3376 else
3377 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3378 (ah->ah_aifs + tq->tqi_aifs) *
3379 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3380 AR5K_INIT_SIFS, AR5K_IFS0);
3381
3382 /* Set IFS1 */
3383 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3384 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3385 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3386 /* Set AR5K_PHY_SETTLING */
3387 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3388 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
3389 | 0x38 :
3390 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
3391 | 0x1C,
3392 AR5K_PHY_SETTLING);
3393 /* Set Frame Control Register */
3394 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3395 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3396 AR5K_PHY_TURBO_SHORT | 0x2020) :
3397 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3398 AR5K_PHY_FRAME_CTL_5210);
3399 }
3400
3401 /*
3402 * Calculate cwmin/max by channel mode
3403 */
3404 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3405 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3406 ah->ah_aifs = AR5K_TUNE_AIFS;
3407 /*XR is only supported on 5212*/
3408 if (IS_CHAN_XR(ah->ah_current_channel) &&
3409 ah->ah_version == AR5K_AR5212) {
3410 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3411 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3412 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3413 /*B mode is not supported on 5210*/
3414 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3415 ah->ah_version != AR5K_AR5210) {
3416 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3417 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3418 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3419 }
3420
3421 cw_min = 1;
3422 while (cw_min < ah->ah_cw_min)
3423 cw_min = (cw_min << 1) | 1;
3424
3425 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3426 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3427 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3428 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3429
3430 /*
3431 * Calculate and set retry limits
3432 */
3433 if (ah->ah_software_retry) {
3434 /* XXX Need to test this */
3435 retry_lg = ah->ah_limit_tx_retries;
3436 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3437 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3438 } else {
3439 retry_lg = AR5K_INIT_LG_RETRY;
3440 retry_sh = AR5K_INIT_SH_RETRY;
3441 }
3442
3443 /*No QCU/DCU [5210]*/
3444 if (ah->ah_version == AR5K_AR5210) {
3445 ath5k_hw_reg_write(ah,
3446 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3447 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3448 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3449 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3450 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3451 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3452 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3453 AR5K_NODCU_RETRY_LMT);
3454 } else {
3455 /*QCU/DCU [5211+]*/
3456 ath5k_hw_reg_write(ah,
3457 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3458 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3459 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3460 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3461 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3462 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3463 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3464
3465 /*===Rest is also for QCU/DCU only [5211+]===*/
3466
3467 /*
3468 * Set initial content window (cw_min/cw_max)
3469 * and arbitrated interframe space (aifs)...
3470 */
3471 ath5k_hw_reg_write(ah,
3472 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3473 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3474 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3475 AR5K_DCU_LCL_IFS_AIFS),
3476 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3477
3478 /*
3479 * Set misc registers
3480 */
3481 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3482 AR5K_QUEUE_MISC(queue));
3483
3484 if (tq->tqi_cbr_period) {
3485 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3486 AR5K_QCU_CBRCFG_INTVAL) |
3487 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3488 AR5K_QCU_CBRCFG_ORN_THRES),
3489 AR5K_QUEUE_CBRCFG(queue));
3490 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3491 AR5K_QCU_MISC_FRSHED_CBR);
3492 if (tq->tqi_cbr_overflow_limit)
3493 AR5K_REG_ENABLE_BITS(ah,
3494 AR5K_QUEUE_MISC(queue),
3495 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3496 }
3497
3498 if (tq->tqi_ready_time)
3499 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3500 AR5K_QCU_RDYTIMECFG_INTVAL) |
3501 AR5K_QCU_RDYTIMECFG_ENABLE,
3502 AR5K_QUEUE_RDYTIMECFG(queue));
3503
3504 if (tq->tqi_burst_time) {
3505 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3506 AR5K_DCU_CHAN_TIME_DUR) |
3507 AR5K_DCU_CHAN_TIME_ENABLE,
3508 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3509
3510 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3511 AR5K_REG_ENABLE_BITS(ah,
3512 AR5K_QUEUE_MISC(queue),
3513 AR5K_QCU_MISC_RDY_VEOL_POLICY);
3514 }
3515
3516 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3517 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3518 AR5K_QUEUE_DFS_MISC(queue));
3519
3520 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3521 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3522 AR5K_QUEUE_DFS_MISC(queue));
3523
3524 /*
3525 * Set registers by queue type
3526 */
3527 switch (tq->tqi_type) {
3528 case AR5K_TX_QUEUE_BEACON:
3529 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3530 AR5K_QCU_MISC_FRSHED_DBA_GT |
3531 AR5K_QCU_MISC_CBREXP_BCN |
3532 AR5K_QCU_MISC_BCN_ENABLE);
3533
3534 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3535 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3536 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3537 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3538 AR5K_DCU_MISC_BCN_ENABLE);
3539
3540 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3541 (AR5K_TUNE_SW_BEACON_RESP -
3542 AR5K_TUNE_DMA_BEACON_RESP) -
3543 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3544 AR5K_QCU_RDYTIMECFG_ENABLE,
3545 AR5K_QUEUE_RDYTIMECFG(queue));
3546 break;
3547
3548 case AR5K_TX_QUEUE_CAB:
3549 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3550 AR5K_QCU_MISC_FRSHED_DBA_GT |
3551 AR5K_QCU_MISC_CBREXP |
3552 AR5K_QCU_MISC_CBREXP_BCN);
3553
3554 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3555 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3556 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3557 break;
3558
3559 case AR5K_TX_QUEUE_UAPSD:
3560 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3561 AR5K_QCU_MISC_CBREXP);
3562 break;
3563
3564 case AR5K_TX_QUEUE_DATA:
3565 default:
3566 break;
3567 }
3568
3569 /*
3570 * Enable interrupts for this tx queue
3571 * in the secondary interrupt mask registers
3572 */
3573 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3574 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3575
3576 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3577 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3578
3579 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3580 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3581
3582 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3583 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3584
3585 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3586 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3587
3588
3589 /* Update secondary interrupt mask registers */
3590 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3591 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3592 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3593 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3594 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3595
3596 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3597 AR5K_SIMR0_QCU_TXOK) |
3598 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3599 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3600 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3601 AR5K_SIMR1_QCU_TXERR) |
3602 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3603 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3604 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3605 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3606 }
3607
3608 return 0;
3609}
3610
3611/*
3612 * Get number of pending frames
3613 * for a specific queue [5211+]
3614 */
3615u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3616 ATH5K_TRACE(ah->ah_sc);
3617 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3618
3619 /* Return if queue is declared inactive */
3620 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3621 return false;
3622
3623 /* XXX: How about AR5K_CFG_TXCNT ? */
3624 if (ah->ah_version == AR5K_AR5210)
3625 return false;
3626
3627 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3628}
3629
3630/*
3631 * Set slot time
3632 */
3633int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3634{
3635 ATH5K_TRACE(ah->ah_sc);
3636 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3637 return -EINVAL;
3638
3639 if (ah->ah_version == AR5K_AR5210)
3640 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3641 ah->ah_turbo), AR5K_SLOT_TIME);
3642 else
3643 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3644
3645 return 0;
3646}
3647
3648/*
3649 * Get slot time
3650 */
3651unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3652{
3653 ATH5K_TRACE(ah->ah_sc);
3654 if (ah->ah_version == AR5K_AR5210)
3655 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3656 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3657 else
3658 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3659}
3660
3661
3662/******************************\
3663 Hardware Descriptor Functions
3664\******************************/
3665
3666/*
3667 * TX Descriptor
3668 */
3669
3670/*
3671 * Initialize the 2-word tx descriptor on 5210/5211
3672 */
3673static int
3674ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3675 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3676 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3677 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3678 unsigned int rtscts_rate, unsigned int rtscts_duration)
3679{
3680 u32 frame_type;
3681 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3682 unsigned int frame_len;
3683
3684 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3685
3686 /*
3687 * Validate input
3688 * - Zero retries don't make sense.
3689 * - A zero rate will put the HW into a mode where it continously sends
3690 * noise on the channel, so it is important to avoid this.
3691 */
3692 if (unlikely(tx_tries0 == 0)) {
3693 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3694 WARN_ON(1);
3695 return -EINVAL;
3696 }
3697 if (unlikely(tx_rate0 == 0)) {
3698 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3699 WARN_ON(1);
3700 return -EINVAL;
3701 }
3702
3703 /* Clear descriptor */
3704 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
3705
3706 /* Setup control descriptor */
3707
3708 /* Verify and set frame length */
3709
3710 /* remove padding we might have added before */
3711 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3712
3713 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
3714 return -EINVAL;
3715
3716 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
3717
3718 /* Verify and set buffer length */
3719
3720 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3721 if(type == AR5K_PKT_TYPE_BEACON)
3722 pkt_len = roundup(pkt_len, 4);
3723
3724 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
3725 return -EINVAL;
3726
3727 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
3728
3729 /*
3730 * Verify and set header length
3731 * XXX: I only found that on 5210 code, does it work on 5211 ?
3732 */
3733 if (ah->ah_version == AR5K_AR5210) {
3734 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3735 return -EINVAL;
3736 tx_ctl->tx_control_0 |=
3737 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3738 }
3739
3740 /*Diferences between 5210-5211*/
3741 if (ah->ah_version == AR5K_AR5210) {
3742 switch (type) {
3743 case AR5K_PKT_TYPE_BEACON:
3744 case AR5K_PKT_TYPE_PROBE_RESP:
3745 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3746 case AR5K_PKT_TYPE_PIFS:
3747 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3748 default:
3749 frame_type = type /*<< 2 ?*/;
3750 }
3751
3752 tx_ctl->tx_control_0 |=
3753 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3754 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3755 } else {
3756 tx_ctl->tx_control_0 |=
3757 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3758 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3759 tx_ctl->tx_control_1 |=
3760 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3761 }
3762#define _TX_FLAGS(_c, _flag) \
3763 if (flags & AR5K_TXDESC_##_flag) \
3764 tx_ctl->tx_control_##_c |= \
3765 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3766
3767 _TX_FLAGS(0, CLRDMASK);
3768 _TX_FLAGS(0, VEOL);
3769 _TX_FLAGS(0, INTREQ);
3770 _TX_FLAGS(0, RTSENA);
3771 _TX_FLAGS(1, NOACK);
3772
3773#undef _TX_FLAGS
3774
3775 /*
3776 * WEP crap
3777 */
3778 if (key_index != AR5K_TXKEYIX_INVALID) {
3779 tx_ctl->tx_control_0 |=
3780 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3781 tx_ctl->tx_control_1 |=
3782 AR5K_REG_SM(key_index,
3783 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3784 }
3785
3786 /*
3787 * RTS/CTS Duration [5210 ?]
3788 */
3789 if ((ah->ah_version == AR5K_AR5210) &&
3790 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3791 tx_ctl->tx_control_1 |= rtscts_duration &
3792 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3793
3794 return 0;
3795}
3796
3797/*
3798 * Initialize the 4-word tx descriptor on 5212
3799 */
3800static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3801 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3802 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3803 unsigned int tx_tries0, unsigned int key_index,
3804 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3805 unsigned int rtscts_duration)
3806{
3807 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3808 unsigned int frame_len;
3809
3810 ATH5K_TRACE(ah->ah_sc);
3811 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3812
3813 /*
3814 * Validate input
3815 * - Zero retries don't make sense.
3816 * - A zero rate will put the HW into a mode where it continously sends
3817 * noise on the channel, so it is important to avoid this.
3818 */
3819 if (unlikely(tx_tries0 == 0)) {
3820 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3821 WARN_ON(1);
3822 return -EINVAL;
3823 }
3824 if (unlikely(tx_rate0 == 0)) {
3825 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3826 WARN_ON(1);
3827 return -EINVAL;
3828 }
3829
3830 /* Clear descriptor */
3831 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
3832
3833 /* Setup control descriptor */
3834
3835 /* Verify and set frame length */
3836
3837 /* remove padding we might have added before */
3838 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3839
3840 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
3841 return -EINVAL;
3842
3843 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
3844
3845 /* Verify and set buffer length */
3846
3847 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3848 if(type == AR5K_PKT_TYPE_BEACON)
3849 pkt_len = roundup(pkt_len, 4);
3850
3851 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
3852 return -EINVAL;
3853
3854 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
3855
3856 tx_ctl->tx_control_0 |=
3857 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3858 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3859 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
3860 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3861 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3862 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3863 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3864
3865#define _TX_FLAGS(_c, _flag) \
3866 if (flags & AR5K_TXDESC_##_flag) \
3867 tx_ctl->tx_control_##_c |= \
3868 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3869
3870 _TX_FLAGS(0, CLRDMASK);
3871 _TX_FLAGS(0, VEOL);
3872 _TX_FLAGS(0, INTREQ);
3873 _TX_FLAGS(0, RTSENA);
3874 _TX_FLAGS(0, CTSENA);
3875 _TX_FLAGS(1, NOACK);
3876
3877#undef _TX_FLAGS
3878
3879 /*
3880 * WEP crap
3881 */
3882 if (key_index != AR5K_TXKEYIX_INVALID) {
3883 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3884 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
3885 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3886 }
3887
3888 /*
3889 * RTS/CTS
3890 */
3891 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3892 if ((flags & AR5K_TXDESC_RTSENA) &&
3893 (flags & AR5K_TXDESC_CTSENA))
3894 return -EINVAL;
3895 tx_ctl->tx_control_2 |= rtscts_duration &
3896 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3897 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3898 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3899 }
3900
3901 return 0;
3902}
3903
3904/*
3905 * Initialize a 4-word multirate tx descriptor on 5212
3906 */
3907static int
3908ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3909 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3910 unsigned int tx_rate3, u_int tx_tries3)
3911{
3912 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3913
3914 /*
3915 * Rates can be 0 as long as the retry count is 0 too.
3916 * A zero rate and nonzero retry count will put the HW into a mode where
3917 * it continously sends noise on the channel, so it is important to
3918 * avoid this.
3919 */
3920 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3921 (tx_rate2 == 0 && tx_tries2 != 0) ||
3922 (tx_rate3 == 0 && tx_tries3 != 0))) {
3923 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3924 WARN_ON(1);
3925 return -EINVAL;
3926 }
3927
3928 if (ah->ah_version == AR5K_AR5212) {
3929 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3930
3931#define _XTX_TRIES(_n) \
3932 if (tx_tries##_n) { \
3933 tx_ctl->tx_control_2 |= \
3934 AR5K_REG_SM(tx_tries##_n, \
3935 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3936 tx_ctl->tx_control_3 |= \
3937 AR5K_REG_SM(tx_rate##_n, \
3938 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3939 }
3940
3941 _XTX_TRIES(1);
3942 _XTX_TRIES(2);
3943 _XTX_TRIES(3);
3944
3945#undef _XTX_TRIES
3946
3947 return 1;
3948 }
3949
3950 return 0;
3951}
3952
3953/*
3954 * Proccess the tx status descriptor on 5210/5211
3955 */
3956static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3957 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3958{
3959 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3960 struct ath5k_hw_tx_status *tx_status;
3961
3962 ATH5K_TRACE(ah->ah_sc);
3963
3964 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3965 tx_status = &desc->ud.ds_tx5210.tx_stat;
3966
3967 /* No frame has been send or error */
3968 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3969 return -EINPROGRESS;
3970
3971 /*
3972 * Get descriptor status
3973 */
3974 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3975 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3976 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3977 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3978 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3979 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3980 /*TODO: ts->ts_virtcol + test*/
3981 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3982 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3983 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3984 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3985 ts->ts_antenna = 1;
3986 ts->ts_status = 0;
3987 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0,
3988 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3989
3990 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3991 if (tx_status->tx_status_0 &
3992 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3993 ts->ts_status |= AR5K_TXERR_XRETRY;
3994
3995 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3996 ts->ts_status |= AR5K_TXERR_FIFO;
3997
3998 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3999 ts->ts_status |= AR5K_TXERR_FILT;
4000 }
4001
4002 return 0;
4003}
4004
4005/*
4006 * Proccess a tx descriptor on 5212
4007 */
4008static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
4009 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
4010{
4011 struct ath5k_hw_4w_tx_ctl *tx_ctl;
4012 struct ath5k_hw_tx_status *tx_status;
4013
4014 ATH5K_TRACE(ah->ah_sc);
4015
4016 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
4017 tx_status = &desc->ud.ds_tx5212.tx_stat;
4018
4019 /* No frame has been send or error */
4020 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
4021 return -EINPROGRESS;
4022
4023 /*
4024 * Get descriptor status
4025 */
4026 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
4027 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
4028 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
4029 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
4030 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
4031 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
4032 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
4033 AR5K_DESC_TX_STATUS1_SEQ_NUM);
4034 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
4035 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
4036 ts->ts_antenna = (tx_status->tx_status_1 &
4037 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
4038 ts->ts_status = 0;
4039
4040 switch (AR5K_REG_MS(tx_status->tx_status_1,
4041 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
4042 case 0:
4043 ts->ts_rate = tx_ctl->tx_control_3 &
4044 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
4045 break;
4046 case 1:
4047 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4048 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
4049 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4050 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
4051 break;
4052 case 2:
4053 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4054 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
4055 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4056 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
4057 break;
4058 case 3:
4059 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4060 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
4061 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4062 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
4063 break;
4064 }
4065
4066 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
4067 if (tx_status->tx_status_0 &
4068 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
4069 ts->ts_status |= AR5K_TXERR_XRETRY;
4070
4071 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
4072 ts->ts_status |= AR5K_TXERR_FIFO;
4073
4074 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
4075 ts->ts_status |= AR5K_TXERR_FILT;
4076 }
4077
4078 return 0;
4079}
4080
4081/*
4082 * RX Descriptor
4083 */
4084
4085/*
4086 * Initialize an rx descriptor
4087 */
4088int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
4089 u32 size, unsigned int flags)
4090{
4091 struct ath5k_hw_rx_ctl *rx_ctl;
4092
4093 ATH5K_TRACE(ah->ah_sc);
4094 rx_ctl = &desc->ud.ds_rx.rx_ctl;
4095
4096 /*
4097 * Clear the descriptor
4098 * If we don't clean the status descriptor,
4099 * while scanning we get too many results,
4100 * most of them virtual, after some secs
4101 * of scanning system hangs. M.F.
4102 */
4103 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
4104
4105 /* Setup descriptor */
4106 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
4107 if (unlikely(rx_ctl->rx_control_1 != size))
4108 return -EINVAL;
4109
4110 if (flags & AR5K_RXDESC_INTREQ)
4111 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
4112
4113 return 0;
4114}
4115
4116/*
4117 * Proccess the rx status descriptor on 5210/5211
4118 */
4119static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
4120 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
4121{
4122 struct ath5k_hw_rx_status *rx_status;
4123
4124 rx_status = &desc->ud.ds_rx.u.rx_stat;
4125
4126 /* No frame received / not ready */
4127 if (unlikely((rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE)
4128 == 0))
4129 return -EINPROGRESS;
4130
4131 /*
4132 * Frame receive status
4133 */
4134 rs->rs_datalen = rx_status->rx_status_0 &
4135 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
4136 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4137 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4138 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4139 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
4140 rs->rs_antenna = rx_status->rx_status_0 &
4141 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4142 rs->rs_more = rx_status->rx_status_0 &
4143 AR5K_5210_RX_DESC_STATUS0_MORE;
4144 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
4145 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4146 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4147 rs->rs_status = 0;
4148 rs->rs_phyerr = 0;
4149
4150 /*
4151 * Key table status
4152 */
4153 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
4154 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4155 AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
4156 else
4157 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4158
4159 /*
4160 * Receive/descriptor errors
4161 */
4162 if ((rx_status->rx_status_1 &
4163 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4164 if (rx_status->rx_status_1 &
4165 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
4166 rs->rs_status |= AR5K_RXERR_CRC;
4167
4168 if (rx_status->rx_status_1 &
4169 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
4170 rs->rs_status |= AR5K_RXERR_FIFO;
4171
4172 if (rx_status->rx_status_1 &
4173 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
4174 rs->rs_status |= AR5K_RXERR_PHY;
4175 rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
4176 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
4177 }
4178
4179 if (rx_status->rx_status_1 &
4180 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4181 rs->rs_status |= AR5K_RXERR_DECRYPT;
4182 }
4183
4184 return 0;
4185}
4186
4187/*
4188 * Proccess the rx status descriptor on 5212
4189 */
4190static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
4191 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
4192{
4193 struct ath5k_hw_rx_status *rx_status;
4194 struct ath5k_hw_rx_error *rx_err;
4195
4196 ATH5K_TRACE(ah->ah_sc);
4197 rx_status = &desc->ud.ds_rx.u.rx_stat;
4198
4199 /* Overlay on error */
4200 rx_err = &desc->ud.ds_rx.u.rx_err;
4201
4202 /* No frame received / not ready */
4203 if (unlikely((rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE)
4204 == 0))
4205 return -EINPROGRESS;
4206
4207 /*
4208 * Frame receive status
4209 */
4210 rs->rs_datalen = rx_status->rx_status_0 &
4211 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
4212 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4213 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4214 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4215 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
4216 rs->rs_antenna = rx_status->rx_status_0 &
4217 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4218 rs->rs_more = rx_status->rx_status_0 &
4219 AR5K_5212_RX_DESC_STATUS0_MORE;
4220 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4221 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4222 rs->rs_status = 0;
4223 rs->rs_phyerr = 0;
4224
4225 /*
4226 * Key table status
4227 */
4228 if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
4229 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4230 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
4231 else
4232 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4233
4234 /*
4235 * Receive/descriptor errors
4236 */
4237 if ((rx_status->rx_status_1 &
4238 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4239 if (rx_status->rx_status_1 &
4240 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
4241 rs->rs_status |= AR5K_RXERR_CRC;
4242
4243 if (rx_status->rx_status_1 &
4244 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
4245 rs->rs_status |= AR5K_RXERR_PHY;
4246 rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
4247 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4248 }
4249
4250 if (rx_status->rx_status_1 &
4251 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4252 rs->rs_status |= AR5K_RXERR_DECRYPT;
4253
4254 if (rx_status->rx_status_1 &
4255 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
4256 rs->rs_status |= AR5K_RXERR_MIC;
4257 }
4258
4259 return 0;
4260}
4261
4262
4263/****************\
4264 GPIO Functions
4265\****************/
4266
4267/*
4268 * Set led state
4269 */
4270void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4271{
4272 u32 led;
4273 /*5210 has different led mode handling*/
4274 u32 led_5210;
4275
4276 ATH5K_TRACE(ah->ah_sc);
4277
4278 /*Reset led status*/
4279 if (ah->ah_version != AR5K_AR5210)
4280 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4281 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4282 else
4283 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4284
4285 /*
4286 * Some blinking values, define at your wish
4287 */
4288 switch (state) {
4289 case AR5K_LED_SCAN:
4290 case AR5K_LED_AUTH:
4291 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4292 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4293 break;
4294
4295 case AR5K_LED_INIT:
4296 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4297 led_5210 = AR5K_PCICFG_LED_PEND;
4298 break;
4299
4300 case AR5K_LED_ASSOC:
4301 case AR5K_LED_RUN:
4302 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4303 led_5210 = AR5K_PCICFG_LED_ASSOC;
4304 break;
4305
4306 default:
4307 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4308 led_5210 = AR5K_PCICFG_LED_PEND;
4309 break;
4310 }
4311
4312 /*Write new status to the register*/
4313 if (ah->ah_version != AR5K_AR5210)
4314 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4315 else
4316 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4317}
4318
4319/*
4320 * Set GPIO outputs
4321 */
4322int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4323{
4324 ATH5K_TRACE(ah->ah_sc);
4325 if (gpio > AR5K_NUM_GPIO)
4326 return -EINVAL;
4327
4328 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4329 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4330
4331 return 0;
4332}
4333
4334/*
4335 * Set GPIO inputs
4336 */
4337int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4338{
4339 ATH5K_TRACE(ah->ah_sc);
4340 if (gpio > AR5K_NUM_GPIO)
4341 return -EINVAL;
4342
4343 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4344 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4345
4346 return 0;
4347}
4348
4349/*
4350 * Get GPIO state
4351 */
4352u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4353{
4354 ATH5K_TRACE(ah->ah_sc);
4355 if (gpio > AR5K_NUM_GPIO)
4356 return 0xffffffff;
4357
4358 /* GPIO input magic */
4359 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4360 0x1;
4361}
4362
4363/*
4364 * Set GPIO state
4365 */
4366int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4367{
4368 u32 data;
4369 ATH5K_TRACE(ah->ah_sc);
4370
4371 if (gpio > AR5K_NUM_GPIO)
4372 return -EINVAL;
4373
4374 /* GPIO output magic */
4375 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4376
4377 data &= ~(1 << gpio);
4378 data |= (val & 1) << gpio;
4379
4380 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4381
4382 return 0;
4383}
4384
4385/*
4386 * Initialize the GPIO interrupt (RFKill switch)
4387 */
4388void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4389 u32 interrupt_level)
4390{
4391 u32 data;
4392
4393 ATH5K_TRACE(ah->ah_sc);
4394 if (gpio > AR5K_NUM_GPIO)
4395 return;
4396
4397 /*
4398 * Set the GPIO interrupt
4399 */
4400 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4401 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4402 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4403 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4404
4405 ath5k_hw_reg_write(ah, interrupt_level ? data :
4406 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4407
4408 ah->ah_imr |= AR5K_IMR_GPIO;
4409
4410 /* Enable GPIO interrupts */
4411 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4412}
4413
4414
4415
4416
4417/****************\
4418 Misc functions
4419\****************/
4420
4421int ath5k_hw_get_capability(struct ath5k_hw *ah,
4422 enum ath5k_capability_type cap_type,
4423 u32 capability, u32 *result)
4424{
4425 ATH5K_TRACE(ah->ah_sc);
4426
4427 switch (cap_type) {
4428 case AR5K_CAP_NUM_TXQUEUES:
4429 if (result) {
4430 if (ah->ah_version == AR5K_AR5210)
4431 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4432 else
4433 *result = AR5K_NUM_TX_QUEUES;
4434 goto yes;
4435 }
4436 case AR5K_CAP_VEOL:
4437 goto yes;
4438 case AR5K_CAP_COMPRESSION:
4439 if (ah->ah_version == AR5K_AR5212)
4440 goto yes;
4441 else
4442 goto no;
4443 case AR5K_CAP_BURST:
4444 goto yes;
4445 case AR5K_CAP_TPC:
4446 goto yes;
4447 case AR5K_CAP_BSSIDMASK:
4448 if (ah->ah_version == AR5K_AR5212)
4449 goto yes;
4450 else
4451 goto no;
4452 case AR5K_CAP_XR:
4453 if (ah->ah_version == AR5K_AR5212)
4454 goto yes;
4455 else
4456 goto no;
4457 default:
4458 goto no;
4459 }
4460
4461no:
4462 return -EINVAL;
4463yes:
4464 return 0;
4465}
4466
4467static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4468 u16 assoc_id)
4469{
4470 ATH5K_TRACE(ah->ah_sc);
4471
4472 if (ah->ah_version == AR5K_AR5210) {
4473 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4474 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4475 return 0;
4476 }
4477
4478 return -EIO;
4479}
4480
4481static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4482{
4483 ATH5K_TRACE(ah->ah_sc);
4484
4485 if (ah->ah_version == AR5K_AR5210) {
4486 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4487 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4488 return 0;
4489 }
4490
4491 return -EIO;
4492}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 18:12:58 -0500