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path: root/drivers/net/wireless/ath5k/hw.c
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-rw-r--r--drivers/net/wireless/ath5k/hw.c791
1 files changed, 445 insertions, 346 deletions
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c
index 01757436353d..87e782291a01 100644
--- a/drivers/net/wireless/ath5k/hw.c
+++ b/drivers/net/wireless/ath5k/hw.c
@@ -1,4 +1,4 @@
1 /* 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org> 4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
@@ -48,14 +48,18 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
48static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *, 48static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
49 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, 49 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50 unsigned int); 50 unsigned int);
51static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *); 51static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
52 struct ath5k_tx_status *);
52static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *, 53static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
53 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, 54 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
54 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, 55 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int); 56 unsigned int, unsigned int);
56static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *); 57static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
57static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *, struct ath5k_desc *); 58 struct ath5k_tx_status *);
58static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *, struct ath5k_desc *); 59static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *, struct ath5k_desc *,
60 struct ath5k_rx_status *);
61static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *, struct ath5k_desc *,
62 struct ath5k_rx_status *);
59static int ath5k_hw_get_capabilities(struct ath5k_hw *); 63static int ath5k_hw_get_capabilities(struct ath5k_hw *);
60 64
61static int ath5k_eeprom_init(struct ath5k_hw *); 65static int ath5k_eeprom_init(struct ath5k_hw *);
@@ -81,12 +85,12 @@ static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
81 85
82static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) 86static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
83{ 87{
84 return turbo == true ? (usec * 80) : (usec * 40); 88 return turbo ? (usec * 80) : (usec * 40);
85} 89}
86 90
87static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) 91static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
88{ 92{
89 return turbo == true ? (clock / 80) : (clock / 40); 93 return turbo ? (clock / 80) : (clock / 40);
90} 94}
91 95
92/* 96/*
@@ -100,7 +104,7 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
100 104
101 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 105 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
102 data = ath5k_hw_reg_read(ah, reg); 106 data = ath5k_hw_reg_read(ah, reg);
103 if ((is_set == true) && (data & flag)) 107 if (is_set && (data & flag))
104 break; 108 break;
105 else if ((data & flag) == val) 109 else if ((data & flag) == val)
106 break; 110 break;
@@ -116,11 +120,69 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
116\***************************************/ 120\***************************************/
117 121
118/* 122/*
123 * Power On Self Test helper function
124 */
125static int ath5k_hw_post(struct ath5k_hw *ah)
126{
127
128 int i, c;
129 u16 cur_reg;
130 u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
131 u32 var_pattern;
132 u32 static_pattern[4] = {
133 0x55555555, 0xaaaaaaaa,
134 0x66666666, 0x99999999
135 };
136 u32 init_val;
137 u32 cur_val;
138
139 for (c = 0; c < 2; c++) {
140
141 cur_reg = regs[c];
142 init_val = ath5k_hw_reg_read(ah, cur_reg);
143
144 for (i = 0; i < 256; i++) {
145 var_pattern = i << 16 | i;
146 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
147 cur_val = ath5k_hw_reg_read(ah, cur_reg);
148
149 if (cur_val != var_pattern) {
150 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
151 return -EAGAIN;
152 }
153
154 /* Found on ndiswrapper dumps */
155 var_pattern = 0x0039080f;
156 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
157 }
158
159 for (i = 0; i < 4; i++) {
160 var_pattern = static_pattern[i];
161 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
162 cur_val = ath5k_hw_reg_read(ah, cur_reg);
163
164 if (cur_val != var_pattern) {
165 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
166 return -EAGAIN;
167 }
168
169 /* Found on ndiswrapper dumps */
170 var_pattern = 0x003b080f;
171 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
172 }
173 }
174
175 return 0;
176
177}
178
179/*
119 * Check if the device is supported and initialize the needed structs 180 * Check if the device is supported and initialize the needed structs
120 */ 181 */
121struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) 182struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
122{ 183{
123 struct ath5k_hw *ah; 184 struct ath5k_hw *ah;
185 struct pci_dev *pdev = sc->pdev;
124 u8 mac[ETH_ALEN]; 186 u8 mac[ETH_ALEN];
125 int ret; 187 int ret;
126 u32 srev; 188 u32 srev;
@@ -140,9 +202,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
140 * HW information 202 * HW information
141 */ 203 */
142 204
143 /* Get reg domain from eeprom */
144 ath5k_get_regdomain(ah);
145
146 ah->ah_op_mode = IEEE80211_IF_TYPE_STA; 205 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
147 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; 206 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
148 ah->ah_turbo = false; 207 ah->ah_turbo = false;
@@ -177,9 +236,9 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
177 } 236 }
178 237
179 if (ah->ah_version == AR5K_AR5212) 238 if (ah->ah_version == AR5K_AR5212)
180 ah->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status; 239 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
181 else if (ah->ah_version <= AR5K_AR5211) 240 else if (ah->ah_version <= AR5K_AR5211)
182 ah->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; 241 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
183 242
184 /* Bring device out of sleep and reset it's units */ 243 /* Bring device out of sleep and reset it's units */
185 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true); 244 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
@@ -203,15 +262,19 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
203 CHANNEL_2GHZ); 262 CHANNEL_2GHZ);
204 263
205 /* Return on unsuported chips (unsupported eeprom etc) */ 264 /* Return on unsuported chips (unsupported eeprom etc) */
206 if(srev >= AR5K_SREV_VER_AR5416){ 265 if ((srev >= AR5K_SREV_VER_AR5416) &&
266 (srev < AR5K_SREV_VER_AR2425)) {
207 ATH5K_ERR(sc, "Device not yet supported.\n"); 267 ATH5K_ERR(sc, "Device not yet supported.\n");
208 ret = -ENODEV; 268 ret = -ENODEV;
209 goto err_free; 269 goto err_free;
270 } else if (srev == AR5K_SREV_VER_AR2425) {
271 ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
210 } 272 }
211 273
212 /* Identify single chip solutions */ 274 /* Identify single chip solutions */
213 if((srev <= AR5K_SREV_VER_AR5414) && 275 if (((srev <= AR5K_SREV_VER_AR5414) &&
214 (srev >= AR5K_SREV_VER_AR2424)) { 276 (srev >= AR5K_SREV_VER_AR2413)) ||
277 (srev == AR5K_SREV_VER_AR2425)) {
215 ah->ah_single_chip = true; 278 ah->ah_single_chip = true;
216 } else { 279 } else {
217 ah->ah_single_chip = false; 280 ah->ah_single_chip = false;
@@ -226,15 +289,81 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
226 ah->ah_radio = AR5K_RF5110; 289 ah->ah_radio = AR5K_RF5110;
227 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) { 290 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
228 ah->ah_radio = AR5K_RF5111; 291 ah->ah_radio = AR5K_RF5111;
229 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) { 292 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
293 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
294
230 ah->ah_radio = AR5K_RF5112; 295 ah->ah_radio = AR5K_RF5112;
231 } else { 296
297 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
298 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
299 } else {
300 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
301 }
302
303 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
304 ah->ah_radio = AR5K_RF2413;
305 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
306 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) {
307
232 ah->ah_radio = AR5K_RF5413; 308 ah->ah_radio = AR5K_RF5413;
309
310 if (ah->ah_mac_srev <= AR5K_SREV_VER_AR5424 &&
311 ah->ah_mac_srev >= AR5K_SREV_VER_AR2424)
312 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424;
313 else
314 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
315 /*
316 * Register returns 0x4 for radio revision
317 * so ath5k_hw_radio_revision doesn't parse the value
318 * correctly. For now we are based on mac's srev to
319 * identify RF2425 radio.
320 */
321 } else if (srev == AR5K_SREV_VER_AR2425) {
322 ah->ah_radio = AR5K_RF2425;
323 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
233 } 324 }
234 325
235 ah->ah_phy = AR5K_PHY(0); 326 ah->ah_phy = AR5K_PHY(0);
236 327
237 /* 328 /*
329 * Identify AR5212-based PCI-E cards
330 * And write some initial settings.
331 *
332 * (doing a "strings" on ndis driver
333 * -ar5211.sys- reveals the following
334 * pci-e related functions:
335 *
336 * pcieClockReq
337 * pcieRxErrNotify
338 * pcieL1SKPEnable
339 * pcieAspm
340 * pcieDisableAspmOnRfWake
341 * pciePowerSaveEnable
342 *
343 * I guess these point to ClockReq but
344 * i'm not sure.)
345 */
346 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
347 ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
348 ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
349 ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
350 ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
351 ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
352 ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
353 ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
354 ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
355 ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
356 ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
357 }
358
359 /*
360 * POST
361 */
362 ret = ath5k_hw_post(ah);
363 if (ret)
364 goto err_free;
365
366 /*
238 * Get card capabilities, values, ... 367 * Get card capabilities, values, ...
239 */ 368 */
240 369
@@ -280,7 +409,8 @@ err:
280 */ 409 */
281static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) 410static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
282{ 411{
283 u32 turbo, mode, clock; 412 struct pci_dev *pdev = ah->ah_sc->pdev;
413 u32 turbo, mode, clock, bus_flags;
284 int ret; 414 int ret;
285 415
286 turbo = 0; 416 turbo = 0;
@@ -357,10 +487,16 @@ static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
357 AR5K_PHY_TURBO); 487 AR5K_PHY_TURBO);
358 } 488 }
359 489
360 /* ...reset chipset and PCI device */ 490 /* reseting PCI on PCI-E cards results card to hang
361 if (ah->ah_single_chip == false && ath5k_hw_nic_reset(ah, 491 * and always return 0xffff... so we ingore that flag
362 AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) { 492 * for PCI-E cards */
363 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip + PCI\n"); 493 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
494
495 /* Reset chipset */
496 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
497 AR5K_RESET_CTL_BASEBAND | bus_flags);
498 if (ret) {
499 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
364 return -EIO; 500 return -EIO;
365 } 501 }
366 502
@@ -405,15 +541,15 @@ const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
405 541
406 /* Get rate tables */ 542 /* Get rate tables */
407 switch (mode) { 543 switch (mode) {
408 case MODE_IEEE80211A: 544 case AR5K_MODE_11A:
409 return &ath5k_rt_11a; 545 return &ath5k_rt_11a;
410 case MODE_ATHEROS_TURBO: 546 case AR5K_MODE_11A_TURBO:
411 return &ath5k_rt_turbo; 547 return &ath5k_rt_turbo;
412 case MODE_IEEE80211B: 548 case AR5K_MODE_11B:
413 return &ath5k_rt_11b; 549 return &ath5k_rt_11b;
414 case MODE_IEEE80211G: 550 case AR5K_MODE_11G:
415 return &ath5k_rt_11g; 551 return &ath5k_rt_11g;
416 case MODE_ATHEROS_TURBOG: 552 case AR5K_MODE_11G_TURBO:
417 return &ath5k_rt_xr; 553 return &ath5k_rt_xr;
418 } 554 }
419 555
@@ -459,15 +595,15 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
459 ds_coef_exp, ds_coef_man, clock; 595 ds_coef_exp, ds_coef_man, clock;
460 596
461 if (!(ah->ah_version == AR5K_AR5212) || 597 if (!(ah->ah_version == AR5K_AR5212) ||
462 !(channel->val & CHANNEL_OFDM)) 598 !(channel->hw_value & CHANNEL_OFDM))
463 BUG(); 599 BUG();
464 600
465 /* Seems there are two PLLs, one for baseband sampling and one 601 /* Seems there are two PLLs, one for baseband sampling and one
466 * for tuning. Tuning basebands are 40 MHz or 80MHz when in 602 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
467 * turbo. */ 603 * turbo. */
468 clock = channel->val & CHANNEL_TURBO ? 80 : 40; 604 clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
469 coef_scaled = ((5 * (clock << 24)) / 2) / 605 coef_scaled = ((5 * (clock << 24)) / 2) /
470 channel->freq; 606 channel->center_freq;
471 607
472 for (coef_exp = 31; coef_exp > 0; coef_exp--) 608 for (coef_exp = 31; coef_exp > 0; coef_exp--)
473 if ((coef_scaled >> coef_exp) & 0x1) 609 if ((coef_scaled >> coef_exp) & 0x1)
@@ -494,8 +630,7 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
494 * ath5k_hw_write_rate_duration - set rate duration during hw resets 630 * ath5k_hw_write_rate_duration - set rate duration during hw resets
495 * 631 *
496 * @ah: the &struct ath5k_hw 632 * @ah: the &struct ath5k_hw
497 * @driver_mode: one of enum ieee80211_phymode or our one of our own 633 * @mode: one of enum ath5k_driver_mode
498 * vendor modes
499 * 634 *
500 * Write the rate duration table for the current mode upon hw reset. This 635 * Write the rate duration table for the current mode upon hw reset. This
501 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting 636 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
@@ -506,19 +641,20 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
506 * 641 *
507 */ 642 */
508static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, 643static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
509 unsigned int driver_mode) 644 unsigned int mode)
510{ 645{
511 struct ath5k_softc *sc = ah->ah_sc; 646 struct ath5k_softc *sc = ah->ah_sc;
512 const struct ath5k_rate_table *rt; 647 const struct ath5k_rate_table *rt;
648 struct ieee80211_rate srate = {};
513 unsigned int i; 649 unsigned int i;
514 650
515 /* Get rate table for the current operating mode */ 651 /* Get rate table for the current operating mode */
516 rt = ath5k_hw_get_rate_table(ah, 652 rt = ath5k_hw_get_rate_table(ah, mode);
517 driver_mode);
518 653
519 /* Write rate duration table */ 654 /* Write rate duration table */
520 for (i = 0; i < rt->rate_count; i++) { 655 for (i = 0; i < rt->rate_count; i++) {
521 const struct ath5k_rate *rate, *control_rate; 656 const struct ath5k_rate *rate, *control_rate;
657
522 u32 reg; 658 u32 reg;
523 u16 tx_time; 659 u16 tx_time;
524 660
@@ -528,14 +664,16 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
528 /* Set ACK timeout */ 664 /* Set ACK timeout */
529 reg = AR5K_RATE_DUR(rate->rate_code); 665 reg = AR5K_RATE_DUR(rate->rate_code);
530 666
667 srate.bitrate = control_rate->rate_kbps/100;
668
531 /* An ACK frame consists of 10 bytes. If you add the FCS, 669 /* An ACK frame consists of 10 bytes. If you add the FCS,
532 * which ieee80211_generic_frame_duration() adds, 670 * which ieee80211_generic_frame_duration() adds,
533 * its 14 bytes. Note we use the control rate and not the 671 * its 14 bytes. Note we use the control rate and not the
534 * actual rate for this rate. See mac80211 tx.c 672 * actual rate for this rate. See mac80211 tx.c
535 * ieee80211_duration() for a brief description of 673 * ieee80211_duration() for a brief description of
536 * what rate we should choose to TX ACKs. */ 674 * what rate we should choose to TX ACKs. */
537 tx_time = ieee80211_generic_frame_duration(sc->hw, 675 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
538 sc->vif, 10, control_rate->rate_kbps/100); 676 sc->vif, 10, &srate));
539 677
540 ath5k_hw_reg_write(ah, tx_time, reg); 678 ath5k_hw_reg_write(ah, tx_time, reg);
541 679
@@ -568,8 +706,9 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
568 struct ieee80211_channel *channel, bool change_channel) 706 struct ieee80211_channel *channel, bool change_channel)
569{ 707{
570 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 708 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
571 u32 data, s_seq, s_ant, s_led[3]; 709 struct pci_dev *pdev = ah->ah_sc->pdev;
572 unsigned int i, mode, freq, ee_mode, ant[2], driver_mode = -1; 710 u32 data, s_seq, s_ant, s_led[3], dma_size;
711 unsigned int i, mode, freq, ee_mode, ant[2];
573 int ret; 712 int ret;
574 713
575 ATH5K_TRACE(ah->ah_sc); 714 ATH5K_TRACE(ah->ah_sc);
@@ -585,7 +724,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
585 */ 724 */
586 /*DCU/Antenna selection not available on 5210*/ 725 /*DCU/Antenna selection not available on 5210*/
587 if (ah->ah_version != AR5K_AR5210) { 726 if (ah->ah_version != AR5K_AR5210) {
588 if (change_channel == true) { 727 if (change_channel) {
589 /* Seq number for queue 0 -do this for all queues ? */ 728 /* Seq number for queue 0 -do this for all queues ? */
590 s_seq = ath5k_hw_reg_read(ah, 729 s_seq = ath5k_hw_reg_read(ah,
591 AR5K_QUEUE_DFS_SEQNUM(0)); 730 AR5K_QUEUE_DFS_SEQNUM(0));
@@ -599,12 +738,12 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
599 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); 738 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
600 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); 739 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
601 740
602 if (change_channel == true && ah->ah_rf_banks != NULL) 741 if (change_channel && ah->ah_rf_banks != NULL)
603 ath5k_hw_get_rf_gain(ah); 742 ath5k_hw_get_rf_gain(ah);
604 743
605 744
606 /*Wakeup the device*/ 745 /*Wakeup the device*/
607 ret = ath5k_hw_nic_wakeup(ah, channel->val, false); 746 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
608 if (ret) 747 if (ret)
609 return ret; 748 return ret;
610 749
@@ -620,43 +759,40 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
620 if (ah->ah_version != AR5K_AR5210) { 759 if (ah->ah_version != AR5K_AR5210) {
621 if (ah->ah_radio != AR5K_RF5111 && 760 if (ah->ah_radio != AR5K_RF5111 &&
622 ah->ah_radio != AR5K_RF5112 && 761 ah->ah_radio != AR5K_RF5112 &&
623 ah->ah_radio != AR5K_RF5413) { 762 ah->ah_radio != AR5K_RF5413 &&
763 ah->ah_radio != AR5K_RF2413 &&
764 ah->ah_radio != AR5K_RF2425) {
624 ATH5K_ERR(ah->ah_sc, 765 ATH5K_ERR(ah->ah_sc,
625 "invalid phy radio: %u\n", ah->ah_radio); 766 "invalid phy radio: %u\n", ah->ah_radio);
626 return -EINVAL; 767 return -EINVAL;
627 } 768 }
628 769
629 switch (channel->val & CHANNEL_MODES) { 770 switch (channel->hw_value & CHANNEL_MODES) {
630 case CHANNEL_A: 771 case CHANNEL_A:
631 mode = AR5K_INI_VAL_11A; 772 mode = AR5K_MODE_11A;
632 freq = AR5K_INI_RFGAIN_5GHZ; 773 freq = AR5K_INI_RFGAIN_5GHZ;
633 ee_mode = AR5K_EEPROM_MODE_11A; 774 ee_mode = AR5K_EEPROM_MODE_11A;
634 driver_mode = MODE_IEEE80211A;
635 break; 775 break;
636 case CHANNEL_G: 776 case CHANNEL_G:
637 mode = AR5K_INI_VAL_11G; 777 mode = AR5K_MODE_11G;
638 freq = AR5K_INI_RFGAIN_2GHZ; 778 freq = AR5K_INI_RFGAIN_2GHZ;
639 ee_mode = AR5K_EEPROM_MODE_11G; 779 ee_mode = AR5K_EEPROM_MODE_11G;
640 driver_mode = MODE_IEEE80211G;
641 break; 780 break;
642 case CHANNEL_B: 781 case CHANNEL_B:
643 mode = AR5K_INI_VAL_11B; 782 mode = AR5K_MODE_11B;
644 freq = AR5K_INI_RFGAIN_2GHZ; 783 freq = AR5K_INI_RFGAIN_2GHZ;
645 ee_mode = AR5K_EEPROM_MODE_11B; 784 ee_mode = AR5K_EEPROM_MODE_11B;
646 driver_mode = MODE_IEEE80211B;
647 break; 785 break;
648 case CHANNEL_T: 786 case CHANNEL_T:
649 mode = AR5K_INI_VAL_11A_TURBO; 787 mode = AR5K_MODE_11A_TURBO;
650 freq = AR5K_INI_RFGAIN_5GHZ; 788 freq = AR5K_INI_RFGAIN_5GHZ;
651 ee_mode = AR5K_EEPROM_MODE_11A; 789 ee_mode = AR5K_EEPROM_MODE_11A;
652 driver_mode = MODE_ATHEROS_TURBO;
653 break; 790 break;
654 /*Is this ok on 5211 too ?*/ 791 /*Is this ok on 5211 too ?*/
655 case CHANNEL_TG: 792 case CHANNEL_TG:
656 mode = AR5K_INI_VAL_11G_TURBO; 793 mode = AR5K_MODE_11G_TURBO;
657 freq = AR5K_INI_RFGAIN_2GHZ; 794 freq = AR5K_INI_RFGAIN_2GHZ;
658 ee_mode = AR5K_EEPROM_MODE_11G; 795 ee_mode = AR5K_EEPROM_MODE_11G;
659 driver_mode = MODE_ATHEROS_TURBOG;
660 break; 796 break;
661 case CHANNEL_XR: 797 case CHANNEL_XR:
662 if (ah->ah_version == AR5K_AR5211) { 798 if (ah->ah_version == AR5K_AR5211) {
@@ -664,14 +800,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
664 "XR mode not available on 5211"); 800 "XR mode not available on 5211");
665 return -EINVAL; 801 return -EINVAL;
666 } 802 }
667 mode = AR5K_INI_VAL_XR; 803 mode = AR5K_MODE_XR;
668 freq = AR5K_INI_RFGAIN_5GHZ; 804 freq = AR5K_INI_RFGAIN_5GHZ;
669 ee_mode = AR5K_EEPROM_MODE_11A; 805 ee_mode = AR5K_EEPROM_MODE_11A;
670 driver_mode = MODE_IEEE80211A;
671 break; 806 break;
672 default: 807 default:
673 ATH5K_ERR(ah->ah_sc, 808 ATH5K_ERR(ah->ah_sc,
674 "invalid channel: %d\n", channel->freq); 809 "invalid channel: %d\n", channel->center_freq);
675 return -EINVAL; 810 return -EINVAL;
676 } 811 }
677 812
@@ -701,15 +836,26 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
701 /* 836 /*
702 * Write some more initial register settings 837 * Write some more initial register settings
703 */ 838 */
704 if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */ 839 if (ah->ah_version == AR5K_AR5212) {
705 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11)); 840 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
706 841
707 if (channel->val == CHANNEL_G) 842 if (channel->hw_value == CHANNEL_G)
708 ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */ 843 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
844 ath5k_hw_reg_write(ah, 0x00f80d80,
845 AR5K_PHY(83));
846 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
847 ath5k_hw_reg_write(ah, 0x00380140,
848 AR5K_PHY(83));
849 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
850 ath5k_hw_reg_write(ah, 0x00fc0ec0,
851 AR5K_PHY(83));
852 else /* 2425 */
853 ath5k_hw_reg_write(ah, 0x00fc0fc0,
854 AR5K_PHY(83));
709 else 855 else
710 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83)); 856 ath5k_hw_reg_write(ah, 0x00000000,
857 AR5K_PHY(83));
711 858
712 ath5k_hw_reg_write(ah, 0x000001b5, 0xa228); /* 0x000009b5 */
713 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); 859 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
714 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060); 860 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);
715 ath5k_hw_reg_write(ah, 0x00000000, 0xa254); 861 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
@@ -722,7 +868,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
722 AR5K_SREV_RAD_5112A) { 868 AR5K_SREV_RAD_5112A) {
723 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, 869 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
724 AR5K_PHY_CCKTXCTL); 870 AR5K_PHY_CCKTXCTL);
725 if (channel->val & CHANNEL_5GHZ) 871 if (channel->hw_value & CHANNEL_5GHZ)
726 data = 0xffb81020; 872 data = 0xffb81020;
727 else 873 else
728 data = 0xffb80d20; 874 data = 0xffb80d20;
@@ -742,7 +888,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
742 * mac80211 are integrated */ 888 * mac80211 are integrated */
743 if (ah->ah_version == AR5K_AR5212 && 889 if (ah->ah_version == AR5K_AR5212 &&
744 ah->ah_sc->vif != NULL) 890 ah->ah_sc->vif != NULL)
745 ath5k_hw_write_rate_duration(ah, driver_mode); 891 ath5k_hw_write_rate_duration(ah, mode);
746 892
747 /* 893 /*
748 * Write RF registers 894 * Write RF registers
@@ -758,7 +904,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
758 904
759 /* Write OFDM timings on 5212*/ 905 /* Write OFDM timings on 5212*/
760 if (ah->ah_version == AR5K_AR5212 && 906 if (ah->ah_version == AR5K_AR5212 &&
761 channel->val & CHANNEL_OFDM) { 907 channel->hw_value & CHANNEL_OFDM) {
762 ret = ath5k_hw_write_ofdm_timings(ah, channel); 908 ret = ath5k_hw_write_ofdm_timings(ah, channel);
763 if (ret) 909 if (ret)
764 return ret; 910 return ret;
@@ -767,7 +913,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
767 /*Enable/disable 802.11b mode on 5111 913 /*Enable/disable 802.11b mode on 5111
768 (enable 2111 frequency converter + CCK)*/ 914 (enable 2111 frequency converter + CCK)*/
769 if (ah->ah_radio == AR5K_RF5111) { 915 if (ah->ah_radio == AR5K_RF5111) {
770 if (driver_mode == MODE_IEEE80211B) 916 if (mode == AR5K_MODE_11B)
771 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 917 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
772 AR5K_TXCFG_B_MODE); 918 AR5K_TXCFG_B_MODE);
773 else 919 else
@@ -885,13 +1031,24 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
885 1031
886 /* 1032 /*
887 * Set Rx/Tx DMA Configuration 1033 * Set Rx/Tx DMA Configuration
888 *(passing dma size not available on 5210) 1034 *
1035 * Set maximum DMA size (512) except for PCI-E cards since
1036 * it causes rx overruns and tx errors (tested on 5424 but since
1037 * rx overruns also occur on 5416/5418 with madwifi we set 128
1038 * for all PCI-E cards to be safe).
1039 *
1040 * In dumps this is 128 for allchips.
1041 *
1042 * XXX: need to check 5210 for this
1043 * TODO: Check out tx triger level, it's always 64 on dumps but I
1044 * guess we can tweak it and see how it goes ;-)
889 */ 1045 */
1046 dma_size = (pdev->is_pcie) ? AR5K_DMASIZE_128B : AR5K_DMASIZE_512B;
890 if (ah->ah_version != AR5K_AR5210) { 1047 if (ah->ah_version != AR5K_AR5210) {
891 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, 1048 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
892 AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); 1049 AR5K_TXCFG_SDMAMR, dma_size);
893 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, 1050 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
894 AR5K_DMASIZE_512B); 1051 AR5K_RXCFG_SDMAMW, dma_size);
895 } 1052 }
896 1053
897 /* 1054 /*
@@ -905,7 +1062,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
905 if (ah->ah_version != AR5K_AR5210) { 1062 if (ah->ah_version != AR5K_AR5210) {
906 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 1063 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
907 AR5K_PHY_RX_DELAY_M; 1064 AR5K_PHY_RX_DELAY_M;
908 data = (channel->val & CHANNEL_CCK) ? 1065 data = (channel->hw_value & CHANNEL_CCK) ?
909 ((data << 2) / 22) : (data / 10); 1066 ((data << 2) / 22) : (data / 10);
910 1067
911 udelay(100 + data); 1068 udelay(100 + data);
@@ -922,11 +1079,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
922 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1079 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
923 AR5K_PHY_AGCCTL_CAL, 0, false)) { 1080 AR5K_PHY_AGCCTL_CAL, 0, false)) {
924 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1081 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
925 channel->freq); 1082 channel->center_freq);
926 return -EAGAIN; 1083 return -EAGAIN;
927 } 1084 }
928 1085
929 ret = ath5k_hw_noise_floor_calibration(ah, channel->freq); 1086 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
930 if (ret) 1087 if (ret)
931 return ret; 1088 return ret;
932 1089
@@ -934,7 +1091,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
934 1091
935 /* A and G modes can use QAM modulation which requires enabling 1092 /* A and G modes can use QAM modulation which requires enabling
936 * I and Q calibration. Don't bother in B mode. */ 1093 * I and Q calibration. Don't bother in B mode. */
937 if (!(driver_mode == MODE_IEEE80211B)) { 1094 if (!(mode == AR5K_MODE_11B)) {
938 ah->ah_calibration = true; 1095 ah->ah_calibration = true;
939 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1096 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
940 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1097 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
@@ -981,6 +1138,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
981 1138
982 /* 1139 /*
983 * Set the 32MHz reference clock on 5212 phy clock sleep register 1140 * Set the 32MHz reference clock on 5212 phy clock sleep register
1141 *
1142 * TODO: Find out how to switch to external 32Khz clock to save power
984 */ 1143 */
985 if (ah->ah_version == AR5K_AR5212) { 1144 if (ah->ah_version == AR5K_AR5212) {
986 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR); 1145 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
@@ -988,9 +1147,15 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
988 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL); 1147 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
989 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); 1148 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
990 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); 1149 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
991 ath5k_hw_reg_write(ah, ah->ah_radio == AR5K_RF5111 ? 1150 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
992 AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112, 1151 }
993 AR5K_PHY_SPENDING); 1152
1153 if (ah->ah_version == AR5K_AR5212) {
1154 ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
1155 ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
1156 ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
1157 if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)
1158 ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
994 } 1159 }
995 1160
996 /* 1161 /*
@@ -1065,7 +1230,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1065 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; 1230 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1066 /* fallthrough */ 1231 /* fallthrough */
1067 case AR5K_PM_NETWORK_SLEEP: 1232 case AR5K_PM_NETWORK_SLEEP:
1068 if (set_chip == true) 1233 if (set_chip)
1069 ath5k_hw_reg_write(ah, 1234 ath5k_hw_reg_write(ah,
1070 AR5K_SLEEP_CTL_SLE | sleep_duration, 1235 AR5K_SLEEP_CTL_SLE | sleep_duration,
1071 AR5K_SLEEP_CTL); 1236 AR5K_SLEEP_CTL);
@@ -1074,7 +1239,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1074 break; 1239 break;
1075 1240
1076 case AR5K_PM_FULL_SLEEP: 1241 case AR5K_PM_FULL_SLEEP:
1077 if (set_chip == true) 1242 if (set_chip)
1078 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP, 1243 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1079 AR5K_SLEEP_CTL); 1244 AR5K_SLEEP_CTL);
1080 1245
@@ -1082,7 +1247,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1082 break; 1247 break;
1083 1248
1084 case AR5K_PM_AWAKE: 1249 case AR5K_PM_AWAKE:
1085 if (set_chip == false) 1250 if (!set_chip)
1086 goto commit; 1251 goto commit;
1087 1252
1088 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE, 1253 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
@@ -1389,7 +1554,7 @@ int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1389 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), 1554 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1390 AR5K_TXCFG_TXFULL); 1555 AR5K_TXCFG_TXFULL);
1391 1556
1392 if (increase == false) { 1557 if (!increase) {
1393 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 1558 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1394 goto done; 1559 goto done;
1395 } else 1560 } else
@@ -1592,9 +1757,10 @@ static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1592/* 1757/*
1593 * Write to eeprom - currently disabled, use at your own risk 1758 * Write to eeprom - currently disabled, use at your own risk
1594 */ 1759 */
1760#if 0
1595static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data) 1761static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1596{ 1762{
1597#if 0 1763
1598 u32 status, timeout; 1764 u32 status, timeout;
1599 1765
1600 ATH5K_TRACE(ah->ah_sc); 1766 ATH5K_TRACE(ah->ah_sc);
@@ -1636,10 +1802,11 @@ static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1636 } 1802 }
1637 udelay(15); 1803 udelay(15);
1638 } 1804 }
1639#endif 1805
1640 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!"); 1806 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1641 return -EIO; 1807 return -EIO;
1642} 1808}
1809#endif
1643 1810
1644/* 1811/*
1645 * Translate binary channel representation in EEPROM to frequency 1812 * Translate binary channel representation in EEPROM to frequency
@@ -2045,50 +2212,6 @@ static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2045} 2212}
2046 2213
2047/* 2214/*
2048 * Read/Write regulatory domain
2049 */
2050static bool ath5k_eeprom_regulation_domain(struct ath5k_hw *ah, bool write,
2051 enum ath5k_regdom *regdomain)
2052{
2053 u16 ee_regdomain;
2054
2055 /* Read current value */
2056 if (write != true) {
2057 ee_regdomain = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2058 *regdomain = ath5k_regdom_to_ieee(ee_regdomain);
2059 return true;
2060 }
2061
2062 ee_regdomain = ath5k_regdom_from_ieee(*regdomain);
2063
2064 /* Try to write a new value */
2065 if (ah->ah_capabilities.cap_eeprom.ee_protect &
2066 AR5K_EEPROM_PROTECT_WR_128_191)
2067 return false;
2068 if (ath5k_hw_eeprom_write(ah, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0)
2069 return false;
2070
2071 ah->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
2072
2073 return true;
2074}
2075
2076/*
2077 * Use the above to write a new regulatory domain
2078 */
2079int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain)
2080{
2081 enum ath5k_regdom ieee_regdomain;
2082
2083 ieee_regdomain = ath5k_regdom_to_ieee(regdomain);
2084
2085 if (ath5k_eeprom_regulation_domain(ah, true, &ieee_regdomain) == true)
2086 return 0;
2087
2088 return -EIO;
2089}
2090
2091/*
2092 * Fill the capabilities struct 2215 * Fill the capabilities struct
2093 */ 2216 */
2094static int ath5k_hw_get_capabilities(struct ath5k_hw *ah) 2217static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
@@ -2110,8 +2233,8 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2110 ah->ah_capabilities.cap_range.range_2ghz_max = 0; 2233 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2111 2234
2112 /* Set supported modes */ 2235 /* Set supported modes */
2113 __set_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode); 2236 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
2114 __set_bit(MODE_ATHEROS_TURBO, ah->ah_capabilities.cap_mode); 2237 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
2115 } else { 2238 } else {
2116 /* 2239 /*
2117 * XXX The tranceiver supports frequencies from 4920 to 6100GHz 2240 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
@@ -2133,12 +2256,12 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2133 ah->ah_capabilities.cap_range.range_5ghz_max = 6100; 2256 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2134 2257
2135 /* Set supported modes */ 2258 /* Set supported modes */
2136 __set_bit(MODE_IEEE80211A, 2259 __set_bit(AR5K_MODE_11A,
2137 ah->ah_capabilities.cap_mode); 2260 ah->ah_capabilities.cap_mode);
2138 __set_bit(MODE_ATHEROS_TURBO, 2261 __set_bit(AR5K_MODE_11A_TURBO,
2139 ah->ah_capabilities.cap_mode); 2262 ah->ah_capabilities.cap_mode);
2140 if (ah->ah_version == AR5K_AR5212) 2263 if (ah->ah_version == AR5K_AR5212)
2141 __set_bit(MODE_ATHEROS_TURBOG, 2264 __set_bit(AR5K_MODE_11G_TURBO,
2142 ah->ah_capabilities.cap_mode); 2265 ah->ah_capabilities.cap_mode);
2143 } 2266 }
2144 2267
@@ -2150,11 +2273,11 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2150 ah->ah_capabilities.cap_range.range_2ghz_max = 2732; 2273 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2151 2274
2152 if (AR5K_EEPROM_HDR_11B(ee_header)) 2275 if (AR5K_EEPROM_HDR_11B(ee_header))
2153 __set_bit(MODE_IEEE80211B, 2276 __set_bit(AR5K_MODE_11B,
2154 ah->ah_capabilities.cap_mode); 2277 ah->ah_capabilities.cap_mode);
2155 2278
2156 if (AR5K_EEPROM_HDR_11G(ee_header)) 2279 if (AR5K_EEPROM_HDR_11G(ee_header))
2157 __set_bit(MODE_IEEE80211G, 2280 __set_bit(AR5K_MODE_11G,
2158 ah->ah_capabilities.cap_mode); 2281 ah->ah_capabilities.cap_mode);
2159 } 2282 }
2160 } 2283 }
@@ -2279,8 +2402,8 @@ void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2279 * Set simple BSSID mask on 5212 2402 * Set simple BSSID mask on 5212
2280 */ 2403 */
2281 if (ah->ah_version == AR5K_AR5212) { 2404 if (ah->ah_version == AR5K_AR5212) {
2282 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM0); 2405 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM0);
2283 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM1); 2406 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM1);
2284 } 2407 }
2285 2408
2286 /* 2409 /*
@@ -2425,6 +2548,8 @@ void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2425{ 2548{
2426 ATH5K_TRACE(ah->ah_sc); 2549 ATH5K_TRACE(ah->ah_sc);
2427 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 2550 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2551
2552 /* TODO: ANI Support */
2428} 2553}
2429 2554
2430/* 2555/*
@@ -2434,6 +2559,8 @@ void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2434{ 2559{
2435 ATH5K_TRACE(ah->ah_sc); 2560 ATH5K_TRACE(ah->ah_sc);
2436 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 2561 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2562
2563 /* TODO: ANI Support */
2437} 2564}
2438 2565
2439/* 2566/*
@@ -2828,15 +2955,19 @@ int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2828 * Update mib counters (statistics) 2955 * Update mib counters (statistics)
2829 */ 2956 */
2830void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, 2957void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2831 struct ath5k_mib_stats *statistics) 2958 struct ieee80211_low_level_stats *stats)
2832{ 2959{
2833 ATH5K_TRACE(ah->ah_sc); 2960 ATH5K_TRACE(ah->ah_sc);
2961
2834 /* Read-And-Clear */ 2962 /* Read-And-Clear */
2835 statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 2963 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2836 statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 2964 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2837 statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 2965 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2838 statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 2966 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2839 statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 2967
2968 /* XXX: Should we use this to track beacon count ?
2969 * -we read it anyway to clear the register */
2970 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2840 2971
2841 /* Reset profile count registers on 5212*/ 2972 /* Reset profile count registers on 5212*/
2842 if (ah->ah_version == AR5K_AR5212) { 2973 if (ah->ah_version == AR5K_AR5212) {
@@ -2937,8 +3068,16 @@ int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
2937 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) 3068 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
2938 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i)); 3069 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
2939 3070
2940 /* Set NULL encryption on non-5210*/ 3071 /*
2941 if (ah->ah_version != AR5K_AR5210) 3072 * Set NULL encryption on AR5212+
3073 *
3074 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
3075 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
3076 *
3077 * Note2: Windows driver (ndiswrapper) sets this to
3078 * 0x00000714 instead of 0x00000007
3079 */
3080 if (ah->ah_version > AR5K_AR5211)
2942 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 3081 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
2943 AR5K_KEYTABLE_TYPE(entry)); 3082 AR5K_KEYTABLE_TYPE(entry));
2944 3083
@@ -3186,19 +3325,19 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3186 return 0; 3325 return 0;
3187 3326
3188 /* Set Slot time */ 3327 /* Set Slot time */
3189 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3328 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3190 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, 3329 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3191 AR5K_SLOT_TIME); 3330 AR5K_SLOT_TIME);
3192 /* Set ACK_CTS timeout */ 3331 /* Set ACK_CTS timeout */
3193 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3332 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3194 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : 3333 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3195 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); 3334 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3196 /* Set Transmit Latency */ 3335 /* Set Transmit Latency */
3197 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3336 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3198 AR5K_INIT_TRANSMIT_LATENCY_TURBO : 3337 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3199 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); 3338 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3200 /* Set IFS0 */ 3339 /* Set IFS0 */
3201 if (ah->ah_turbo == true) 3340 if (ah->ah_turbo)
3202 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + 3341 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3203 (ah->ah_aifs + tq->tqi_aifs) * 3342 (ah->ah_aifs + tq->tqi_aifs) *
3204 AR5K_INIT_SLOT_TIME_TURBO) << 3343 AR5K_INIT_SLOT_TIME_TURBO) <<
@@ -3211,16 +3350,16 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3211 AR5K_INIT_SIFS, AR5K_IFS0); 3350 AR5K_INIT_SIFS, AR5K_IFS0);
3212 3351
3213 /* Set IFS1 */ 3352 /* Set IFS1 */
3214 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3353 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3215 AR5K_INIT_PROTO_TIME_CNTRL_TURBO : 3354 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3216 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); 3355 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3217 /* Set PHY register 0x9844 (??) */ 3356 /* Set PHY register 0x9844 (??) */
3218 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3357 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3219 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 : 3358 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
3220 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C, 3359 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
3221 AR5K_PHY(17)); 3360 AR5K_PHY(17));
3222 /* Set Frame Control Register */ 3361 /* Set Frame Control Register */
3223 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3362 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3224 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | 3363 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3225 AR5K_PHY_TURBO_SHORT | 0x2020) : 3364 AR5K_PHY_TURBO_SHORT | 0x2020) :
3226 (AR5K_PHY_FRAME_CTL_INI | 0x1020), 3365 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
@@ -3259,7 +3398,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3259 /* 3398 /*
3260 * Calculate and set retry limits 3399 * Calculate and set retry limits
3261 */ 3400 */
3262 if (ah->ah_software_retry == true) { 3401 if (ah->ah_software_retry) {
3263 /* XXX Need to test this */ 3402 /* XXX Need to test this */
3264 retry_lg = ah->ah_limit_tx_retries; 3403 retry_lg = ah->ah_limit_tx_retries;
3265 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? 3404 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
@@ -3507,10 +3646,10 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3507 unsigned int rtscts_rate, unsigned int rtscts_duration) 3646 unsigned int rtscts_rate, unsigned int rtscts_duration)
3508{ 3647{
3509 u32 frame_type; 3648 u32 frame_type;
3510 struct ath5k_hw_2w_tx_desc *tx_desc; 3649 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3511 unsigned int frame_len; 3650 unsigned int frame_len;
3512 3651
3513 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0; 3652 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3514 3653
3515 /* 3654 /*
3516 * Validate input 3655 * Validate input
@@ -3529,12 +3668,8 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3529 return -EINVAL; 3668 return -EINVAL;
3530 } 3669 }
3531 3670
3532 /* Clear status descriptor */ 3671 /* Clear descriptor */
3533 memset(desc->ds_hw, 0, sizeof(struct ath5k_hw_tx_status)); 3672 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
3534
3535 /* Initialize control descriptor */
3536 tx_desc->tx_control_0 = 0;
3537 tx_desc->tx_control_1 = 0;
3538 3673
3539 /* Setup control descriptor */ 3674 /* Setup control descriptor */
3540 3675
@@ -3546,7 +3681,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3546 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN) 3681 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
3547 return -EINVAL; 3682 return -EINVAL;
3548 3683
3549 tx_desc->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN; 3684 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
3550 3685
3551 /* Verify and set buffer length */ 3686 /* Verify and set buffer length */
3552 3687
@@ -3557,7 +3692,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3557 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN) 3692 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
3558 return -EINVAL; 3693 return -EINVAL;
3559 3694
3560 tx_desc->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN; 3695 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
3561 3696
3562 /* 3697 /*
3563 * Verify and set header length 3698 * Verify and set header length
@@ -3566,7 +3701,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3566 if (ah->ah_version == AR5K_AR5210) { 3701 if (ah->ah_version == AR5K_AR5210) {
3567 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN) 3702 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3568 return -EINVAL; 3703 return -EINVAL;
3569 tx_desc->tx_control_0 |= 3704 tx_ctl->tx_control_0 |=
3570 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN); 3705 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3571 } 3706 }
3572 3707
@@ -3582,19 +3717,19 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3582 frame_type = type /*<< 2 ?*/; 3717 frame_type = type /*<< 2 ?*/;
3583 } 3718 }
3584 3719
3585 tx_desc->tx_control_0 |= 3720 tx_ctl->tx_control_0 |=
3586 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) | 3721 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3587 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); 3722 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3588 } else { 3723 } else {
3589 tx_desc->tx_control_0 |= 3724 tx_ctl->tx_control_0 |=
3590 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) | 3725 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3591 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT); 3726 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3592 tx_desc->tx_control_1 |= 3727 tx_ctl->tx_control_1 |=
3593 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE); 3728 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3594 } 3729 }
3595#define _TX_FLAGS(_c, _flag) \ 3730#define _TX_FLAGS(_c, _flag) \
3596 if (flags & AR5K_TXDESC_##_flag) \ 3731 if (flags & AR5K_TXDESC_##_flag) \
3597 tx_desc->tx_control_##_c |= \ 3732 tx_ctl->tx_control_##_c |= \
3598 AR5K_2W_TX_DESC_CTL##_c##_##_flag 3733 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3599 3734
3600 _TX_FLAGS(0, CLRDMASK); 3735 _TX_FLAGS(0, CLRDMASK);
@@ -3609,9 +3744,9 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3609 * WEP crap 3744 * WEP crap
3610 */ 3745 */
3611 if (key_index != AR5K_TXKEYIX_INVALID) { 3746 if (key_index != AR5K_TXKEYIX_INVALID) {
3612 tx_desc->tx_control_0 |= 3747 tx_ctl->tx_control_0 |=
3613 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; 3748 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3614 tx_desc->tx_control_1 |= 3749 tx_ctl->tx_control_1 |=
3615 AR5K_REG_SM(key_index, 3750 AR5K_REG_SM(key_index,
3616 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); 3751 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3617 } 3752 }
@@ -3621,7 +3756,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3621 */ 3756 */
3622 if ((ah->ah_version == AR5K_AR5210) && 3757 if ((ah->ah_version == AR5K_AR5210) &&
3623 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) 3758 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3624 tx_desc->tx_control_1 |= rtscts_duration & 3759 tx_ctl->tx_control_1 |= rtscts_duration &
3625 AR5K_2W_TX_DESC_CTL1_RTS_DURATION; 3760 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3626 3761
3627 return 0; 3762 return 0;
@@ -3637,13 +3772,11 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3637 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate, 3772 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3638 unsigned int rtscts_duration) 3773 unsigned int rtscts_duration)
3639{ 3774{
3640 struct ath5k_hw_4w_tx_desc *tx_desc; 3775 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3641 struct ath5k_hw_tx_status *tx_status;
3642 unsigned int frame_len; 3776 unsigned int frame_len;
3643 3777
3644 ATH5K_TRACE(ah->ah_sc); 3778 ATH5K_TRACE(ah->ah_sc);
3645 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; 3779 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3646 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3647 3780
3648 /* 3781 /*
3649 * Validate input 3782 * Validate input
@@ -3662,14 +3795,8 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3662 return -EINVAL; 3795 return -EINVAL;
3663 } 3796 }
3664 3797
3665 /* Clear status descriptor */ 3798 /* Clear descriptor */
3666 memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status)); 3799 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
3667
3668 /* Initialize control descriptor */
3669 tx_desc->tx_control_0 = 0;
3670 tx_desc->tx_control_1 = 0;
3671 tx_desc->tx_control_2 = 0;
3672 tx_desc->tx_control_3 = 0;
3673 3800
3674 /* Setup control descriptor */ 3801 /* Setup control descriptor */
3675 3802
@@ -3681,7 +3808,7 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3681 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN) 3808 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
3682 return -EINVAL; 3809 return -EINVAL;
3683 3810
3684 tx_desc->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN; 3811 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
3685 3812
3686 /* Verify and set buffer length */ 3813 /* Verify and set buffer length */
3687 3814
@@ -3692,20 +3819,20 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3692 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN) 3819 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
3693 return -EINVAL; 3820 return -EINVAL;
3694 3821
3695 tx_desc->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN; 3822 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
3696 3823
3697 tx_desc->tx_control_0 |= 3824 tx_ctl->tx_control_0 |=
3698 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | 3825 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3699 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); 3826 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3700 tx_desc->tx_control_1 |= AR5K_REG_SM(type, 3827 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
3701 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); 3828 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3702 tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, 3829 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3703 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); 3830 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3704 tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; 3831 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3705 3832
3706#define _TX_FLAGS(_c, _flag) \ 3833#define _TX_FLAGS(_c, _flag) \
3707 if (flags & AR5K_TXDESC_##_flag) \ 3834 if (flags & AR5K_TXDESC_##_flag) \
3708 tx_desc->tx_control_##_c |= \ 3835 tx_ctl->tx_control_##_c |= \
3709 AR5K_4W_TX_DESC_CTL##_c##_##_flag 3836 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3710 3837
3711 _TX_FLAGS(0, CLRDMASK); 3838 _TX_FLAGS(0, CLRDMASK);
@@ -3721,8 +3848,8 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3721 * WEP crap 3848 * WEP crap
3722 */ 3849 */
3723 if (key_index != AR5K_TXKEYIX_INVALID) { 3850 if (key_index != AR5K_TXKEYIX_INVALID) {
3724 tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; 3851 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3725 tx_desc->tx_control_1 |= AR5K_REG_SM(key_index, 3852 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
3726 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); 3853 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3727 } 3854 }
3728 3855
@@ -3733,9 +3860,9 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3733 if ((flags & AR5K_TXDESC_RTSENA) && 3860 if ((flags & AR5K_TXDESC_RTSENA) &&
3734 (flags & AR5K_TXDESC_CTSENA)) 3861 (flags & AR5K_TXDESC_CTSENA))
3735 return -EINVAL; 3862 return -EINVAL;
3736 tx_desc->tx_control_2 |= rtscts_duration & 3863 tx_ctl->tx_control_2 |= rtscts_duration &
3737 AR5K_4W_TX_DESC_CTL2_RTS_DURATION; 3864 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3738 tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate, 3865 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3739 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); 3866 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3740 } 3867 }
3741 3868
@@ -3750,7 +3877,7 @@ ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3750 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, 3877 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3751 unsigned int tx_rate3, u_int tx_tries3) 3878 unsigned int tx_rate3, u_int tx_tries3)
3752{ 3879{
3753 struct ath5k_hw_4w_tx_desc *tx_desc; 3880 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3754 3881
3755 /* 3882 /*
3756 * Rates can be 0 as long as the retry count is 0 too. 3883 * Rates can be 0 as long as the retry count is 0 too.
@@ -3767,14 +3894,14 @@ ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3767 } 3894 }
3768 3895
3769 if (ah->ah_version == AR5K_AR5212) { 3896 if (ah->ah_version == AR5K_AR5212) {
3770 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; 3897 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3771 3898
3772#define _XTX_TRIES(_n) \ 3899#define _XTX_TRIES(_n) \
3773 if (tx_tries##_n) { \ 3900 if (tx_tries##_n) { \
3774 tx_desc->tx_control_2 |= \ 3901 tx_ctl->tx_control_2 |= \
3775 AR5K_REG_SM(tx_tries##_n, \ 3902 AR5K_REG_SM(tx_tries##_n, \
3776 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \ 3903 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3777 tx_desc->tx_control_3 |= \ 3904 tx_ctl->tx_control_3 |= \
3778 AR5K_REG_SM(tx_rate##_n, \ 3905 AR5K_REG_SM(tx_rate##_n, \
3779 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \ 3906 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3780 } 3907 }
@@ -3795,13 +3922,15 @@ ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3795 * Proccess the tx status descriptor on 5210/5211 3922 * Proccess the tx status descriptor on 5210/5211
3796 */ 3923 */
3797static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah, 3924static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3798 struct ath5k_desc *desc) 3925 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3799{ 3926{
3927 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3800 struct ath5k_hw_tx_status *tx_status; 3928 struct ath5k_hw_tx_status *tx_status;
3801 struct ath5k_hw_2w_tx_desc *tx_desc;
3802 3929
3803 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0; 3930 ATH5K_TRACE(ah->ah_sc);
3804 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0]; 3931
3932 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3933 tx_status = &desc->ud.ds_tx5210.tx_stat;
3805 3934
3806 /* No frame has been send or error */ 3935 /* No frame has been send or error */
3807 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) 3936 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
@@ -3810,32 +3939,32 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3810 /* 3939 /*
3811 * Get descriptor status 3940 * Get descriptor status
3812 */ 3941 */
3813 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, 3942 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3814 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); 3943 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3815 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, 3944 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3816 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); 3945 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3817 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, 3946 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3818 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); 3947 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3819 /*TODO: desc->ds_us.tx.ts_virtcol + test*/ 3948 /*TODO: ts->ts_virtcol + test*/
3820 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, 3949 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3821 AR5K_DESC_TX_STATUS1_SEQ_NUM); 3950 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3822 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, 3951 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3823 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 3952 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3824 desc->ds_us.tx.ts_antenna = 1; 3953 ts->ts_antenna = 1;
3825 desc->ds_us.tx.ts_status = 0; 3954 ts->ts_status = 0;
3826 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0, 3955 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0,
3827 AR5K_2W_TX_DESC_CTL0_XMIT_RATE); 3956 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3828 3957
3829 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ 3958 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3830 if (tx_status->tx_status_0 & 3959 if (tx_status->tx_status_0 &
3831 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 3960 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3832 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; 3961 ts->ts_status |= AR5K_TXERR_XRETRY;
3833 3962
3834 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) 3963 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3835 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; 3964 ts->ts_status |= AR5K_TXERR_FIFO;
3836 3965
3837 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) 3966 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3838 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; 3967 ts->ts_status |= AR5K_TXERR_FILT;
3839 } 3968 }
3840 3969
3841 return 0; 3970 return 0;
@@ -3845,14 +3974,15 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3845 * Proccess a tx descriptor on 5212 3974 * Proccess a tx descriptor on 5212
3846 */ 3975 */
3847static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah, 3976static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3848 struct ath5k_desc *desc) 3977 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3849{ 3978{
3979 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3850 struct ath5k_hw_tx_status *tx_status; 3980 struct ath5k_hw_tx_status *tx_status;
3851 struct ath5k_hw_4w_tx_desc *tx_desc;
3852 3981
3853 ATH5K_TRACE(ah->ah_sc); 3982 ATH5K_TRACE(ah->ah_sc);
3854 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; 3983
3855 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2]; 3984 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3985 tx_status = &desc->ud.ds_tx5212.tx_stat;
3856 3986
3857 /* No frame has been send or error */ 3987 /* No frame has been send or error */
3858 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) 3988 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
@@ -3861,42 +3991,42 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3861 /* 3991 /*
3862 * Get descriptor status 3992 * Get descriptor status
3863 */ 3993 */
3864 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, 3994 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3865 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); 3995 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3866 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, 3996 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3867 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); 3997 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3868 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, 3998 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3869 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); 3999 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3870 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, 4000 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3871 AR5K_DESC_TX_STATUS1_SEQ_NUM); 4001 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3872 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, 4002 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3873 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 4003 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3874 desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & 4004 ts->ts_antenna = (tx_status->tx_status_1 &
3875 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; 4005 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
3876 desc->ds_us.tx.ts_status = 0; 4006 ts->ts_status = 0;
3877 4007
3878 switch (AR5K_REG_MS(tx_status->tx_status_1, 4008 switch (AR5K_REG_MS(tx_status->tx_status_1,
3879 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { 4009 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
3880 case 0: 4010 case 0:
3881 desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & 4011 ts->ts_rate = tx_ctl->tx_control_3 &
3882 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; 4012 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3883 break; 4013 break;
3884 case 1: 4014 case 1:
3885 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, 4015 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
3886 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); 4016 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
3887 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, 4017 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
3888 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); 4018 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
3889 break; 4019 break;
3890 case 2: 4020 case 2:
3891 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, 4021 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
3892 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); 4022 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
3893 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, 4023 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
3894 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); 4024 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
3895 break; 4025 break;
3896 case 3: 4026 case 3:
3897 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, 4027 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
3898 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); 4028 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
3899 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, 4029 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
3900 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); 4030 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
3901 break; 4031 break;
3902 } 4032 }
@@ -3904,13 +4034,13 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3904 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ 4034 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3905 if (tx_status->tx_status_0 & 4035 if (tx_status->tx_status_0 &
3906 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 4036 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3907 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; 4037 ts->ts_status |= AR5K_TXERR_XRETRY;
3908 4038
3909 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) 4039 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3910 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; 4040 ts->ts_status |= AR5K_TXERR_FIFO;
3911 4041
3912 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) 4042 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3913 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; 4043 ts->ts_status |= AR5K_TXERR_FILT;
3914 } 4044 }
3915 4045
3916 return 0; 4046 return 0;
@@ -3926,31 +4056,27 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3926int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 4056int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3927 u32 size, unsigned int flags) 4057 u32 size, unsigned int flags)
3928{ 4058{
3929 struct ath5k_rx_desc *rx_desc; 4059 struct ath5k_hw_rx_ctl *rx_ctl;
3930 4060
3931 ATH5K_TRACE(ah->ah_sc); 4061 ATH5K_TRACE(ah->ah_sc);
3932 rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0; 4062 rx_ctl = &desc->ud.ds_rx.rx_ctl;
3933 4063
3934 /* 4064 /*
3935 *Clear ds_hw 4065 * Clear the descriptor
3936 * If we don't clean the status descriptor, 4066 * If we don't clean the status descriptor,
3937 * while scanning we get too many results, 4067 * while scanning we get too many results,
3938 * most of them virtual, after some secs 4068 * most of them virtual, after some secs
3939 * of scanning system hangs. M.F. 4069 * of scanning system hangs. M.F.
3940 */ 4070 */
3941 memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); 4071 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
3942
3943 /*Initialize rx descriptor*/
3944 rx_desc->rx_control_0 = 0;
3945 rx_desc->rx_control_1 = 0;
3946 4072
3947 /* Setup descriptor */ 4073 /* Setup descriptor */
3948 rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; 4074 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
3949 if (unlikely(rx_desc->rx_control_1 != size)) 4075 if (unlikely(rx_ctl->rx_control_1 != size))
3950 return -EINVAL; 4076 return -EINVAL;
3951 4077
3952 if (flags & AR5K_RXDESC_INTREQ) 4078 if (flags & AR5K_RXDESC_INTREQ)
3953 rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; 4079 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
3954 4080
3955 return 0; 4081 return 0;
3956} 4082}
@@ -3958,67 +4084,68 @@ int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3958/* 4084/*
3959 * Proccess the rx status descriptor on 5210/5211 4085 * Proccess the rx status descriptor on 5210/5211
3960 */ 4086 */
3961static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *ah, 4087static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
3962 struct ath5k_desc *desc) 4088 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
3963{ 4089{
3964 struct ath5k_hw_old_rx_status *rx_status; 4090 struct ath5k_hw_rx_status *rx_status;
3965 4091
3966 rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0]; 4092 rx_status = &desc->ud.ds_rx.u.rx_stat;
3967 4093
3968 /* No frame received / not ready */ 4094 /* No frame received / not ready */
3969 if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) 4095 if (unlikely((rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE)
3970 == 0)) 4096 == 0))
3971 return -EINPROGRESS; 4097 return -EINPROGRESS;
3972 4098
3973 /* 4099 /*
3974 * Frame receive status 4100 * Frame receive status
3975 */ 4101 */
3976 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 4102 rs->rs_datalen = rx_status->rx_status_0 &
3977 AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; 4103 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
3978 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, 4104 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
3979 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); 4105 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
3980 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, 4106 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
3981 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); 4107 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
3982 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 4108 rs->rs_antenna = rx_status->rx_status_0 &
3983 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; 4109 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA;
3984 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 4110 rs->rs_more = rx_status->rx_status_0 &
3985 AR5K_OLD_RX_DESC_STATUS0_MORE; 4111 AR5K_5210_RX_DESC_STATUS0_MORE;
3986 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, 4112 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
3987 AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); 4113 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
3988 desc->ds_us.rx.rs_status = 0; 4114 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4115 rs->rs_status = 0;
3989 4116
3990 /* 4117 /*
3991 * Key table status 4118 * Key table status
3992 */ 4119 */
3993 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) 4120 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
3994 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, 4121 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
3995 AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); 4122 AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
3996 else 4123 else
3997 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; 4124 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
3998 4125
3999 /* 4126 /*
4000 * Receive/descriptor errors 4127 * Receive/descriptor errors
4001 */ 4128 */
4002 if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) 4129 if ((rx_status->rx_status_1 &
4003 == 0) { 4130 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4004 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) 4131 if (rx_status->rx_status_1 &
4005 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; 4132 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
4133 rs->rs_status |= AR5K_RXERR_CRC;
4006 4134
4007 if (rx_status->rx_status_1 & 4135 if (rx_status->rx_status_1 &
4008 AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN) 4136 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
4009 desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO; 4137 rs->rs_status |= AR5K_RXERR_FIFO;
4010 4138
4011 if (rx_status->rx_status_1 & 4139 if (rx_status->rx_status_1 &
4012 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) { 4140 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
4013 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; 4141 rs->rs_status |= AR5K_RXERR_PHY;
4014 desc->ds_us.rx.rs_phyerr = 4142 rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
4015 AR5K_REG_MS(rx_status->rx_status_1, 4143 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
4016 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR);
4017 } 4144 }
4018 4145
4019 if (rx_status->rx_status_1 & 4146 if (rx_status->rx_status_1 &
4020 AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) 4147 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4021 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; 4148 rs->rs_status |= AR5K_RXERR_DECRYPT;
4022 } 4149 }
4023 4150
4024 return 0; 4151 return 0;
@@ -4027,71 +4154,72 @@ static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *ah,
4027/* 4154/*
4028 * Proccess the rx status descriptor on 5212 4155 * Proccess the rx status descriptor on 5212
4029 */ 4156 */
4030static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *ah, 4157static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
4031 struct ath5k_desc *desc) 4158 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
4032{ 4159{
4033 struct ath5k_hw_new_rx_status *rx_status; 4160 struct ath5k_hw_rx_status *rx_status;
4034 struct ath5k_hw_rx_error *rx_err; 4161 struct ath5k_hw_rx_error *rx_err;
4035 4162
4036 ATH5K_TRACE(ah->ah_sc); 4163 ATH5K_TRACE(ah->ah_sc);
4037 rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0]; 4164 rx_status = &desc->ud.ds_rx.u.rx_stat;
4038 4165
4039 /* Overlay on error */ 4166 /* Overlay on error */
4040 rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0]; 4167 rx_err = &desc->ud.ds_rx.u.rx_err;
4041 4168
4042 /* No frame received / not ready */ 4169 /* No frame received / not ready */
4043 if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) 4170 if (unlikely((rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE)
4044 == 0)) 4171 == 0))
4045 return -EINPROGRESS; 4172 return -EINPROGRESS;
4046 4173
4047 /* 4174 /*
4048 * Frame receive status 4175 * Frame receive status
4049 */ 4176 */
4050 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 4177 rs->rs_datalen = rx_status->rx_status_0 &
4051 AR5K_NEW_RX_DESC_STATUS0_DATA_LEN; 4178 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
4052 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, 4179 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4053 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); 4180 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4054 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, 4181 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4055 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); 4182 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
4056 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 4183 rs->rs_antenna = rx_status->rx_status_0 &
4057 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA; 4184 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4058 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 4185 rs->rs_more = rx_status->rx_status_0 &
4059 AR5K_NEW_RX_DESC_STATUS0_MORE; 4186 AR5K_5212_RX_DESC_STATUS0_MORE;
4060 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, 4187 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4061 AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); 4188 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4062 desc->ds_us.rx.rs_status = 0; 4189 rs->rs_status = 0;
4063 4190
4064 /* 4191 /*
4065 * Key table status 4192 * Key table status
4066 */ 4193 */
4067 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID) 4194 if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
4068 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, 4195 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4069 AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX); 4196 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
4070 else 4197 else
4071 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; 4198 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4072 4199
4073 /* 4200 /*
4074 * Receive/descriptor errors 4201 * Receive/descriptor errors
4075 */ 4202 */
4076 if ((rx_status->rx_status_1 & 4203 if ((rx_status->rx_status_1 &
4077 AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { 4204 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4078 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR) 4205 if (rx_status->rx_status_1 &
4079 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; 4206 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
4207 rs->rs_status |= AR5K_RXERR_CRC;
4080 4208
4081 if (rx_status->rx_status_1 & 4209 if (rx_status->rx_status_1 &
4082 AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) { 4210 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
4083 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; 4211 rs->rs_status |= AR5K_RXERR_PHY;
4084 desc->ds_us.rx.rs_phyerr = 4212 rs->rs_phyerr = AR5K_REG_MS(rx_err->rx_error_1,
4085 AR5K_REG_MS(rx_err->rx_error_1, 4213 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4086 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4087 } 4214 }
4088 4215
4089 if (rx_status->rx_status_1 & 4216 if (rx_status->rx_status_1 &
4090 AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) 4217 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4091 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; 4218 rs->rs_status |= AR5K_RXERR_DECRYPT;
4092 4219
4093 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) 4220 if (rx_status->rx_status_1 &
4094 desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; 4221 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
4222 rs->rs_status |= AR5K_RXERR_MIC;
4095 } 4223 }
4096 4224
4097 return 0; 4225 return 0;
@@ -4250,35 +4378,6 @@ void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4250} 4378}
4251 4379
4252 4380
4253/*********************************\
4254 Regulatory Domain/Channels Setup
4255\*********************************/
4256
4257u16 ath5k_get_regdomain(struct ath5k_hw *ah)
4258{
4259 u16 regdomain;
4260 enum ath5k_regdom ieee_regdomain;
4261#ifdef COUNTRYCODE
4262 u16 code;
4263#endif
4264
4265 ath5k_eeprom_regulation_domain(ah, false, &ieee_regdomain);
4266 ah->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
4267
4268#ifdef COUNTRYCODE
4269 /*
4270 * Get the regulation domain by country code. This will ignore
4271 * the settings found in the EEPROM.
4272 */
4273 code = ieee80211_name2countrycode(COUNTRYCODE);
4274 ieee_regdomain = ieee80211_countrycode2regdomain(code);
4275#endif
4276
4277 regdomain = ath5k_regdom_from_ieee(ieee_regdomain);
4278 ah->ah_capabilities.cap_regdomain.reg_current = regdomain;
4279
4280 return regdomain;
4281}
4282 4381
4283 4382
4284/****************\ 4383/****************\
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 01:36:56 -0500