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-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/antenna.c117
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c288
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c57
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c21
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mci.c43
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mci.h14
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c197
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h95
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h1231
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h12
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.c65
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c58
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/gpio.c72
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.c38
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/htc.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_beacon.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_gpio.c13
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c5
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_main.c51
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_txrx.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/hw-ops.h7
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c57
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c15
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c66
-rw-r--r--drivers/net/wireless/ath/ath9k/mci.c94
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c819
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h9
-rw-r--r--drivers/net/wireless/ath/ath9k/wow.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c15
40 files changed, 2559 insertions, 944 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index ff007f500feb..e09ec40ce71a 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -237,7 +237,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel,
237 entry_cck->fir_step_level); 237 entry_cck->fir_step_level);
238 238
239 /* Skip MRC CCK for pre AR9003 families */ 239 /* Skip MRC CCK for pre AR9003 families */
240 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah)) 240 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
241 return; 241 return;
242 242
243 if (aniState->mrcCCK != entry_cck->mrc_cck_on) 243 if (aniState->mrcCCK != entry_cck->mrc_cck_on)
diff --git a/drivers/net/wireless/ath/ath9k/antenna.c b/drivers/net/wireless/ath/ath9k/antenna.c
index bbcfeb3b2a60..664844c5d3d5 100644
--- a/drivers/net/wireless/ath/ath9k/antenna.c
+++ b/drivers/net/wireless/ath/ath9k/antenna.c
@@ -311,6 +311,9 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
311 struct ath_ant_comb *antcomb, 311 struct ath_ant_comb *antcomb,
312 int alt_ratio) 312 int alt_ratio)
313{ 313{
314 ant_conf->main_gaintb = 0;
315 ant_conf->alt_gaintb = 0;
316
314 if (ant_conf->div_group == 0) { 317 if (ant_conf->div_group == 0) {
315 /* Adjust the fast_div_bias based on main and alt lna conf */ 318 /* Adjust the fast_div_bias based on main and alt lna conf */
316 switch ((ant_conf->main_lna_conf << 4) | 319 switch ((ant_conf->main_lna_conf << 4) |
@@ -360,18 +363,12 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
360 ant_conf->alt_lna_conf) { 363 ant_conf->alt_lna_conf) {
361 case 0x01: /* A-B LNA2 */ 364 case 0x01: /* A-B LNA2 */
362 ant_conf->fast_div_bias = 0x1; 365 ant_conf->fast_div_bias = 0x1;
363 ant_conf->main_gaintb = 0;
364 ant_conf->alt_gaintb = 0;
365 break; 366 break;
366 case 0x02: /* A-B LNA1 */ 367 case 0x02: /* A-B LNA1 */
367 ant_conf->fast_div_bias = 0x1; 368 ant_conf->fast_div_bias = 0x1;
368 ant_conf->main_gaintb = 0;
369 ant_conf->alt_gaintb = 0;
370 break; 369 break;
371 case 0x03: /* A-B A+B */ 370 case 0x03: /* A-B A+B */
372 ant_conf->fast_div_bias = 0x1; 371 ant_conf->fast_div_bias = 0x1;
373 ant_conf->main_gaintb = 0;
374 ant_conf->alt_gaintb = 0;
375 break; 372 break;
376 case 0x10: /* LNA2 A-B */ 373 case 0x10: /* LNA2 A-B */
377 if (!(antcomb->scan) && 374 if (!(antcomb->scan) &&
@@ -379,13 +376,9 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
379 ant_conf->fast_div_bias = 0x3f; 376 ant_conf->fast_div_bias = 0x3f;
380 else 377 else
381 ant_conf->fast_div_bias = 0x1; 378 ant_conf->fast_div_bias = 0x1;
382 ant_conf->main_gaintb = 0;
383 ant_conf->alt_gaintb = 0;
384 break; 379 break;
385 case 0x12: /* LNA2 LNA1 */ 380 case 0x12: /* LNA2 LNA1 */
386 ant_conf->fast_div_bias = 0x1; 381 ant_conf->fast_div_bias = 0x1;
387 ant_conf->main_gaintb = 0;
388 ant_conf->alt_gaintb = 0;
389 break; 382 break;
390 case 0x13: /* LNA2 A+B */ 383 case 0x13: /* LNA2 A+B */
391 if (!(antcomb->scan) && 384 if (!(antcomb->scan) &&
@@ -393,8 +386,6 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
393 ant_conf->fast_div_bias = 0x3f; 386 ant_conf->fast_div_bias = 0x3f;
394 else 387 else
395 ant_conf->fast_div_bias = 0x1; 388 ant_conf->fast_div_bias = 0x1;
396 ant_conf->main_gaintb = 0;
397 ant_conf->alt_gaintb = 0;
398 break; 389 break;
399 case 0x20: /* LNA1 A-B */ 390 case 0x20: /* LNA1 A-B */
400 if (!(antcomb->scan) && 391 if (!(antcomb->scan) &&
@@ -402,13 +393,9 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
402 ant_conf->fast_div_bias = 0x3f; 393 ant_conf->fast_div_bias = 0x3f;
403 else 394 else
404 ant_conf->fast_div_bias = 0x1; 395 ant_conf->fast_div_bias = 0x1;
405 ant_conf->main_gaintb = 0;
406 ant_conf->alt_gaintb = 0;
407 break; 396 break;
408 case 0x21: /* LNA1 LNA2 */ 397 case 0x21: /* LNA1 LNA2 */
409 ant_conf->fast_div_bias = 0x1; 398 ant_conf->fast_div_bias = 0x1;
410 ant_conf->main_gaintb = 0;
411 ant_conf->alt_gaintb = 0;
412 break; 399 break;
413 case 0x23: /* LNA1 A+B */ 400 case 0x23: /* LNA1 A+B */
414 if (!(antcomb->scan) && 401 if (!(antcomb->scan) &&
@@ -416,23 +403,15 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
416 ant_conf->fast_div_bias = 0x3f; 403 ant_conf->fast_div_bias = 0x3f;
417 else 404 else
418 ant_conf->fast_div_bias = 0x1; 405 ant_conf->fast_div_bias = 0x1;
419 ant_conf->main_gaintb = 0;
420 ant_conf->alt_gaintb = 0;
421 break; 406 break;
422 case 0x30: /* A+B A-B */ 407 case 0x30: /* A+B A-B */
423 ant_conf->fast_div_bias = 0x1; 408 ant_conf->fast_div_bias = 0x1;
424 ant_conf->main_gaintb = 0;
425 ant_conf->alt_gaintb = 0;
426 break; 409 break;
427 case 0x31: /* A+B LNA2 */ 410 case 0x31: /* A+B LNA2 */
428 ant_conf->fast_div_bias = 0x1; 411 ant_conf->fast_div_bias = 0x1;
429 ant_conf->main_gaintb = 0;
430 ant_conf->alt_gaintb = 0;
431 break; 412 break;
432 case 0x32: /* A+B LNA1 */ 413 case 0x32: /* A+B LNA1 */
433 ant_conf->fast_div_bias = 0x1; 414 ant_conf->fast_div_bias = 0x1;
434 ant_conf->main_gaintb = 0;
435 ant_conf->alt_gaintb = 0;
436 break; 415 break;
437 default: 416 default:
438 break; 417 break;
@@ -443,18 +422,12 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
443 ant_conf->alt_lna_conf) { 422 ant_conf->alt_lna_conf) {
444 case 0x01: /* A-B LNA2 */ 423 case 0x01: /* A-B LNA2 */
445 ant_conf->fast_div_bias = 0x1; 424 ant_conf->fast_div_bias = 0x1;
446 ant_conf->main_gaintb = 0;
447 ant_conf->alt_gaintb = 0;
448 break; 425 break;
449 case 0x02: /* A-B LNA1 */ 426 case 0x02: /* A-B LNA1 */
450 ant_conf->fast_div_bias = 0x1; 427 ant_conf->fast_div_bias = 0x1;
451 ant_conf->main_gaintb = 0;
452 ant_conf->alt_gaintb = 0;
453 break; 428 break;
454 case 0x03: /* A-B A+B */ 429 case 0x03: /* A-B A+B */
455 ant_conf->fast_div_bias = 0x1; 430 ant_conf->fast_div_bias = 0x1;
456 ant_conf->main_gaintb = 0;
457 ant_conf->alt_gaintb = 0;
458 break; 431 break;
459 case 0x10: /* LNA2 A-B */ 432 case 0x10: /* LNA2 A-B */
460 if (!(antcomb->scan) && 433 if (!(antcomb->scan) &&
@@ -462,13 +435,9 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
462 ant_conf->fast_div_bias = 0x1; 435 ant_conf->fast_div_bias = 0x1;
463 else 436 else
464 ant_conf->fast_div_bias = 0x2; 437 ant_conf->fast_div_bias = 0x2;
465 ant_conf->main_gaintb = 0;
466 ant_conf->alt_gaintb = 0;
467 break; 438 break;
468 case 0x12: /* LNA2 LNA1 */ 439 case 0x12: /* LNA2 LNA1 */
469 ant_conf->fast_div_bias = 0x1; 440 ant_conf->fast_div_bias = 0x1;
470 ant_conf->main_gaintb = 0;
471 ant_conf->alt_gaintb = 0;
472 break; 441 break;
473 case 0x13: /* LNA2 A+B */ 442 case 0x13: /* LNA2 A+B */
474 if (!(antcomb->scan) && 443 if (!(antcomb->scan) &&
@@ -476,8 +445,6 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
476 ant_conf->fast_div_bias = 0x1; 445 ant_conf->fast_div_bias = 0x1;
477 else 446 else
478 ant_conf->fast_div_bias = 0x2; 447 ant_conf->fast_div_bias = 0x2;
479 ant_conf->main_gaintb = 0;
480 ant_conf->alt_gaintb = 0;
481 break; 448 break;
482 case 0x20: /* LNA1 A-B */ 449 case 0x20: /* LNA1 A-B */
483 if (!(antcomb->scan) && 450 if (!(antcomb->scan) &&
@@ -485,13 +452,9 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
485 ant_conf->fast_div_bias = 0x1; 452 ant_conf->fast_div_bias = 0x1;
486 else 453 else
487 ant_conf->fast_div_bias = 0x2; 454 ant_conf->fast_div_bias = 0x2;
488 ant_conf->main_gaintb = 0;
489 ant_conf->alt_gaintb = 0;
490 break; 455 break;
491 case 0x21: /* LNA1 LNA2 */ 456 case 0x21: /* LNA1 LNA2 */
492 ant_conf->fast_div_bias = 0x1; 457 ant_conf->fast_div_bias = 0x1;
493 ant_conf->main_gaintb = 0;
494 ant_conf->alt_gaintb = 0;
495 break; 458 break;
496 case 0x23: /* LNA1 A+B */ 459 case 0x23: /* LNA1 A+B */
497 if (!(antcomb->scan) && 460 if (!(antcomb->scan) &&
@@ -499,23 +462,77 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
499 ant_conf->fast_div_bias = 0x1; 462 ant_conf->fast_div_bias = 0x1;
500 else 463 else
501 ant_conf->fast_div_bias = 0x2; 464 ant_conf->fast_div_bias = 0x2;
502 ant_conf->main_gaintb = 0;
503 ant_conf->alt_gaintb = 0;
504 break; 465 break;
505 case 0x30: /* A+B A-B */ 466 case 0x30: /* A+B A-B */
506 ant_conf->fast_div_bias = 0x1; 467 ant_conf->fast_div_bias = 0x1;
507 ant_conf->main_gaintb = 0;
508 ant_conf->alt_gaintb = 0;
509 break; 468 break;
510 case 0x31: /* A+B LNA2 */ 469 case 0x31: /* A+B LNA2 */
511 ant_conf->fast_div_bias = 0x1; 470 ant_conf->fast_div_bias = 0x1;
512 ant_conf->main_gaintb = 0;
513 ant_conf->alt_gaintb = 0;
514 break; 471 break;
515 case 0x32: /* A+B LNA1 */ 472 case 0x32: /* A+B LNA1 */
516 ant_conf->fast_div_bias = 0x1; 473 ant_conf->fast_div_bias = 0x1;
517 ant_conf->main_gaintb = 0; 474 break;
518 ant_conf->alt_gaintb = 0; 475 default:
476 break;
477 }
478 } else if (ant_conf->div_group == 3) {
479 switch ((ant_conf->main_lna_conf << 4) |
480 ant_conf->alt_lna_conf) {
481 case 0x01: /* A-B LNA2 */
482 ant_conf->fast_div_bias = 0x1;
483 break;
484 case 0x02: /* A-B LNA1 */
485 ant_conf->fast_div_bias = 0x39;
486 break;
487 case 0x03: /* A-B A+B */
488 ant_conf->fast_div_bias = 0x1;
489 break;
490 case 0x10: /* LNA2 A-B */
491 if ((antcomb->scan == 0) &&
492 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)) {
493 ant_conf->fast_div_bias = 0x3f;
494 } else {
495 ant_conf->fast_div_bias = 0x1;
496 }
497 break;
498 case 0x12: /* LNA2 LNA1 */
499 ant_conf->fast_div_bias = 0x39;
500 break;
501 case 0x13: /* LNA2 A+B */
502 if ((antcomb->scan == 0) &&
503 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)) {
504 ant_conf->fast_div_bias = 0x3f;
505 } else {
506 ant_conf->fast_div_bias = 0x1;
507 }
508 break;
509 case 0x20: /* LNA1 A-B */
510 if ((antcomb->scan == 0) &&
511 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)) {
512 ant_conf->fast_div_bias = 0x3f;
513 } else {
514 ant_conf->fast_div_bias = 0x4;
515 }
516 break;
517 case 0x21: /* LNA1 LNA2 */
518 ant_conf->fast_div_bias = 0x6;
519 break;
520 case 0x23: /* LNA1 A+B */
521 if ((antcomb->scan == 0) &&
522 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)) {
523 ant_conf->fast_div_bias = 0x3f;
524 } else {
525 ant_conf->fast_div_bias = 0x6;
526 }
527 break;
528 case 0x30: /* A+B A-B */
529 ant_conf->fast_div_bias = 0x1;
530 break;
531 case 0x31: /* A+B LNA2 */
532 ant_conf->fast_div_bias = 0x6;
533 break;
534 case 0x32: /* A+B LNA1 */
535 ant_conf->fast_div_bias = 0x1;
519 break; 536 break;
520 default: 537 default:
521 break; 538 break;
@@ -759,6 +776,7 @@ div_comb_done:
759void ath_ant_comb_update(struct ath_softc *sc) 776void ath_ant_comb_update(struct ath_softc *sc)
760{ 777{
761 struct ath_hw *ah = sc->sc_ah; 778 struct ath_hw *ah = sc->sc_ah;
779 struct ath_common *common = ath9k_hw_common(ah);
762 struct ath_hw_antcomb_conf div_ant_conf; 780 struct ath_hw_antcomb_conf div_ant_conf;
763 u8 lna_conf; 781 u8 lna_conf;
764 782
@@ -773,4 +791,7 @@ void ath_ant_comb_update(struct ath_softc *sc)
773 div_ant_conf.alt_lna_conf = lna_conf; 791 div_ant_conf.alt_lna_conf = lna_conf;
774 792
775 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf); 793 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
794
795 if (common->antenna_diversity)
796 ath9k_hw_antctrl_shared_chain_lnadiv(ah, true);
776} 797}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index d066f2516e47..5bbe5057ba18 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -138,7 +138,8 @@ static const struct ar9300_eeprom ar9300_default = {
138 }, 138 },
139 .base_ext1 = { 139 .base_ext1 = {
140 .ant_div_control = 0, 140 .ant_div_control = 0,
141 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 141 .future = {0, 0, 0},
142 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
142 }, 143 },
143 .calFreqPier2G = { 144 .calFreqPier2G = {
144 FREQ2FBIN(2412, 1), 145 FREQ2FBIN(2412, 1),
@@ -713,7 +714,8 @@ static const struct ar9300_eeprom ar9300_x113 = {
713 }, 714 },
714 .base_ext1 = { 715 .base_ext1 = {
715 .ant_div_control = 0, 716 .ant_div_control = 0,
716 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 717 .future = {0, 0, 0},
718 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
717 }, 719 },
718 .calFreqPier2G = { 720 .calFreqPier2G = {
719 FREQ2FBIN(2412, 1), 721 FREQ2FBIN(2412, 1),
@@ -1289,7 +1291,8 @@ static const struct ar9300_eeprom ar9300_h112 = {
1289 }, 1291 },
1290 .base_ext1 = { 1292 .base_ext1 = {
1291 .ant_div_control = 0, 1293 .ant_div_control = 0,
1292 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 1294 .future = {0, 0, 0},
1295 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
1293 }, 1296 },
1294 .calFreqPier2G = { 1297 .calFreqPier2G = {
1295 FREQ2FBIN(2412, 1), 1298 FREQ2FBIN(2412, 1),
@@ -1865,7 +1868,8 @@ static const struct ar9300_eeprom ar9300_x112 = {
1865 }, 1868 },
1866 .base_ext1 = { 1869 .base_ext1 = {
1867 .ant_div_control = 0, 1870 .ant_div_control = 0,
1868 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 1871 .future = {0, 0, 0},
1872 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
1869 }, 1873 },
1870 .calFreqPier2G = { 1874 .calFreqPier2G = {
1871 FREQ2FBIN(2412, 1), 1875 FREQ2FBIN(2412, 1),
@@ -2440,7 +2444,8 @@ static const struct ar9300_eeprom ar9300_h116 = {
2440 }, 2444 },
2441 .base_ext1 = { 2445 .base_ext1 = {
2442 .ant_div_control = 0, 2446 .ant_div_control = 0,
2443 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 2447 .future = {0, 0, 0},
2448 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
2444 }, 2449 },
2445 .calFreqPier2G = { 2450 .calFreqPier2G = {
2446 FREQ2FBIN(2412, 1), 2451 FREQ2FBIN(2412, 1),
@@ -3524,7 +3529,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3524 3529
3525 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3530 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3526 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); 3531 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3527 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah)) 3532 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))
3528 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3533 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3529 else { 3534 else {
3530 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3535 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3561,9 +3566,9 @@ static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
3561 3566
3562static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 3567static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3563{ 3568{
3569 struct ath9k_hw_capabilities *pCap = &ah->caps;
3564 int chain; 3570 int chain;
3565 u32 regval; 3571 u32 regval;
3566 u32 ant_div_ctl1;
3567 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = { 3572 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3568 AR_PHY_SWITCH_CHAIN_0, 3573 AR_PHY_SWITCH_CHAIN_0,
3569 AR_PHY_SWITCH_CHAIN_1, 3574 AR_PHY_SWITCH_CHAIN_1,
@@ -3572,7 +3577,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3572 3577
3573 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); 3578 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3574 3579
3575 if (AR_SREV_9462(ah)) { 3580 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3576 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3581 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3577 AR_SWITCH_TABLE_COM_AR9462_ALL, value); 3582 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3578 } else if (AR_SREV_9550(ah)) { 3583 } else if (AR_SREV_9550(ah)) {
@@ -3616,7 +3621,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3616 } 3621 }
3617 } 3622 }
3618 3623
3619 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 3624 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3620 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); 3625 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3621 /* 3626 /*
3622 * main_lnaconf, alt_lnaconf, main_tb, alt_tb 3627 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
@@ -3626,41 +3631,44 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3626 regval &= (~AR_ANT_DIV_CTRL_ALL); 3631 regval &= (~AR_ANT_DIV_CTRL_ALL);
3627 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; 3632 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3628 /* enable_lnadiv */ 3633 /* enable_lnadiv */
3629 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV); 3634 regval &= (~AR_PHY_ANT_DIV_LNADIV);
3630 regval |= ((value >> 6) & 0x1) << 3635 regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
3631 AR_PHY_9485_ANT_DIV_LNADIV_S; 3636
3637 if (AR_SREV_9565(ah)) {
3638 if (ah->shared_chain_lnadiv) {
3639 regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);
3640 } else {
3641 regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S);
3642 regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S);
3643 }
3644 }
3645
3632 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 3646 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3633 3647
3634 /*enable fast_div */ 3648 /*enable fast_div */
3635 regval = REG_READ(ah, AR_PHY_CCK_DETECT); 3649 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3636 regval &= (~AR_FAST_DIV_ENABLE); 3650 regval &= (~AR_FAST_DIV_ENABLE);
3637 regval |= ((value >> 7) & 0x1) << 3651 regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
3638 AR_FAST_DIV_ENABLE_S;
3639 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); 3652 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3640 ant_div_ctl1 = 3653
3641 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 3654 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
3642 /* check whether antenna diversity is enabled */
3643 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3644 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3655 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3645 /* 3656 /*
3646 * clear bits 25-30 main_lnaconf, alt_lnaconf, 3657 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3647 * main_tb, alt_tb 3658 * main_tb, alt_tb
3648 */ 3659 */
3649 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF | 3660 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
3650 AR_PHY_9485_ANT_DIV_ALT_LNACONF | 3661 AR_PHY_ANT_DIV_ALT_LNACONF |
3651 AR_PHY_9485_ANT_DIV_ALT_GAINTB | 3662 AR_PHY_ANT_DIV_ALT_GAINTB |
3652 AR_PHY_9485_ANT_DIV_MAIN_GAINTB)); 3663 AR_PHY_ANT_DIV_MAIN_GAINTB));
3653 /* by default use LNA1 for the main antenna */ 3664 /* by default use LNA1 for the main antenna */
3654 regval |= (AR_PHY_9485_ANT_DIV_LNA1 << 3665 regval |= (AR_PHY_ANT_DIV_LNA1 <<
3655 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S); 3666 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
3656 regval |= (AR_PHY_9485_ANT_DIV_LNA2 << 3667 regval |= (AR_PHY_ANT_DIV_LNA2 <<
3657 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S); 3668 AR_PHY_ANT_DIV_ALT_LNACONF_S);
3658 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 3669 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3659 } 3670 }
3660
3661
3662 } 3671 }
3663
3664} 3672}
3665 3673
3666static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) 3674static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
@@ -3847,7 +3855,7 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3847 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3855 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3848 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3856 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3849 return; 3857 return;
3850 } else if (AR_SREV_9462(ah)) { 3858 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3851 reg_val = le32_to_cpu(pBase->swreg); 3859 reg_val = le32_to_cpu(pBase->swreg);
3852 REG_WRITE(ah, AR_PHY_PMU1, reg_val); 3860 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3853 } else { 3861 } else {
@@ -3878,7 +3886,7 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3878 while (!REG_READ_FIELD(ah, AR_PHY_PMU2, 3886 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3879 AR_PHY_PMU2_PGM)) 3887 AR_PHY_PMU2_PGM))
3880 udelay(10); 3888 udelay(10);
3881 } else if (AR_SREV_9462(ah)) 3889 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
3882 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); 3890 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3883 else { 3891 else {
3884 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | 3892 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
@@ -3981,6 +3989,62 @@ static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
3981 bias & 0x3); 3989 bias & 0x3);
3982} 3990}
3983 3991
3992static int ar9003_hw_get_thermometer(struct ath_hw *ah)
3993{
3994 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3995 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3996 int thermometer = (pBase->miscConfiguration >> 1) & 0x3;
3997
3998 return --thermometer;
3999}
4000
4001static void ar9003_hw_thermometer_apply(struct ath_hw *ah)
4002{
4003 int thermometer = ar9003_hw_get_thermometer(ah);
4004 u8 therm_on = (thermometer < 0) ? 0 : 1;
4005
4006 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4007 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4008 if (ah->caps.tx_chainmask & BIT(1))
4009 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4010 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4011 if (ah->caps.tx_chainmask & BIT(2))
4012 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4013 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4014
4015 therm_on = (thermometer < 0) ? 0 : (thermometer == 0);
4016 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4017 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4018 if (ah->caps.tx_chainmask & BIT(1)) {
4019 therm_on = (thermometer < 0) ? 0 : (thermometer == 1);
4020 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4021 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4022 }
4023 if (ah->caps.tx_chainmask & BIT(2)) {
4024 therm_on = (thermometer < 0) ? 0 : (thermometer == 2);
4025 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4026 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4027 }
4028}
4029
4030static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
4031{
4032 u32 data, ko, kg;
4033
4034 if (!AR_SREV_9462_20(ah))
4035 return;
4036 ar9300_otp_read_word(ah, 1, &data);
4037 ko = data & 0xff;
4038 kg = (data >> 8) & 0xff;
4039 if (ko || kg) {
4040 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4041 AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET, ko);
4042 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4043 AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN,
4044 kg + 256);
4045 }
4046}
4047
3984static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, 4048static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3985 struct ath9k_channel *chan) 4049 struct ath9k_channel *chan)
3986{ 4050{
@@ -3996,6 +4060,8 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3996 ar9003_hw_internal_regulator_apply(ah); 4060 ar9003_hw_internal_regulator_apply(ah);
3997 ar9003_hw_apply_tuning_caps(ah); 4061 ar9003_hw_apply_tuning_caps(ah);
3998 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz); 4062 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
4063 ar9003_hw_thermometer_apply(ah);
4064 ar9003_hw_thermo_cal_apply(ah);
3999} 4065}
4000 4066
4001static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, 4067static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
@@ -4532,7 +4598,7 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
4532{ 4598{
4533 int tempSlope = 0; 4599 int tempSlope = 0;
4534 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4600 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4535 int f[3], t[3]; 4601 int f[8], t[8], i;
4536 4602
4537 REG_RMW(ah, AR_PHY_TPC_11_B0, 4603 REG_RMW(ah, AR_PHY_TPC_11_B0,
4538 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4604 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
@@ -4565,7 +4631,14 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
4565 */ 4631 */
4566 if (frequency < 4000) 4632 if (frequency < 4000)
4567 tempSlope = eep->modalHeader2G.tempSlope; 4633 tempSlope = eep->modalHeader2G.tempSlope;
4568 else if (eep->base_ext2.tempSlopeLow != 0) { 4634 else if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) {
4635 for (i = 0; i < 8; i++) {
4636 t[i] = eep->base_ext1.tempslopextension[i];
4637 f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0);
4638 }
4639 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4640 f, t, 8);
4641 } else if (eep->base_ext2.tempSlopeLow != 0) {
4569 t[0] = eep->base_ext2.tempSlopeLow; 4642 t[0] = eep->base_ext2.tempSlopeLow;
4570 f[0] = 5180; 4643 f[0] = 5180;
4571 t[1] = eep->modalHeader5G.tempSlope; 4644 t[1] = eep->modalHeader5G.tempSlope;
@@ -4905,90 +4978,79 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4905 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], 4978 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4906 chan->channel); 4979 chan->channel);
4907 4980
4908 /* 4981 /*
4909 * compare test group from regulatory 4982 * compare test group from regulatory
4910 * channel list with test mode from pCtlMode 4983 * channel list with test mode from pCtlMode
4911 * list 4984 * list
4912 */ 4985 */
4913 if ((((cfgCtl & ~CTL_MODE_M) | 4986 if ((((cfgCtl & ~CTL_MODE_M) |
4914 (pCtlMode[ctlMode] & CTL_MODE_M)) == 4987 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4915 ctlIndex[i]) || 4988 ctlIndex[i]) ||
4916 (((cfgCtl & ~CTL_MODE_M) | 4989 (((cfgCtl & ~CTL_MODE_M) |
4917 (pCtlMode[ctlMode] & CTL_MODE_M)) == 4990 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4918 ((ctlIndex[i] & CTL_MODE_M) | 4991 ((ctlIndex[i] & CTL_MODE_M) |
4919 SD_NO_CTL))) { 4992 SD_NO_CTL))) {
4920 twiceMinEdgePower = 4993 twiceMinEdgePower =
4921 ar9003_hw_get_max_edge_power(pEepData, 4994 ar9003_hw_get_max_edge_power(pEepData,
4922 freq, i, 4995 freq, i,
4923 is2ghz); 4996 is2ghz);
4924 4997
4925 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) 4998 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4926 /* 4999 /*
4927 * Find the minimum of all CTL 5000 * Find the minimum of all CTL
4928 * edge powers that apply to 5001 * edge powers that apply to
4929 * this channel 5002 * this channel
4930 */ 5003 */
4931 twiceMaxEdgePower = 5004 twiceMaxEdgePower =
4932 min(twiceMaxEdgePower, 5005 min(twiceMaxEdgePower,
4933 twiceMinEdgePower); 5006 twiceMinEdgePower);
4934 else { 5007 else {
4935 /* specific */ 5008 /* specific */
4936 twiceMaxEdgePower = 5009 twiceMaxEdgePower = twiceMinEdgePower;
4937 twiceMinEdgePower; 5010 break;
4938 break;
4939 }
4940 } 5011 }
4941 } 5012 }
5013 }
4942 5014
4943 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 5015 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4944 5016
4945 ath_dbg(common, REGULATORY, 5017 ath_dbg(common, REGULATORY,
4946 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", 5018 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4947 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, 5019 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4948 scaledPower, minCtlPower); 5020 scaledPower, minCtlPower);
4949 5021
4950 /* Apply ctl mode to correct target power set */ 5022 /* Apply ctl mode to correct target power set */
4951 switch (pCtlMode[ctlMode]) { 5023 switch (pCtlMode[ctlMode]) {
4952 case CTL_11B: 5024 case CTL_11B:
4953 for (i = ALL_TARGET_LEGACY_1L_5L; 5025 for (i = ALL_TARGET_LEGACY_1L_5L;
4954 i <= ALL_TARGET_LEGACY_11S; i++) 5026 i <= ALL_TARGET_LEGACY_11S; i++)
4955 pPwrArray[i] = 5027 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
4956 (u8)min((u16)pPwrArray[i], 5028 minCtlPower);
4957 minCtlPower); 5029 break;
4958 break; 5030 case CTL_11A:
4959 case CTL_11A: 5031 case CTL_11G:
4960 case CTL_11G: 5032 for (i = ALL_TARGET_LEGACY_6_24;
4961 for (i = ALL_TARGET_LEGACY_6_24; 5033 i <= ALL_TARGET_LEGACY_54; i++)
4962 i <= ALL_TARGET_LEGACY_54; i++) 5034 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
4963 pPwrArray[i] = 5035 minCtlPower);
4964 (u8)min((u16)pPwrArray[i], 5036 break;
4965 minCtlPower); 5037 case CTL_5GHT20:
4966 break; 5038 case CTL_2GHT20:
4967 case CTL_5GHT20: 5039 for (i = ALL_TARGET_HT20_0_8_16;
4968 case CTL_2GHT20: 5040 i <= ALL_TARGET_HT20_23; i++)
4969 for (i = ALL_TARGET_HT20_0_8_16; 5041 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
4970 i <= ALL_TARGET_HT20_21; i++) 5042 minCtlPower);
4971 pPwrArray[i] = 5043 break;
4972 (u8)min((u16)pPwrArray[i], 5044 case CTL_5GHT40:
4973 minCtlPower); 5045 case CTL_2GHT40:
4974 pPwrArray[ALL_TARGET_HT20_22] = 5046 for (i = ALL_TARGET_HT40_0_8_16;
4975 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22], 5047 i <= ALL_TARGET_HT40_23; i++)
4976 minCtlPower); 5048 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
4977 pPwrArray[ALL_TARGET_HT20_23] = 5049 minCtlPower);
4978 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23], 5050 break;
4979 minCtlPower); 5051 default:
4980 break; 5052 break;
4981 case CTL_5GHT40: 5053 }
4982 case CTL_2GHT40:
4983 for (i = ALL_TARGET_HT40_0_8_16;
4984 i <= ALL_TARGET_HT40_23; i++)
4985 pPwrArray[i] =
4986 (u8)min((u16)pPwrArray[i],
4987 minCtlPower);
4988 break;
4989 default:
4990 break;
4991 }
4992 } /* end ctl mode checking */ 5054 } /* end ctl mode checking */
4993} 5055}
4994 5056
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 3a1ff55bceb9..41b1a75e6bec 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -267,7 +267,8 @@ struct cal_ctl_data_5g {
267 267
268struct ar9300_BaseExtension_1 { 268struct ar9300_BaseExtension_1 {
269 u8 ant_div_control; 269 u8 ant_div_control;
270 u8 future[11]; 270 u8 future[3];
271 u8 tempslopextension[8];
271 int8_t quick_drop_low; 272 int8_t quick_drop_low;
272 int8_t quick_drop_high; 273 int8_t quick_drop_high;
273} __packed; 274} __packed;
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 1e8a4da5952f..1a36fa262639 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -24,6 +24,7 @@
24#include "ar955x_1p0_initvals.h" 24#include "ar955x_1p0_initvals.h"
25#include "ar9580_1p0_initvals.h" 25#include "ar9580_1p0_initvals.h"
26#include "ar9462_2p0_initvals.h" 26#include "ar9462_2p0_initvals.h"
27#include "ar9565_1p0_initvals.h"
27 28
28/* General hardware code for the AR9003 hadware family */ 29/* General hardware code for the AR9003 hadware family */
29 30
@@ -34,14 +35,12 @@
34 */ 35 */
35static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 36static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
36{ 37{
37#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
38 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
39
40#define AR9462_BB_CTX_COEFJ(x) \ 38#define AR9462_BB_CTX_COEFJ(x) \
41 ar9462_##x##_baseband_core_txfir_coeff_japan_2484 39 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
42 40
43#define AR9462_BBC_TXIFR_COEFFJ \ 41#define AR9462_BBC_TXIFR_COEFFJ \
44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484 42 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
43
45 if (AR_SREV_9330_11(ah)) { 44 if (AR_SREV_9330_11(ah)) {
46 /* mac */ 45 /* mac */
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
@@ -220,10 +219,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
220 219
221 /* Awake -> Sleep Setting */ 220 /* Awake -> Sleep Setting */
222 INIT_INI_ARRAY(&ah->iniPcieSerdes, 221 INIT_INI_ARRAY(&ah->iniPcieSerdes,
223 PCIE_PLL_ON_CREQ_DIS_L1_2P0); 222 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0);
224 /* Sleep -> Awake Setting */ 223 /* Sleep -> Awake Setting */
225 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 224 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
226 PCIE_PLL_ON_CREQ_DIS_L1_2P0); 225 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0);
227 226
228 /* Fast clock modal settings */ 227 /* Fast clock modal settings */
229 INIT_INI_ARRAY(&ah->iniModesFastClock, 228 INIT_INI_ARRAY(&ah->iniModesFastClock,
@@ -302,6 +301,39 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
302 301
303 INIT_INI_ARRAY(&ah->iniModesFastClock, 302 INIT_INI_ARRAY(&ah->iniModesFastClock,
304 ar9580_1p0_modes_fast_clock); 303 ar9580_1p0_modes_fast_clock);
304 } else if (AR_SREV_9565(ah)) {
305 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
306 ar9565_1p0_mac_core);
307 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
308 ar9565_1p0_mac_postamble);
309
310 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
311 ar9565_1p0_baseband_core);
312 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
313 ar9565_1p0_baseband_postamble);
314
315 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
316 ar9565_1p0_radio_core);
317 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
318 ar9565_1p0_radio_postamble);
319
320 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
321 ar9565_1p0_soc_preamble);
322 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
323 ar9565_1p0_soc_postamble);
324
325 INIT_INI_ARRAY(&ah->iniModesRxGain,
326 ar9565_1p0_Common_rx_gain_table);
327 INIT_INI_ARRAY(&ah->iniModesTxGain,
328 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
329
330 INIT_INI_ARRAY(&ah->iniPcieSerdes,
331 ar9565_1p0_pciephy_pll_on_clkreq_disable_L1);
332 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
333 ar9565_1p0_pciephy_pll_on_clkreq_disable_L1);
334
335 INIT_INI_ARRAY(&ah->iniModesFastClock,
336 ar9565_1p0_modes_fast_clock);
305 } else { 337 } else {
306 /* mac */ 338 /* mac */
307 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 339 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
@@ -374,6 +406,9 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
374 else if (AR_SREV_9462_20(ah)) 406 else if (AR_SREV_9462_20(ah))
375 INIT_INI_ARRAY(&ah->iniModesTxGain, 407 INIT_INI_ARRAY(&ah->iniModesTxGain,
376 ar9462_modes_low_ob_db_tx_gain_table_2p0); 408 ar9462_modes_low_ob_db_tx_gain_table_2p0);
409 else if (AR_SREV_9565(ah))
410 INIT_INI_ARRAY(&ah->iniModesTxGain,
411 ar9565_1p0_modes_low_ob_db_tx_gain_table);
377 else 412 else
378 INIT_INI_ARRAY(&ah->iniModesTxGain, 413 INIT_INI_ARRAY(&ah->iniModesTxGain,
379 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 414 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
@@ -402,6 +437,9 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
402 else if (AR_SREV_9462_20(ah)) 437 else if (AR_SREV_9462_20(ah))
403 INIT_INI_ARRAY(&ah->iniModesTxGain, 438 INIT_INI_ARRAY(&ah->iniModesTxGain,
404 ar9462_modes_high_ob_db_tx_gain_table_2p0); 439 ar9462_modes_high_ob_db_tx_gain_table_2p0);
440 else if (AR_SREV_9565(ah))
441 INIT_INI_ARRAY(&ah->iniModesTxGain,
442 ar9565_1p0_modes_high_ob_db_tx_gain_table);
405 else 443 else
406 INIT_INI_ARRAY(&ah->iniModesTxGain, 444 INIT_INI_ARRAY(&ah->iniModesTxGain,
407 ar9300Modes_high_ob_db_tx_gain_table_2p2); 445 ar9300Modes_high_ob_db_tx_gain_table_2p2);
@@ -424,6 +462,9 @@ static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
424 else if (AR_SREV_9580(ah)) 462 else if (AR_SREV_9580(ah))
425 INIT_INI_ARRAY(&ah->iniModesTxGain, 463 INIT_INI_ARRAY(&ah->iniModesTxGain,
426 ar9580_1p0_low_ob_db_tx_gain_table); 464 ar9580_1p0_low_ob_db_tx_gain_table);
465 else if (AR_SREV_9565(ah))
466 INIT_INI_ARRAY(&ah->iniModesTxGain,
467 ar9565_1p0_modes_low_ob_db_tx_gain_table);
427 else 468 else
428 INIT_INI_ARRAY(&ah->iniModesTxGain, 469 INIT_INI_ARRAY(&ah->iniModesTxGain,
429 ar9300Modes_low_ob_db_tx_gain_table_2p2); 470 ar9300Modes_low_ob_db_tx_gain_table_2p2);
@@ -446,6 +487,9 @@ static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
446 else if (AR_SREV_9580(ah)) 487 else if (AR_SREV_9580(ah))
447 INIT_INI_ARRAY(&ah->iniModesTxGain, 488 INIT_INI_ARRAY(&ah->iniModesTxGain,
448 ar9580_1p0_high_power_tx_gain_table); 489 ar9580_1p0_high_power_tx_gain_table);
490 else if (AR_SREV_9565(ah))
491 INIT_INI_ARRAY(&ah->iniModesTxGain,
492 ar9565_1p0_modes_high_power_tx_gain_table);
449 else 493 else
450 INIT_INI_ARRAY(&ah->iniModesTxGain, 494 INIT_INI_ARRAY(&ah->iniModesTxGain,
451 ar9300Modes_high_power_tx_gain_table_2p2); 495 ar9300Modes_high_power_tx_gain_table_2p2);
@@ -538,6 +582,9 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
538 } else if (AR_SREV_9580(ah)) 582 } else if (AR_SREV_9580(ah))
539 INIT_INI_ARRAY(&ah->iniModesRxGain, 583 INIT_INI_ARRAY(&ah->iniModesRxGain,
540 ar9580_1p0_wo_xlna_rx_gain_table); 584 ar9580_1p0_wo_xlna_rx_gain_table);
585 else if (AR_SREV_9565(ah))
586 INIT_INI_ARRAY(&ah->iniModesRxGain,
587 ar9565_1p0_common_wo_xlna_rx_gain_table);
541 else 588 else
542 INIT_INI_ARRAY(&ah->iniModesRxGain, 589 INIT_INI_ARRAY(&ah->iniModesRxGain,
543 ar9300Common_wo_xlna_rx_gain_table_2p2); 590 ar9300Common_wo_xlna_rx_gain_table_2p2);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 78816b8b2173..301bf72c53bf 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -31,7 +31,7 @@ ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
31 u32 val, ctl12, ctl17; 31 u32 val, ctl12, ctl17;
32 u8 desc_len; 32 u8 desc_len;
33 33
34 desc_len = (AR_SREV_9462(ah) ? 0x18 : 0x17); 34 desc_len = ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x18 : 0x17);
35 35
36 val = (ATHEROS_VENDOR_ID << AR_DescId_S) | 36 val = (ATHEROS_VENDOR_ID << AR_DescId_S) |
37 (1 << AR_TxRxDesc_S) | 37 (1 << AR_TxRxDesc_S) |
@@ -182,6 +182,7 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
182 struct ath9k_hw_capabilities *pCap = &ah->caps; 182 struct ath9k_hw_capabilities *pCap = &ah->caps;
183 struct ath_common *common = ath9k_hw_common(ah); 183 struct ath_common *common = ath9k_hw_common(ah);
184 u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ; 184 u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ;
185 bool fatal_int;
185 186
186 if (ath9k_hw_mci_is_enabled(ah)) 187 if (ath9k_hw_mci_is_enabled(ah))
187 async_mask |= AR_INTR_ASYNC_MASK_MCI; 188 async_mask |= AR_INTR_ASYNC_MASK_MCI;
@@ -310,6 +311,22 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
310 311
311 if (sync_cause) { 312 if (sync_cause) {
312 ath9k_debug_sync_cause(common, sync_cause); 313 ath9k_debug_sync_cause(common, sync_cause);
314 fatal_int =
315 (sync_cause &
316 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
317 ? true : false;
318
319 if (fatal_int) {
320 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
321 ath_dbg(common, ANY,
322 "received PCI FATAL interrupt\n");
323 }
324 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
325 ath_dbg(common, ANY,
326 "received PCI PERR interrupt\n");
327 }
328 *masked |= ATH9K_INT_FATAL;
329 }
313 330
314 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 331 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
315 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 332 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
@@ -531,7 +548,7 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
531 rxs->rs_status |= ATH9K_RXERR_PHY; 548 rxs->rs_status |= ATH9K_RXERR_PHY;
532 rxs->rs_phyerr = phyerr; 549 rxs->rs_phyerr = phyerr;
533 } 550 }
534 }; 551 }
535 } 552 }
536 553
537 if (rxsp->status11 & AR_KeyMiss) 554 if (rxsp->status11 & AR_KeyMiss)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.c b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
index 9a34fcaae3ff..44c202ce6c66 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mci.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
@@ -714,6 +714,7 @@ bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan)
714 714
715 return true; 715 return true;
716} 716}
717EXPORT_SYMBOL(ar9003_mci_start_reset);
717 718
718int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, 719int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
719 struct ath9k_hw_cal_data *caldata) 720 struct ath9k_hw_cal_data *caldata)
@@ -812,8 +813,8 @@ static void ar9003_mci_osla_setup(struct ath_hw *ah, bool enable)
812 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1); 813 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1);
813} 814}
814 815
815void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, 816int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
816 bool is_full_sleep) 817 bool is_full_sleep)
817{ 818{
818 struct ath_common *common = ath9k_hw_common(ah); 819 struct ath_common *common = ath9k_hw_common(ah);
819 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 820 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
@@ -823,14 +824,13 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
823 is_full_sleep, is_2g); 824 is_full_sleep, is_2g);
824 825
825 if (!mci->gpm_addr && !mci->sched_addr) { 826 if (!mci->gpm_addr && !mci->sched_addr) {
826 ath_dbg(common, MCI, 827 ath_err(common, "MCI GPM and schedule buffers are not allocated\n");
827 "MCI GPM and schedule buffers are not allocated\n"); 828 return -ENOMEM;
828 return;
829 } 829 }
830 830
831 if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) { 831 if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {
832 ath_dbg(common, MCI, "BTCOEX control register is dead\n"); 832 ath_err(common, "BTCOEX control register is dead\n");
833 return; 833 return -EINVAL;
834 } 834 }
835 835
836 /* Program MCI DMA related registers */ 836 /* Program MCI DMA related registers */
@@ -912,6 +912,8 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
912 912
913 if (en_int) 913 if (en_int)
914 ar9003_mci_enable_interrupt(ah); 914 ar9003_mci_enable_interrupt(ah);
915
916 return 0;
915} 917}
916 918
917void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep) 919void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
@@ -1026,6 +1028,7 @@ void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force)
1026 1028
1027 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) 1029 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA))
1028 ar9003_mci_osla_setup(ah, true); 1030 ar9003_mci_osla_setup(ah, true);
1031 REG_WRITE(ah, AR_SELFGEN_MASK, 0x02);
1029 } else { 1032 } else {
1030 ar9003_mci_send_lna_take(ah, true); 1033 ar9003_mci_send_lna_take(ah, true);
1031 udelay(5); 1034 udelay(5);
@@ -1142,8 +1145,8 @@ void ar9003_mci_init_cal_done(struct ath_hw *ah)
1142 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false); 1145 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
1143} 1146}
1144 1147
1145void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf, 1148int ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
1146 u16 len, u32 sched_addr) 1149 u16 len, u32 sched_addr)
1147{ 1150{
1148 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 1151 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1149 1152
@@ -1152,7 +1155,7 @@ void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
1152 mci->gpm_len = len; 1155 mci->gpm_len = len;
1153 mci->sched_addr = sched_addr; 1156 mci->sched_addr = sched_addr;
1154 1157
1155 ar9003_mci_reset(ah, true, true, true); 1158 return ar9003_mci_reset(ah, true, true, true);
1156} 1159}
1157EXPORT_SYMBOL(ar9003_mci_setup); 1160EXPORT_SYMBOL(ar9003_mci_setup);
1158 1161
@@ -1201,12 +1204,6 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type)
1201 1204
1202 ar9003_mci_2g5g_switch(ah, false); 1205 ar9003_mci_2g5g_switch(ah, false);
1203 break; 1206 break;
1204 case MCI_STATE_SET_BT_CAL_START:
1205 mci->bt_state = MCI_BT_CAL_START;
1206 break;
1207 case MCI_STATE_SET_BT_CAL:
1208 mci->bt_state = MCI_BT_CAL;
1209 break;
1210 case MCI_STATE_RESET_REQ_WAKE: 1207 case MCI_STATE_RESET_REQ_WAKE:
1211 ar9003_mci_reset_req_wakeup(ah); 1208 ar9003_mci_reset_req_wakeup(ah);
1212 mci->update_2g5g = true; 1209 mci->update_2g5g = true;
@@ -1240,6 +1237,10 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type)
1240 case MCI_STATE_NEED_FTP_STOMP: 1237 case MCI_STATE_NEED_FTP_STOMP:
1241 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP); 1238 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP);
1242 break; 1239 break;
1240 case MCI_STATE_NEED_FLUSH_BT_INFO:
1241 value = (!mci->unhalt_bt_gpm && mci->need_flush_btinfo) ? 1 : 0;
1242 mci->need_flush_btinfo = false;
1243 break;
1243 default: 1244 default:
1244 break; 1245 break;
1245 } 1246 }
@@ -1289,7 +1290,7 @@ void ar9003_mci_set_power_awake(struct ath_hw *ah)
1289 } 1290 }
1290 REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18))); 1291 REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18)));
1291 lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3; 1292 lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3;
1292 bt_sleep = REG_READ(ah, AR_MCI_RX_STATUS) & AR_MCI_RX_REMOTE_SLEEP; 1293 bt_sleep = MS(REG_READ(ah, AR_MCI_RX_STATUS), AR_MCI_RX_REMOTE_SLEEP);
1293 1294
1294 REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2); 1295 REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2);
1295 REG_WRITE(ah, AR_DIAG_SW, diag_sw); 1296 REG_WRITE(ah, AR_DIAG_SW, diag_sw);
@@ -1327,6 +1328,10 @@ u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, bool first, u32 *more)
1327 1328
1328 if (first) { 1329 if (first) {
1329 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); 1330 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1331
1332 if (gpm_ptr >= mci->gpm_len)
1333 gpm_ptr = 0;
1334
1330 mci->gpm_idx = gpm_ptr; 1335 mci->gpm_idx = gpm_ptr;
1331 return gpm_ptr; 1336 return gpm_ptr;
1332 } 1337 }
@@ -1371,6 +1376,10 @@ u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, bool first, u32 *more)
1371 more_gpm = MCI_GPM_NOMORE; 1376 more_gpm = MCI_GPM_NOMORE;
1372 1377
1373 temp_index = mci->gpm_idx; 1378 temp_index = mci->gpm_idx;
1379
1380 if (temp_index >= mci->gpm_len)
1381 temp_index = 0;
1382
1374 mci->gpm_idx++; 1383 mci->gpm_idx++;
1375 1384
1376 if (mci->gpm_idx >= mci->gpm_len) 1385 if (mci->gpm_idx >= mci->gpm_len)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.h b/drivers/net/wireless/ath/ath9k/ar9003_mci.h
index d33b8e128855..2a2d01889613 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mci.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.h
@@ -190,8 +190,6 @@ enum mci_bt_state {
190enum mci_state_type { 190enum mci_state_type {
191 MCI_STATE_ENABLE, 191 MCI_STATE_ENABLE,
192 MCI_STATE_SET_BT_AWAKE, 192 MCI_STATE_SET_BT_AWAKE,
193 MCI_STATE_SET_BT_CAL_START,
194 MCI_STATE_SET_BT_CAL,
195 MCI_STATE_LAST_SCHD_MSG_OFFSET, 193 MCI_STATE_LAST_SCHD_MSG_OFFSET,
196 MCI_STATE_REMOTE_SLEEP, 194 MCI_STATE_REMOTE_SLEEP,
197 MCI_STATE_RESET_REQ_WAKE, 195 MCI_STATE_RESET_REQ_WAKE,
@@ -202,6 +200,7 @@ enum mci_state_type {
202 MCI_STATE_RECOVER_RX, 200 MCI_STATE_RECOVER_RX,
203 MCI_STATE_NEED_FTP_STOMP, 201 MCI_STATE_NEED_FTP_STOMP,
204 MCI_STATE_DEBUG, 202 MCI_STATE_DEBUG,
203 MCI_STATE_NEED_FLUSH_BT_INFO,
205 MCI_STATE_MAX 204 MCI_STATE_MAX
206}; 205};
207 206
@@ -213,7 +212,8 @@ enum mci_gpm_coex_opcode {
213 MCI_GPM_COEX_WLAN_CHANNELS, 212 MCI_GPM_COEX_WLAN_CHANNELS,
214 MCI_GPM_COEX_BT_PROFILE_INFO, 213 MCI_GPM_COEX_BT_PROFILE_INFO,
215 MCI_GPM_COEX_BT_STATUS_UPDATE, 214 MCI_GPM_COEX_BT_STATUS_UPDATE,
216 MCI_GPM_COEX_BT_UPDATE_FLAGS 215 MCI_GPM_COEX_BT_UPDATE_FLAGS,
216 MCI_GPM_COEX_NOOP,
217}; 217};
218 218
219#define MCI_GPM_NOMORE 0 219#define MCI_GPM_NOMORE 0
@@ -249,8 +249,8 @@ bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
249 u32 *payload, u8 len, bool wait_done, 249 u32 *payload, u8 len, bool wait_done,
250 bool check_bt); 250 bool check_bt);
251u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type); 251u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type);
252void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf, 252int ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
253 u16 len, u32 sched_addr); 253 u16 len, u32 sched_addr);
254void ar9003_mci_cleanup(struct ath_hw *ah); 254void ar9003_mci_cleanup(struct ath_hw *ah);
255void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr, 255void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
256 u32 *rx_msg_intr); 256 u32 *rx_msg_intr);
@@ -272,8 +272,8 @@ void ar9003_mci_check_bt(struct ath_hw *ah);
272bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan); 272bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan);
273int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, 273int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
274 struct ath9k_hw_cal_data *caldata); 274 struct ath9k_hw_cal_data *caldata);
275void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, 275int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
276 bool is_full_sleep); 276 bool is_full_sleep);
277void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked); 277void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked);
278void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah); 278void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah);
279void ar9003_mci_set_power_awake(struct ath_hw *ah); 279void ar9003_mci_set_power_awake(struct ath_hw *ah);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index e476f9f92ce3..759f5f5a7154 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -88,7 +88,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
88 channelSel = (freq * 4) / div; 88 channelSel = (freq * 4) / div;
89 chan_frac = (((freq * 4) % div) * 0x20000) / div; 89 chan_frac = (((freq * 4) % div) * 0x20000) / div;
90 channelSel = (channelSel << 17) | chan_frac; 90 channelSel = (channelSel << 17) | chan_frac;
91 } else if (AR_SREV_9485(ah)) { 91 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
92 u32 chan_frac; 92 u32 chan_frac;
93 93
94 /* 94 /*
@@ -206,6 +206,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
206 for (i = 0; i < max_spur_cnts; i++) { 206 for (i = 0; i < max_spur_cnts; i++) {
207 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) 207 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
208 continue; 208 continue;
209
209 negative = 0; 210 negative = 0;
210 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 211 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
211 AR_SREV_9550(ah)) 212 AR_SREV_9550(ah))
@@ -301,7 +302,9 @@ static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
301 int freq_offset, 302 int freq_offset,
302 int spur_freq_sd, 303 int spur_freq_sd,
303 int spur_delta_phase, 304 int spur_delta_phase,
304 int spur_subchannel_sd) 305 int spur_subchannel_sd,
306 int range,
307 int synth_freq)
305{ 308{
306 int mask_index = 0; 309 int mask_index = 0;
307 310
@@ -316,8 +319,11 @@ static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
316 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); 319 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 320 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); 321 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 322
320 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); 323 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
324 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
325 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
326
321 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 327 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
322 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); 328 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
323 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 329 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
@@ -358,9 +364,44 @@ static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
358 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); 364 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
359} 365}
360 366
367static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
368 int freq_offset)
369{
370 int mask_index = 0;
371
372 mask_index = (freq_offset << 4) / 5;
373 if (mask_index < 0)
374 mask_index = mask_index - 1;
375
376 mask_index = mask_index & 0x7f;
377
378 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
379 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
380 mask_index);
381
382 /* A == B */
383 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
384 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
385 mask_index);
386
387 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
388 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
389 mask_index);
390 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
391 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
392 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
393 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
394
395 /* A == B */
396 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
397 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
398}
399
361static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, 400static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
362 struct ath9k_channel *chan, 401 struct ath9k_channel *chan,
363 int freq_offset) 402 int freq_offset,
403 int range,
404 int synth_freq)
364{ 405{
365 int spur_freq_sd = 0; 406 int spur_freq_sd = 0;
366 int spur_subchannel_sd = 0; 407 int spur_subchannel_sd = 0;
@@ -402,7 +443,8 @@ static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
402 freq_offset, 443 freq_offset,
403 spur_freq_sd, 444 spur_freq_sd,
404 spur_delta_phase, 445 spur_delta_phase,
405 spur_subchannel_sd); 446 spur_subchannel_sd,
447 range, synth_freq);
406} 448}
407 449
408/* Spur mitigation for OFDM */ 450/* Spur mitigation for OFDM */
@@ -447,7 +489,17 @@ static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
447 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode); 489 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
448 freq_offset -= synth_freq; 490 freq_offset -= synth_freq;
449 if (abs(freq_offset) < range) { 491 if (abs(freq_offset) < range) {
450 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset); 492 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
493 range, synth_freq);
494
495 if (AR_SREV_9565(ah) && (i < 4)) {
496 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
497 mode);
498 freq_offset -= synth_freq;
499 if (abs(freq_offset) < range)
500 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
501 }
502
451 break; 503 break;
452 } 504 }
453 } 505 }
@@ -456,7 +508,8 @@ static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456static void ar9003_hw_spur_mitigate(struct ath_hw *ah, 508static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
457 struct ath9k_channel *chan) 509 struct ath9k_channel *chan)
458{ 510{
459 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); 511 if (!AR_SREV_9565(ah))
512 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
460 ar9003_hw_spur_mitigate_ofdm(ah, chan); 513 ar9003_hw_spur_mitigate_ofdm(ah, chan);
461} 514}
462 515
@@ -552,9 +605,6 @@ static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
552 605
553 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 606 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
554 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 607 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
555 else if (AR_SREV_9462(ah))
556 /* xxx only when MCI support is enabled */
557 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
558 else 608 else
559 REG_WRITE(ah, AR_SELFGEN_MASK, tx); 609 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
560 610
@@ -736,7 +786,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
736 if (chan->channel == 2484) 786 if (chan->channel == 2484)
737 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1); 787 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
738 788
739 if (AR_SREV_9462(ah)) 789 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
740 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, 790 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
741 AR_GLB_SWREG_DISCONT_EN_BT_WLAN); 791 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
742 792
@@ -746,9 +796,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
746 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 796 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
747 ath9k_hw_apply_txpower(ah, chan, false); 797 ath9k_hw_apply_txpower(ah, chan, false);
748 798
749 if (AR_SREV_9462(ah)) { 799 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
750 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, 800 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
751 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) 801 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
752 ah->enabled_cals |= TX_IQ_CAL; 802 ah->enabled_cals |= TX_IQ_CAL;
753 else 803 else
754 ah->enabled_cals &= ~TX_IQ_CAL; 804 ah->enabled_cals &= ~TX_IQ_CAL;
@@ -1111,7 +1161,7 @@ static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1111 if (AR_SREV_9330(ah)) 1161 if (AR_SREV_9330(ah))
1112 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; 1162 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1113 1163
1114 if (AR_SREV_9462(ah)) { 1164 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1115 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; 1165 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1116 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; 1166 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1117 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; 1167 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
@@ -1223,17 +1273,17 @@ static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1223} 1273}
1224 1274
1225static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, 1275static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1226 struct ath_hw_antcomb_conf *antconf) 1276 struct ath_hw_antcomb_conf *antconf)
1227{ 1277{
1228 u32 regval; 1278 u32 regval;
1229 1279
1230 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1280 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1231 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >> 1281 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1232 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S; 1282 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1233 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >> 1283 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1234 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S; 1284 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1235 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >> 1285 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1236 AR_PHY_9485_ANT_FAST_DIV_BIAS_S; 1286 AR_PHY_ANT_FAST_DIV_BIAS_S;
1237 1287
1238 if (AR_SREV_9330_11(ah)) { 1288 if (AR_SREV_9330_11(ah)) {
1239 antconf->lna1_lna2_delta = -9; 1289 antconf->lna1_lna2_delta = -9;
@@ -1241,6 +1291,9 @@ static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1241 } else if (AR_SREV_9485(ah)) { 1291 } else if (AR_SREV_9485(ah)) {
1242 antconf->lna1_lna2_delta = -9; 1292 antconf->lna1_lna2_delta = -9;
1243 antconf->div_group = 2; 1293 antconf->div_group = 2;
1294 } else if (AR_SREV_9565(ah)) {
1295 antconf->lna1_lna2_delta = -3;
1296 antconf->div_group = 3;
1244 } else { 1297 } else {
1245 antconf->lna1_lna2_delta = -3; 1298 antconf->lna1_lna2_delta = -3;
1246 antconf->div_group = 0; 1299 antconf->div_group = 0;
@@ -1253,26 +1306,84 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1253 u32 regval; 1306 u32 regval;
1254 1307
1255 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1308 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1256 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF | 1309 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1257 AR_PHY_9485_ANT_DIV_ALT_LNACONF | 1310 AR_PHY_ANT_DIV_ALT_LNACONF |
1258 AR_PHY_9485_ANT_FAST_DIV_BIAS | 1311 AR_PHY_ANT_FAST_DIV_BIAS |
1259 AR_PHY_9485_ANT_DIV_MAIN_GAINTB | 1312 AR_PHY_ANT_DIV_MAIN_GAINTB |
1260 AR_PHY_9485_ANT_DIV_ALT_GAINTB); 1313 AR_PHY_ANT_DIV_ALT_GAINTB);
1261 regval |= ((antconf->main_lna_conf << 1314 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1262 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S) 1315 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1263 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF); 1316 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1264 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S) 1317 & AR_PHY_ANT_DIV_ALT_LNACONF);
1265 & AR_PHY_9485_ANT_DIV_ALT_LNACONF); 1318 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1266 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S) 1319 & AR_PHY_ANT_FAST_DIV_BIAS);
1267 & AR_PHY_9485_ANT_FAST_DIV_BIAS); 1320 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1268 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S) 1321 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1269 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB); 1322 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1270 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S) 1323 & AR_PHY_ANT_DIV_ALT_GAINTB);
1271 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1272 1324
1273 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1325 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1274} 1326}
1275 1327
1328static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1329 bool enable)
1330{
1331 u8 ant_div_ctl1;
1332 u32 regval;
1333
1334 if (!AR_SREV_9565(ah))
1335 return;
1336
1337 ah->shared_chain_lnadiv = enable;
1338 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1339
1340 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1341 regval &= (~AR_ANT_DIV_CTRL_ALL);
1342 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1343 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1344 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1345
1346 if (enable)
1347 regval |= AR_ANT_DIV_ENABLE;
1348
1349 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1350
1351 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1352 regval &= ~AR_FAST_DIV_ENABLE;
1353 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1354
1355 if (enable)
1356 regval |= AR_FAST_DIV_ENABLE;
1357
1358 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1359
1360 if (enable) {
1361 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1362 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1363 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
1364 REG_SET_BIT(ah, AR_PHY_RESTART,
1365 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1366 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1367 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1368 } else {
1369 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1370 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1371 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1372 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1373 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1374 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1375
1376 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1377 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1378 AR_PHY_ANT_DIV_ALT_LNACONF |
1379 AR_PHY_ANT_DIV_MAIN_GAINTB |
1380 AR_PHY_ANT_DIV_ALT_GAINTB);
1381 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1382 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1383 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1384 }
1385}
1386
1276static int ar9003_hw_fast_chan_change(struct ath_hw *ah, 1387static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1277 struct ath9k_channel *chan, 1388 struct ath9k_channel *chan,
1278 u8 *ini_reloaded) 1389 u8 *ini_reloaded)
@@ -1312,10 +1423,10 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1312 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); 1423 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1313 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); 1424 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1314 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); 1425 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1426
1315 if (AR_SREV_9462_20(ah)) 1427 if (AR_SREV_9462_20(ah))
1316 ar9003_hw_prog_ini(ah, 1428 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1317 &ah->ini_radio_post_sys2ant, 1429 modesIndex);
1318 modesIndex);
1319 1430
1320 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1431 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1321 1432
@@ -1326,6 +1437,9 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1326 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1437 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1327 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); 1438 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1328 1439
1440 if (AR_SREV_9565(ah))
1441 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1442
1329 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); 1443 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1330 1444
1331 ah->modes_index = modesIndex; 1445 ah->modes_index = modesIndex;
@@ -1368,6 +1482,7 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1368 1482
1369 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; 1483 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1370 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; 1484 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1485 ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
1371 1486
1372 ar9003_hw_set_nf_limits(ah); 1487 ar9003_hw_set_nf_limits(ah);
1373 ar9003_hw_set_radar_conf(ah); 1488 ar9003_hw_set_radar_conf(ah);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 84d3d4956861..9a48e3d2f231 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -223,15 +223,24 @@
223#define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c) 223#define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c)
224#define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20) 224#define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20)
225 225
226#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0 226#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
227#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 227#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
228#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F 228#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
229#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0 229#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
230#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B 0x00FE0000
231#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_S 17
232#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B 0x0001F000
233#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B_S 12
230 234
231#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0 235#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
232#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5 236#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
233#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F 237#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
234#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0 238#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
239#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B 0x00FE0000
240#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_S 17
241#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B 0x0001F000
242#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B_S 12
243
235 244
236/* 245/*
237 * MRC Feild Definitions 246 * MRC Feild Definitions
@@ -271,23 +280,25 @@
271#define AR_ANT_DIV_ENABLE_S 24 280#define AR_ANT_DIV_ENABLE_S 24
272 281
273 282
274#define AR_PHY_9485_ANT_FAST_DIV_BIAS 0x00007e00 283#define AR_PHY_ANT_FAST_DIV_BIAS 0x00007e00
275#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S 9 284#define AR_PHY_ANT_FAST_DIV_BIAS_S 9
276#define AR_PHY_9485_ANT_DIV_LNADIV 0x01000000 285#define AR_PHY_ANT_SW_RX_PROT 0x00800000
277#define AR_PHY_9485_ANT_DIV_LNADIV_S 24 286#define AR_PHY_ANT_SW_RX_PROT_S 23
278#define AR_PHY_9485_ANT_DIV_ALT_LNACONF 0x06000000 287#define AR_PHY_ANT_DIV_LNADIV 0x01000000
279#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S 25 288#define AR_PHY_ANT_DIV_LNADIV_S 24
280#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF 0x18000000 289#define AR_PHY_ANT_DIV_ALT_LNACONF 0x06000000
281#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S 27 290#define AR_PHY_ANT_DIV_ALT_LNACONF_S 25
282#define AR_PHY_9485_ANT_DIV_ALT_GAINTB 0x20000000 291#define AR_PHY_ANT_DIV_MAIN_LNACONF 0x18000000
283#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S 29 292#define AR_PHY_ANT_DIV_MAIN_LNACONF_S 27
284#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB 0x40000000 293#define AR_PHY_ANT_DIV_ALT_GAINTB 0x20000000
285#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S 30 294#define AR_PHY_ANT_DIV_ALT_GAINTB_S 29
286 295#define AR_PHY_ANT_DIV_MAIN_GAINTB 0x40000000
287#define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2 0x0 296#define AR_PHY_ANT_DIV_MAIN_GAINTB_S 30
288#define AR_PHY_9485_ANT_DIV_LNA2 0x1 297
289#define AR_PHY_9485_ANT_DIV_LNA1 0x2 298#define AR_PHY_ANT_DIV_LNA1_MINUS_LNA2 0x0
290#define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2 0x3 299#define AR_PHY_ANT_DIV_LNA2 0x1
300#define AR_PHY_ANT_DIV_LNA1 0x2
301#define AR_PHY_ANT_DIV_LNA1_PLUS_LNA2 0x3
291 302
292#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c) 303#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
293#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30) 304#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
@@ -413,6 +424,8 @@
413#define AR_PHY_FIND_SIG_RELSTEP 0x1f 424#define AR_PHY_FIND_SIG_RELSTEP 0x1f
414#define AR_PHY_FIND_SIG_RELSTEP_S 0 425#define AR_PHY_FIND_SIG_RELSTEP_S 0
415#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5 426#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
427#define AR_PHY_RESTART_ENABLE_DIV_M2FLAG 0x00200000
428#define AR_PHY_RESTART_ENABLE_DIV_M2FLAG_S 21
416#define AR_PHY_RESTART_DIV_GC 0x001C0000 429#define AR_PHY_RESTART_DIV_GC 0x001C0000
417#define AR_PHY_RESTART_DIV_GC_S 18 430#define AR_PHY_RESTART_DIV_GC_S 18
418#define AR_PHY_RESTART_ENA 0x01 431#define AR_PHY_RESTART_ENA 0x01
@@ -609,6 +622,12 @@
609#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff 622#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
610#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0 623#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
611 624
625#define AR_PHY_BB_THERM_ADC_3 (AR_SM_BASE + 0x250)
626#define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN 0x0001ff00
627#define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN_S 8
628#define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET 0x000000ff
629#define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_S 0
630
612#define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254) 631#define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)
613#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff 632#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff
614#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0 633#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0
@@ -630,8 +649,8 @@
630#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1 649#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1
631 650
632#define AR_PHY_65NM_CH0_SYNTH4 0x1608c 651#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
633#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT (AR_SREV_9462(ah) ? 0x00000001 : 0x00000002) 652#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
634#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S (AR_SREV_9462(ah) ? 0 : 1) 653#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
635#define AR_PHY_65NM_CH0_SYNTH7 0x16098 654#define AR_PHY_65NM_CH0_SYNTH7 0x16098
636#define AR_PHY_65NM_CH0_BIAS1 0x160c0 655#define AR_PHY_65NM_CH0_BIAS1 0x160c0
637#define AR_PHY_65NM_CH0_BIAS2 0x160c4 656#define AR_PHY_65NM_CH0_BIAS2 0x160c4
@@ -641,7 +660,7 @@
641#define AR_PHY_65NM_CH2_RXTX4 0x1690c 660#define AR_PHY_65NM_CH2_RXTX4 0x1690c
642 661
643#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ 662#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
644 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280))) 663 (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
645#define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300) 664#define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
646#define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8) 665#define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)
647 666
@@ -669,7 +688,7 @@
669#define AR_SWITCH_TABLE_ALL_S (0) 688#define AR_SWITCH_TABLE_ALL_S (0)
670 689
671#define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\ 690#define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\
672 (AR_SREV_9462(ah) ? 0x16294 : 0x1628c)) 691 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16294 : 0x1628c))
673 692
674#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 693#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
675#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 694#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
@@ -691,17 +710,17 @@
691#define AR_CH0_TOP2_XPABIASLVL_S 12 710#define AR_CH0_TOP2_XPABIASLVL_S 12
692 711
693#define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \ 712#define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \
694 (AR_SREV_9462(ah) ? 0x16298 : 0x16290)) 713 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : 0x16290))
695#define AR_CH0_XTAL_CAPINDAC 0x7f000000 714#define AR_CH0_XTAL_CAPINDAC 0x7f000000
696#define AR_CH0_XTAL_CAPINDAC_S 24 715#define AR_CH0_XTAL_CAPINDAC_S 24
697#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 716#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
698#define AR_CH0_XTAL_CAPOUTDAC_S 17 717#define AR_CH0_XTAL_CAPOUTDAC_S 17
699 718
700#define AR_PHY_PMU1 (AR_SREV_9462(ah) ? 0x16340 : 0x16c40) 719#define AR_PHY_PMU1 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : 0x16c40)
701#define AR_PHY_PMU1_PWD 0x1 720#define AR_PHY_PMU1_PWD 0x1
702#define AR_PHY_PMU1_PWD_S 0 721#define AR_PHY_PMU1_PWD_S 0
703 722
704#define AR_PHY_PMU2 (AR_SREV_9462(ah) ? 0x16344 : 0x16c44) 723#define AR_PHY_PMU2 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : 0x16c44)
705#define AR_PHY_PMU2_PGM 0x00200000 724#define AR_PHY_PMU2_PGM 0x00200000
706#define AR_PHY_PMU2_PGM_S 21 725#define AR_PHY_PMU2_PGM_S 21
707 726
@@ -881,6 +900,8 @@
881 900
882#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 901#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
883#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 902#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
903#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR 0x20000000
904#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR_S 29
884 905
885#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000 906#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
886#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30 907#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30
@@ -1244,4 +1265,24 @@
1244#define AR_PHY_CL_TAB_CL_GAIN_MOD 0x1f 1265#define AR_PHY_CL_TAB_CL_GAIN_MOD 0x1f
1245#define AR_PHY_CL_TAB_CL_GAIN_MOD_S 0 1266#define AR_PHY_CL_TAB_CL_GAIN_MOD_S 0
1246 1267
1268#define AR_BTCOEX_WL_LNADIV 0x1a64
1269#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD 0x00003FFF
1270#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S 0
1271#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY 0x00004000
1272#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S 14
1273#define AR_BTCOEX_WL_LNADIV_FORCE_ON 0x00008000
1274#define AR_BTCOEX_WL_LNADIV_FORCE_ON_S 15
1275#define AR_BTCOEX_WL_LNADIV_MODE_OPTION 0x00030000
1276#define AR_BTCOEX_WL_LNADIV_MODE_OPTION_S 16
1277#define AR_BTCOEX_WL_LNADIV_MODE 0x007c0000
1278#define AR_BTCOEX_WL_LNADIV_MODE_S 18
1279#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ 0x00800000
1280#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S 23
1281#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE 0x01000000
1282#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S 24
1283#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT 0x02000000
1284#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S 25
1285#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD 0xFC000000
1286#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S 26
1287
1247#endif /* AR9003_PHY_H */ 1288#endif /* AR9003_PHY_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
index 4ef7dcccaa2f..58f30f65c6b6 100644
--- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
@@ -58,7 +58,7 @@ static const u32 ar9462_2p0_baseband_postamble[][5] = {
58 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, 58 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
59 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, 59 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
60 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, 60 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
61 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, 61 {0x00009e3c, 0xcf946222, 0xcf946222, 0xcfd5c782, 0xcfd5c282},
62 {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27}, 62 {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
63 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, 63 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
64 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, 64 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
diff --git a/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
new file mode 100644
index 000000000000..843e79f67ff2
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
@@ -0,0 +1,1231 @@
1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef INITVALS_9565_1P0_H
19#define INITVALS_9565_1P0_H
20
21/* AR9565 1.0 */
22
23static const u32 ar9565_1p0_mac_core[][2] = {
24 /* Addr allmodes */
25 {0x00000008, 0x00000000},
26 {0x00000030, 0x000a0085},
27 {0x00000034, 0x00000005},
28 {0x00000040, 0x00000000},
29 {0x00000044, 0x00000000},
30 {0x00000048, 0x00000008},
31 {0x0000004c, 0x00000010},
32 {0x00000050, 0x00000000},
33 {0x00001040, 0x002ffc0f},
34 {0x00001044, 0x002ffc0f},
35 {0x00001048, 0x002ffc0f},
36 {0x0000104c, 0x002ffc0f},
37 {0x00001050, 0x002ffc0f},
38 {0x00001054, 0x002ffc0f},
39 {0x00001058, 0x002ffc0f},
40 {0x0000105c, 0x002ffc0f},
41 {0x00001060, 0x002ffc0f},
42 {0x00001064, 0x002ffc0f},
43 {0x000010f0, 0x00000100},
44 {0x00001270, 0x00000000},
45 {0x000012b0, 0x00000000},
46 {0x000012f0, 0x00000000},
47 {0x0000143c, 0x00000000},
48 {0x0000147c, 0x00000000},
49 {0x00001810, 0x0f000003},
50 {0x00008000, 0x00000000},
51 {0x00008004, 0x00000000},
52 {0x00008008, 0x00000000},
53 {0x0000800c, 0x00000000},
54 {0x00008018, 0x00000000},
55 {0x00008020, 0x00000000},
56 {0x00008038, 0x00000000},
57 {0x0000803c, 0x00000000},
58 {0x00008040, 0x00000000},
59 {0x00008044, 0x00000000},
60 {0x00008048, 0x00000000},
61 {0x00008054, 0x00000000},
62 {0x00008058, 0x00000000},
63 {0x0000805c, 0x000fc78f},
64 {0x00008060, 0x0000000f},
65 {0x00008064, 0x00000000},
66 {0x00008070, 0x00000310},
67 {0x00008074, 0x00000020},
68 {0x00008078, 0x00000000},
69 {0x0000809c, 0x0000000f},
70 {0x000080a0, 0x00000000},
71 {0x000080a4, 0x02ff0000},
72 {0x000080a8, 0x0e070605},
73 {0x000080ac, 0x0000000d},
74 {0x000080b0, 0x00000000},
75 {0x000080b4, 0x00000000},
76 {0x000080b8, 0x00000000},
77 {0x000080bc, 0x00000000},
78 {0x000080c0, 0x2a800000},
79 {0x000080c4, 0x06900168},
80 {0x000080c8, 0x13881c20},
81 {0x000080cc, 0x01f40000},
82 {0x000080d0, 0x00252500},
83 {0x000080d4, 0x00b00005},
84 {0x000080d8, 0x00400002},
85 {0x000080dc, 0x00000000},
86 {0x000080e0, 0xffffffff},
87 {0x000080e4, 0x0000ffff},
88 {0x000080e8, 0x3f3f3f3f},
89 {0x000080ec, 0x00000000},
90 {0x000080f0, 0x00000000},
91 {0x000080f4, 0x00000000},
92 {0x000080fc, 0x00020000},
93 {0x00008100, 0x00000000},
94 {0x00008108, 0x00000052},
95 {0x0000810c, 0x00000000},
96 {0x00008110, 0x00000000},
97 {0x00008114, 0x000007ff},
98 {0x00008118, 0x000000aa},
99 {0x0000811c, 0x00003210},
100 {0x00008124, 0x00000000},
101 {0x00008128, 0x00000000},
102 {0x0000812c, 0x00000000},
103 {0x00008130, 0x00000000},
104 {0x00008134, 0x00000000},
105 {0x00008138, 0x00000000},
106 {0x0000813c, 0x0000ffff},
107 {0x00008144, 0xffffffff},
108 {0x00008168, 0x00000000},
109 {0x0000816c, 0x00000000},
110 {0x00008170, 0x18486200},
111 {0x00008174, 0x33332210},
112 {0x00008178, 0x00000000},
113 {0x0000817c, 0x00020000},
114 {0x000081c4, 0x33332210},
115 {0x000081c8, 0x00000000},
116 {0x000081cc, 0x00000000},
117 {0x000081d4, 0x00000000},
118 {0x000081ec, 0x00000000},
119 {0x000081f0, 0x00000000},
120 {0x000081f4, 0x00000000},
121 {0x000081f8, 0x00000000},
122 {0x000081fc, 0x00000000},
123 {0x00008240, 0x00100000},
124 {0x00008244, 0x0010f424},
125 {0x00008248, 0x00000800},
126 {0x0000824c, 0x0001e848},
127 {0x00008250, 0x00000000},
128 {0x00008254, 0x00000000},
129 {0x00008258, 0x00000000},
130 {0x0000825c, 0x40000000},
131 {0x00008260, 0x00080922},
132 {0x00008264, 0x9d400010},
133 {0x00008268, 0xffffffff},
134 {0x0000826c, 0x0000ffff},
135 {0x00008270, 0x00000000},
136 {0x00008274, 0x40000000},
137 {0x00008278, 0x003e4180},
138 {0x0000827c, 0x00000004},
139 {0x00008284, 0x0000002c},
140 {0x00008288, 0x0000002c},
141 {0x0000828c, 0x000000ff},
142 {0x00008294, 0x00000000},
143 {0x00008298, 0x00000000},
144 {0x0000829c, 0x00000000},
145 {0x00008300, 0x00000140},
146 {0x00008314, 0x00000000},
147 {0x0000831c, 0x0000010d},
148 {0x00008328, 0x00000000},
149 {0x0000832c, 0x0000001f},
150 {0x00008330, 0x00000302},
151 {0x00008334, 0x00000700},
152 {0x00008338, 0xffff0000},
153 {0x0000833c, 0x02400000},
154 {0x00008340, 0x000107ff},
155 {0x00008344, 0xaa48105b},
156 {0x00008348, 0x008f0000},
157 {0x0000835c, 0x00000000},
158 {0x00008360, 0xffffffff},
159 {0x00008364, 0xffffffff},
160 {0x00008368, 0x00000000},
161 {0x00008370, 0x00000000},
162 {0x00008374, 0x000000ff},
163 {0x00008378, 0x00000000},
164 {0x0000837c, 0x00000000},
165 {0x00008380, 0xffffffff},
166 {0x00008384, 0xffffffff},
167 {0x00008390, 0xffffffff},
168 {0x00008394, 0xffffffff},
169 {0x00008398, 0x00000000},
170 {0x0000839c, 0x00000000},
171 {0x000083a4, 0x0000fa14},
172 {0x000083a8, 0x000f0c00},
173 {0x000083ac, 0x33332210},
174 {0x000083b0, 0x33332210},
175 {0x000083b4, 0x33332210},
176 {0x000083b8, 0x33332210},
177 {0x000083bc, 0x00000000},
178 {0x000083c0, 0x00000000},
179 {0x000083c4, 0x00000000},
180 {0x000083c8, 0x00000000},
181 {0x000083cc, 0x00000200},
182 {0x000083d0, 0x800301ff},
183};
184
185static const u32 ar9565_1p0_mac_postamble[][5] = {
186 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
187 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
188 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
189 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
190 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
191 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
192 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
193 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
194 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
195};
196
197static const u32 ar9565_1p0_baseband_core[][2] = {
198 /* Addr allmodes */
199 {0x00009800, 0xafe68e30},
200 {0x00009804, 0xfd14e000},
201 {0x00009808, 0x9c0a8f6b},
202 {0x0000980c, 0x04800000},
203 {0x00009814, 0x9280c00a},
204 {0x00009818, 0x00000000},
205 {0x0000981c, 0x00020028},
206 {0x00009834, 0x6400a290},
207 {0x00009838, 0x0108ecff},
208 {0x0000983c, 0x0d000600},
209 {0x00009880, 0x201fff00},
210 {0x00009884, 0x00001042},
211 {0x000098a4, 0x00200400},
212 {0x000098b0, 0x32840bbe},
213 {0x000098d0, 0x004b6a8e},
214 {0x000098d4, 0x00000820},
215 {0x000098dc, 0x00000000},
216 {0x000098e4, 0x01ffffff},
217 {0x000098e8, 0x01ffffff},
218 {0x000098ec, 0x01ffffff},
219 {0x000098f0, 0x00000000},
220 {0x000098f4, 0x00000000},
221 {0x00009bf0, 0x80000000},
222 {0x00009c04, 0xff55ff55},
223 {0x00009c08, 0x0320ff55},
224 {0x00009c0c, 0x00000000},
225 {0x00009c10, 0x00000000},
226 {0x00009c14, 0x00046384},
227 {0x00009c18, 0x05b6b440},
228 {0x00009c1c, 0x00b6b440},
229 {0x00009d00, 0xc080a333},
230 {0x00009d04, 0x40206c10},
231 {0x00009d08, 0x009c4060},
232 {0x00009d0c, 0x1883800a},
233 {0x00009d10, 0x01834061},
234 {0x00009d14, 0x00c00400},
235 {0x00009d18, 0x00000000},
236 {0x00009e08, 0x0078230c},
237 {0x00009e24, 0x990bb515},
238 {0x00009e28, 0x126f0000},
239 {0x00009e30, 0x06336f77},
240 {0x00009e34, 0x6af6532f},
241 {0x00009e38, 0x0cc80c00},
242 {0x00009e40, 0x0d261820},
243 {0x00009e4c, 0x00001004},
244 {0x00009e50, 0x00ff03f1},
245 {0x00009e54, 0xe4c355c7},
246 {0x00009e5c, 0xe9198724},
247 {0x00009fc0, 0x823e4fc8},
248 {0x00009fc4, 0x0001efb5},
249 {0x00009fcc, 0x40000014},
250 {0x0000a20c, 0x00000000},
251 {0x0000a220, 0x00000000},
252 {0x0000a224, 0x00000000},
253 {0x0000a228, 0x10002310},
254 {0x0000a23c, 0x00000000},
255 {0x0000a244, 0x0c000000},
256 {0x0000a2a0, 0x00000001},
257 {0x0000a2c0, 0x00000001},
258 {0x0000a2c8, 0x00000000},
259 {0x0000a2cc, 0x18c43433},
260 {0x0000a2d4, 0x00000000},
261 {0x0000a2ec, 0x00000000},
262 {0x0000a2f0, 0x00000000},
263 {0x0000a2f4, 0x00000000},
264 {0x0000a2f8, 0x00000000},
265 {0x0000a344, 0x00000000},
266 {0x0000a34c, 0x00000000},
267 {0x0000a350, 0x0000a000},
268 {0x0000a364, 0x00000000},
269 {0x0000a370, 0x00000000},
270 {0x0000a390, 0x00000001},
271 {0x0000a394, 0x00000444},
272 {0x0000a398, 0x001f0e0f},
273 {0x0000a39c, 0x0075393f},
274 {0x0000a3a0, 0xb79f6427},
275 {0x0000a3a4, 0x00000000},
276 {0x0000a3a8, 0xaaaaaaaa},
277 {0x0000a3ac, 0x3c466478},
278 {0x0000a3c0, 0x20202020},
279 {0x0000a3c4, 0x22222220},
280 {0x0000a3c8, 0x20200020},
281 {0x0000a3cc, 0x20202020},
282 {0x0000a3d0, 0x20202020},
283 {0x0000a3d4, 0x20202020},
284 {0x0000a3d8, 0x20202020},
285 {0x0000a3dc, 0x20202020},
286 {0x0000a3e0, 0x20202020},
287 {0x0000a3e4, 0x20202020},
288 {0x0000a3e8, 0x20202020},
289 {0x0000a3ec, 0x20202020},
290 {0x0000a3f0, 0x00000000},
291 {0x0000a3f4, 0x00000006},
292 {0x0000a3f8, 0x0c9bd380},
293 {0x0000a3fc, 0x000f0f01},
294 {0x0000a400, 0x8fa91f01},
295 {0x0000a404, 0x00000000},
296 {0x0000a408, 0x0e79e5c6},
297 {0x0000a40c, 0x00820820},
298 {0x0000a414, 0x1ce739ce},
299 {0x0000a418, 0x2d001dce},
300 {0x0000a41c, 0x1ce739ce},
301 {0x0000a420, 0x000001ce},
302 {0x0000a424, 0x1ce739ce},
303 {0x0000a428, 0x000001ce},
304 {0x0000a42c, 0x1ce739ce},
305 {0x0000a430, 0x1ce739ce},
306 {0x0000a434, 0x00000000},
307 {0x0000a438, 0x00001801},
308 {0x0000a43c, 0x00000000},
309 {0x0000a440, 0x00000000},
310 {0x0000a444, 0x00000000},
311 {0x0000a448, 0x05000096},
312 {0x0000a44c, 0x00000001},
313 {0x0000a450, 0x00010000},
314 {0x0000a454, 0x03000000},
315 {0x0000a458, 0x00000000},
316 {0x0000a644, 0xbfad9d74},
317 {0x0000a648, 0x0048060a},
318 {0x0000a64c, 0x00003c37},
319 {0x0000a670, 0x03020100},
320 {0x0000a674, 0x09080504},
321 {0x0000a678, 0x0d0c0b0a},
322 {0x0000a67c, 0x13121110},
323 {0x0000a680, 0x31301514},
324 {0x0000a684, 0x35343332},
325 {0x0000a688, 0x00000036},
326 {0x0000a690, 0x00000838},
327 {0x0000a6b4, 0x00512c01},
328 {0x0000a7c0, 0x00000000},
329 {0x0000a7c4, 0xfffffffc},
330 {0x0000a7c8, 0x00000000},
331 {0x0000a7cc, 0x00000000},
332 {0x0000a7d0, 0x00000000},
333 {0x0000a7d4, 0x00000004},
334 {0x0000a7dc, 0x00000001},
335 {0x0000a7f0, 0x80000000},
336};
337
338static const u32 ar9565_1p0_baseband_postamble[][5] = {
339 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
340 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a800d},
341 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a01ae},
342 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x63c640da},
343 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x09143c81},
344 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
345 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
346 {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
347 {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
348 {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
349 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000d8},
350 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e},
351 {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
352 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
353 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
354 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
355 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
356 {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
357 {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
358 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
359 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
360 {0x0000a204, 0x07318fc0, 0x07318fc4, 0x07318fc4, 0x07318fc0},
361 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
362 {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f},
363 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
364 {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
365 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
366 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
367 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
368 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
369 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
370 {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
371 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
372 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
373 {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
374 {0x0000a288, 0x00100510, 0x00100510, 0x00100510, 0x00100510},
375 {0x0000a28c, 0x00021551, 0x00021551, 0x00021551, 0x00021551},
376 {0x0000a2c4, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18},
377 {0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982},
378 {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
379 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
380 {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
381 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
382};
383
384static const u32 ar9565_1p0_radio_core[][2] = {
385 /* Addr allmodes */
386 {0x00016000, 0x36db6db6},
387 {0x00016004, 0x6db6db40},
388 {0x00016008, 0x73f00000},
389 {0x0001600c, 0x00000000},
390 {0x00016010, 0x6d823601},
391 {0x00016040, 0x7f80fff8},
392 {0x0001604c, 0x1c99e04f},
393 {0x00016050, 0x6db6db6c},
394 {0x00016058, 0x6c200000},
395 {0x00016080, 0x000c0000},
396 {0x00016084, 0x9a68048c},
397 {0x00016088, 0x54214514},
398 {0x0001608c, 0x1203040b},
399 {0x00016090, 0x24926490},
400 {0x00016098, 0xd28b3330},
401 {0x000160a0, 0x0a108ffe},
402 {0x000160a4, 0x812fc491},
403 {0x000160a8, 0x423c8000},
404 {0x000160b4, 0x92000000},
405 {0x000160b8, 0x0285dddc},
406 {0x000160bc, 0x02908888},
407 {0x000160c0, 0x006db6d0},
408 {0x000160c4, 0x6dd6db60},
409 {0x000160c8, 0x6db6db6c},
410 {0x000160cc, 0x6de6c1b0},
411 {0x00016100, 0x3fffbe04},
412 {0x00016104, 0xfff80000},
413 {0x00016108, 0x00200400},
414 {0x00016110, 0x00000000},
415 {0x00016144, 0x02084080},
416 {0x00016148, 0x000080c0},
417 {0x00016280, 0x050a0001},
418 {0x00016284, 0x3d841440},
419 {0x00016288, 0x00000000},
420 {0x0001628c, 0xe3000000},
421 {0x00016290, 0xa1004080},
422 {0x00016294, 0x40000028},
423 {0x00016298, 0x55aa2900},
424 {0x00016340, 0x131c827a},
425 {0x00016344, 0x00300000},
426};
427
428static const u32 ar9565_1p0_radio_postamble[][5] = {
429 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
430 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
431 {0x000160ac, 0xa4646c08, 0xa4646c08, 0xa4646c08, 0xa4646c08},
432 {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
433 {0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000},
434 {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
435};
436
437static const u32 ar9565_1p0_soc_preamble[][2] = {
438 /* Addr allmodes */
439 {0x00004078, 0x00000002},
440 {0x000040a4, 0x00a0c9c9},
441 {0x00007020, 0x00000000},
442 {0x00007034, 0x00000002},
443 {0x00007038, 0x000004c2},
444};
445
446static const u32 ar9565_1p0_soc_postamble[][5] = {
447 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
448 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233},
449};
450
451static const u32 ar9565_1p0_Common_rx_gain_table[][2] = {
452 /* Addr allmodes */
453 {0x0000a000, 0x00010000},
454 {0x0000a004, 0x00030002},
455 {0x0000a008, 0x00050004},
456 {0x0000a00c, 0x00810080},
457 {0x0000a010, 0x00830082},
458 {0x0000a014, 0x01810180},
459 {0x0000a018, 0x01830182},
460 {0x0000a01c, 0x01850184},
461 {0x0000a020, 0x01890188},
462 {0x0000a024, 0x018b018a},
463 {0x0000a028, 0x018d018c},
464 {0x0000a02c, 0x01910190},
465 {0x0000a030, 0x01930192},
466 {0x0000a034, 0x01950194},
467 {0x0000a038, 0x038a0196},
468 {0x0000a03c, 0x038c038b},
469 {0x0000a040, 0x0390038d},
470 {0x0000a044, 0x03920391},
471 {0x0000a048, 0x03940393},
472 {0x0000a04c, 0x03960395},
473 {0x0000a050, 0x00000000},
474 {0x0000a054, 0x00000000},
475 {0x0000a058, 0x00000000},
476 {0x0000a05c, 0x00000000},
477 {0x0000a060, 0x00000000},
478 {0x0000a064, 0x00000000},
479 {0x0000a068, 0x00000000},
480 {0x0000a06c, 0x00000000},
481 {0x0000a070, 0x00000000},
482 {0x0000a074, 0x00000000},
483 {0x0000a078, 0x00000000},
484 {0x0000a07c, 0x00000000},
485 {0x0000a080, 0x22222229},
486 {0x0000a084, 0x1d1d1d1d},
487 {0x0000a088, 0x1d1d1d1d},
488 {0x0000a08c, 0x1d1d1d1d},
489 {0x0000a090, 0x171d1d1d},
490 {0x0000a094, 0x11111717},
491 {0x0000a098, 0x00030311},
492 {0x0000a09c, 0x00000000},
493 {0x0000a0a0, 0x00000000},
494 {0x0000a0a4, 0x00000000},
495 {0x0000a0a8, 0x00000000},
496 {0x0000a0ac, 0x00000000},
497 {0x0000a0b0, 0x00000000},
498 {0x0000a0b4, 0x00000000},
499 {0x0000a0b8, 0x00000000},
500 {0x0000a0bc, 0x00000000},
501 {0x0000a0c0, 0x001f0000},
502 {0x0000a0c4, 0x01000101},
503 {0x0000a0c8, 0x011e011f},
504 {0x0000a0cc, 0x011c011d},
505 {0x0000a0d0, 0x02030204},
506 {0x0000a0d4, 0x02010202},
507 {0x0000a0d8, 0x021f0200},
508 {0x0000a0dc, 0x0302021e},
509 {0x0000a0e0, 0x03000301},
510 {0x0000a0e4, 0x031e031f},
511 {0x0000a0e8, 0x0402031d},
512 {0x0000a0ec, 0x04000401},
513 {0x0000a0f0, 0x041e041f},
514 {0x0000a0f4, 0x0502041d},
515 {0x0000a0f8, 0x05000501},
516 {0x0000a0fc, 0x051e051f},
517 {0x0000a100, 0x06010602},
518 {0x0000a104, 0x061f0600},
519 {0x0000a108, 0x061d061e},
520 {0x0000a10c, 0x07020703},
521 {0x0000a110, 0x07000701},
522 {0x0000a114, 0x00000000},
523 {0x0000a118, 0x00000000},
524 {0x0000a11c, 0x00000000},
525 {0x0000a120, 0x00000000},
526 {0x0000a124, 0x00000000},
527 {0x0000a128, 0x00000000},
528 {0x0000a12c, 0x00000000},
529 {0x0000a130, 0x00000000},
530 {0x0000a134, 0x00000000},
531 {0x0000a138, 0x00000000},
532 {0x0000a13c, 0x00000000},
533 {0x0000a140, 0x001f0000},
534 {0x0000a144, 0x01000101},
535 {0x0000a148, 0x011e011f},
536 {0x0000a14c, 0x011c011d},
537 {0x0000a150, 0x02030204},
538 {0x0000a154, 0x02010202},
539 {0x0000a158, 0x021f0200},
540 {0x0000a15c, 0x0302021e},
541 {0x0000a160, 0x03000301},
542 {0x0000a164, 0x031e031f},
543 {0x0000a168, 0x0402031d},
544 {0x0000a16c, 0x04000401},
545 {0x0000a170, 0x041e041f},
546 {0x0000a174, 0x0502041d},
547 {0x0000a178, 0x05000501},
548 {0x0000a17c, 0x051e051f},
549 {0x0000a180, 0x06010602},
550 {0x0000a184, 0x061f0600},
551 {0x0000a188, 0x061d061e},
552 {0x0000a18c, 0x07020703},
553 {0x0000a190, 0x07000701},
554 {0x0000a194, 0x00000000},
555 {0x0000a198, 0x00000000},
556 {0x0000a19c, 0x00000000},
557 {0x0000a1a0, 0x00000000},
558 {0x0000a1a4, 0x00000000},
559 {0x0000a1a8, 0x00000000},
560 {0x0000a1ac, 0x00000000},
561 {0x0000a1b0, 0x00000000},
562 {0x0000a1b4, 0x00000000},
563 {0x0000a1b8, 0x00000000},
564 {0x0000a1bc, 0x00000000},
565 {0x0000a1c0, 0x00000000},
566 {0x0000a1c4, 0x00000000},
567 {0x0000a1c8, 0x00000000},
568 {0x0000a1cc, 0x00000000},
569 {0x0000a1d0, 0x00000000},
570 {0x0000a1d4, 0x00000000},
571 {0x0000a1d8, 0x00000000},
572 {0x0000a1dc, 0x00000000},
573 {0x0000a1e0, 0x00000000},
574 {0x0000a1e4, 0x00000000},
575 {0x0000a1e8, 0x00000000},
576 {0x0000a1ec, 0x00000000},
577 {0x0000a1f0, 0x00000396},
578 {0x0000a1f4, 0x00000396},
579 {0x0000a1f8, 0x00000396},
580 {0x0000a1fc, 0x00000196},
581 {0x0000b000, 0x00010000},
582 {0x0000b004, 0x00030002},
583 {0x0000b008, 0x00050004},
584 {0x0000b00c, 0x00810080},
585 {0x0000b010, 0x00830082},
586 {0x0000b014, 0x01810180},
587 {0x0000b018, 0x01830182},
588 {0x0000b01c, 0x01850184},
589 {0x0000b020, 0x02810280},
590 {0x0000b024, 0x02830282},
591 {0x0000b028, 0x02850284},
592 {0x0000b02c, 0x02890288},
593 {0x0000b030, 0x028b028a},
594 {0x0000b034, 0x0388028c},
595 {0x0000b038, 0x038a0389},
596 {0x0000b03c, 0x038c038b},
597 {0x0000b040, 0x0390038d},
598 {0x0000b044, 0x03920391},
599 {0x0000b048, 0x03940393},
600 {0x0000b04c, 0x03960395},
601 {0x0000b050, 0x00000000},
602 {0x0000b054, 0x00000000},
603 {0x0000b058, 0x00000000},
604 {0x0000b05c, 0x00000000},
605 {0x0000b060, 0x00000000},
606 {0x0000b064, 0x00000000},
607 {0x0000b068, 0x00000000},
608 {0x0000b06c, 0x00000000},
609 {0x0000b070, 0x00000000},
610 {0x0000b074, 0x00000000},
611 {0x0000b078, 0x00000000},
612 {0x0000b07c, 0x00000000},
613 {0x0000b080, 0x32323232},
614 {0x0000b084, 0x2f2f3232},
615 {0x0000b088, 0x23282a2d},
616 {0x0000b08c, 0x1c1e2123},
617 {0x0000b090, 0x14171919},
618 {0x0000b094, 0x0e0e1214},
619 {0x0000b098, 0x03050707},
620 {0x0000b09c, 0x00030303},
621 {0x0000b0a0, 0x00000000},
622 {0x0000b0a4, 0x00000000},
623 {0x0000b0a8, 0x00000000},
624 {0x0000b0ac, 0x00000000},
625 {0x0000b0b0, 0x00000000},
626 {0x0000b0b4, 0x00000000},
627 {0x0000b0b8, 0x00000000},
628 {0x0000b0bc, 0x00000000},
629 {0x0000b0c0, 0x003f0020},
630 {0x0000b0c4, 0x00400041},
631 {0x0000b0c8, 0x0140005f},
632 {0x0000b0cc, 0x0160015f},
633 {0x0000b0d0, 0x017e017f},
634 {0x0000b0d4, 0x02410242},
635 {0x0000b0d8, 0x025f0240},
636 {0x0000b0dc, 0x027f0260},
637 {0x0000b0e0, 0x0341027e},
638 {0x0000b0e4, 0x035f0340},
639 {0x0000b0e8, 0x037f0360},
640 {0x0000b0ec, 0x04400441},
641 {0x0000b0f0, 0x0460045f},
642 {0x0000b0f4, 0x0541047f},
643 {0x0000b0f8, 0x055f0540},
644 {0x0000b0fc, 0x057f0560},
645 {0x0000b100, 0x06400641},
646 {0x0000b104, 0x0660065f},
647 {0x0000b108, 0x067e067f},
648 {0x0000b10c, 0x07410742},
649 {0x0000b110, 0x075f0740},
650 {0x0000b114, 0x077f0760},
651 {0x0000b118, 0x07800781},
652 {0x0000b11c, 0x07a0079f},
653 {0x0000b120, 0x07c107bf},
654 {0x0000b124, 0x000007c0},
655 {0x0000b128, 0x00000000},
656 {0x0000b12c, 0x00000000},
657 {0x0000b130, 0x00000000},
658 {0x0000b134, 0x00000000},
659 {0x0000b138, 0x00000000},
660 {0x0000b13c, 0x00000000},
661 {0x0000b140, 0x003f0020},
662 {0x0000b144, 0x00400041},
663 {0x0000b148, 0x0140005f},
664 {0x0000b14c, 0x0160015f},
665 {0x0000b150, 0x017e017f},
666 {0x0000b154, 0x02410242},
667 {0x0000b158, 0x025f0240},
668 {0x0000b15c, 0x027f0260},
669 {0x0000b160, 0x0341027e},
670 {0x0000b164, 0x035f0340},
671 {0x0000b168, 0x037f0360},
672 {0x0000b16c, 0x04400441},
673 {0x0000b170, 0x0460045f},
674 {0x0000b174, 0x0541047f},
675 {0x0000b178, 0x055f0540},
676 {0x0000b17c, 0x057f0560},
677 {0x0000b180, 0x06400641},
678 {0x0000b184, 0x0660065f},
679 {0x0000b188, 0x067e067f},
680 {0x0000b18c, 0x07410742},
681 {0x0000b190, 0x075f0740},
682 {0x0000b194, 0x077f0760},
683 {0x0000b198, 0x07800781},
684 {0x0000b19c, 0x07a0079f},
685 {0x0000b1a0, 0x07c107bf},
686 {0x0000b1a4, 0x000007c0},
687 {0x0000b1a8, 0x00000000},
688 {0x0000b1ac, 0x00000000},
689 {0x0000b1b0, 0x00000000},
690 {0x0000b1b4, 0x00000000},
691 {0x0000b1b8, 0x00000000},
692 {0x0000b1bc, 0x00000000},
693 {0x0000b1c0, 0x00000000},
694 {0x0000b1c4, 0x00000000},
695 {0x0000b1c8, 0x00000000},
696 {0x0000b1cc, 0x00000000},
697 {0x0000b1d0, 0x00000000},
698 {0x0000b1d4, 0x00000000},
699 {0x0000b1d8, 0x00000000},
700 {0x0000b1dc, 0x00000000},
701 {0x0000b1e0, 0x00000000},
702 {0x0000b1e4, 0x00000000},
703 {0x0000b1e8, 0x00000000},
704 {0x0000b1ec, 0x00000000},
705 {0x0000b1f0, 0x00000396},
706 {0x0000b1f4, 0x00000396},
707 {0x0000b1f8, 0x00000396},
708 {0x0000b1fc, 0x00000196},
709};
710
711static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = {
712 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
713 {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
714 {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
715 {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
716 {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
717 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
718 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
719 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
720 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
721 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
722 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
723 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
724 {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
725 {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
726 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
727 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
728 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
729 {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
730 {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
731 {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
732 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
733 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
734 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
735 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
736 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
737 {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
738 {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
739 {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
740 {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
741 {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
742 {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
743 {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
744 {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
745 {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
746 {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
747 {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
748 {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
749 {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
750 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
751 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
752 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
753 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
754 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
755 {0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
756 {0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
757 {0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
758 {0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
759 {0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
760 {0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
761 {0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
762 {0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
763 {0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
764 {0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
765 {0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
766 {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
767 {0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
768 {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
769};
770
771static const u32 ar9565_1p0_pciephy_pll_on_clkreq_disable_L1[][2] = {
772 /* Addr allmodes */
773 {0x00018c00, 0x18212ede},
774 {0x00018c04, 0x000801d8},
775 {0x00018c08, 0x0003780c},
776};
777
778static const u32 ar9565_1p0_modes_fast_clock[][3] = {
779 /* Addr 5G_HT20 5G_HT40 */
780 {0x00001030, 0x00000268, 0x000004d0},
781 {0x00001070, 0x0000018c, 0x00000318},
782 {0x000010b0, 0x00000fd0, 0x00001fa0},
783 {0x00008014, 0x044c044c, 0x08980898},
784 {0x0000801c, 0x148ec02b, 0x148ec057},
785 {0x00008318, 0x000044c0, 0x00008980},
786 {0x00009e00, 0x03721821, 0x03721821},
787 {0x0000a230, 0x0000400b, 0x00004016},
788 {0x0000a254, 0x00000898, 0x00001130},
789};
790
791static const u32 ar9565_1p0_common_wo_xlna_rx_gain_table[][2] = {
792 /* Addr allmodes */
793 {0x0000a000, 0x00010000},
794 {0x0000a004, 0x00030002},
795 {0x0000a008, 0x00050004},
796 {0x0000a00c, 0x00810080},
797 {0x0000a010, 0x00830082},
798 {0x0000a014, 0x01810180},
799 {0x0000a018, 0x01830182},
800 {0x0000a01c, 0x01850184},
801 {0x0000a020, 0x01890188},
802 {0x0000a024, 0x018b018a},
803 {0x0000a028, 0x018d018c},
804 {0x0000a02c, 0x03820190},
805 {0x0000a030, 0x03840383},
806 {0x0000a034, 0x03880385},
807 {0x0000a038, 0x038a0389},
808 {0x0000a03c, 0x038c038b},
809 {0x0000a040, 0x0390038d},
810 {0x0000a044, 0x03920391},
811 {0x0000a048, 0x03940393},
812 {0x0000a04c, 0x03960395},
813 {0x0000a050, 0x00000000},
814 {0x0000a054, 0x00000000},
815 {0x0000a058, 0x00000000},
816 {0x0000a05c, 0x00000000},
817 {0x0000a060, 0x00000000},
818 {0x0000a064, 0x00000000},
819 {0x0000a068, 0x00000000},
820 {0x0000a06c, 0x00000000},
821 {0x0000a070, 0x00000000},
822 {0x0000a074, 0x00000000},
823 {0x0000a078, 0x00000000},
824 {0x0000a07c, 0x00000000},
825 {0x0000a080, 0x29292929},
826 {0x0000a084, 0x29292929},
827 {0x0000a088, 0x29292929},
828 {0x0000a08c, 0x29292929},
829 {0x0000a090, 0x22292929},
830 {0x0000a094, 0x1d1d2222},
831 {0x0000a098, 0x0c111117},
832 {0x0000a09c, 0x00030303},
833 {0x0000a0a0, 0x00000000},
834 {0x0000a0a4, 0x00000000},
835 {0x0000a0a8, 0x00000000},
836 {0x0000a0ac, 0x00000000},
837 {0x0000a0b0, 0x00000000},
838 {0x0000a0b4, 0x00000000},
839 {0x0000a0b8, 0x00000000},
840 {0x0000a0bc, 0x00000000},
841 {0x0000a0c0, 0x00bf00a0},
842 {0x0000a0c4, 0x11a011a1},
843 {0x0000a0c8, 0x11be11bf},
844 {0x0000a0cc, 0x11bc11bd},
845 {0x0000a0d0, 0x22632264},
846 {0x0000a0d4, 0x22612262},
847 {0x0000a0d8, 0x227f2260},
848 {0x0000a0dc, 0x4322227e},
849 {0x0000a0e0, 0x43204321},
850 {0x0000a0e4, 0x433e433f},
851 {0x0000a0e8, 0x4462433d},
852 {0x0000a0ec, 0x44604461},
853 {0x0000a0f0, 0x447e447f},
854 {0x0000a0f4, 0x5582447d},
855 {0x0000a0f8, 0x55805581},
856 {0x0000a0fc, 0x559e559f},
857 {0x0000a100, 0x66816682},
858 {0x0000a104, 0x669f6680},
859 {0x0000a108, 0x669d669e},
860 {0x0000a10c, 0x77627763},
861 {0x0000a110, 0x77607761},
862 {0x0000a114, 0x00000000},
863 {0x0000a118, 0x00000000},
864 {0x0000a11c, 0x00000000},
865 {0x0000a120, 0x00000000},
866 {0x0000a124, 0x00000000},
867 {0x0000a128, 0x00000000},
868 {0x0000a12c, 0x00000000},
869 {0x0000a130, 0x00000000},
870 {0x0000a134, 0x00000000},
871 {0x0000a138, 0x00000000},
872 {0x0000a13c, 0x00000000},
873 {0x0000a140, 0x00bf00a0},
874 {0x0000a144, 0x11a011a1},
875 {0x0000a148, 0x11be11bf},
876 {0x0000a14c, 0x11bc11bd},
877 {0x0000a150, 0x22632264},
878 {0x0000a154, 0x22612262},
879 {0x0000a158, 0x227f2260},
880 {0x0000a15c, 0x4322227e},
881 {0x0000a160, 0x43204321},
882 {0x0000a164, 0x433e433f},
883 {0x0000a168, 0x4462433d},
884 {0x0000a16c, 0x44604461},
885 {0x0000a170, 0x447e447f},
886 {0x0000a174, 0x5582447d},
887 {0x0000a178, 0x55805581},
888 {0x0000a17c, 0x559e559f},
889 {0x0000a180, 0x66816682},
890 {0x0000a184, 0x669f6680},
891 {0x0000a188, 0x669d669e},
892 {0x0000a18c, 0x77627763},
893 {0x0000a190, 0x77607761},
894 {0x0000a194, 0x00000000},
895 {0x0000a198, 0x00000000},
896 {0x0000a19c, 0x00000000},
897 {0x0000a1a0, 0x00000000},
898 {0x0000a1a4, 0x00000000},
899 {0x0000a1a8, 0x00000000},
900 {0x0000a1ac, 0x00000000},
901 {0x0000a1b0, 0x00000000},
902 {0x0000a1b4, 0x00000000},
903 {0x0000a1b8, 0x00000000},
904 {0x0000a1bc, 0x00000000},
905 {0x0000a1c0, 0x00000000},
906 {0x0000a1c4, 0x00000000},
907 {0x0000a1c8, 0x00000000},
908 {0x0000a1cc, 0x00000000},
909 {0x0000a1d0, 0x00000000},
910 {0x0000a1d4, 0x00000000},
911 {0x0000a1d8, 0x00000000},
912 {0x0000a1dc, 0x00000000},
913 {0x0000a1e0, 0x00000000},
914 {0x0000a1e4, 0x00000000},
915 {0x0000a1e8, 0x00000000},
916 {0x0000a1ec, 0x00000000},
917 {0x0000a1f0, 0x00000396},
918 {0x0000a1f4, 0x00000396},
919 {0x0000a1f8, 0x00000396},
920 {0x0000a1fc, 0x00000196},
921 {0x0000b000, 0x00010000},
922 {0x0000b004, 0x00030002},
923 {0x0000b008, 0x00050004},
924 {0x0000b00c, 0x00810080},
925 {0x0000b010, 0x00830082},
926 {0x0000b014, 0x01810180},
927 {0x0000b018, 0x01830182},
928 {0x0000b01c, 0x01850184},
929 {0x0000b020, 0x02810280},
930 {0x0000b024, 0x02830282},
931 {0x0000b028, 0x02850284},
932 {0x0000b02c, 0x02890288},
933 {0x0000b030, 0x028b028a},
934 {0x0000b034, 0x0388028c},
935 {0x0000b038, 0x038a0389},
936 {0x0000b03c, 0x038c038b},
937 {0x0000b040, 0x0390038d},
938 {0x0000b044, 0x03920391},
939 {0x0000b048, 0x03940393},
940 {0x0000b04c, 0x03960395},
941 {0x0000b050, 0x00000000},
942 {0x0000b054, 0x00000000},
943 {0x0000b058, 0x00000000},
944 {0x0000b05c, 0x00000000},
945 {0x0000b060, 0x00000000},
946 {0x0000b064, 0x00000000},
947 {0x0000b068, 0x00000000},
948 {0x0000b06c, 0x00000000},
949 {0x0000b070, 0x00000000},
950 {0x0000b074, 0x00000000},
951 {0x0000b078, 0x00000000},
952 {0x0000b07c, 0x00000000},
953 {0x0000b080, 0x32323232},
954 {0x0000b084, 0x2f2f3232},
955 {0x0000b088, 0x23282a2d},
956 {0x0000b08c, 0x1c1e2123},
957 {0x0000b090, 0x14171919},
958 {0x0000b094, 0x0e0e1214},
959 {0x0000b098, 0x03050707},
960 {0x0000b09c, 0x00030303},
961 {0x0000b0a0, 0x00000000},
962 {0x0000b0a4, 0x00000000},
963 {0x0000b0a8, 0x00000000},
964 {0x0000b0ac, 0x00000000},
965 {0x0000b0b0, 0x00000000},
966 {0x0000b0b4, 0x00000000},
967 {0x0000b0b8, 0x00000000},
968 {0x0000b0bc, 0x00000000},
969 {0x0000b0c0, 0x003f0020},
970 {0x0000b0c4, 0x00400041},
971 {0x0000b0c8, 0x0140005f},
972 {0x0000b0cc, 0x0160015f},
973 {0x0000b0d0, 0x017e017f},
974 {0x0000b0d4, 0x02410242},
975 {0x0000b0d8, 0x025f0240},
976 {0x0000b0dc, 0x027f0260},
977 {0x0000b0e0, 0x0341027e},
978 {0x0000b0e4, 0x035f0340},
979 {0x0000b0e8, 0x037f0360},
980 {0x0000b0ec, 0x04400441},
981 {0x0000b0f0, 0x0460045f},
982 {0x0000b0f4, 0x0541047f},
983 {0x0000b0f8, 0x055f0540},
984 {0x0000b0fc, 0x057f0560},
985 {0x0000b100, 0x06400641},
986 {0x0000b104, 0x0660065f},
987 {0x0000b108, 0x067e067f},
988 {0x0000b10c, 0x07410742},
989 {0x0000b110, 0x075f0740},
990 {0x0000b114, 0x077f0760},
991 {0x0000b118, 0x07800781},
992 {0x0000b11c, 0x07a0079f},
993 {0x0000b120, 0x07c107bf},
994 {0x0000b124, 0x000007c0},
995 {0x0000b128, 0x00000000},
996 {0x0000b12c, 0x00000000},
997 {0x0000b130, 0x00000000},
998 {0x0000b134, 0x00000000},
999 {0x0000b138, 0x00000000},
1000 {0x0000b13c, 0x00000000},
1001 {0x0000b140, 0x003f0020},
1002 {0x0000b144, 0x00400041},
1003 {0x0000b148, 0x0140005f},
1004 {0x0000b14c, 0x0160015f},
1005 {0x0000b150, 0x017e017f},
1006 {0x0000b154, 0x02410242},
1007 {0x0000b158, 0x025f0240},
1008 {0x0000b15c, 0x027f0260},
1009 {0x0000b160, 0x0341027e},
1010 {0x0000b164, 0x035f0340},
1011 {0x0000b168, 0x037f0360},
1012 {0x0000b16c, 0x04400441},
1013 {0x0000b170, 0x0460045f},
1014 {0x0000b174, 0x0541047f},
1015 {0x0000b178, 0x055f0540},
1016 {0x0000b17c, 0x057f0560},
1017 {0x0000b180, 0x06400641},
1018 {0x0000b184, 0x0660065f},
1019 {0x0000b188, 0x067e067f},
1020 {0x0000b18c, 0x07410742},
1021 {0x0000b190, 0x075f0740},
1022 {0x0000b194, 0x077f0760},
1023 {0x0000b198, 0x07800781},
1024 {0x0000b19c, 0x07a0079f},
1025 {0x0000b1a0, 0x07c107bf},
1026 {0x0000b1a4, 0x000007c0},
1027 {0x0000b1a8, 0x00000000},
1028 {0x0000b1ac, 0x00000000},
1029 {0x0000b1b0, 0x00000000},
1030 {0x0000b1b4, 0x00000000},
1031 {0x0000b1b8, 0x00000000},
1032 {0x0000b1bc, 0x00000000},
1033 {0x0000b1c0, 0x00000000},
1034 {0x0000b1c4, 0x00000000},
1035 {0x0000b1c8, 0x00000000},
1036 {0x0000b1cc, 0x00000000},
1037 {0x0000b1d0, 0x00000000},
1038 {0x0000b1d4, 0x00000000},
1039 {0x0000b1d8, 0x00000000},
1040 {0x0000b1dc, 0x00000000},
1041 {0x0000b1e0, 0x00000000},
1042 {0x0000b1e4, 0x00000000},
1043 {0x0000b1e8, 0x00000000},
1044 {0x0000b1ec, 0x00000000},
1045 {0x0000b1f0, 0x00000396},
1046 {0x0000b1f4, 0x00000396},
1047 {0x0000b1f8, 0x00000396},
1048 {0x0000b1fc, 0x00000196},
1049};
1050
1051static const u32 ar9565_1p0_modes_low_ob_db_tx_gain_table[][5] = {
1052 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1053 {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
1054 {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
1055 {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
1056 {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
1057 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
1058 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1059 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
1060 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
1061 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
1062 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
1063 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
1064 {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
1065 {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
1066 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
1067 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
1068 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
1069 {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
1070 {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
1071 {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
1072 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
1073 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
1074 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
1075 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
1076 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
1077 {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
1078 {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
1079 {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
1080 {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
1081 {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
1082 {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
1083 {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1084 {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1085 {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1086 {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1087 {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1088 {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1089 {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1090 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1091 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1092 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1093 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1094 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1095 {0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1096 {0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1097 {0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1098 {0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1099 {0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1100 {0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1101 {0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1102 {0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1103 {0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1104 {0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1105 {0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1106 {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
1107 {0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1108 {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1109};
1110
1111static const u32 ar9565_1p0_modes_high_ob_db_tx_gain_table[][5] = {
1112 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1113 {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
1114 {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
1115 {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
1116 {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
1117 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
1118 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
1119 {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
1120 {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
1121 {0x0000a50c, 0x10022223, 0x10022223, 0x0c000200, 0x0c000200},
1122 {0x0000a510, 0x15022620, 0x15022620, 0x10000202, 0x10000202},
1123 {0x0000a514, 0x19022622, 0x19022622, 0x13000400, 0x13000400},
1124 {0x0000a518, 0x1c022822, 0x1c022822, 0x17000402, 0x17000402},
1125 {0x0000a51c, 0x21022842, 0x21022842, 0x1b000404, 0x1b000404},
1126 {0x0000a520, 0x24022c41, 0x24022c41, 0x1e000603, 0x1e000603},
1127 {0x0000a524, 0x29023042, 0x29023042, 0x23000a02, 0x23000a02},
1128 {0x0000a528, 0x2d023044, 0x2d023044, 0x27000a04, 0x27000a04},
1129 {0x0000a52c, 0x31023644, 0x31023644, 0x2a000a20, 0x2a000a20},
1130 {0x0000a530, 0x36025643, 0x36025643, 0x2e000e20, 0x2e000e20},
1131 {0x0000a534, 0x3a025a44, 0x3a025a44, 0x32000e22, 0x32000e22},
1132 {0x0000a538, 0x3d025e45, 0x3d025e45, 0x36000e24, 0x36000e24},
1133 {0x0000a53c, 0x43025e4a, 0x43025e4a, 0x3a001640, 0x3a001640},
1134 {0x0000a540, 0x4a025e6c, 0x4a025e6c, 0x3e001660, 0x3e001660},
1135 {0x0000a544, 0x50025e8e, 0x50025e8e, 0x41001861, 0x41001861},
1136 {0x0000a548, 0x56025eb2, 0x56025eb2, 0x45001a81, 0x45001a81},
1137 {0x0000a54c, 0x5c025eb5, 0x5c025eb5, 0x49001a83, 0x49001a83},
1138 {0x0000a550, 0x62025ef6, 0x62025ef6, 0x4c001c84, 0x4c001c84},
1139 {0x0000a554, 0x65025f56, 0x65025f56, 0x4f001ce3, 0x4f001ce3},
1140 {0x0000a558, 0x69027f56, 0x69027f56, 0x53001ce5, 0x53001ce5},
1141 {0x0000a55c, 0x6d029f56, 0x6d029f56, 0x57001ce9, 0x57001ce9},
1142 {0x0000a560, 0x73049f56, 0x73049f56, 0x5b001ceb, 0x5b001ceb},
1143 {0x0000a564, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},
1144 {0x0000a568, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},
1145 {0x0000a56c, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},
1146 {0x0000a570, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},
1147 {0x0000a574, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},
1148 {0x0000a578, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},
1149 {0x0000a57c, 0x7804ff56, 0x7804ff56, 0x5d001eec, 0x5d001eec},
1150 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1151 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1152 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1153 {0x0000a60c, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
1154 {0x0000a610, 0x00804201, 0x00804201, 0x00000000, 0x00000000},
1155 {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
1156 {0x0000a618, 0x00804201, 0x00804201, 0x01404501, 0x01404501},
1157 {0x0000a61c, 0x02008201, 0x02008201, 0x02008501, 0x02008501},
1158 {0x0000a620, 0x02c10a03, 0x02c10a03, 0x0280ca03, 0x0280ca03},
1159 {0x0000a624, 0x04815205, 0x04815205, 0x02c10b04, 0x02c10b04},
1160 {0x0000a628, 0x0581d406, 0x0581d406, 0x03814b04, 0x03814b04},
1161 {0x0000a62c, 0x0581d607, 0x0581d607, 0x05018e05, 0x05018e05},
1162 {0x0000a630, 0x0581d607, 0x0581d607, 0x05019406, 0x05019406},
1163 {0x0000a634, 0x0581d607, 0x0581d607, 0x05019406, 0x05019406},
1164 {0x0000a638, 0x0581d607, 0x0581d607, 0x05019406, 0x05019406},
1165 {0x0000a63c, 0x0581d607, 0x0581d607, 0x05019406, 0x05019406},
1166 {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
1167 {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060},
1168 {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
1169};
1170
1171static const u32 ar9565_1p0_modes_high_power_tx_gain_table[][5] = {
1172 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1173 {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
1174 {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
1175 {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
1176 {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
1177 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
1178 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
1179 {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
1180 {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
1181 {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
1182 {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
1183 {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
1184 {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
1185 {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
1186 {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
1187 {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
1188 {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
1189 {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
1190 {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
1191 {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
1192 {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
1193 {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
1194 {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
1195 {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
1196 {0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81},
1197 {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
1198 {0x0000a550, 0x5f025ef6, 0x5f025ef6, 0x44001c84, 0x44001c84},
1199 {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
1200 {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
1201 {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
1202 {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
1203 {0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
1204 {0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
1205 {0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
1206 {0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
1207 {0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
1208 {0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
1209 {0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
1210 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1211 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1212 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1213 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1214 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1215 {0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1216 {0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1217 {0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1218 {0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1219 {0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1220 {0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1221 {0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1222 {0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1223 {0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1224 {0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1225 {0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1226 {0x00016044, 0x056d82e6, 0x056d82e6, 0x056d82e6, 0x056d82e6},
1227 {0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1228 {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1229};
1230
1231#endif /* INITVALS_9565_1P0_H */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index b09285c36c4a..dfe6a4707fd2 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -173,6 +173,8 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
173 173
174#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 174#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
175 175
176#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
177
176#define ATH_TX_COMPLETE_POLL_INT 1000 178#define ATH_TX_COMPLETE_POLL_INT 1000
177 179
178enum ATH_AGGR_STATUS { 180enum ATH_AGGR_STATUS {
@@ -280,6 +282,7 @@ struct ath_tx_control {
280 struct ath_txq *txq; 282 struct ath_txq *txq;
281 struct ath_node *an; 283 struct ath_node *an;
282 u8 paprd; 284 u8 paprd;
285 struct ieee80211_sta *sta;
283}; 286};
284 287
285#define ATH_TX_ERROR 0x01 288#define ATH_TX_ERROR 0x01
@@ -422,7 +425,6 @@ void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
422void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 425void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
423void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif); 426void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
424void ath9k_set_beacon(struct ath_softc *sc); 427void ath9k_set_beacon(struct ath_softc *sc);
425void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
426 428
427/*******************/ 429/*******************/
428/* Link Monitoring */ 430/* Link Monitoring */
@@ -472,7 +474,7 @@ struct ath_btcoex {
472 unsigned long op_flags; 474 unsigned long op_flags;
473 int bt_stomp_type; /* Types of BT stomping */ 475 int bt_stomp_type; /* Types of BT stomping */
474 u32 btcoex_no_stomp; /* in usec */ 476 u32 btcoex_no_stomp; /* in usec */
475 u32 btcoex_period; /* in usec */ 477 u32 btcoex_period; /* in msec */
476 u32 btscan_no_stomp; /* in usec */ 478 u32 btscan_no_stomp; /* in usec */
477 u32 duty_cycle; 479 u32 duty_cycle;
478 u32 bt_wait_time; 480 u32 bt_wait_time;
@@ -537,6 +539,7 @@ struct ath9k_wow_pattern {
537#ifdef CONFIG_MAC80211_LEDS 539#ifdef CONFIG_MAC80211_LEDS
538void ath_init_leds(struct ath_softc *sc); 540void ath_init_leds(struct ath_softc *sc);
539void ath_deinit_leds(struct ath_softc *sc); 541void ath_deinit_leds(struct ath_softc *sc);
542void ath_fill_led_pin(struct ath_softc *sc);
540#else 543#else
541static inline void ath_init_leds(struct ath_softc *sc) 544static inline void ath_init_leds(struct ath_softc *sc)
542{ 545{
@@ -545,6 +548,9 @@ static inline void ath_init_leds(struct ath_softc *sc)
545static inline void ath_deinit_leds(struct ath_softc *sc) 548static inline void ath_deinit_leds(struct ath_softc *sc)
546{ 549{
547} 550}
551static inline void ath_fill_led_pin(struct ath_softc *sc)
552{
553}
548#endif 554#endif
549 555
550/*******************************/ 556/*******************************/
@@ -596,8 +602,6 @@ struct ath_ant_comb {
596 int main_conf; 602 int main_conf;
597 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 603 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
598 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 604 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
599 int first_bias;
600 int second_bias;
601 bool first_ratio; 605 bool first_ratio;
602 bool second_ratio; 606 bool second_ratio;
603 unsigned long scan_start_time; 607 unsigned long scan_start_time;
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index acd437384fe4..419e9a3f2fed 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -43,8 +43,8 @@ static const u32 ar9003_wlan_weights[ATH_BTCOEX_STOMP_MAX]
43 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */ 43 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */
44}; 44};
45 45
46static const u32 ar9462_wlan_weights[ATH_BTCOEX_STOMP_MAX] 46static const u32 mci_wlan_weights[ATH_BTCOEX_STOMP_MAX]
47 [AR9300_NUM_WLAN_WEIGHTS] = { 47 [AR9300_NUM_WLAN_WEIGHTS] = {
48 { 0x01017d01, 0x41414101, 0x41414101, 0x41414141 }, /* STOMP_ALL */ 48 { 0x01017d01, 0x41414101, 0x41414101, 0x41414141 }, /* STOMP_ALL */
49 { 0x01017d01, 0x3b3b3b01, 0x3b3b3b01, 0x3b3b3b3b }, /* STOMP_LOW */ 49 { 0x01017d01, 0x3b3b3b01, 0x3b3b3b01, 0x3b3b3b3b }, /* STOMP_LOW */
50 { 0x01017d01, 0x01010101, 0x01010101, 0x01010101 }, /* STOMP_NONE */ 50 { 0x01017d01, 0x01010101, 0x01010101, 0x01010101 }, /* STOMP_NONE */
@@ -208,14 +208,37 @@ static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
208 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 208 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
209} 209}
210 210
211/*
212 * For AR9002, bt_weight/wlan_weight are used.
213 * For AR9003 and above, stomp_type is used.
214 */
211void ath9k_hw_btcoex_set_weight(struct ath_hw *ah, 215void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
212 u32 bt_weight, 216 u32 bt_weight,
213 u32 wlan_weight) 217 u32 wlan_weight,
218 enum ath_stomp_type stomp_type)
214{ 219{
215 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 220 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
216 221
217 btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) | 222 if (AR_SREV_9300_20_OR_LATER(ah)) {
218 SM(wlan_weight, AR_BTCOEX_WL_WGHT); 223 const u32 *weight = ar9003_wlan_weights[stomp_type];
224 int i;
225
226 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
227 if ((stomp_type == ATH_BTCOEX_STOMP_LOW) &&
228 btcoex_hw->mci.stomp_ftp)
229 stomp_type = ATH_BTCOEX_STOMP_LOW_FTP;
230 weight = mci_wlan_weights[stomp_type];
231 }
232
233 for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
234 btcoex_hw->bt_weight[i] = AR9300_BT_WGHT;
235 btcoex_hw->wlan_weight[i] = weight[i];
236 }
237 } else {
238 btcoex_hw->bt_coex_weights =
239 SM(bt_weight, AR_BTCOEX_BT_WGHT) |
240 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
241 }
219} 242}
220EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight); 243EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
221 244
@@ -282,7 +305,7 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah)
282 ath9k_hw_btcoex_enable_2wire(ah); 305 ath9k_hw_btcoex_enable_2wire(ah);
283 break; 306 break;
284 case ATH_BTCOEX_CFG_3WIRE: 307 case ATH_BTCOEX_CFG_3WIRE:
285 if (AR_SREV_9462(ah)) { 308 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
286 ath9k_hw_btcoex_enable_mci(ah); 309 ath9k_hw_btcoex_enable_mci(ah);
287 return; 310 return;
288 } 311 }
@@ -304,7 +327,7 @@ void ath9k_hw_btcoex_disable(struct ath_hw *ah)
304 int i; 327 int i;
305 328
306 btcoex_hw->enabled = false; 329 btcoex_hw->enabled = false;
307 if (AR_SREV_9462(ah)) { 330 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
308 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE); 331 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
309 for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++) 332 for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
310 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), 333 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
@@ -332,26 +355,6 @@ void ath9k_hw_btcoex_disable(struct ath_hw *ah)
332} 355}
333EXPORT_SYMBOL(ath9k_hw_btcoex_disable); 356EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
334 357
335static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,
336 enum ath_stomp_type stomp_type)
337{
338 struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
339 const u32 *weight = ar9003_wlan_weights[stomp_type];
340 int i;
341
342 if (AR_SREV_9462(ah)) {
343 if ((stomp_type == ATH_BTCOEX_STOMP_LOW) &&
344 btcoex->mci.stomp_ftp)
345 stomp_type = ATH_BTCOEX_STOMP_LOW_FTP;
346 weight = ar9462_wlan_weights[stomp_type];
347 }
348
349 for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
350 btcoex->bt_weight[i] = AR9300_BT_WGHT;
351 btcoex->wlan_weight[i] = weight[i];
352 }
353}
354
355/* 358/*
356 * Configures appropriate weight based on stomp type. 359 * Configures appropriate weight based on stomp type.
357 */ 360 */
@@ -359,22 +362,22 @@ void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
359 enum ath_stomp_type stomp_type) 362 enum ath_stomp_type stomp_type)
360{ 363{
361 if (AR_SREV_9300_20_OR_LATER(ah)) { 364 if (AR_SREV_9300_20_OR_LATER(ah)) {
362 ar9003_btcoex_bt_stomp(ah, stomp_type); 365 ath9k_hw_btcoex_set_weight(ah, 0, 0, stomp_type);
363 return; 366 return;
364 } 367 }
365 368
366 switch (stomp_type) { 369 switch (stomp_type) {
367 case ATH_BTCOEX_STOMP_ALL: 370 case ATH_BTCOEX_STOMP_ALL:
368 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, 371 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
369 AR_STOMP_ALL_WLAN_WGHT); 372 AR_STOMP_ALL_WLAN_WGHT, 0);
370 break; 373 break;
371 case ATH_BTCOEX_STOMP_LOW: 374 case ATH_BTCOEX_STOMP_LOW:
372 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, 375 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
373 AR_STOMP_LOW_WLAN_WGHT); 376 AR_STOMP_LOW_WLAN_WGHT, 0);
374 break; 377 break;
375 case ATH_BTCOEX_STOMP_NONE: 378 case ATH_BTCOEX_STOMP_NONE:
376 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, 379 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
377 AR_STOMP_NONE_WLAN_WGHT); 380 AR_STOMP_NONE_WLAN_WGHT, 0);
378 break; 381 break;
379 default: 382 default:
380 ath_dbg(ath9k_hw_common(ah), BTCOEX, "Invalid Stomptype\n"); 383 ath_dbg(ath9k_hw_common(ah), BTCOEX, "Invalid Stomptype\n");
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.h b/drivers/net/wireless/ath/ath9k/btcoex.h
index 20092f98658f..385197ad79b0 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.h
+++ b/drivers/net/wireless/ath/ath9k/btcoex.h
@@ -107,7 +107,8 @@ void ath9k_hw_btcoex_init_mci(struct ath_hw *ah);
107void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum); 107void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum);
108void ath9k_hw_btcoex_set_weight(struct ath_hw *ah, 108void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
109 u32 bt_weight, 109 u32 bt_weight,
110 u32 wlan_weight); 110 u32 wlan_weight,
111 enum ath_stomp_type stomp_type);
111void ath9k_hw_btcoex_disable(struct ath_hw *ah); 112void ath9k_hw_btcoex_disable(struct ath_hw *ah);
112void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah, 113void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
113 enum ath_stomp_type stomp_type); 114 enum ath_stomp_type stomp_type);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index c8ef30127adb..6727b566d294 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -222,6 +222,57 @@ static const struct file_operations fops_disable_ani = {
222 .llseek = default_llseek, 222 .llseek = default_llseek,
223}; 223};
224 224
225static ssize_t read_file_ant_diversity(struct file *file, char __user *user_buf,
226 size_t count, loff_t *ppos)
227{
228 struct ath_softc *sc = file->private_data;
229 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
230 char buf[32];
231 unsigned int len;
232
233 len = sprintf(buf, "%d\n", common->antenna_diversity);
234 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
235}
236
237static ssize_t write_file_ant_diversity(struct file *file,
238 const char __user *user_buf,
239 size_t count, loff_t *ppos)
240{
241 struct ath_softc *sc = file->private_data;
242 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
243 unsigned long antenna_diversity;
244 char buf[32];
245 ssize_t len;
246
247 len = min(count, sizeof(buf) - 1);
248 if (copy_from_user(buf, user_buf, len))
249 return -EFAULT;
250
251 if (!AR_SREV_9565(sc->sc_ah))
252 goto exit;
253
254 buf[len] = '\0';
255 if (strict_strtoul(buf, 0, &antenna_diversity))
256 return -EINVAL;
257
258 common->antenna_diversity = !!antenna_diversity;
259 ath9k_ps_wakeup(sc);
260 ath_ant_comb_update(sc);
261 ath_dbg(common, CONFIG, "Antenna diversity: %d\n",
262 common->antenna_diversity);
263 ath9k_ps_restore(sc);
264exit:
265 return count;
266}
267
268static const struct file_operations fops_ant_diversity = {
269 .read = read_file_ant_diversity,
270 .write = write_file_ant_diversity,
271 .open = simple_open,
272 .owner = THIS_MODULE,
273 .llseek = default_llseek,
274};
275
225static ssize_t read_file_dma(struct file *file, char __user *user_buf, 276static ssize_t read_file_dma(struct file *file, char __user *user_buf,
226 size_t count, loff_t *ppos) 277 size_t count, loff_t *ppos)
227{ 278{
@@ -373,6 +424,8 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
373 sc->debug.stats.istats.tsfoor++; 424 sc->debug.stats.istats.tsfoor++;
374 if (status & ATH9K_INT_MCI) 425 if (status & ATH9K_INT_MCI)
375 sc->debug.stats.istats.mci++; 426 sc->debug.stats.istats.mci++;
427 if (status & ATH9K_INT_GENTIMER)
428 sc->debug.stats.istats.gen_timer++;
376} 429}
377 430
378static ssize_t read_file_interrupt(struct file *file, char __user *user_buf, 431static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
@@ -418,6 +471,7 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
418 PR_IS("DTIM", dtim); 471 PR_IS("DTIM", dtim);
419 PR_IS("TSFOOR", tsfoor); 472 PR_IS("TSFOOR", tsfoor);
420 PR_IS("MCI", mci); 473 PR_IS("MCI", mci);
474 PR_IS("GENTIMER", gen_timer);
421 PR_IS("TOTAL", total); 475 PR_IS("TOTAL", total);
422 476
423 len += snprintf(buf + len, mxlen - len, 477 len += snprintf(buf + len, mxlen - len,
@@ -1598,12 +1652,12 @@ int ath9k_init_debug(struct ath_hw *ah)
1598 debugfs_create_file("samples", S_IRUSR, sc->debug.debugfs_phy, sc, 1652 debugfs_create_file("samples", S_IRUSR, sc->debug.debugfs_phy, sc,
1599 &fops_samps); 1653 &fops_samps);
1600#endif 1654#endif
1601
1602 debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR, 1655 debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
1603 sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask); 1656 sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
1604
1605 debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR, 1657 debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
1606 sc->debug.debugfs_phy, &sc->sc_ah->gpio_val); 1658 sc->debug.debugfs_phy, &sc->sc_ah->gpio_val);
1659 debugfs_create_file("diversity", S_IRUSR | S_IWUSR,
1660 sc->debug.debugfs_phy, sc, &fops_ant_diversity);
1607 1661
1608 return 0; 1662 return 0;
1609} 1663}
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index 8b9d080d89da..2ed9785a38fa 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -41,7 +41,6 @@ enum ath_reset_type {
41 RESET_TYPE_PLL_HANG, 41 RESET_TYPE_PLL_HANG,
42 RESET_TYPE_MAC_HANG, 42 RESET_TYPE_MAC_HANG,
43 RESET_TYPE_BEACON_STUCK, 43 RESET_TYPE_BEACON_STUCK,
44 RESET_TYPE_MCI,
45 __RESET_TYPE_MAX 44 __RESET_TYPE_MAX
46}; 45};
47 46
@@ -74,6 +73,8 @@ enum ath_reset_type {
74 * from a beacon differs from the PCU's internal TSF by more than a 73 * from a beacon differs from the PCU's internal TSF by more than a
75 * (programmable) threshold 74 * (programmable) threshold
76 * @local_timeout: Internal bus timeout. 75 * @local_timeout: Internal bus timeout.
76 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
77 * @gen_timer: Generic hardware timer interrupt
77 */ 78 */
78struct ath_interrupt_stats { 79struct ath_interrupt_stats {
79 u32 total; 80 u32 total;
@@ -100,6 +101,7 @@ struct ath_interrupt_stats {
100 u32 bb_watchdog; 101 u32 bb_watchdog;
101 u32 tsfoor; 102 u32 tsfoor;
102 u32 mci; 103 u32 mci;
104 u32 gen_timer;
103 105
104 /* Sync-cause stats */ 106 /* Sync-cause stats */
105 u32 sync_cause_all; 107 u32 sync_cause_all;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 484b31305906..319c651fa6c5 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -96,6 +96,7 @@
96 96
97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
99#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
99#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 100#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
100 101
101#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 102#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
@@ -108,7 +109,7 @@
108#define EEP_RFSILENT_ENABLED_S 0 109#define EEP_RFSILENT_ENABLED_S 0
109#define EEP_RFSILENT_POLARITY 0x0002 110#define EEP_RFSILENT_POLARITY 0x0002
110#define EEP_RFSILENT_POLARITY_S 1 111#define EEP_RFSILENT_POLARITY_S 1
111#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9462(ah) ? 0x00fc : 0x001c) 112#define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c)
112#define EEP_RFSILENT_GPIO_SEL_S 2 113#define EEP_RFSILENT_GPIO_SEL_S 2
113 114
114#define AR5416_OPFLAGS_11A 0x01 115#define AR5416_OPFLAGS_11A 0x01
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 9f83f71742a5..d9ed141a053e 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -44,25 +44,6 @@ void ath_init_leds(struct ath_softc *sc)
44 if (AR_SREV_9100(sc->sc_ah)) 44 if (AR_SREV_9100(sc->sc_ah))
45 return; 45 return;
46 46
47 if (sc->sc_ah->led_pin < 0) {
48 if (AR_SREV_9287(sc->sc_ah))
49 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
50 else if (AR_SREV_9485(sc->sc_ah))
51 sc->sc_ah->led_pin = ATH_LED_PIN_9485;
52 else if (AR_SREV_9300(sc->sc_ah))
53 sc->sc_ah->led_pin = ATH_LED_PIN_9300;
54 else if (AR_SREV_9462(sc->sc_ah))
55 sc->sc_ah->led_pin = ATH_LED_PIN_9462;
56 else
57 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
58 }
59
60 /* Configure gpio 1 for output */
61 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
62 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
63 /* LED off, active low */
64 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
65
66 if (!led_blink) 47 if (!led_blink)
67 sc->led_cdev.default_trigger = 48 sc->led_cdev.default_trigger =
68 ieee80211_get_radio_led_name(sc->hw); 49 ieee80211_get_radio_led_name(sc->hw);
@@ -78,6 +59,31 @@ void ath_init_leds(struct ath_softc *sc)
78 59
79 sc->led_registered = true; 60 sc->led_registered = true;
80} 61}
62
63void ath_fill_led_pin(struct ath_softc *sc)
64{
65 struct ath_hw *ah = sc->sc_ah;
66
67 if (AR_SREV_9100(ah) || (ah->led_pin >= 0))
68 return;
69
70 if (AR_SREV_9287(ah))
71 ah->led_pin = ATH_LED_PIN_9287;
72 else if (AR_SREV_9485(sc->sc_ah))
73 ah->led_pin = ATH_LED_PIN_9485;
74 else if (AR_SREV_9300(sc->sc_ah))
75 ah->led_pin = ATH_LED_PIN_9300;
76 else if (AR_SREV_9462(sc->sc_ah) || AR_SREV_9565(sc->sc_ah))
77 ah->led_pin = ATH_LED_PIN_9462;
78 else
79 ah->led_pin = ATH_LED_PIN_DEF;
80
81 /* Configure gpio 1 for output */
82 ath9k_hw_cfg_output(ah, ah->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
83
84 /* LED off, active low */
85 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
86}
81#endif 87#endif
82 88
83/*******************/ 89/*******************/
@@ -228,7 +234,12 @@ static void ath_btcoex_period_timer(unsigned long data)
228 ath9k_hw_btcoex_enable(ah); 234 ath9k_hw_btcoex_enable(ah);
229 spin_unlock_bh(&btcoex->btcoex_lock); 235 spin_unlock_bh(&btcoex->btcoex_lock);
230 236
231 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) { 237 /*
238 * btcoex_period is in msec while (btocex/btscan_)no_stomp are in usec,
239 * ensure that we properly convert btcoex_period to usec
240 * for any comparision with (btcoex/btscan_)no_stomp.
241 */
242 if (btcoex->btcoex_period * 1000 != btcoex->btcoex_no_stomp) {
232 if (btcoex->hw_timer_enabled) 243 if (btcoex->hw_timer_enabled)
233 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer); 244 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
234 245
@@ -309,8 +320,10 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc)
309 ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n"); 320 ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n");
310 321
311 /* make sure duty cycle timer is also stopped when resuming */ 322 /* make sure duty cycle timer is also stopped when resuming */
312 if (btcoex->hw_timer_enabled) 323 if (btcoex->hw_timer_enabled) {
313 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer); 324 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
325 btcoex->hw_timer_enabled = false;
326 }
314 327
315 btcoex->bt_priority_cnt = 0; 328 btcoex->bt_priority_cnt = 0;
316 btcoex->bt_priority_time = jiffies; 329 btcoex->bt_priority_time = jiffies;
@@ -331,18 +344,20 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc)
331 344
332 del_timer_sync(&btcoex->period_timer); 345 del_timer_sync(&btcoex->period_timer);
333 346
334 if (btcoex->hw_timer_enabled) 347 if (btcoex->hw_timer_enabled) {
335 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer); 348 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
336 349 btcoex->hw_timer_enabled = false;
337 btcoex->hw_timer_enabled = false; 350 }
338} 351}
339 352
340void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) 353void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
341{ 354{
342 struct ath_btcoex *btcoex = &sc->btcoex; 355 struct ath_btcoex *btcoex = &sc->btcoex;
343 356
344 if (btcoex->hw_timer_enabled) 357 if (btcoex->hw_timer_enabled) {
345 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer); 358 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
359 btcoex->hw_timer_enabled = false;
360 }
346} 361}
347 362
348u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen) 363u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen)
@@ -380,7 +395,10 @@ void ath9k_start_btcoex(struct ath_softc *sc)
380 !ah->btcoex_hw.enabled) { 395 !ah->btcoex_hw.enabled) {
381 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) 396 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI))
382 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, 397 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
383 AR_STOMP_LOW_WLAN_WGHT); 398 AR_STOMP_LOW_WLAN_WGHT, 0);
399 else
400 ath9k_hw_btcoex_set_weight(ah, 0, 0,
401 ATH_BTCOEX_STOMP_NONE);
384 ath9k_hw_btcoex_enable(ah); 402 ath9k_hw_btcoex_enable(ah);
385 403
386 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) 404 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
@@ -397,7 +415,7 @@ void ath9k_stop_btcoex(struct ath_softc *sc)
397 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) 415 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
398 ath9k_btcoex_timer_pause(sc); 416 ath9k_btcoex_timer_pause(sc);
399 ath9k_hw_btcoex_disable(ah); 417 ath9k_hw_btcoex_disable(ah);
400 if (AR_SREV_9462(ah)) 418 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
401 ath_mci_flush_profile(&sc->btcoex.mci); 419 ath_mci_flush_profile(&sc->btcoex.mci);
402 } 420 }
403} 421}
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index aa327adcc3d8..924c4616c3d9 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -973,8 +973,8 @@ static void ath9k_hif_usb_dealloc_urbs(struct hif_device_usb *hif_dev)
973static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev) 973static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
974{ 974{
975 int transfer, err; 975 int transfer, err;
976 const void *data = hif_dev->firmware->data; 976 const void *data = hif_dev->fw_data;
977 size_t len = hif_dev->firmware->size; 977 size_t len = hif_dev->fw_size;
978 u32 addr = AR9271_FIRMWARE; 978 u32 addr = AR9271_FIRMWARE;
979 u8 *buf = kzalloc(4096, GFP_KERNEL); 979 u8 *buf = kzalloc(4096, GFP_KERNEL);
980 u32 firm_offset; 980 u32 firm_offset;
@@ -1017,7 +1017,7 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
1017 return -EIO; 1017 return -EIO;
1018 1018
1019 dev_info(&hif_dev->udev->dev, "ath9k_htc: Transferred FW: %s, size: %ld\n", 1019 dev_info(&hif_dev->udev->dev, "ath9k_htc: Transferred FW: %s, size: %ld\n",
1020 hif_dev->fw_name, (unsigned long) hif_dev->firmware->size); 1020 hif_dev->fw_name, (unsigned long) hif_dev->fw_size);
1021 1021
1022 return 0; 1022 return 0;
1023} 1023}
@@ -1072,14 +1072,15 @@ static void ath9k_hif_usb_dev_deinit(struct hif_device_usb *hif_dev)
1072 */ 1072 */
1073static void ath9k_hif_usb_firmware_fail(struct hif_device_usb *hif_dev) 1073static void ath9k_hif_usb_firmware_fail(struct hif_device_usb *hif_dev)
1074{ 1074{
1075 struct device *parent = hif_dev->udev->dev.parent; 1075 struct device *dev = &hif_dev->udev->dev;
1076 struct device *parent = dev->parent;
1076 1077
1077 complete(&hif_dev->fw_done); 1078 complete(&hif_dev->fw_done);
1078 1079
1079 if (parent) 1080 if (parent)
1080 device_lock(parent); 1081 device_lock(parent);
1081 1082
1082 device_release_driver(&hif_dev->udev->dev); 1083 device_release_driver(dev);
1083 1084
1084 if (parent) 1085 if (parent)
1085 device_unlock(parent); 1086 device_unlock(parent);
@@ -1099,11 +1100,11 @@ static void ath9k_hif_usb_firmware_cb(const struct firmware *fw, void *context)
1099 1100
1100 hif_dev->htc_handle = ath9k_htc_hw_alloc(hif_dev, &hif_usb, 1101 hif_dev->htc_handle = ath9k_htc_hw_alloc(hif_dev, &hif_usb,
1101 &hif_dev->udev->dev); 1102 &hif_dev->udev->dev);
1102 if (hif_dev->htc_handle == NULL) { 1103 if (hif_dev->htc_handle == NULL)
1103 goto err_fw; 1104 goto err_dev_alloc;
1104 }
1105 1105
1106 hif_dev->firmware = fw; 1106 hif_dev->fw_data = fw->data;
1107 hif_dev->fw_size = fw->size;
1107 1108
1108 /* Proceed with initialization */ 1109 /* Proceed with initialization */
1109 1110
@@ -1121,6 +1122,8 @@ static void ath9k_hif_usb_firmware_cb(const struct firmware *fw, void *context)
1121 goto err_htc_hw_init; 1122 goto err_htc_hw_init;
1122 } 1123 }
1123 1124
1125 release_firmware(fw);
1126 hif_dev->flags |= HIF_USB_READY;
1124 complete(&hif_dev->fw_done); 1127 complete(&hif_dev->fw_done);
1125 1128
1126 return; 1129 return;
@@ -1129,8 +1132,8 @@ err_htc_hw_init:
1129 ath9k_hif_usb_dev_deinit(hif_dev); 1132 ath9k_hif_usb_dev_deinit(hif_dev);
1130err_dev_init: 1133err_dev_init:
1131 ath9k_htc_hw_free(hif_dev->htc_handle); 1134 ath9k_htc_hw_free(hif_dev->htc_handle);
1135err_dev_alloc:
1132 release_firmware(fw); 1136 release_firmware(fw);
1133 hif_dev->firmware = NULL;
1134err_fw: 1137err_fw:
1135 ath9k_hif_usb_firmware_fail(hif_dev); 1138 ath9k_hif_usb_firmware_fail(hif_dev);
1136} 1139}
@@ -1277,11 +1280,10 @@ static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
1277 1280
1278 wait_for_completion(&hif_dev->fw_done); 1281 wait_for_completion(&hif_dev->fw_done);
1279 1282
1280 if (hif_dev->firmware) { 1283 if (hif_dev->flags & HIF_USB_READY) {
1281 ath9k_htc_hw_deinit(hif_dev->htc_handle, unplugged); 1284 ath9k_htc_hw_deinit(hif_dev->htc_handle, unplugged);
1282 ath9k_htc_hw_free(hif_dev->htc_handle); 1285 ath9k_htc_hw_free(hif_dev->htc_handle);
1283 ath9k_hif_usb_dev_deinit(hif_dev); 1286 ath9k_hif_usb_dev_deinit(hif_dev);
1284 release_firmware(hif_dev->firmware);
1285 } 1287 }
1286 1288
1287 usb_set_intfdata(interface, NULL); 1289 usb_set_intfdata(interface, NULL);
@@ -1317,13 +1319,23 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
1317 struct hif_device_usb *hif_dev = usb_get_intfdata(interface); 1319 struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
1318 struct htc_target *htc_handle = hif_dev->htc_handle; 1320 struct htc_target *htc_handle = hif_dev->htc_handle;
1319 int ret; 1321 int ret;
1322 const struct firmware *fw;
1320 1323
1321 ret = ath9k_hif_usb_alloc_urbs(hif_dev); 1324 ret = ath9k_hif_usb_alloc_urbs(hif_dev);
1322 if (ret) 1325 if (ret)
1323 return ret; 1326 return ret;
1324 1327
1325 if (hif_dev->firmware) { 1328 if (hif_dev->flags & HIF_USB_READY) {
1329 /* request cached firmware during suspend/resume cycle */
1330 ret = request_firmware(&fw, hif_dev->fw_name,
1331 &hif_dev->udev->dev);
1332 if (ret)
1333 goto fail_resume;
1334
1335 hif_dev->fw_data = fw->data;
1336 hif_dev->fw_size = fw->size;
1326 ret = ath9k_hif_usb_download_fw(hif_dev); 1337 ret = ath9k_hif_usb_download_fw(hif_dev);
1338 release_firmware(fw);
1327 if (ret) 1339 if (ret)
1328 goto fail_resume; 1340 goto fail_resume;
1329 } else { 1341 } else {
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.h b/drivers/net/wireless/ath/ath9k/hif_usb.h
index 487ff658b4c1..51496e74b83e 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.h
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.h
@@ -85,12 +85,14 @@ struct cmd_buf {
85}; 85};
86 86
87#define HIF_USB_START BIT(0) 87#define HIF_USB_START BIT(0)
88#define HIF_USB_READY BIT(1)
88 89
89struct hif_device_usb { 90struct hif_device_usb {
90 struct usb_device *udev; 91 struct usb_device *udev;
91 struct usb_interface *interface; 92 struct usb_interface *interface;
92 const struct usb_device_id *usb_device_id; 93 const struct usb_device_id *usb_device_id;
93 const struct firmware *firmware; 94 const void *fw_data;
95 size_t fw_size;
94 struct completion fw_done; 96 struct completion fw_done;
95 struct htc_target *htc_handle; 97 struct htc_target *htc_handle;
96 struct hif_usb_tx tx; 98 struct hif_usb_tx tx;
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 936e920fb88e..b30596fcf73a 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -542,6 +542,7 @@ void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv);
542 542
543int ath9k_tx_init(struct ath9k_htc_priv *priv); 543int ath9k_tx_init(struct ath9k_htc_priv *priv);
544int ath9k_htc_tx_start(struct ath9k_htc_priv *priv, 544int ath9k_htc_tx_start(struct ath9k_htc_priv *priv,
545 struct ieee80211_sta *sta,
545 struct sk_buff *skb, u8 slot, bool is_cab); 546 struct sk_buff *skb, u8 slot, bool is_cab);
546void ath9k_tx_cleanup(struct ath9k_htc_priv *priv); 547void ath9k_tx_cleanup(struct ath9k_htc_priv *priv);
547bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype); 548bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index 77d541feb910..f42d2eb6af99 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -326,7 +326,7 @@ static void ath9k_htc_send_buffered(struct ath9k_htc_priv *priv,
326 goto next; 326 goto next;
327 } 327 }
328 328
329 ret = ath9k_htc_tx_start(priv, skb, tx_slot, true); 329 ret = ath9k_htc_tx_start(priv, NULL, skb, tx_slot, true);
330 if (ret != 0) { 330 if (ret != 0) {
331 ath9k_htc_tx_clear_slot(priv, tx_slot); 331 ath9k_htc_tx_clear_slot(priv, tx_slot);
332 dev_kfree_skb_any(skb); 332 dev_kfree_skb_any(skb);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
index 07df279c8d46..0eacfc13c915 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
@@ -161,7 +161,7 @@ void ath9k_htc_start_btcoex(struct ath9k_htc_priv *priv)
161 161
162 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) { 162 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) {
163 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, 163 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
164 AR_STOMP_LOW_WLAN_WGHT); 164 AR_STOMP_LOW_WLAN_WGHT, 0);
165 ath9k_hw_btcoex_enable(ah); 165 ath9k_hw_btcoex_enable(ah);
166 ath_htc_resume_btcoex_work(priv); 166 ath_htc_resume_btcoex_work(priv);
167 } 167 }
@@ -173,17 +173,26 @@ void ath9k_htc_stop_btcoex(struct ath9k_htc_priv *priv)
173 173
174 if (ah->btcoex_hw.enabled && 174 if (ah->btcoex_hw.enabled &&
175 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { 175 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
176 ath9k_hw_btcoex_disable(ah);
177 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 176 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
178 ath_htc_cancel_btcoex_work(priv); 177 ath_htc_cancel_btcoex_work(priv);
178 ath9k_hw_btcoex_disable(ah);
179 } 179 }
180} 180}
181 181
182void ath9k_htc_init_btcoex(struct ath9k_htc_priv *priv, char *product) 182void ath9k_htc_init_btcoex(struct ath9k_htc_priv *priv, char *product)
183{ 183{
184 struct ath_hw *ah = priv->ah; 184 struct ath_hw *ah = priv->ah;
185 struct ath_common *common = ath9k_hw_common(ah);
185 int qnum; 186 int qnum;
186 187
188 /*
189 * Check if BTCOEX is globally disabled.
190 */
191 if (!common->btcoex_enabled) {
192 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_NONE;
193 return;
194 }
195
187 if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) { 196 if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
188 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE; 197 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
189 } 198 }
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index a035a380d669..d98255eb1b9a 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -30,6 +30,10 @@ int htc_modparam_nohwcrypt;
30module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444); 30module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32 32
33static int ath9k_htc_btcoex_enable;
34module_param_named(btcoex_enable, ath9k_htc_btcoex_enable, int, 0444);
35MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
36
33#define CHAN2G(_freq, _idx) { \ 37#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \ 38 .center_freq = (_freq), \
35 .hw_value = (_idx), \ 39 .hw_value = (_idx), \
@@ -635,6 +639,7 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
635 common->hw = priv->hw; 639 common->hw = priv->hw;
636 common->priv = priv; 640 common->priv = priv;
637 common->debug_mask = ath9k_debug; 641 common->debug_mask = ath9k_debug;
642 common->btcoex_enabled = ath9k_htc_btcoex_enable == 1;
638 643
639 spin_lock_init(&priv->beacon_lock); 644 spin_lock_init(&priv->beacon_lock);
640 spin_lock_init(&priv->tx.tx_lock); 645 spin_lock_init(&priv->tx.tx_lock);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index c785129692ff..ca78e33ca23e 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -489,24 +489,20 @@ static int ath9k_htc_add_station(struct ath9k_htc_priv *priv,
489 ista = (struct ath9k_htc_sta *) sta->drv_priv; 489 ista = (struct ath9k_htc_sta *) sta->drv_priv;
490 memcpy(&tsta.macaddr, sta->addr, ETH_ALEN); 490 memcpy(&tsta.macaddr, sta->addr, ETH_ALEN);
491 memcpy(&tsta.bssid, common->curbssid, ETH_ALEN); 491 memcpy(&tsta.bssid, common->curbssid, ETH_ALEN);
492 tsta.is_vif_sta = 0;
493 ista->index = sta_idx; 492 ista->index = sta_idx;
493 tsta.is_vif_sta = 0;
494 maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
495 sta->ht_cap.ampdu_factor);
496 tsta.maxampdu = cpu_to_be16(maxampdu);
494 } else { 497 } else {
495 memcpy(&tsta.macaddr, vif->addr, ETH_ALEN); 498 memcpy(&tsta.macaddr, vif->addr, ETH_ALEN);
496 tsta.is_vif_sta = 1; 499 tsta.is_vif_sta = 1;
500 tsta.maxampdu = cpu_to_be16(0xffff);
497 } 501 }
498 502
499 tsta.sta_index = sta_idx; 503 tsta.sta_index = sta_idx;
500 tsta.vif_index = avp->index; 504 tsta.vif_index = avp->index;
501 505
502 if (!sta) {
503 tsta.maxampdu = cpu_to_be16(0xffff);
504 } else {
505 maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
506 sta->ht_cap.ampdu_factor);
507 tsta.maxampdu = cpu_to_be16(maxampdu);
508 }
509
510 WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta); 506 WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta);
511 if (ret) { 507 if (ret) {
512 if (sta) 508 if (sta)
@@ -856,7 +852,9 @@ set_timer:
856/* mac80211 Callbacks */ 852/* mac80211 Callbacks */
857/**********************/ 853/**********************/
858 854
859static void ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 855static void ath9k_htc_tx(struct ieee80211_hw *hw,
856 struct ieee80211_tx_control *control,
857 struct sk_buff *skb)
860{ 858{
861 struct ieee80211_hdr *hdr; 859 struct ieee80211_hdr *hdr;
862 struct ath9k_htc_priv *priv = hw->priv; 860 struct ath9k_htc_priv *priv = hw->priv;
@@ -883,7 +881,7 @@ static void ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
883 goto fail_tx; 881 goto fail_tx;
884 } 882 }
885 883
886 ret = ath9k_htc_tx_start(priv, skb, slot, false); 884 ret = ath9k_htc_tx_start(priv, control->sta, skb, slot, false);
887 if (ret != 0) { 885 if (ret != 0) {
888 ath_dbg(common, XMIT, "Tx failed\n"); 886 ath_dbg(common, XMIT, "Tx failed\n");
889 goto clear_slot; 887 goto clear_slot;
@@ -1331,6 +1329,34 @@ static int ath9k_htc_sta_remove(struct ieee80211_hw *hw,
1331 return ret; 1329 return ret;
1332} 1330}
1333 1331
1332static void ath9k_htc_sta_rc_update(struct ieee80211_hw *hw,
1333 struct ieee80211_vif *vif,
1334 struct ieee80211_sta *sta, u32 changed)
1335{
1336 struct ath9k_htc_priv *priv = hw->priv;
1337 struct ath_common *common = ath9k_hw_common(priv->ah);
1338 struct ath9k_htc_target_rate trate;
1339
1340 mutex_lock(&priv->mutex);
1341 ath9k_htc_ps_wakeup(priv);
1342
1343 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) {
1344 memset(&trate, 0, sizeof(struct ath9k_htc_target_rate));
1345 ath9k_htc_setup_rate(priv, sta, &trate);
1346 if (!ath9k_htc_send_rate_cmd(priv, &trate))
1347 ath_dbg(common, CONFIG,
1348 "Supported rates for sta: %pM updated, rate caps: 0x%X\n",
1349 sta->addr, be32_to_cpu(trate.capflags));
1350 else
1351 ath_dbg(common, CONFIG,
1352 "Unable to update supported rates for sta: %pM\n",
1353 sta->addr);
1354 }
1355
1356 ath9k_htc_ps_restore(priv);
1357 mutex_unlock(&priv->mutex);
1358}
1359
1334static int ath9k_htc_conf_tx(struct ieee80211_hw *hw, 1360static int ath9k_htc_conf_tx(struct ieee80211_hw *hw,
1335 struct ieee80211_vif *vif, u16 queue, 1361 struct ieee80211_vif *vif, u16 queue,
1336 const struct ieee80211_tx_queue_params *params) 1362 const struct ieee80211_tx_queue_params *params)
@@ -1419,7 +1445,7 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw,
1419 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1445 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1420 if (priv->ah->sw_mgmt_crypto && 1446 if (priv->ah->sw_mgmt_crypto &&
1421 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1447 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1422 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; 1448 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1423 ret = 0; 1449 ret = 0;
1424 } 1450 }
1425 break; 1451 break;
@@ -1758,6 +1784,7 @@ struct ieee80211_ops ath9k_htc_ops = {
1758 .sta_add = ath9k_htc_sta_add, 1784 .sta_add = ath9k_htc_sta_add,
1759 .sta_remove = ath9k_htc_sta_remove, 1785 .sta_remove = ath9k_htc_sta_remove,
1760 .conf_tx = ath9k_htc_conf_tx, 1786 .conf_tx = ath9k_htc_conf_tx,
1787 .sta_rc_update = ath9k_htc_sta_rc_update,
1761 .bss_info_changed = ath9k_htc_bss_info_changed, 1788 .bss_info_changed = ath9k_htc_bss_info_changed,
1762 .set_key = ath9k_htc_set_key, 1789 .set_key = ath9k_htc_set_key,
1763 .get_tsf = ath9k_htc_get_tsf, 1790 .get_tsf = ath9k_htc_get_tsf,
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 47e61d0da33b..06cdcb772d78 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -333,12 +333,12 @@ static void ath9k_htc_tx_data(struct ath9k_htc_priv *priv,
333} 333}
334 334
335int ath9k_htc_tx_start(struct ath9k_htc_priv *priv, 335int ath9k_htc_tx_start(struct ath9k_htc_priv *priv,
336 struct ieee80211_sta *sta,
336 struct sk_buff *skb, 337 struct sk_buff *skb,
337 u8 slot, bool is_cab) 338 u8 slot, bool is_cab)
338{ 339{
339 struct ieee80211_hdr *hdr; 340 struct ieee80211_hdr *hdr;
340 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 341 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
341 struct ieee80211_sta *sta = tx_info->control.sta;
342 struct ieee80211_vif *vif = tx_info->control.vif; 342 struct ieee80211_vif *vif = tx_info->control.vif;
343 struct ath9k_htc_sta *ista; 343 struct ath9k_htc_sta *ista;
344 struct ath9k_htc_vif *avp = NULL; 344 struct ath9k_htc_vif *avp = NULL;
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index 265bf77598a2..0f2b97f6b739 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -78,6 +78,13 @@ static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
78 ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf); 78 ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);
79} 79}
80 80
81static inline void ath9k_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
82 bool enable)
83{
84 if (ath9k_hw_ops(ah)->antctrl_shared_chain_lnadiv)
85 ath9k_hw_ops(ah)->antctrl_shared_chain_lnadiv(ah, enable);
86}
87
81/* Private hardware call ops */ 88/* Private hardware call ops */
82 89
83/* PHY ops */ 90/* PHY ops */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 4faf0a395876..f9a6ec5cf470 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -24,6 +24,7 @@
24#include "rc.h" 24#include "rc.h"
25#include "ar9003_mac.h" 25#include "ar9003_mac.h"
26#include "ar9003_mci.h" 26#include "ar9003_mci.h"
27#include "ar9003_phy.h"
27#include "debug.h" 28#include "debug.h"
28#include "ath9k.h" 29#include "ath9k.h"
29 30
@@ -355,7 +356,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
355 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 356 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
356 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 357 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
357 358
358 if (AR_SREV_9462(ah)) 359 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
359 ah->is_pciexpress = true; 360 ah->is_pciexpress = true;
360 else 361 else
361 ah->is_pciexpress = (val & 362 ah->is_pciexpress = (val &
@@ -602,6 +603,11 @@ static int __ath9k_hw_init(struct ath_hw *ah)
602 if (AR_SREV_9462(ah)) 603 if (AR_SREV_9462(ah))
603 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 604 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
604 605
606 if (AR_SREV_9565(ah)) {
607 ah->WARegVal |= AR_WA_BIT22;
608 REG_WRITE(ah, AR_WA, ah->WARegVal);
609 }
610
605 ath9k_hw_init_defaults(ah); 611 ath9k_hw_init_defaults(ah);
606 ath9k_hw_init_config(ah); 612 ath9k_hw_init_config(ah);
607 613
@@ -647,6 +653,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
647 case AR_SREV_VERSION_9340: 653 case AR_SREV_VERSION_9340:
648 case AR_SREV_VERSION_9462: 654 case AR_SREV_VERSION_9462:
649 case AR_SREV_VERSION_9550: 655 case AR_SREV_VERSION_9550:
656 case AR_SREV_VERSION_9565:
650 break; 657 break;
651 default: 658 default:
652 ath_err(common, 659 ath_err(common,
@@ -708,7 +715,7 @@ int ath9k_hw_init(struct ath_hw *ah)
708 int ret; 715 int ret;
709 struct ath_common *common = ath9k_hw_common(ah); 716 struct ath_common *common = ath9k_hw_common(ah);
710 717
711 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 718 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
712 switch (ah->hw_version.devid) { 719 switch (ah->hw_version.devid) {
713 case AR5416_DEVID_PCI: 720 case AR5416_DEVID_PCI:
714 case AR5416_DEVID_PCIE: 721 case AR5416_DEVID_PCIE:
@@ -728,6 +735,7 @@ int ath9k_hw_init(struct ath_hw *ah)
728 case AR9300_DEVID_AR9580: 735 case AR9300_DEVID_AR9580:
729 case AR9300_DEVID_AR9462: 736 case AR9300_DEVID_AR9462:
730 case AR9485_DEVID_AR1111: 737 case AR9485_DEVID_AR1111:
738 case AR9300_DEVID_AR9565:
731 break; 739 break;
732 default: 740 default:
733 if (common->bus_ops->ath_bus_type == ATH_USB) 741 if (common->bus_ops->ath_bus_type == ATH_USB)
@@ -800,8 +808,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
800{ 808{
801 u32 pll; 809 u32 pll;
802 810
803 if (AR_SREV_9485(ah)) { 811 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
804
805 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 812 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
807 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 814 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
@@ -912,7 +919,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
912 } 919 }
913 920
914 pll = ath9k_hw_compute_pll_control(ah, chan); 921 pll = ath9k_hw_compute_pll_control(ah, chan);
915 922 if (AR_SREV_9565(ah))
923 pll |= 0x40000;
916 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 924 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
917 925
918 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 926 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
@@ -1726,12 +1734,12 @@ static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1726 if (!ret) 1734 if (!ret)
1727 goto fail; 1735 goto fail;
1728 1736
1729 ath9k_hw_loadnf(ah, ah->curchan);
1730 ath9k_hw_start_nfcal(ah, true);
1731
1732 if (ath9k_hw_mci_is_enabled(ah)) 1737 if (ath9k_hw_mci_is_enabled(ah))
1733 ar9003_mci_2g5g_switch(ah, false); 1738 ar9003_mci_2g5g_switch(ah, false);
1734 1739
1740 ath9k_hw_loadnf(ah, ah->curchan);
1741 ath9k_hw_start_nfcal(ah, true);
1742
1735 if (AR_SREV_9271(ah)) 1743 if (AR_SREV_9271(ah))
1736 ar9002_hw_load_ani_reg(ah, chan); 1744 ar9002_hw_load_ani_reg(ah, chan);
1737 1745
@@ -2018,6 +2026,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2018 2026
2019 ath9k_hw_apply_gpio_override(ah); 2027 ath9k_hw_apply_gpio_override(ah);
2020 2028
2029 if (AR_SREV_9565(ah) && ah->shared_chain_lnadiv)
2030 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2031
2021 return 0; 2032 return 0;
2022} 2033}
2023EXPORT_SYMBOL(ath9k_hw_reset); 2034EXPORT_SYMBOL(ath9k_hw_reset);
@@ -2034,7 +2045,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah)
2034{ 2045{
2035 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2046 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2036 2047
2037 if (AR_SREV_9462(ah)) { 2048 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2038 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2049 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2039 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2050 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2040 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2051 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
@@ -2401,7 +2412,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2401 if (eeval & AR5416_OPFLAGS_11G) 2412 if (eeval & AR5416_OPFLAGS_11G)
2402 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2413 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2403 2414
2404 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2415 if (AR_SREV_9485(ah) ||
2416 AR_SREV_9285(ah) ||
2417 AR_SREV_9330(ah) ||
2418 AR_SREV_9565(ah))
2405 chip_chainmask = 1; 2419 chip_chainmask = 1;
2406 else if (AR_SREV_9462(ah)) 2420 else if (AR_SREV_9462(ah))
2407 chip_chainmask = 3; 2421 chip_chainmask = 3;
@@ -2489,7 +2503,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2489 2503
2490 if (AR_SREV_9300_20_OR_LATER(ah)) { 2504 if (AR_SREV_9300_20_OR_LATER(ah)) {
2491 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2505 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2492 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2506 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
2493 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2507 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2494 2508
2495 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2509 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
@@ -2525,7 +2539,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2525 } 2539 }
2526 2540
2527 2541
2528 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2542 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2529 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2543 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2530 /* 2544 /*
2531 * enable the diversity-combining algorithm only when 2545 * enable the diversity-combining algorithm only when
@@ -2568,14 +2582,12 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2568 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2582 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2569 } 2583 }
2570 2584
2571 if (AR_SREV_9462(ah)) { 2585 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2572
2573 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2586 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2574 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2587 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2575 2588
2576 if (AR_SREV_9462_20(ah)) 2589 if (AR_SREV_9462_20(ah))
2577 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2590 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2578
2579 } 2591 }
2580 2592
2581 2593
@@ -2741,7 +2753,7 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2741 2753
2742 ENABLE_REGWRITE_BUFFER(ah); 2754 ENABLE_REGWRITE_BUFFER(ah);
2743 2755
2744 if (AR_SREV_9462(ah)) 2756 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2745 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2757 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2746 2758
2747 REG_WRITE(ah, AR_RX_FILTER, bits); 2759 REG_WRITE(ah, AR_RX_FILTER, bits);
@@ -3038,7 +3050,7 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3038 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3050 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3039 gen_tmr_configuration[timer->index].mode_mask); 3051 gen_tmr_configuration[timer->index].mode_mask);
3040 3052
3041 if (AR_SREV_9462(ah)) { 3053 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3042 /* 3054 /*
3043 * Starting from AR9462, each generic timer can select which tsf 3055 * Starting from AR9462, each generic timer can select which tsf
3044 * to use. But we still follow the old rule, 0 - 7 use tsf and 3056 * to use. But we still follow the old rule, 0 - 7 use tsf and
@@ -3072,6 +3084,16 @@ void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3072 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3084 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3073 gen_tmr_configuration[timer->index].mode_mask); 3085 gen_tmr_configuration[timer->index].mode_mask);
3074 3086
3087 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3088 /*
3089 * Need to switch back to TSF if it was using TSF2.
3090 */
3091 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3092 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3093 (1 << timer->index));
3094 }
3095 }
3096
3075 /* Disable both trigger and thresh interrupt masks */ 3097 /* Disable both trigger and thresh interrupt masks */
3076 REG_CLR_BIT(ah, AR_IMR_S5, 3098 REG_CLR_BIT(ah, AR_IMR_S5,
3077 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3099 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
@@ -3153,6 +3175,7 @@ static struct {
3153 { AR_SREV_VERSION_9485, "9485" }, 3175 { AR_SREV_VERSION_9485, "9485" },
3154 { AR_SREV_VERSION_9462, "9462" }, 3176 { AR_SREV_VERSION_9462, "9462" },
3155 { AR_SREV_VERSION_9550, "9550" }, 3177 { AR_SREV_VERSION_9550, "9550" },
3178 { AR_SREV_VERSION_9565, "9565" },
3156}; 3179};
3157 3180
3158/* For devices with external radios */ 3181/* For devices with external radios */
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index de6968fc64f4..566a4ce4f156 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -50,6 +50,7 @@
50#define AR9300_DEVID_AR9330 0x0035 50#define AR9300_DEVID_AR9330 0x0035
51#define AR9300_DEVID_QCA955X 0x0038 51#define AR9300_DEVID_QCA955X 0x0038
52#define AR9485_DEVID_AR1111 0x0037 52#define AR9485_DEVID_AR1111 0x0037
53#define AR9300_DEVID_AR9565 0x0036
53 54
54#define AR5416_AR9100_DEVID 0x000b 55#define AR5416_AR9100_DEVID 0x000b
55 56
@@ -685,7 +686,7 @@ struct ath_hw_ops {
685 struct ath_hw_antcomb_conf *antconf); 686 struct ath_hw_antcomb_conf *antconf);
686 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 687 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
687 struct ath_hw_antcomb_conf *antconf); 688 struct ath_hw_antcomb_conf *antconf);
688 689 void (*antctrl_shared_chain_lnadiv)(struct ath_hw *hw, bool enable);
689}; 690};
690 691
691struct ath_nf_limits { 692struct ath_nf_limits {
@@ -729,6 +730,7 @@ struct ath_hw {
729 bool aspm_enabled; 730 bool aspm_enabled;
730 bool is_monitoring; 731 bool is_monitoring;
731 bool need_an_top2_fixup; 732 bool need_an_top2_fixup;
733 bool shared_chain_lnadiv;
732 u16 tx_trig_level; 734 u16 tx_trig_level;
733 735
734 u32 nf_regs[6]; 736 u32 nf_regs[6];
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index f33712140fa5..fad3ccd5cd91 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -46,6 +46,10 @@ static int ath9k_btcoex_enable;
46module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 46module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
47MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 47MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
48 48
49static int ath9k_enable_diversity;
50module_param_named(enable_diversity, ath9k_enable_diversity, int, 0444);
51MODULE_PARM_DESC(enable_diversity, "Enable Antenna diversity for AR9565");
52
49bool is_ath9k_unloaded; 53bool is_ath9k_unloaded;
50/* We use the hw_value as an index into our private channel structure */ 54/* We use the hw_value as an index into our private channel structure */
51 55
@@ -258,7 +262,7 @@ static void setup_ht_cap(struct ath_softc *sc,
258 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 262 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
259 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 263 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
260 264
261 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) 265 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
262 max_streams = 1; 266 max_streams = 1;
263 else if (AR_SREV_9462(ah)) 267 else if (AR_SREV_9462(ah))
264 max_streams = 2; 268 max_streams = 2;
@@ -546,6 +550,14 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
546 common->debug_mask = ath9k_debug; 550 common->debug_mask = ath9k_debug;
547 common->btcoex_enabled = ath9k_btcoex_enable == 1; 551 common->btcoex_enabled = ath9k_btcoex_enable == 1;
548 common->disable_ani = false; 552 common->disable_ani = false;
553
554 /*
555 * Enable Antenna diversity only when BTCOEX is disabled
556 * and the user manually requests the feature.
557 */
558 if (!common->btcoex_enabled && ath9k_enable_diversity)
559 common->antenna_diversity = 1;
560
549 spin_lock_init(&common->cc_lock); 561 spin_lock_init(&common->cc_lock);
550 562
551 spin_lock_init(&sc->sc_serial_rw); 563 spin_lock_init(&sc->sc_serial_rw);
@@ -597,6 +609,7 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
597 609
598 ath9k_cmn_init_crypto(sc->sc_ah); 610 ath9k_cmn_init_crypto(sc->sc_ah);
599 ath9k_init_misc(sc); 611 ath9k_init_misc(sc);
612 ath_fill_led_pin(sc);
600 613
601 if (common->bus_ops->aspm_init) 614 if (common->bus_ops->aspm_init)
602 common->bus_ops->aspm_init(common); 615 common->bus_ops->aspm_init(common);
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index a22df749b8db..31ab82e3ba85 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -696,7 +696,9 @@ mutex_unlock:
696 return r; 696 return r;
697} 697}
698 698
699static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 699static void ath9k_tx(struct ieee80211_hw *hw,
700 struct ieee80211_tx_control *control,
701 struct sk_buff *skb)
700{ 702{
701 struct ath_softc *sc = hw->priv; 703 struct ath_softc *sc = hw->priv;
702 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 704 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -756,6 +758,7 @@ static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
756 758
757 memset(&txctl, 0, sizeof(struct ath_tx_control)); 759 memset(&txctl, 0, sizeof(struct ath_tx_control));
758 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 760 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
761 txctl.sta = control->sta;
759 762
760 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 763 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
761 764
@@ -983,47 +986,21 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
983 struct ath_softc *sc = hw->priv; 986 struct ath_softc *sc = hw->priv;
984 struct ath_hw *ah = sc->sc_ah; 987 struct ath_hw *ah = sc->sc_ah;
985 struct ath_common *common = ath9k_hw_common(ah); 988 struct ath_common *common = ath9k_hw_common(ah);
986 int ret = 0;
987 989
988 ath9k_ps_wakeup(sc);
989 mutex_lock(&sc->mutex); 990 mutex_lock(&sc->mutex);
990 991
991 switch (vif->type) {
992 case NL80211_IFTYPE_STATION:
993 case NL80211_IFTYPE_WDS:
994 case NL80211_IFTYPE_ADHOC:
995 case NL80211_IFTYPE_AP:
996 case NL80211_IFTYPE_MESH_POINT:
997 break;
998 default:
999 ath_err(common, "Interface type %d not yet supported\n",
1000 vif->type);
1001 ret = -EOPNOTSUPP;
1002 goto out;
1003 }
1004
1005 if (ath9k_uses_beacons(vif->type)) {
1006 if (sc->nbcnvifs >= ATH_BCBUF) {
1007 ath_err(common, "Not enough beacon buffers when adding"
1008 " new interface of type: %i\n",
1009 vif->type);
1010 ret = -ENOBUFS;
1011 goto out;
1012 }
1013 }
1014
1015 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 992 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1016
1017 sc->nvifs++; 993 sc->nvifs++;
1018 994
995 ath9k_ps_wakeup(sc);
1019 ath9k_calculate_summary_state(hw, vif); 996 ath9k_calculate_summary_state(hw, vif);
997 ath9k_ps_restore(sc);
998
1020 if (ath9k_uses_beacons(vif->type)) 999 if (ath9k_uses_beacons(vif->type))
1021 ath9k_beacon_assign_slot(sc, vif); 1000 ath9k_beacon_assign_slot(sc, vif);
1022 1001
1023out:
1024 mutex_unlock(&sc->mutex); 1002 mutex_unlock(&sc->mutex);
1025 ath9k_ps_restore(sc); 1003 return 0;
1026 return ret;
1027} 1004}
1028 1005
1029static int ath9k_change_interface(struct ieee80211_hw *hw, 1006static int ath9k_change_interface(struct ieee80211_hw *hw,
@@ -1033,21 +1010,9 @@ static int ath9k_change_interface(struct ieee80211_hw *hw,
1033{ 1010{
1034 struct ath_softc *sc = hw->priv; 1011 struct ath_softc *sc = hw->priv;
1035 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1012 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1036 int ret = 0;
1037 1013
1038 ath_dbg(common, CONFIG, "Change Interface\n"); 1014 ath_dbg(common, CONFIG, "Change Interface\n");
1039
1040 mutex_lock(&sc->mutex); 1015 mutex_lock(&sc->mutex);
1041 ath9k_ps_wakeup(sc);
1042
1043 if (ath9k_uses_beacons(new_type) &&
1044 !ath9k_uses_beacons(vif->type)) {
1045 if (sc->nbcnvifs >= ATH_BCBUF) {
1046 ath_err(common, "No beacon slot available\n");
1047 ret = -ENOBUFS;
1048 goto out;
1049 }
1050 }
1051 1016
1052 if (ath9k_uses_beacons(vif->type)) 1017 if (ath9k_uses_beacons(vif->type))
1053 ath9k_beacon_remove_slot(sc, vif); 1018 ath9k_beacon_remove_slot(sc, vif);
@@ -1055,14 +1020,15 @@ static int ath9k_change_interface(struct ieee80211_hw *hw,
1055 vif->type = new_type; 1020 vif->type = new_type;
1056 vif->p2p = p2p; 1021 vif->p2p = p2p;
1057 1022
1023 ath9k_ps_wakeup(sc);
1058 ath9k_calculate_summary_state(hw, vif); 1024 ath9k_calculate_summary_state(hw, vif);
1025 ath9k_ps_restore(sc);
1026
1059 if (ath9k_uses_beacons(vif->type)) 1027 if (ath9k_uses_beacons(vif->type))
1060 ath9k_beacon_assign_slot(sc, vif); 1028 ath9k_beacon_assign_slot(sc, vif);
1061 1029
1062out:
1063 ath9k_ps_restore(sc);
1064 mutex_unlock(&sc->mutex); 1030 mutex_unlock(&sc->mutex);
1065 return ret; 1031 return 0;
1066} 1032}
1067 1033
1068static void ath9k_remove_interface(struct ieee80211_hw *hw, 1034static void ath9k_remove_interface(struct ieee80211_hw *hw,
@@ -1073,7 +1039,6 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
1073 1039
1074 ath_dbg(common, CONFIG, "Detach Interface\n"); 1040 ath_dbg(common, CONFIG, "Detach Interface\n");
1075 1041
1076 ath9k_ps_wakeup(sc);
1077 mutex_lock(&sc->mutex); 1042 mutex_lock(&sc->mutex);
1078 1043
1079 sc->nvifs--; 1044 sc->nvifs--;
@@ -1081,10 +1046,11 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
1081 if (ath9k_uses_beacons(vif->type)) 1046 if (ath9k_uses_beacons(vif->type))
1082 ath9k_beacon_remove_slot(sc, vif); 1047 ath9k_beacon_remove_slot(sc, vif);
1083 1048
1049 ath9k_ps_wakeup(sc);
1084 ath9k_calculate_summary_state(hw, NULL); 1050 ath9k_calculate_summary_state(hw, NULL);
1051 ath9k_ps_restore(sc);
1085 1052
1086 mutex_unlock(&sc->mutex); 1053 mutex_unlock(&sc->mutex);
1087 ath9k_ps_restore(sc);
1088} 1054}
1089 1055
1090static void ath9k_enable_ps(struct ath_softc *sc) 1056static void ath9k_enable_ps(struct ath_softc *sc)
@@ -1440,7 +1406,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
1440 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1406 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1441 if (sc->sc_ah->sw_mgmt_crypto && 1407 if (sc->sc_ah->sw_mgmt_crypto &&
1442 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1408 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1443 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; 1409 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1444 ret = 0; 1410 ret = 0;
1445 } 1411 }
1446 break; 1412 break;
@@ -2257,7 +2223,7 @@ static int ath9k_suspend(struct ieee80211_hw *hw,
2257 mutex_lock(&sc->mutex); 2223 mutex_lock(&sc->mutex);
2258 2224
2259 ath_cancel_work(sc); 2225 ath_cancel_work(sc);
2260 del_timer_sync(&common->ani.timer); 2226 ath_stop_ani(sc);
2261 del_timer_sync(&sc->rx_poll_timer); 2227 del_timer_sync(&sc->rx_poll_timer);
2262 2228
2263 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 2229 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
diff --git a/drivers/net/wireless/ath/ath9k/mci.c b/drivers/net/wireless/ath/ath9k/mci.c
index fb536e7e661b..ec2d7c807567 100644
--- a/drivers/net/wireless/ath/ath9k/mci.c
+++ b/drivers/net/wireless/ath/ath9k/mci.c
@@ -80,6 +80,7 @@ void ath_mci_flush_profile(struct ath_mci_profile *mci)
80 struct ath_mci_profile_info *info, *tinfo; 80 struct ath_mci_profile_info *info, *tinfo;
81 81
82 mci->aggr_limit = 0; 82 mci->aggr_limit = 0;
83 mci->num_mgmt = 0;
83 84
84 if (list_empty(&mci->info)) 85 if (list_empty(&mci->info))
85 return; 86 return;
@@ -120,7 +121,14 @@ static void ath_mci_update_scheme(struct ath_softc *sc)
120 if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING) 121 if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
121 goto skip_tuning; 122 goto skip_tuning;
122 123
124 mci->aggr_limit = 0;
123 btcoex->duty_cycle = ath_mci_duty_cycle[num_profile]; 125 btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
126 btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
127 if (NUM_PROF(mci))
128 btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
129 else
130 btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
131 ATH_BTCOEX_STOMP_LOW;
124 132
125 if (num_profile == 1) { 133 if (num_profile == 1) {
126 info = list_first_entry(&mci->info, 134 info = list_first_entry(&mci->info,
@@ -132,7 +140,8 @@ static void ath_mci_update_scheme(struct ath_softc *sc)
132 else if (info->T == 6) { 140 else if (info->T == 6) {
133 mci->aggr_limit = 6; 141 mci->aggr_limit = 6;
134 btcoex->duty_cycle = 30; 142 btcoex->duty_cycle = 30;
135 } 143 } else
144 mci->aggr_limit = 6;
136 ath_dbg(common, MCI, 145 ath_dbg(common, MCI,
137 "Single SCO, aggregation limit %d 1/4 ms\n", 146 "Single SCO, aggregation limit %d 1/4 ms\n",
138 mci->aggr_limit); 147 mci->aggr_limit);
@@ -191,6 +200,23 @@ skip_tuning:
191 ath9k_btcoex_timer_resume(sc); 200 ath9k_btcoex_timer_resume(sc);
192} 201}
193 202
203static void ath_mci_wait_btcal_done(struct ath_softc *sc)
204{
205 struct ath_hw *ah = sc->sc_ah;
206
207 /* Stop tx & rx */
208 ieee80211_stop_queues(sc->hw);
209 ath_stoprecv(sc);
210 ath_drain_all_txq(sc, false);
211
212 /* Wait for cal done */
213 ar9003_mci_start_reset(ah, ah->curchan);
214
215 /* Resume tx & rx */
216 ath_startrecv(sc);
217 ieee80211_wake_queues(sc->hw);
218}
219
194static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) 220static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
195{ 221{
196 struct ath_hw *ah = sc->sc_ah; 222 struct ath_hw *ah = sc->sc_ah;
@@ -201,8 +227,8 @@ static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
201 switch (opcode) { 227 switch (opcode) {
202 case MCI_GPM_BT_CAL_REQ: 228 case MCI_GPM_BT_CAL_REQ:
203 if (mci_hw->bt_state == MCI_BT_AWAKE) { 229 if (mci_hw->bt_state == MCI_BT_AWAKE) {
204 ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START); 230 mci_hw->bt_state = MCI_BT_CAL_START;
205 ath9k_queue_reset(sc, RESET_TYPE_MCI); 231 ath_mci_wait_btcal_done(sc);
206 } 232 }
207 ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state); 233 ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
208 break; 234 break;
@@ -224,8 +250,8 @@ static void ath9k_mci_work(struct work_struct *work)
224 ath_mci_update_scheme(sc); 250 ath_mci_update_scheme(sc);
225} 251}
226 252
227static void ath_mci_process_profile(struct ath_softc *sc, 253static u8 ath_mci_process_profile(struct ath_softc *sc,
228 struct ath_mci_profile_info *info) 254 struct ath_mci_profile_info *info)
229{ 255{
230 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 256 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
231 struct ath_btcoex *btcoex = &sc->btcoex; 257 struct ath_btcoex *btcoex = &sc->btcoex;
@@ -251,25 +277,15 @@ static void ath_mci_process_profile(struct ath_softc *sc,
251 277
252 if (info->start) { 278 if (info->start) {
253 if (!entry && !ath_mci_add_profile(common, mci, info)) 279 if (!entry && !ath_mci_add_profile(common, mci, info))
254 return; 280 return 0;
255 } else 281 } else
256 ath_mci_del_profile(common, mci, entry); 282 ath_mci_del_profile(common, mci, entry);
257 283
258 btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD; 284 return 1;
259 mci->aggr_limit = mci->num_sco ? 6 : 0;
260
261 btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
262 if (NUM_PROF(mci))
263 btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
264 else
265 btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
266 ATH_BTCOEX_STOMP_LOW;
267
268 ieee80211_queue_work(sc->hw, &sc->mci_work);
269} 285}
270 286
271static void ath_mci_process_status(struct ath_softc *sc, 287static u8 ath_mci_process_status(struct ath_softc *sc,
272 struct ath_mci_profile_status *status) 288 struct ath_mci_profile_status *status)
273{ 289{
274 struct ath_btcoex *btcoex = &sc->btcoex; 290 struct ath_btcoex *btcoex = &sc->btcoex;
275 struct ath_mci_profile *mci = &btcoex->mci; 291 struct ath_mci_profile *mci = &btcoex->mci;
@@ -278,14 +294,14 @@ static void ath_mci_process_status(struct ath_softc *sc,
278 294
279 /* Link status type are not handled */ 295 /* Link status type are not handled */
280 if (status->is_link) 296 if (status->is_link)
281 return; 297 return 0;
282 298
283 info.conn_handle = status->conn_handle; 299 info.conn_handle = status->conn_handle;
284 if (ath_mci_find_profile(mci, &info)) 300 if (ath_mci_find_profile(mci, &info))
285 return; 301 return 0;
286 302
287 if (status->conn_handle >= ATH_MCI_MAX_PROFILE) 303 if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
288 return; 304 return 0;
289 305
290 if (status->is_critical) 306 if (status->is_critical)
291 __set_bit(status->conn_handle, mci->status); 307 __set_bit(status->conn_handle, mci->status);
@@ -299,7 +315,9 @@ static void ath_mci_process_status(struct ath_softc *sc,
299 } while (++i < ATH_MCI_MAX_PROFILE); 315 } while (++i < ATH_MCI_MAX_PROFILE);
300 316
301 if (old_num_mgmt != mci->num_mgmt) 317 if (old_num_mgmt != mci->num_mgmt)
302 ieee80211_queue_work(sc->hw, &sc->mci_work); 318 return 1;
319
320 return 0;
303} 321}
304 322
305static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) 323static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
@@ -308,9 +326,16 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
308 struct ath_mci_profile_info profile_info; 326 struct ath_mci_profile_info profile_info;
309 struct ath_mci_profile_status profile_status; 327 struct ath_mci_profile_status profile_status;
310 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 328 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
311 u8 major, minor; 329 u8 major, minor, update_scheme = 0;
312 u32 seq_num; 330 u32 seq_num;
313 331
332 if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
333 ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
334 ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
335 ath_mci_flush_profile(&sc->btcoex.mci);
336 ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
337 }
338
314 switch (opcode) { 339 switch (opcode) {
315 case MCI_GPM_COEX_VERSION_QUERY: 340 case MCI_GPM_COEX_VERSION_QUERY:
316 ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION); 341 ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
@@ -336,7 +361,7 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
336 break; 361 break;
337 } 362 }
338 363
339 ath_mci_process_profile(sc, &profile_info); 364 update_scheme += ath_mci_process_profile(sc, &profile_info);
340 break; 365 break;
341 case MCI_GPM_COEX_BT_STATUS_UPDATE: 366 case MCI_GPM_COEX_BT_STATUS_UPDATE:
342 profile_status.is_link = *(rx_payload + 367 profile_status.is_link = *(rx_payload +
@@ -352,12 +377,14 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
352 profile_status.is_link, profile_status.conn_handle, 377 profile_status.is_link, profile_status.conn_handle,
353 profile_status.is_critical, seq_num); 378 profile_status.is_critical, seq_num);
354 379
355 ath_mci_process_status(sc, &profile_status); 380 update_scheme += ath_mci_process_status(sc, &profile_status);
356 break; 381 break;
357 default: 382 default:
358 ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode); 383 ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
359 break; 384 break;
360 } 385 }
386 if (update_scheme)
387 ieee80211_queue_work(sc->hw, &sc->mci_work);
361} 388}
362 389
363int ath_mci_setup(struct ath_softc *sc) 390int ath_mci_setup(struct ath_softc *sc)
@@ -365,6 +392,7 @@ int ath_mci_setup(struct ath_softc *sc)
365 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 392 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
366 struct ath_mci_coex *mci = &sc->mci_coex; 393 struct ath_mci_coex *mci = &sc->mci_coex;
367 struct ath_mci_buf *buf = &mci->sched_buf; 394 struct ath_mci_buf *buf = &mci->sched_buf;
395 int ret;
368 396
369 buf->bf_addr = dma_alloc_coherent(sc->dev, 397 buf->bf_addr = dma_alloc_coherent(sc->dev,
370 ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE, 398 ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
@@ -384,9 +412,13 @@ int ath_mci_setup(struct ath_softc *sc)
384 mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len; 412 mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
385 mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len; 413 mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
386 414
387 ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr, 415 ret = ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
388 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4), 416 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
389 mci->sched_buf.bf_paddr); 417 mci->sched_buf.bf_paddr);
418 if (ret) {
419 ath_err(common, "Failed to initialize MCI\n");
420 return ret;
421 }
390 422
391 INIT_WORK(&sc->mci_work, ath9k_mci_work); 423 INIT_WORK(&sc->mci_work, ath9k_mci_work);
392 ath_dbg(common, MCI, "MCI Initialized\n"); 424 ath_dbg(common, MCI, "MCI Initialized\n");
@@ -551,9 +583,11 @@ void ath_mci_intr(struct ath_softc *sc)
551 } 583 }
552 584
553 if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || 585 if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
554 (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) 586 (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
555 mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR | 587 mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
556 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT); 588 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
589 ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
590 }
557} 591}
558 592
559void ath_mci_enable(struct ath_softc *sc) 593void ath_mci_enable(struct ath_softc *sc)
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index ef11dc639461..0e630a99b68b 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -38,6 +38,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
38 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 38 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
39 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ 39 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
40 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */ 40 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */
41 { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */
41 { 0 } 42 { 0 }
42}; 43};
43 44
@@ -122,7 +123,8 @@ static void ath_pci_aspm_init(struct ath_common *common)
122 if (!parent) 123 if (!parent)
123 return; 124 return;
124 125
125 if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { 126 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
127 (AR_SREV_9285(ah))) {
126 /* Bluetooth coexistance requires disabling ASPM. */ 128 /* Bluetooth coexistance requires disabling ASPM. */
127 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, 129 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
128 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 130 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index e034add9cd5a..27ed80b54881 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -25,141 +25,141 @@ static const struct ath_rate_table ar5416_11na_ratetable = {
25 8, /* MCS start */ 25 8, /* MCS start */
26 { 26 {
27 [0] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 6000, 27 [0] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 6000,
28 5400, 0, 12, 0, 0, 0, 0 }, /* 6 Mb */ 28 5400, 0, 12 }, /* 6 Mb */
29 [1] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 9000, 29 [1] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 9000,
30 7800, 1, 18, 0, 1, 1, 1 }, /* 9 Mb */ 30 7800, 1, 18 }, /* 9 Mb */
31 [2] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 12000, 31 [2] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 12000,
32 10000, 2, 24, 2, 2, 2, 2 }, /* 12 Mb */ 32 10000, 2, 24 }, /* 12 Mb */
33 [3] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 18000, 33 [3] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 18000,
34 13900, 3, 36, 2, 3, 3, 3 }, /* 18 Mb */ 34 13900, 3, 36 }, /* 18 Mb */
35 [4] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 24000, 35 [4] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 24000,
36 17300, 4, 48, 4, 4, 4, 4 }, /* 24 Mb */ 36 17300, 4, 48 }, /* 24 Mb */
37 [5] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 36000, 37 [5] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 36000,
38 23000, 5, 72, 4, 5, 5, 5 }, /* 36 Mb */ 38 23000, 5, 72 }, /* 36 Mb */
39 [6] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 48000, 39 [6] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 48000,
40 27400, 6, 96, 4, 6, 6, 6 }, /* 48 Mb */ 40 27400, 6, 96 }, /* 48 Mb */
41 [7] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 54000, 41 [7] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 54000,
42 29300, 7, 108, 4, 7, 7, 7 }, /* 54 Mb */ 42 29300, 7, 108 }, /* 54 Mb */
43 [8] = { RC_HT_SDT_2040, WLAN_RC_PHY_HT_20_SS, 6500, 43 [8] = { RC_HT_SDT_2040, WLAN_RC_PHY_HT_20_SS, 6500,
44 6400, 0, 0, 0, 38, 8, 38 }, /* 6.5 Mb */ 44 6400, 0, 0 }, /* 6.5 Mb */
45 [9] = { RC_HT_SDT_20, WLAN_RC_PHY_HT_20_SS, 13000, 45 [9] = { RC_HT_SDT_20, WLAN_RC_PHY_HT_20_SS, 13000,
46 12700, 1, 1, 2, 39, 9, 39 }, /* 13 Mb */ 46 12700, 1, 1 }, /* 13 Mb */
47 [10] = { RC_HT_SDT_20, WLAN_RC_PHY_HT_20_SS, 19500, 47 [10] = { RC_HT_SDT_20, WLAN_RC_PHY_HT_20_SS, 19500,
48 18800, 2, 2, 2, 40, 10, 40 }, /* 19.5 Mb */ 48 18800, 2, 2 }, /* 19.5 Mb */
49 [11] = { RC_HT_SD_20, WLAN_RC_PHY_HT_20_SS, 26000, 49 [11] = { RC_HT_SD_20, WLAN_RC_PHY_HT_20_SS, 26000,
50 25000, 3, 3, 4, 41, 11, 41 }, /* 26 Mb */ 50 25000, 3, 3 }, /* 26 Mb */
51 [12] = { RC_HT_SD_20, WLAN_RC_PHY_HT_20_SS, 39000, 51 [12] = { RC_HT_SD_20, WLAN_RC_PHY_HT_20_SS, 39000,
52 36700, 4, 4, 4, 42, 12, 42 }, /* 39 Mb */ 52 36700, 4, 4 }, /* 39 Mb */
53 [13] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 52000, 53 [13] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 52000,
54 48100, 5, 5, 4, 43, 13, 43 }, /* 52 Mb */ 54 48100, 5, 5 }, /* 52 Mb */
55 [14] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 58500, 55 [14] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 58500,
56 53500, 6, 6, 4, 44, 14, 44 }, /* 58.5 Mb */ 56 53500, 6, 6 }, /* 58.5 Mb */
57 [15] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 65000, 57 [15] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 65000,
58 59000, 7, 7, 4, 45, 16, 46 }, /* 65 Mb */ 58 59000, 7, 7 }, /* 65 Mb */
59 [16] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS_HGI, 72200, 59 [16] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS_HGI, 72200,
60 65400, 7, 7, 4, 45, 16, 46 }, /* 75 Mb */ 60 65400, 7, 7 }, /* 75 Mb */
61 [17] = { RC_INVALID, WLAN_RC_PHY_HT_20_DS, 13000, 61 [17] = { RC_INVALID, WLAN_RC_PHY_HT_20_DS, 13000,
62 12700, 8, 8, 0, 47, 17, 47 }, /* 13 Mb */ 62 12700, 8, 8 }, /* 13 Mb */
63 [18] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_DS, 26000, 63 [18] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_DS, 26000,
64 24800, 9, 9, 2, 48, 18, 48 }, /* 26 Mb */ 64 24800, 9, 9 }, /* 26 Mb */
65 [19] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_DS, 39000, 65 [19] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_DS, 39000,
66 36600, 10, 10, 2, 49, 19, 49 }, /* 39 Mb */ 66 36600, 10, 10 }, /* 39 Mb */
67 [20] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 52000, 67 [20] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 52000,
68 48100, 11, 11, 4, 50, 20, 50 }, /* 52 Mb */ 68 48100, 11, 11 }, /* 52 Mb */
69 [21] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 78000, 69 [21] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 78000,
70 69500, 12, 12, 4, 51, 21, 51 }, /* 78 Mb */ 70 69500, 12, 12 }, /* 78 Mb */
71 [22] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 104000, 71 [22] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 104000,
72 89500, 13, 13, 4, 52, 22, 52 }, /* 104 Mb */ 72 89500, 13, 13 }, /* 104 Mb */
73 [23] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 117000, 73 [23] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 117000,
74 98900, 14, 14, 4, 53, 23, 53 }, /* 117 Mb */ 74 98900, 14, 14 }, /* 117 Mb */
75 [24] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 130000, 75 [24] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 130000,
76 108300, 15, 15, 4, 54, 25, 55 }, /* 130 Mb */ 76 108300, 15, 15 }, /* 130 Mb */
77 [25] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS_HGI, 144400, 77 [25] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS_HGI, 144400,
78 120000, 15, 15, 4, 54, 25, 55 }, /* 144.4 Mb */ 78 120000, 15, 15 }, /* 144.4 Mb */
79 [26] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 19500, 79 [26] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 19500,
80 17400, 16, 16, 0, 56, 26, 56 }, /* 19.5 Mb */ 80 17400, 16, 16 }, /* 19.5 Mb */
81 [27] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 39000, 81 [27] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 39000,
82 35100, 17, 17, 2, 57, 27, 57 }, /* 39 Mb */ 82 35100, 17, 17 }, /* 39 Mb */
83 [28] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 58500, 83 [28] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 58500,
84 52600, 18, 18, 2, 58, 28, 58 }, /* 58.5 Mb */ 84 52600, 18, 18 }, /* 58.5 Mb */
85 [29] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 78000, 85 [29] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 78000,
86 70400, 19, 19, 4, 59, 29, 59 }, /* 78 Mb */ 86 70400, 19, 19 }, /* 78 Mb */
87 [30] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 117000, 87 [30] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 117000,
88 104900, 20, 20, 4, 60, 31, 61 }, /* 117 Mb */ 88 104900, 20, 20 }, /* 117 Mb */
89 [31] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS_HGI, 130000, 89 [31] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS_HGI, 130000,
90 115800, 20, 20, 4, 60, 31, 61 }, /* 130 Mb*/ 90 115800, 20, 20 }, /* 130 Mb*/
91 [32] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 156000, 91 [32] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 156000,
92 137200, 21, 21, 4, 62, 33, 63 }, /* 156 Mb */ 92 137200, 21, 21 }, /* 156 Mb */
93 [33] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 173300, 93 [33] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 173300,
94 151100, 21, 21, 4, 62, 33, 63 }, /* 173.3 Mb */ 94 151100, 21, 21 }, /* 173.3 Mb */
95 [34] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 175500, 95 [34] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 175500,
96 152800, 22, 22, 4, 64, 35, 65 }, /* 175.5 Mb */ 96 152800, 22, 22 }, /* 175.5 Mb */
97 [35] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 195000, 97 [35] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 195000,
98 168400, 22, 22, 4, 64, 35, 65 }, /* 195 Mb*/ 98 168400, 22, 22 }, /* 195 Mb*/
99 [36] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 195000, 99 [36] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 195000,
100 168400, 23, 23, 4, 66, 37, 67 }, /* 195 Mb */ 100 168400, 23, 23 }, /* 195 Mb */
101 [37] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 216700, 101 [37] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 216700,
102 185000, 23, 23, 4, 66, 37, 67 }, /* 216.7 Mb */ 102 185000, 23, 23 }, /* 216.7 Mb */
103 [38] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 13500, 103 [38] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 13500,
104 13200, 0, 0, 0, 38, 38, 38 }, /* 13.5 Mb*/ 104 13200, 0, 0 }, /* 13.5 Mb*/
105 [39] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 27500, 105 [39] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 27500,
106 25900, 1, 1, 2, 39, 39, 39 }, /* 27.0 Mb*/ 106 25900, 1, 1 }, /* 27.0 Mb*/
107 [40] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 40500, 107 [40] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 40500,
108 38600, 2, 2, 2, 40, 40, 40 }, /* 40.5 Mb*/ 108 38600, 2, 2 }, /* 40.5 Mb*/
109 [41] = { RC_HT_SD_40, WLAN_RC_PHY_HT_40_SS, 54000, 109 [41] = { RC_HT_SD_40, WLAN_RC_PHY_HT_40_SS, 54000,
110 49800, 3, 3, 4, 41, 41, 41 }, /* 54 Mb */ 110 49800, 3, 3 }, /* 54 Mb */
111 [42] = { RC_HT_SD_40, WLAN_RC_PHY_HT_40_SS, 81500, 111 [42] = { RC_HT_SD_40, WLAN_RC_PHY_HT_40_SS, 81500,
112 72200, 4, 4, 4, 42, 42, 42 }, /* 81 Mb */ 112 72200, 4, 4 }, /* 81 Mb */
113 [43] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 108000, 113 [43] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 108000,
114 92900, 5, 5, 4, 43, 43, 43 }, /* 108 Mb */ 114 92900, 5, 5 }, /* 108 Mb */
115 [44] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 121500, 115 [44] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 121500,
116 102700, 6, 6, 4, 44, 44, 44 }, /* 121.5 Mb*/ 116 102700, 6, 6 }, /* 121.5 Mb*/
117 [45] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 135000, 117 [45] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 135000,
118 112000, 7, 7, 4, 45, 46, 46 }, /* 135 Mb */ 118 112000, 7, 7 }, /* 135 Mb */
119 [46] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS_HGI, 150000, 119 [46] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS_HGI, 150000,
120 122000, 7, 7, 4, 45, 46, 46 }, /* 150 Mb */ 120 122000, 7, 7 }, /* 150 Mb */
121 [47] = { RC_INVALID, WLAN_RC_PHY_HT_40_DS, 27000, 121 [47] = { RC_INVALID, WLAN_RC_PHY_HT_40_DS, 27000,
122 25800, 8, 8, 0, 47, 47, 47 }, /* 27 Mb */ 122 25800, 8, 8 }, /* 27 Mb */
123 [48] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_DS, 54000, 123 [48] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_DS, 54000,
124 49800, 9, 9, 2, 48, 48, 48 }, /* 54 Mb */ 124 49800, 9, 9 }, /* 54 Mb */
125 [49] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_DS, 81000, 125 [49] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_DS, 81000,
126 71900, 10, 10, 2, 49, 49, 49 }, /* 81 Mb */ 126 71900, 10, 10 }, /* 81 Mb */
127 [50] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 108000, 127 [50] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 108000,
128 92500, 11, 11, 4, 50, 50, 50 }, /* 108 Mb */ 128 92500, 11, 11 }, /* 108 Mb */
129 [51] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 162000, 129 [51] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 162000,
130 130300, 12, 12, 4, 51, 51, 51 }, /* 162 Mb */ 130 130300, 12, 12 }, /* 162 Mb */
131 [52] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 216000, 131 [52] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 216000,
132 162800, 13, 13, 4, 52, 52, 52 }, /* 216 Mb */ 132 162800, 13, 13 }, /* 216 Mb */
133 [53] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 243000, 133 [53] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 243000,
134 178200, 14, 14, 4, 53, 53, 53 }, /* 243 Mb */ 134 178200, 14, 14 }, /* 243 Mb */
135 [54] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 270000, 135 [54] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 270000,
136 192100, 15, 15, 4, 54, 55, 55 }, /* 270 Mb */ 136 192100, 15, 15 }, /* 270 Mb */
137 [55] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS_HGI, 300000, 137 [55] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS_HGI, 300000,
138 207000, 15, 15, 4, 54, 55, 55 }, /* 300 Mb */ 138 207000, 15, 15 }, /* 300 Mb */
139 [56] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 40500, 139 [56] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 40500,
140 36100, 16, 16, 0, 56, 56, 56 }, /* 40.5 Mb */ 140 36100, 16, 16 }, /* 40.5 Mb */
141 [57] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 81000, 141 [57] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 81000,
142 72900, 17, 17, 2, 57, 57, 57 }, /* 81 Mb */ 142 72900, 17, 17 }, /* 81 Mb */
143 [58] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 121500, 143 [58] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 121500,
144 108300, 18, 18, 2, 58, 58, 58 }, /* 121.5 Mb */ 144 108300, 18, 18 }, /* 121.5 Mb */
145 [59] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 162000, 145 [59] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 162000,
146 142000, 19, 19, 4, 59, 59, 59 }, /* 162 Mb */ 146 142000, 19, 19 }, /* 162 Mb */
147 [60] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 243000, 147 [60] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 243000,
148 205100, 20, 20, 4, 60, 61, 61 }, /* 243 Mb */ 148 205100, 20, 20 }, /* 243 Mb */
149 [61] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS_HGI, 270000, 149 [61] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS_HGI, 270000,
150 224700, 20, 20, 4, 60, 61, 61 }, /* 270 Mb */ 150 224700, 20, 20 }, /* 270 Mb */
151 [62] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 324000, 151 [62] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 324000,
152 263100, 21, 21, 4, 62, 63, 63 }, /* 324 Mb */ 152 263100, 21, 21 }, /* 324 Mb */
153 [63] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 360000, 153 [63] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 360000,
154 288000, 21, 21, 4, 62, 63, 63 }, /* 360 Mb */ 154 288000, 21, 21 }, /* 360 Mb */
155 [64] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 364500, 155 [64] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 364500,
156 290700, 22, 22, 4, 64, 65, 65 }, /* 364.5 Mb */ 156 290700, 22, 22 }, /* 364.5 Mb */
157 [65] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 405000, 157 [65] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 405000,
158 317200, 22, 22, 4, 64, 65, 65 }, /* 405 Mb */ 158 317200, 22, 22 }, /* 405 Mb */
159 [66] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 405000, 159 [66] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 405000,
160 317200, 23, 23, 4, 66, 67, 67 }, /* 405 Mb */ 160 317200, 23, 23 }, /* 405 Mb */
161 [67] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 450000, 161 [67] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 450000,
162 346400, 23, 23, 4, 66, 67, 67 }, /* 450 Mb */ 162 346400, 23, 23 }, /* 450 Mb */
163 }, 163 },
164 50, /* probe interval */ 164 50, /* probe interval */
165 WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ 165 WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
@@ -173,149 +173,149 @@ static const struct ath_rate_table ar5416_11ng_ratetable = {
173 12, /* MCS start */ 173 12, /* MCS start */
174 { 174 {
175 [0] = { RC_ALL, WLAN_RC_PHY_CCK, 1000, 175 [0] = { RC_ALL, WLAN_RC_PHY_CCK, 1000,
176 900, 0, 2, 0, 0, 0, 0 }, /* 1 Mb */ 176 900, 0, 2 }, /* 1 Mb */
177 [1] = { RC_ALL, WLAN_RC_PHY_CCK, 2000, 177 [1] = { RC_ALL, WLAN_RC_PHY_CCK, 2000,
178 1900, 1, 4, 1, 1, 1, 1 }, /* 2 Mb */ 178 1900, 1, 4 }, /* 2 Mb */
179 [2] = { RC_ALL, WLAN_RC_PHY_CCK, 5500, 179 [2] = { RC_ALL, WLAN_RC_PHY_CCK, 5500,
180 4900, 2, 11, 2, 2, 2, 2 }, /* 5.5 Mb */ 180 4900, 2, 11 }, /* 5.5 Mb */
181 [3] = { RC_ALL, WLAN_RC_PHY_CCK, 11000, 181 [3] = { RC_ALL, WLAN_RC_PHY_CCK, 11000,
182 8100, 3, 22, 3, 3, 3, 3 }, /* 11 Mb */ 182 8100, 3, 22 }, /* 11 Mb */
183 [4] = { RC_INVALID, WLAN_RC_PHY_OFDM, 6000, 183 [4] = { RC_INVALID, WLAN_RC_PHY_OFDM, 6000,
184 5400, 4, 12, 4, 4, 4, 4 }, /* 6 Mb */ 184 5400, 4, 12 }, /* 6 Mb */
185 [5] = { RC_INVALID, WLAN_RC_PHY_OFDM, 9000, 185 [5] = { RC_INVALID, WLAN_RC_PHY_OFDM, 9000,
186 7800, 5, 18, 4, 5, 5, 5 }, /* 9 Mb */ 186 7800, 5, 18 }, /* 9 Mb */
187 [6] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 12000, 187 [6] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 12000,
188 10100, 6, 24, 6, 6, 6, 6 }, /* 12 Mb */ 188 10100, 6, 24 }, /* 12 Mb */
189 [7] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 18000, 189 [7] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 18000,
190 14100, 7, 36, 6, 7, 7, 7 }, /* 18 Mb */ 190 14100, 7, 36 }, /* 18 Mb */
191 [8] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 24000, 191 [8] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 24000,
192 17700, 8, 48, 8, 8, 8, 8 }, /* 24 Mb */ 192 17700, 8, 48 }, /* 24 Mb */
193 [9] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 36000, 193 [9] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 36000,
194 23700, 9, 72, 8, 9, 9, 9 }, /* 36 Mb */ 194 23700, 9, 72 }, /* 36 Mb */
195 [10] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 48000, 195 [10] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 48000,
196 27400, 10, 96, 8, 10, 10, 10 }, /* 48 Mb */ 196 27400, 10, 96 }, /* 48 Mb */
197 [11] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 54000, 197 [11] = { RC_L_SDT, WLAN_RC_PHY_OFDM, 54000,
198 30900, 11, 108, 8, 11, 11, 11 }, /* 54 Mb */ 198 30900, 11, 108 }, /* 54 Mb */
199 [12] = { RC_INVALID, WLAN_RC_PHY_HT_20_SS, 6500, 199 [12] = { RC_INVALID, WLAN_RC_PHY_HT_20_SS, 6500,
200 6400, 0, 0, 4, 42, 12, 42 }, /* 6.5 Mb */ 200 6400, 0, 0 }, /* 6.5 Mb */
201 [13] = { RC_HT_SDT_20, WLAN_RC_PHY_HT_20_SS, 13000, 201 [13] = { RC_HT_SDT_20, WLAN_RC_PHY_HT_20_SS, 13000,
202 12700, 1, 1, 6, 43, 13, 43 }, /* 13 Mb */ 202 12700, 1, 1 }, /* 13 Mb */
203 [14] = { RC_HT_SDT_20, WLAN_RC_PHY_HT_20_SS, 19500, 203 [14] = { RC_HT_SDT_20, WLAN_RC_PHY_HT_20_SS, 19500,
204 18800, 2, 2, 6, 44, 14, 44 }, /* 19.5 Mb*/ 204 18800, 2, 2 }, /* 19.5 Mb*/
205 [15] = { RC_HT_SD_20, WLAN_RC_PHY_HT_20_SS, 26000, 205 [15] = { RC_HT_SD_20, WLAN_RC_PHY_HT_20_SS, 26000,
206 25000, 3, 3, 8, 45, 15, 45 }, /* 26 Mb */ 206 25000, 3, 3 }, /* 26 Mb */
207 [16] = { RC_HT_SD_20, WLAN_RC_PHY_HT_20_SS, 39000, 207 [16] = { RC_HT_SD_20, WLAN_RC_PHY_HT_20_SS, 39000,
208 36700, 4, 4, 8, 46, 16, 46 }, /* 39 Mb */ 208 36700, 4, 4 }, /* 39 Mb */
209 [17] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 52000, 209 [17] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 52000,
210 48100, 5, 5, 8, 47, 17, 47 }, /* 52 Mb */ 210 48100, 5, 5 }, /* 52 Mb */
211 [18] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 58500, 211 [18] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 58500,
212 53500, 6, 6, 8, 48, 18, 48 }, /* 58.5 Mb */ 212 53500, 6, 6 }, /* 58.5 Mb */
213 [19] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 65000, 213 [19] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS, 65000,
214 59000, 7, 7, 8, 49, 20, 50 }, /* 65 Mb */ 214 59000, 7, 7 }, /* 65 Mb */
215 [20] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS_HGI, 72200, 215 [20] = { RC_HT_S_20, WLAN_RC_PHY_HT_20_SS_HGI, 72200,
216 65400, 7, 7, 8, 49, 20, 50 }, /* 65 Mb*/ 216 65400, 7, 7 }, /* 65 Mb*/
217 [21] = { RC_INVALID, WLAN_RC_PHY_HT_20_DS, 13000, 217 [21] = { RC_INVALID, WLAN_RC_PHY_HT_20_DS, 13000,
218 12700, 8, 8, 4, 51, 21, 51 }, /* 13 Mb */ 218 12700, 8, 8 }, /* 13 Mb */
219 [22] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_DS, 26000, 219 [22] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_DS, 26000,
220 24800, 9, 9, 6, 52, 22, 52 }, /* 26 Mb */ 220 24800, 9, 9 }, /* 26 Mb */
221 [23] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_DS, 39000, 221 [23] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_DS, 39000,
222 36600, 10, 10, 6, 53, 23, 53 }, /* 39 Mb */ 222 36600, 10, 10 }, /* 39 Mb */
223 [24] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 52000, 223 [24] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 52000,
224 48100, 11, 11, 8, 54, 24, 54 }, /* 52 Mb */ 224 48100, 11, 11 }, /* 52 Mb */
225 [25] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 78000, 225 [25] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 78000,
226 69500, 12, 12, 8, 55, 25, 55 }, /* 78 Mb */ 226 69500, 12, 12 }, /* 78 Mb */
227 [26] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 104000, 227 [26] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 104000,
228 89500, 13, 13, 8, 56, 26, 56 }, /* 104 Mb */ 228 89500, 13, 13 }, /* 104 Mb */
229 [27] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 117000, 229 [27] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 117000,
230 98900, 14, 14, 8, 57, 27, 57 }, /* 117 Mb */ 230 98900, 14, 14 }, /* 117 Mb */
231 [28] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 130000, 231 [28] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS, 130000,
232 108300, 15, 15, 8, 58, 29, 59 }, /* 130 Mb */ 232 108300, 15, 15 }, /* 130 Mb */
233 [29] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS_HGI, 144400, 233 [29] = { RC_HT_DT_20, WLAN_RC_PHY_HT_20_DS_HGI, 144400,
234 120000, 15, 15, 8, 58, 29, 59 }, /* 144.4 Mb */ 234 120000, 15, 15 }, /* 144.4 Mb */
235 [30] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 19500, 235 [30] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 19500,
236 17400, 16, 16, 4, 60, 30, 60 }, /* 19.5 Mb */ 236 17400, 16, 16 }, /* 19.5 Mb */
237 [31] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 39000, 237 [31] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 39000,
238 35100, 17, 17, 6, 61, 31, 61 }, /* 39 Mb */ 238 35100, 17, 17 }, /* 39 Mb */
239 [32] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 58500, 239 [32] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 58500,
240 52600, 18, 18, 6, 62, 32, 62 }, /* 58.5 Mb */ 240 52600, 18, 18 }, /* 58.5 Mb */
241 [33] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 78000, 241 [33] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 78000,
242 70400, 19, 19, 8, 63, 33, 63 }, /* 78 Mb */ 242 70400, 19, 19 }, /* 78 Mb */
243 [34] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 117000, 243 [34] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS, 117000,
244 104900, 20, 20, 8, 64, 35, 65 }, /* 117 Mb */ 244 104900, 20, 20 }, /* 117 Mb */
245 [35] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS_HGI, 130000, 245 [35] = { RC_INVALID, WLAN_RC_PHY_HT_20_TS_HGI, 130000,
246 115800, 20, 20, 8, 64, 35, 65 }, /* 130 Mb */ 246 115800, 20, 20 }, /* 130 Mb */
247 [36] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 156000, 247 [36] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 156000,
248 137200, 21, 21, 8, 66, 37, 67 }, /* 156 Mb */ 248 137200, 21, 21 }, /* 156 Mb */
249 [37] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 173300, 249 [37] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 173300,
250 151100, 21, 21, 8, 66, 37, 67 }, /* 173.3 Mb */ 250 151100, 21, 21 }, /* 173.3 Mb */
251 [38] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 175500, 251 [38] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 175500,
252 152800, 22, 22, 8, 68, 39, 69 }, /* 175.5 Mb */ 252 152800, 22, 22 }, /* 175.5 Mb */
253 [39] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 195000, 253 [39] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 195000,
254 168400, 22, 22, 8, 68, 39, 69 }, /* 195 Mb */ 254 168400, 22, 22 }, /* 195 Mb */
255 [40] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 195000, 255 [40] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS, 195000,
256 168400, 23, 23, 8, 70, 41, 71 }, /* 195 Mb */ 256 168400, 23, 23 }, /* 195 Mb */
257 [41] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 216700, 257 [41] = { RC_HT_T_20, WLAN_RC_PHY_HT_20_TS_HGI, 216700,
258 185000, 23, 23, 8, 70, 41, 71 }, /* 216.7 Mb */ 258 185000, 23, 23 }, /* 216.7 Mb */
259 [42] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 13500, 259 [42] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 13500,
260 13200, 0, 0, 8, 42, 42, 42 }, /* 13.5 Mb */ 260 13200, 0, 0 }, /* 13.5 Mb */
261 [43] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 27500, 261 [43] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 27500,
262 25900, 1, 1, 8, 43, 43, 43 }, /* 27.0 Mb */ 262 25900, 1, 1 }, /* 27.0 Mb */
263 [44] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 40500, 263 [44] = { RC_HT_SDT_40, WLAN_RC_PHY_HT_40_SS, 40500,
264 38600, 2, 2, 8, 44, 44, 44 }, /* 40.5 Mb */ 264 38600, 2, 2 }, /* 40.5 Mb */
265 [45] = { RC_HT_SD_40, WLAN_RC_PHY_HT_40_SS, 54000, 265 [45] = { RC_HT_SD_40, WLAN_RC_PHY_HT_40_SS, 54000,
266 49800, 3, 3, 8, 45, 45, 45 }, /* 54 Mb */ 266 49800, 3, 3 }, /* 54 Mb */
267 [46] = { RC_HT_SD_40, WLAN_RC_PHY_HT_40_SS, 81500, 267 [46] = { RC_HT_SD_40, WLAN_RC_PHY_HT_40_SS, 81500,
268 72200, 4, 4, 8, 46, 46, 46 }, /* 81 Mb */ 268 72200, 4, 4 }, /* 81 Mb */
269 [47] = { RC_HT_S_40 , WLAN_RC_PHY_HT_40_SS, 108000, 269 [47] = { RC_HT_S_40 , WLAN_RC_PHY_HT_40_SS, 108000,
270 92900, 5, 5, 8, 47, 47, 47 }, /* 108 Mb */ 270 92900, 5, 5 }, /* 108 Mb */
271 [48] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 121500, 271 [48] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 121500,
272 102700, 6, 6, 8, 48, 48, 48 }, /* 121.5 Mb */ 272 102700, 6, 6 }, /* 121.5 Mb */
273 [49] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 135000, 273 [49] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS, 135000,
274 112000, 7, 7, 8, 49, 50, 50 }, /* 135 Mb */ 274 112000, 7, 7 }, /* 135 Mb */
275 [50] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS_HGI, 150000, 275 [50] = { RC_HT_S_40, WLAN_RC_PHY_HT_40_SS_HGI, 150000,
276 122000, 7, 7, 8, 49, 50, 50 }, /* 150 Mb */ 276 122000, 7, 7 }, /* 150 Mb */
277 [51] = { RC_INVALID, WLAN_RC_PHY_HT_40_DS, 27000, 277 [51] = { RC_INVALID, WLAN_RC_PHY_HT_40_DS, 27000,
278 25800, 8, 8, 8, 51, 51, 51 }, /* 27 Mb */ 278 25800, 8, 8 }, /* 27 Mb */
279 [52] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_DS, 54000, 279 [52] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_DS, 54000,
280 49800, 9, 9, 8, 52, 52, 52 }, /* 54 Mb */ 280 49800, 9, 9 }, /* 54 Mb */
281 [53] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_DS, 81000, 281 [53] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_DS, 81000,
282 71900, 10, 10, 8, 53, 53, 53 }, /* 81 Mb */ 282 71900, 10, 10 }, /* 81 Mb */
283 [54] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 108000, 283 [54] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 108000,
284 92500, 11, 11, 8, 54, 54, 54 }, /* 108 Mb */ 284 92500, 11, 11 }, /* 108 Mb */
285 [55] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 162000, 285 [55] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 162000,
286 130300, 12, 12, 8, 55, 55, 55 }, /* 162 Mb */ 286 130300, 12, 12 }, /* 162 Mb */
287 [56] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 216000, 287 [56] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 216000,
288 162800, 13, 13, 8, 56, 56, 56 }, /* 216 Mb */ 288 162800, 13, 13 }, /* 216 Mb */
289 [57] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 243000, 289 [57] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 243000,
290 178200, 14, 14, 8, 57, 57, 57 }, /* 243 Mb */ 290 178200, 14, 14 }, /* 243 Mb */
291 [58] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 270000, 291 [58] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS, 270000,
292 192100, 15, 15, 8, 58, 59, 59 }, /* 270 Mb */ 292 192100, 15, 15 }, /* 270 Mb */
293 [59] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS_HGI, 300000, 293 [59] = { RC_HT_DT_40, WLAN_RC_PHY_HT_40_DS_HGI, 300000,
294 207000, 15, 15, 8, 58, 59, 59 }, /* 300 Mb */ 294 207000, 15, 15 }, /* 300 Mb */
295 [60] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 40500, 295 [60] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 40500,
296 36100, 16, 16, 8, 60, 60, 60 }, /* 40.5 Mb */ 296 36100, 16, 16 }, /* 40.5 Mb */
297 [61] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 81000, 297 [61] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 81000,
298 72900, 17, 17, 8, 61, 61, 61 }, /* 81 Mb */ 298 72900, 17, 17 }, /* 81 Mb */
299 [62] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 121500, 299 [62] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 121500,
300 108300, 18, 18, 8, 62, 62, 62 }, /* 121.5 Mb */ 300 108300, 18, 18 }, /* 121.5 Mb */
301 [63] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 162000, 301 [63] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 162000,
302 142000, 19, 19, 8, 63, 63, 63 }, /* 162 Mb */ 302 142000, 19, 19 }, /* 162 Mb */
303 [64] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 243000, 303 [64] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS, 243000,
304 205100, 20, 20, 8, 64, 65, 65 }, /* 243 Mb */ 304 205100, 20, 20 }, /* 243 Mb */
305 [65] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS_HGI, 270000, 305 [65] = { RC_INVALID, WLAN_RC_PHY_HT_40_TS_HGI, 270000,
306 224700, 20, 20, 8, 64, 65, 65 }, /* 270 Mb */ 306 224700, 20, 20 }, /* 270 Mb */
307 [66] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 324000, 307 [66] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 324000,
308 263100, 21, 21, 8, 66, 67, 67 }, /* 324 Mb */ 308 263100, 21, 21 }, /* 324 Mb */
309 [67] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 360000, 309 [67] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 360000,
310 288000, 21, 21, 8, 66, 67, 67 }, /* 360 Mb */ 310 288000, 21, 21 }, /* 360 Mb */
311 [68] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 364500, 311 [68] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 364500,
312 290700, 22, 22, 8, 68, 69, 69 }, /* 364.5 Mb */ 312 290700, 22, 22 }, /* 364.5 Mb */
313 [69] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 405000, 313 [69] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 405000,
314 317200, 22, 22, 8, 68, 69, 69 }, /* 405 Mb */ 314 317200, 22, 22 }, /* 405 Mb */
315 [70] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 405000, 315 [70] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS, 405000,
316 317200, 23, 23, 8, 70, 71, 71 }, /* 405 Mb */ 316 317200, 23, 23 }, /* 405 Mb */
317 [71] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 450000, 317 [71] = { RC_HT_T_40, WLAN_RC_PHY_HT_40_TS_HGI, 450000,
318 346400, 23, 23, 8, 70, 71, 71 }, /* 450 Mb */ 318 346400, 23, 23 }, /* 450 Mb */
319 }, 319 },
320 50, /* probe interval */ 320 50, /* probe interval */
321 WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ 321 WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
@@ -326,21 +326,21 @@ static const struct ath_rate_table ar5416_11a_ratetable = {
326 0, 326 0,
327 { 327 {
328 { RC_L_SDT, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */ 328 { RC_L_SDT, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */
329 5400, 0, 12, 0}, 329 5400, 0, 12},
330 { RC_L_SDT, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */ 330 { RC_L_SDT, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */
331 7800, 1, 18, 0}, 331 7800, 1, 18},
332 { RC_L_SDT, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */ 332 { RC_L_SDT, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */
333 10000, 2, 24, 2}, 333 10000, 2, 24},
334 { RC_L_SDT, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */ 334 { RC_L_SDT, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */
335 13900, 3, 36, 2}, 335 13900, 3, 36},
336 { RC_L_SDT, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */ 336 { RC_L_SDT, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */
337 17300, 4, 48, 4}, 337 17300, 4, 48},
338 { RC_L_SDT, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */ 338 { RC_L_SDT, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */
339 23000, 5, 72, 4}, 339 23000, 5, 72},
340 { RC_L_SDT, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */ 340 { RC_L_SDT, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */
341 27400, 6, 96, 4}, 341 27400, 6, 96},
342 { RC_L_SDT, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */ 342 { RC_L_SDT, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */
343 29300, 7, 108, 4}, 343 29300, 7, 108},
344 }, 344 },
345 50, /* probe interval */ 345 50, /* probe interval */
346 0, /* Phy rates allowed initially */ 346 0, /* Phy rates allowed initially */
@@ -351,63 +351,62 @@ static const struct ath_rate_table ar5416_11g_ratetable = {
351 0, 351 0,
352 { 352 {
353 { RC_L_SDT, WLAN_RC_PHY_CCK, 1000, /* 1 Mb */ 353 { RC_L_SDT, WLAN_RC_PHY_CCK, 1000, /* 1 Mb */
354 900, 0, 2, 0}, 354 900, 0, 2},
355 { RC_L_SDT, WLAN_RC_PHY_CCK, 2000, /* 2 Mb */ 355 { RC_L_SDT, WLAN_RC_PHY_CCK, 2000, /* 2 Mb */
356 1900, 1, 4, 1}, 356 1900, 1, 4},
357 { RC_L_SDT, WLAN_RC_PHY_CCK, 5500, /* 5.5 Mb */ 357 { RC_L_SDT, WLAN_RC_PHY_CCK, 5500, /* 5.5 Mb */
358 4900, 2, 11, 2}, 358 4900, 2, 11},
359 { RC_L_SDT, WLAN_RC_PHY_CCK, 11000, /* 11 Mb */ 359 { RC_L_SDT, WLAN_RC_PHY_CCK, 11000, /* 11 Mb */
360 8100, 3, 22, 3}, 360 8100, 3, 22},
361 { RC_INVALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */ 361 { RC_INVALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */
362 5400, 4, 12, 4}, 362 5400, 4, 12},
363 { RC_INVALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */ 363 { RC_INVALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */
364 7800, 5, 18, 4}, 364 7800, 5, 18},
365 { RC_L_SDT, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */ 365 { RC_L_SDT, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */
366 10000, 6, 24, 6}, 366 10000, 6, 24},
367 { RC_L_SDT, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */ 367 { RC_L_SDT, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */
368 13900, 7, 36, 6}, 368 13900, 7, 36},
369 { RC_L_SDT, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */ 369 { RC_L_SDT, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */
370 17300, 8, 48, 8}, 370 17300, 8, 48},
371 { RC_L_SDT, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */ 371 { RC_L_SDT, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */
372 23000, 9, 72, 8}, 372 23000, 9, 72},
373 { RC_L_SDT, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */ 373 { RC_L_SDT, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */
374 27400, 10, 96, 8}, 374 27400, 10, 96},
375 { RC_L_SDT, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */ 375 { RC_L_SDT, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */
376 29300, 11, 108, 8}, 376 29300, 11, 108},
377 }, 377 },
378 50, /* probe interval */ 378 50, /* probe interval */
379 0, /* Phy rates allowed initially */ 379 0, /* Phy rates allowed initially */
380}; 380};
381 381
382static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table, 382static int ath_rc_get_rateindex(struct ath_rate_priv *ath_rc_priv,
383 struct ieee80211_tx_rate *rate) 383 struct ieee80211_tx_rate *rate)
384{ 384{
385 int rix = 0, i = 0; 385 const struct ath_rate_table *rate_table = ath_rc_priv->rate_table;
386 static const int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 }; 386 int rix, i, idx = 0;
387 387
388 if (!(rate->flags & IEEE80211_TX_RC_MCS)) 388 if (!(rate->flags & IEEE80211_TX_RC_MCS))
389 return rate->idx; 389 return rate->idx;
390 390
391 while (i < ARRAY_SIZE(mcs_rix_off) && rate->idx > mcs_rix_off[i]) { 391 for (i = 0; i < ath_rc_priv->max_valid_rate; i++) {
392 rix++; i++; 392 idx = ath_rc_priv->valid_rate_index[i];
393
394 if (WLAN_RC_PHY_HT(rate_table->info[idx].phy) &&
395 rate_table->info[idx].ratecode == rate->idx)
396 break;
393 } 397 }
394 398
395 rix += rate->idx + rate_table->mcs_start; 399 rix = idx;
396 400
397 if ((rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) && 401 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
398 (rate->flags & IEEE80211_TX_RC_SHORT_GI)) 402 rix++;
399 rix = rate_table->info[rix].ht_index;
400 else if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
401 rix = rate_table->info[rix].sgi_index;
402 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
403 rix = rate_table->info[rix].cw40index;
404 403
405 return rix; 404 return rix;
406} 405}
407 406
408static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table, 407static void ath_rc_sort_validrates(struct ath_rate_priv *ath_rc_priv)
409 struct ath_rate_priv *ath_rc_priv)
410{ 408{
409 const struct ath_rate_table *rate_table = ath_rc_priv->rate_table;
411 u8 i, j, idx, idx_next; 410 u8 i, j, idx, idx_next;
412 411
413 for (i = ath_rc_priv->max_valid_rate - 1; i > 0; i--) { 412 for (i = ath_rc_priv->max_valid_rate - 1; i > 0; i--) {
@@ -424,21 +423,6 @@ static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
424 } 423 }
425} 424}
426 425
427static void ath_rc_init_valid_rate_idx(struct ath_rate_priv *ath_rc_priv)
428{
429 u8 i;
430
431 for (i = 0; i < ath_rc_priv->rate_table_size; i++)
432 ath_rc_priv->valid_rate_index[i] = 0;
433}
434
435static inline void ath_rc_set_valid_rate_idx(struct ath_rate_priv *ath_rc_priv,
436 u8 index, int valid_tx_rate)
437{
438 BUG_ON(index > ath_rc_priv->rate_table_size);
439 ath_rc_priv->valid_rate_index[index] = !!valid_tx_rate;
440}
441
442static inline 426static inline
443int ath_rc_get_nextvalid_txrate(const struct ath_rate_table *rate_table, 427int ath_rc_get_nextvalid_txrate(const struct ath_rate_table *rate_table,
444 struct ath_rate_priv *ath_rc_priv, 428 struct ath_rate_priv *ath_rc_priv,
@@ -479,8 +463,7 @@ static int ath_rc_valid_phyrate(u32 phy, u32 capflag, int ignore_cw)
479} 463}
480 464
481static inline int 465static inline int
482ath_rc_get_lower_rix(const struct ath_rate_table *rate_table, 466ath_rc_get_lower_rix(struct ath_rate_priv *ath_rc_priv,
483 struct ath_rate_priv *ath_rc_priv,
484 u8 cur_valid_txrate, u8 *next_idx) 467 u8 cur_valid_txrate, u8 *next_idx)
485{ 468{
486 int8_t i; 469 int8_t i;
@@ -495,10 +478,9 @@ ath_rc_get_lower_rix(const struct ath_rate_table *rate_table,
495 return 0; 478 return 0;
496} 479}
497 480
498static u8 ath_rc_init_validrates(struct ath_rate_priv *ath_rc_priv, 481static u8 ath_rc_init_validrates(struct ath_rate_priv *ath_rc_priv)
499 const struct ath_rate_table *rate_table,
500 u32 capflag)
501{ 482{
483 const struct ath_rate_table *rate_table = ath_rc_priv->rate_table;
502 u8 i, hi = 0; 484 u8 i, hi = 0;
503 485
504 for (i = 0; i < rate_table->rate_cnt; i++) { 486 for (i = 0; i < rate_table->rate_cnt; i++) {
@@ -506,14 +488,14 @@ static u8 ath_rc_init_validrates(struct ath_rate_priv *ath_rc_priv,
506 u32 phy = rate_table->info[i].phy; 488 u32 phy = rate_table->info[i].phy;
507 u8 valid_rate_count = 0; 489 u8 valid_rate_count = 0;
508 490
509 if (!ath_rc_valid_phyrate(phy, capflag, 0)) 491 if (!ath_rc_valid_phyrate(phy, ath_rc_priv->ht_cap, 0))
510 continue; 492 continue;
511 493
512 valid_rate_count = ath_rc_priv->valid_phy_ratecnt[phy]; 494 valid_rate_count = ath_rc_priv->valid_phy_ratecnt[phy];
513 495
514 ath_rc_priv->valid_phy_rateidx[phy][valid_rate_count] = i; 496 ath_rc_priv->valid_phy_rateidx[phy][valid_rate_count] = i;
515 ath_rc_priv->valid_phy_ratecnt[phy] += 1; 497 ath_rc_priv->valid_phy_ratecnt[phy] += 1;
516 ath_rc_set_valid_rate_idx(ath_rc_priv, i, 1); 498 ath_rc_priv->valid_rate_index[i] = true;
517 hi = i; 499 hi = i;
518 } 500 }
519 } 501 }
@@ -521,76 +503,73 @@ static u8 ath_rc_init_validrates(struct ath_rate_priv *ath_rc_priv,
521 return hi; 503 return hi;
522} 504}
523 505
524static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv, 506static inline bool ath_rc_check_legacy(u8 rate, u8 dot11rate, u16 rate_flags,
525 const struct ath_rate_table *rate_table, 507 u32 phy, u32 capflag)
526 struct ath_rateset *rateset,
527 u32 capflag)
528{ 508{
529 u8 i, j, hi = 0; 509 if (rate != dot11rate || WLAN_RC_PHY_HT(phy))
510 return false;
530 511
531 /* Use intersection of working rates and valid rates */ 512 if ((rate_flags & WLAN_RC_CAP_MODE(capflag)) != WLAN_RC_CAP_MODE(capflag))
532 for (i = 0; i < rateset->rs_nrates; i++) { 513 return false;
533 for (j = 0; j < rate_table->rate_cnt; j++) {
534 u32 phy = rate_table->info[j].phy;
535 u16 rate_flags = rate_table->info[j].rate_flags;
536 u8 rate = rateset->rs_rates[i];
537 u8 dot11rate = rate_table->info[j].dot11rate;
538
539 /* We allow a rate only if its valid and the
540 * capflag matches one of the validity
541 * (VALID/VALID_20/VALID_40) flags */
542
543 if ((rate == dot11rate) &&
544 (rate_flags & WLAN_RC_CAP_MODE(capflag)) ==
545 WLAN_RC_CAP_MODE(capflag) &&
546 (rate_flags & WLAN_RC_CAP_STREAM(capflag)) &&
547 !WLAN_RC_PHY_HT(phy)) {
548 u8 valid_rate_count = 0;
549
550 if (!ath_rc_valid_phyrate(phy, capflag, 0))
551 continue;
552
553 valid_rate_count =
554 ath_rc_priv->valid_phy_ratecnt[phy];
555
556 ath_rc_priv->valid_phy_rateidx[phy]
557 [valid_rate_count] = j;
558 ath_rc_priv->valid_phy_ratecnt[phy] += 1;
559 ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
560 hi = max(hi, j);
561 }
562 }
563 }
564 514
565 return hi; 515 if (!(rate_flags & WLAN_RC_CAP_STREAM(capflag)))
516 return false;
517
518 return true;
566} 519}
567 520
568static u8 ath_rc_setvalid_htrates(struct ath_rate_priv *ath_rc_priv, 521static inline bool ath_rc_check_ht(u8 rate, u8 dot11rate, u16 rate_flags,
569 const struct ath_rate_table *rate_table, 522 u32 phy, u32 capflag)
570 struct ath_rateset *rateset, u32 capflag)
571{ 523{
572 u8 i, j, hi = 0; 524 if (rate != dot11rate || !WLAN_RC_PHY_HT(phy))
525 return false;
526
527 if (!WLAN_RC_PHY_HT_VALID(rate_flags, capflag))
528 return false;
529
530 if (!(rate_flags & WLAN_RC_CAP_STREAM(capflag)))
531 return false;
532
533 return true;
534}
535
536static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv, bool legacy)
537{
538 const struct ath_rate_table *rate_table = ath_rc_priv->rate_table;
539 struct ath_rateset *rateset;
540 u32 phy, capflag = ath_rc_priv->ht_cap;
541 u16 rate_flags;
542 u8 i, j, hi = 0, rate, dot11rate, valid_rate_count;
543
544 if (legacy)
545 rateset = &ath_rc_priv->neg_rates;
546 else
547 rateset = &ath_rc_priv->neg_ht_rates;
573 548
574 /* Use intersection of working rates and valid rates */
575 for (i = 0; i < rateset->rs_nrates; i++) { 549 for (i = 0; i < rateset->rs_nrates; i++) {
576 for (j = 0; j < rate_table->rate_cnt; j++) { 550 for (j = 0; j < rate_table->rate_cnt; j++) {
577 u32 phy = rate_table->info[j].phy; 551 phy = rate_table->info[j].phy;
578 u16 rate_flags = rate_table->info[j].rate_flags; 552 rate_flags = rate_table->info[j].rate_flags;
579 u8 rate = rateset->rs_rates[i]; 553 rate = rateset->rs_rates[i];
580 u8 dot11rate = rate_table->info[j].dot11rate; 554 dot11rate = rate_table->info[j].dot11rate;
581 555
582 if ((rate != dot11rate) || !WLAN_RC_PHY_HT(phy) || 556 if (legacy &&
583 !(rate_flags & WLAN_RC_CAP_STREAM(capflag)) || 557 !ath_rc_check_legacy(rate, dot11rate,
584 !WLAN_RC_PHY_HT_VALID(rate_flags, capflag)) 558 rate_flags, phy, capflag))
559 continue;
560
561 if (!legacy &&
562 !ath_rc_check_ht(rate, dot11rate,
563 rate_flags, phy, capflag))
585 continue; 564 continue;
586 565
587 if (!ath_rc_valid_phyrate(phy, capflag, 0)) 566 if (!ath_rc_valid_phyrate(phy, capflag, 0))
588 continue; 567 continue;
589 568
590 ath_rc_priv->valid_phy_rateidx[phy] 569 valid_rate_count = ath_rc_priv->valid_phy_ratecnt[phy];
591 [ath_rc_priv->valid_phy_ratecnt[phy]] = j; 570 ath_rc_priv->valid_phy_rateidx[phy][valid_rate_count] = j;
592 ath_rc_priv->valid_phy_ratecnt[phy] += 1; 571 ath_rc_priv->valid_phy_ratecnt[phy] += 1;
593 ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1); 572 ath_rc_priv->valid_rate_index[j] = true;
594 hi = max(hi, j); 573 hi = max(hi, j);
595 } 574 }
596 } 575 }
@@ -598,13 +577,10 @@ static u8 ath_rc_setvalid_htrates(struct ath_rate_priv *ath_rc_priv,
598 return hi; 577 return hi;
599} 578}
600 579
601/* Finds the highest rate index we can use */ 580static u8 ath_rc_get_highest_rix(struct ath_rate_priv *ath_rc_priv,
602static u8 ath_rc_get_highest_rix(struct ath_softc *sc, 581 int *is_probing)
603 struct ath_rate_priv *ath_rc_priv,
604 const struct ath_rate_table *rate_table,
605 int *is_probing,
606 bool legacy)
607{ 582{
583 const struct ath_rate_table *rate_table = ath_rc_priv->rate_table;
608 u32 best_thruput, this_thruput, now_msec; 584 u32 best_thruput, this_thruput, now_msec;
609 u8 rate, next_rate, best_rate, maxindex, minindex; 585 u8 rate, next_rate, best_rate, maxindex, minindex;
610 int8_t index = 0; 586 int8_t index = 0;
@@ -624,8 +600,6 @@ static u8 ath_rc_get_highest_rix(struct ath_softc *sc,
624 u8 per_thres; 600 u8 per_thres;
625 601
626 rate = ath_rc_priv->valid_rate_index[index]; 602 rate = ath_rc_priv->valid_rate_index[index];
627 if (legacy && !(rate_table->info[rate].rate_flags & RC_LEGACY))
628 continue;
629 if (rate > ath_rc_priv->rate_max_phy) 603 if (rate > ath_rc_priv->rate_max_phy)
630 continue; 604 continue;
631 605
@@ -707,8 +681,6 @@ static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table,
707 rate->count = tries; 681 rate->count = tries;
708 rate->idx = rate_table->info[rix].ratecode; 682 rate->idx = rate_table->info[rix].ratecode;
709 683
710 if (txrc->short_preamble)
711 rate->flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
712 if (txrc->rts || rtsctsenable) 684 if (txrc->rts || rtsctsenable)
713 rate->flags |= IEEE80211_TX_RC_USE_RTS_CTS; 685 rate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
714 686
@@ -726,37 +698,25 @@ static void ath_rc_rate_set_rtscts(struct ath_softc *sc,
726 const struct ath_rate_table *rate_table, 698 const struct ath_rate_table *rate_table,
727 struct ieee80211_tx_info *tx_info) 699 struct ieee80211_tx_info *tx_info)
728{ 700{
729 struct ieee80211_tx_rate *rates = tx_info->control.rates; 701 struct ieee80211_bss_conf *bss_conf;
730 int i = 0, rix = 0, cix, enable_g_protection = 0;
731 702
732 /* get the cix for the lowest valid rix */ 703 if (!tx_info->control.vif)
733 for (i = 3; i >= 0; i--) { 704 return;
734 if (rates[i].count && (rates[i].idx >= 0)) { 705 /*
735 rix = ath_rc_get_rateindex(rate_table, &rates[i]); 706 * For legacy frames, mac80211 takes care of CTS protection.
736 break; 707 */
737 } 708 if (!(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS))
738 } 709 return;
739 cix = rate_table->info[rix].ctrl_rate;
740 710
741 /* All protection frames are transmited at 2Mb/s for 802.11g, 711 bss_conf = &tx_info->control.vif->bss_conf;
742 * otherwise we transmit them at 1Mb/s */ 712
743 if (sc->hw->conf.channel->band == IEEE80211_BAND_2GHZ && 713 if (!bss_conf->basic_rates)
744 !conf_is_ht(&sc->hw->conf)) 714 return;
745 enable_g_protection = 1;
746 715
747 /* 716 /*
748 * If 802.11g protection is enabled, determine whether to use RTS/CTS or 717 * For now, use the lowest allowed basic rate for HT frames.
749 * just CTS. Note that this is only done for OFDM/HT unicast frames.
750 */ 718 */
751 if ((tx_info->control.vif && 719 tx_info->control.rts_cts_rate_idx = __ffs(bss_conf->basic_rates);
752 tx_info->control.vif->bss_conf.use_cts_prot) &&
753 (rate_table->info[rix].phy == WLAN_RC_PHY_OFDM ||
754 WLAN_RC_PHY_HT(rate_table->info[rix].phy))) {
755 rates[0].flags |= IEEE80211_TX_RC_USE_CTS_PROTECT;
756 cix = rate_table->info[enable_g_protection].ctrl_rate;
757 }
758
759 tx_info->control.rts_cts_rate_idx = cix;
760} 720}
761 721
762static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta, 722static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
@@ -789,14 +749,8 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
789 try_per_rate = 4; 749 try_per_rate = 4;
790 750
791 rate_table = ath_rc_priv->rate_table; 751 rate_table = ath_rc_priv->rate_table;
792 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, 752 rix = ath_rc_get_highest_rix(ath_rc_priv, &is_probe);
793 &is_probe, false);
794 753
795 /*
796 * If we're in HT mode and both us and our peer supports LDPC.
797 * We don't need to check our own device's capabilities as our own
798 * ht capabilities would have already been intersected with our peer's.
799 */
800 if (conf_is_ht(&sc->hw->conf) && 754 if (conf_is_ht(&sc->hw->conf) &&
801 (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)) 755 (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
802 tx_info->flags |= IEEE80211_TX_CTL_LDPC; 756 tx_info->flags |= IEEE80211_TX_CTL_LDPC;
@@ -806,52 +760,45 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
806 tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT); 760 tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
807 761
808 if (is_probe) { 762 if (is_probe) {
809 /* set one try for probe rates. For the 763 /*
810 * probes don't enable rts */ 764 * Set one try for probe rates. For the
765 * probes don't enable RTS.
766 */
811 ath_rc_rate_set_series(rate_table, &rates[i++], txrc, 767 ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
812 1, rix, 0); 768 1, rix, 0);
813 769 /*
814 /* Get the next tried/allowed rate. No RTS for the next series 770 * Get the next tried/allowed rate.
815 * after the probe rate 771 * No RTS for the next series after the probe rate.
816 */ 772 */
817 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &rix); 773 ath_rc_get_lower_rix(ath_rc_priv, rix, &rix);
818 ath_rc_rate_set_series(rate_table, &rates[i++], txrc, 774 ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
819 try_per_rate, rix, 0); 775 try_per_rate, rix, 0);
820 776
821 tx_info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE; 777 tx_info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
822 } else { 778 } else {
823 /* Set the chosen rate. No RTS for first series entry. */ 779 /*
780 * Set the chosen rate. No RTS for first series entry.
781 */
824 ath_rc_rate_set_series(rate_table, &rates[i++], txrc, 782 ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
825 try_per_rate, rix, 0); 783 try_per_rate, rix, 0);
826 } 784 }
827 785
828 /* Fill in the other rates for multirate retry */ 786 for ( ; i < 4; i++) {
829 for ( ; i < 3; i++) { 787 /*
788 * Use twice the number of tries for the last MRR segment.
789 */
790 if (i + 1 == 4)
791 try_per_rate = 8;
792
793 ath_rc_get_lower_rix(ath_rc_priv, rix, &rix);
830 794
831 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &rix); 795 /*
832 /* All other rates in the series have RTS enabled */ 796 * All other rates in the series have RTS enabled.
797 */
833 ath_rc_rate_set_series(rate_table, &rates[i], txrc, 798 ath_rc_rate_set_series(rate_table, &rates[i], txrc,
834 try_per_rate, rix, 1); 799 try_per_rate, rix, 1);
835 } 800 }
836 801
837 /* Use twice the number of tries for the last MRR segment. */
838 try_per_rate = 8;
839
840 /*
841 * If the last rate in the rate series is MCS and has
842 * more than 80% of per thresh, then use a legacy rate
843 * as last retry to ensure that the frame is tried in both
844 * MCS and legacy rate.
845 */
846 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &rix);
847 if (WLAN_RC_PHY_HT(rate_table->info[rix].phy) &&
848 (ath_rc_priv->per[rix] > 45))
849 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table,
850 &is_probe, true);
851
852 /* All other rates in the series have RTS enabled */
853 ath_rc_rate_set_series(rate_table, &rates[i], txrc,
854 try_per_rate, rix, 1);
855 /* 802 /*
856 * NB:Change rate series to enable aggregation when operating 803 * NB:Change rate series to enable aggregation when operating
857 * at lower MCS rates. When first rate in series is MCS2 804 * at lower MCS rates. When first rate in series is MCS2
@@ -893,7 +840,6 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
893 rates[0].count = ATH_TXMAXTRY; 840 rates[0].count = ATH_TXMAXTRY;
894 } 841 }
895 842
896 /* Setup RTS/CTS */
897 ath_rc_rate_set_rtscts(sc, rate_table, tx_info); 843 ath_rc_rate_set_rtscts(sc, rate_table, tx_info);
898} 844}
899 845
@@ -1046,9 +992,6 @@ static void ath_debug_stat_retries(struct ath_rate_priv *rc, int rix,
1046 stats->per = per; 992 stats->per = per;
1047} 993}
1048 994
1049/* Update PER, RSSI and whatever else that the code thinks it is doing.
1050 If you can make sense of all this, you really need to go out more. */
1051
1052static void ath_rc_update_ht(struct ath_softc *sc, 995static void ath_rc_update_ht(struct ath_softc *sc,
1053 struct ath_rate_priv *ath_rc_priv, 996 struct ath_rate_priv *ath_rc_priv,
1054 struct ieee80211_tx_info *tx_info, 997 struct ieee80211_tx_info *tx_info,
@@ -1077,8 +1020,8 @@ static void ath_rc_update_ht(struct ath_softc *sc,
1077 if (ath_rc_priv->per[tx_rate] >= 55 && tx_rate > 0 && 1020 if (ath_rc_priv->per[tx_rate] >= 55 && tx_rate > 0 &&
1078 rate_table->info[tx_rate].ratekbps <= 1021 rate_table->info[tx_rate].ratekbps <=
1079 rate_table->info[ath_rc_priv->rate_max_phy].ratekbps) { 1022 rate_table->info[ath_rc_priv->rate_max_phy].ratekbps) {
1080 ath_rc_get_lower_rix(rate_table, ath_rc_priv, 1023 ath_rc_get_lower_rix(ath_rc_priv, (u8)tx_rate,
1081 (u8)tx_rate, &ath_rc_priv->rate_max_phy); 1024 &ath_rc_priv->rate_max_phy);
1082 1025
1083 /* Don't probe for a little while. */ 1026 /* Don't probe for a little while. */
1084 ath_rc_priv->probe_time = now_msec; 1027 ath_rc_priv->probe_time = now_msec;
@@ -1122,25 +1065,42 @@ static void ath_rc_update_ht(struct ath_softc *sc,
1122 1065
1123} 1066}
1124 1067
1068static void ath_debug_stat_rc(struct ath_rate_priv *rc, int final_rate)
1069{
1070 struct ath_rc_stats *stats;
1071
1072 stats = &rc->rcstats[final_rate];
1073 stats->success++;
1074}
1125 1075
1126static void ath_rc_tx_status(struct ath_softc *sc, 1076static void ath_rc_tx_status(struct ath_softc *sc,
1127 struct ath_rate_priv *ath_rc_priv, 1077 struct ath_rate_priv *ath_rc_priv,
1128 struct ieee80211_tx_info *tx_info, 1078 struct sk_buff *skb)
1129 int final_ts_idx, int xretries, int long_retry)
1130{ 1079{
1131 const struct ath_rate_table *rate_table; 1080 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1132 struct ieee80211_tx_rate *rates = tx_info->status.rates; 1081 struct ieee80211_tx_rate *rates = tx_info->status.rates;
1082 struct ieee80211_tx_rate *rate;
1083 int final_ts_idx = 0, xretries = 0, long_retry = 0;
1133 u8 flags; 1084 u8 flags;
1134 u32 i = 0, rix; 1085 u32 i = 0, rix;
1135 1086
1136 rate_table = ath_rc_priv->rate_table; 1087 for (i = 0; i < sc->hw->max_rates; i++) {
1088 rate = &tx_info->status.rates[i];
1089 if (rate->idx < 0 || !rate->count)
1090 break;
1091
1092 final_ts_idx = i;
1093 long_retry = rate->count - 1;
1094 }
1095
1096 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK))
1097 xretries = 1;
1137 1098
1138 /* 1099 /*
1139 * If the first rate is not the final index, there 1100 * If the first rate is not the final index, there
1140 * are intermediate rate failures to be processed. 1101 * are intermediate rate failures to be processed.
1141 */ 1102 */
1142 if (final_ts_idx != 0) { 1103 if (final_ts_idx != 0) {
1143 /* Process intermediate rates that failed.*/
1144 for (i = 0; i < final_ts_idx ; i++) { 1104 for (i = 0; i < final_ts_idx ; i++) {
1145 if (rates[i].count != 0 && (rates[i].idx >= 0)) { 1105 if (rates[i].count != 0 && (rates[i].idx >= 0)) {
1146 flags = rates[i].flags; 1106 flags = rates[i].flags;
@@ -1152,32 +1112,24 @@ static void ath_rc_tx_status(struct ath_softc *sc,
1152 !(ath_rc_priv->ht_cap & WLAN_RC_40_FLAG)) 1112 !(ath_rc_priv->ht_cap & WLAN_RC_40_FLAG))
1153 return; 1113 return;
1154 1114
1155 rix = ath_rc_get_rateindex(rate_table, &rates[i]); 1115 rix = ath_rc_get_rateindex(ath_rc_priv, &rates[i]);
1156 ath_rc_update_ht(sc, ath_rc_priv, tx_info, 1116 ath_rc_update_ht(sc, ath_rc_priv, tx_info,
1157 rix, xretries ? 1 : 2, 1117 rix, xretries ? 1 : 2,
1158 rates[i].count); 1118 rates[i].count);
1159 } 1119 }
1160 } 1120 }
1161 } else {
1162 /*
1163 * Handle the special case of MIMO PS burst, where the second
1164 * aggregate is sent out with only one rate and one try.
1165 * Treating it as an excessive retry penalizes the rate
1166 * inordinately.
1167 */
1168 if (rates[0].count == 1 && xretries == 1)
1169 xretries = 2;
1170 } 1121 }
1171 1122
1172 flags = rates[i].flags; 1123 flags = rates[final_ts_idx].flags;
1173 1124
1174 /* If HT40 and we have switched mode from 40 to 20 => don't update */ 1125 /* If HT40 and we have switched mode from 40 to 20 => don't update */
1175 if ((flags & IEEE80211_TX_RC_40_MHZ_WIDTH) && 1126 if ((flags & IEEE80211_TX_RC_40_MHZ_WIDTH) &&
1176 !(ath_rc_priv->ht_cap & WLAN_RC_40_FLAG)) 1127 !(ath_rc_priv->ht_cap & WLAN_RC_40_FLAG))
1177 return; 1128 return;
1178 1129
1179 rix = ath_rc_get_rateindex(rate_table, &rates[i]); 1130 rix = ath_rc_get_rateindex(ath_rc_priv, &rates[final_ts_idx]);
1180 ath_rc_update_ht(sc, ath_rc_priv, tx_info, rix, xretries, long_retry); 1131 ath_rc_update_ht(sc, ath_rc_priv, tx_info, rix, xretries, long_retry);
1132 ath_debug_stat_rc(ath_rc_priv, rix);
1181} 1133}
1182 1134
1183static const 1135static const
@@ -1185,8 +1137,6 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1185 enum ieee80211_band band, 1137 enum ieee80211_band band,
1186 bool is_ht) 1138 bool is_ht)
1187{ 1139{
1188 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1189
1190 switch(band) { 1140 switch(band) {
1191 case IEEE80211_BAND_2GHZ: 1141 case IEEE80211_BAND_2GHZ:
1192 if (is_ht) 1142 if (is_ht)
@@ -1197,34 +1147,25 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1197 return &ar5416_11na_ratetable; 1147 return &ar5416_11na_ratetable;
1198 return &ar5416_11a_ratetable; 1148 return &ar5416_11a_ratetable;
1199 default: 1149 default:
1200 ath_dbg(common, CONFIG, "Invalid band\n");
1201 return NULL; 1150 return NULL;
1202 } 1151 }
1203} 1152}
1204 1153
1205static void ath_rc_init(struct ath_softc *sc, 1154static void ath_rc_init(struct ath_softc *sc,
1206 struct ath_rate_priv *ath_rc_priv, 1155 struct ath_rate_priv *ath_rc_priv)
1207 struct ieee80211_supported_band *sband,
1208 struct ieee80211_sta *sta,
1209 const struct ath_rate_table *rate_table)
1210{ 1156{
1157 const struct ath_rate_table *rate_table = ath_rc_priv->rate_table;
1211 struct ath_rateset *rateset = &ath_rc_priv->neg_rates; 1158 struct ath_rateset *rateset = &ath_rc_priv->neg_rates;
1212 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1159 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1213 struct ath_rateset *ht_mcs = &ath_rc_priv->neg_ht_rates;
1214 u8 i, j, k, hi = 0, hthi = 0; 1160 u8 i, j, k, hi = 0, hthi = 0;
1215 1161
1216 /* Initial rate table size. Will change depending
1217 * on the working rate set */
1218 ath_rc_priv->rate_table_size = RATE_TABLE_SIZE; 1162 ath_rc_priv->rate_table_size = RATE_TABLE_SIZE;
1219 1163
1220 /* Initialize thresholds according to the global rate table */
1221 for (i = 0 ; i < ath_rc_priv->rate_table_size; i++) { 1164 for (i = 0 ; i < ath_rc_priv->rate_table_size; i++) {
1222 ath_rc_priv->per[i] = 0; 1165 ath_rc_priv->per[i] = 0;
1166 ath_rc_priv->valid_rate_index[i] = 0;
1223 } 1167 }
1224 1168
1225 /* Determine the valid rates */
1226 ath_rc_init_valid_rate_idx(ath_rc_priv);
1227
1228 for (i = 0; i < WLAN_RC_PHY_MAX; i++) { 1169 for (i = 0; i < WLAN_RC_PHY_MAX; i++) {
1229 for (j = 0; j < RATE_TABLE_SIZE; j++) 1170 for (j = 0; j < RATE_TABLE_SIZE; j++)
1230 ath_rc_priv->valid_phy_rateidx[i][j] = 0; 1171 ath_rc_priv->valid_phy_rateidx[i][j] = 0;
@@ -1232,25 +1173,19 @@ static void ath_rc_init(struct ath_softc *sc,
1232 } 1173 }
1233 1174
1234 if (!rateset->rs_nrates) { 1175 if (!rateset->rs_nrates) {
1235 /* No working rate, just initialize valid rates */ 1176 hi = ath_rc_init_validrates(ath_rc_priv);
1236 hi = ath_rc_init_validrates(ath_rc_priv, rate_table,
1237 ath_rc_priv->ht_cap);
1238 } else { 1177 } else {
1239 /* Use intersection of working rates and valid rates */ 1178 hi = ath_rc_setvalid_rates(ath_rc_priv, true);
1240 hi = ath_rc_setvalid_rates(ath_rc_priv, rate_table, 1179
1241 rateset, ath_rc_priv->ht_cap); 1180 if (ath_rc_priv->ht_cap & WLAN_RC_HT_FLAG)
1242 if (ath_rc_priv->ht_cap & WLAN_RC_HT_FLAG) { 1181 hthi = ath_rc_setvalid_rates(ath_rc_priv, false);
1243 hthi = ath_rc_setvalid_htrates(ath_rc_priv, 1182
1244 rate_table,
1245 ht_mcs,
1246 ath_rc_priv->ht_cap);
1247 }
1248 hi = max(hi, hthi); 1183 hi = max(hi, hthi);
1249 } 1184 }
1250 1185
1251 ath_rc_priv->rate_table_size = hi + 1; 1186 ath_rc_priv->rate_table_size = hi + 1;
1252 ath_rc_priv->rate_max_phy = 0; 1187 ath_rc_priv->rate_max_phy = 0;
1253 BUG_ON(ath_rc_priv->rate_table_size > RATE_TABLE_SIZE); 1188 WARN_ON(ath_rc_priv->rate_table_size > RATE_TABLE_SIZE);
1254 1189
1255 for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) { 1190 for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) {
1256 for (j = 0; j < ath_rc_priv->valid_phy_ratecnt[i]; j++) { 1191 for (j = 0; j < ath_rc_priv->valid_phy_ratecnt[i]; j++) {
@@ -1258,28 +1193,26 @@ static void ath_rc_init(struct ath_softc *sc,
1258 ath_rc_priv->valid_phy_rateidx[i][j]; 1193 ath_rc_priv->valid_phy_rateidx[i][j];
1259 } 1194 }
1260 1195
1261 if (!ath_rc_valid_phyrate(i, rate_table->initial_ratemax, 1) 1196 if (!ath_rc_valid_phyrate(i, rate_table->initial_ratemax, 1) ||
1262 || !ath_rc_priv->valid_phy_ratecnt[i]) 1197 !ath_rc_priv->valid_phy_ratecnt[i])
1263 continue; 1198 continue;
1264 1199
1265 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_phy_rateidx[i][j-1]; 1200 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_phy_rateidx[i][j-1];
1266 } 1201 }
1267 BUG_ON(ath_rc_priv->rate_table_size > RATE_TABLE_SIZE); 1202 WARN_ON(ath_rc_priv->rate_table_size > RATE_TABLE_SIZE);
1268 BUG_ON(k > RATE_TABLE_SIZE); 1203 WARN_ON(k > RATE_TABLE_SIZE);
1269 1204
1270 ath_rc_priv->max_valid_rate = k; 1205 ath_rc_priv->max_valid_rate = k;
1271 ath_rc_sort_validrates(rate_table, ath_rc_priv); 1206 ath_rc_sort_validrates(ath_rc_priv);
1272 ath_rc_priv->rate_max_phy = (k > 4) ? 1207 ath_rc_priv->rate_max_phy = (k > 4) ?
1273 ath_rc_priv->valid_rate_index[k-4] : 1208 ath_rc_priv->valid_rate_index[k-4] :
1274 ath_rc_priv->valid_rate_index[k-1]; 1209 ath_rc_priv->valid_rate_index[k-1];
1275 ath_rc_priv->rate_table = rate_table;
1276 1210
1277 ath_dbg(common, CONFIG, "RC Initialized with capabilities: 0x%x\n", 1211 ath_dbg(common, CONFIG, "RC Initialized with capabilities: 0x%x\n",
1278 ath_rc_priv->ht_cap); 1212 ath_rc_priv->ht_cap);
1279} 1213}
1280 1214
1281static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta, 1215static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta)
1282 bool is_cw40, bool is_sgi)
1283{ 1216{
1284 u8 caps = 0; 1217 u8 caps = 0;
1285 1218
@@ -1289,10 +1222,14 @@ static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
1289 caps |= WLAN_RC_TS_FLAG | WLAN_RC_DS_FLAG; 1222 caps |= WLAN_RC_TS_FLAG | WLAN_RC_DS_FLAG;
1290 else if (sta->ht_cap.mcs.rx_mask[1]) 1223 else if (sta->ht_cap.mcs.rx_mask[1])
1291 caps |= WLAN_RC_DS_FLAG; 1224 caps |= WLAN_RC_DS_FLAG;
1292 if (is_cw40) 1225 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) {
1293 caps |= WLAN_RC_40_FLAG; 1226 caps |= WLAN_RC_40_FLAG;
1294 if (is_sgi) 1227 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40)
1295 caps |= WLAN_RC_SGI_FLAG; 1228 caps |= WLAN_RC_SGI_FLAG;
1229 } else {
1230 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
1231 caps |= WLAN_RC_SGI_FLAG;
1232 }
1296 } 1233 }
1297 1234
1298 return caps; 1235 return caps;
@@ -1319,15 +1256,6 @@ static bool ath_tx_aggr_check(struct ath_softc *sc, struct ieee80211_sta *sta,
1319/* mac80211 Rate Control callbacks */ 1256/* mac80211 Rate Control callbacks */
1320/***********************************/ 1257/***********************************/
1321 1258
1322static void ath_debug_stat_rc(struct ath_rate_priv *rc, int final_rate)
1323{
1324 struct ath_rc_stats *stats;
1325
1326 stats = &rc->rcstats[final_rate];
1327 stats->success++;
1328}
1329
1330
1331static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband, 1259static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1332 struct ieee80211_sta *sta, void *priv_sta, 1260 struct ieee80211_sta *sta, void *priv_sta,
1333 struct sk_buff *skb) 1261 struct sk_buff *skb)
@@ -1335,22 +1263,8 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1335 struct ath_softc *sc = priv; 1263 struct ath_softc *sc = priv;
1336 struct ath_rate_priv *ath_rc_priv = priv_sta; 1264 struct ath_rate_priv *ath_rc_priv = priv_sta;
1337 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1265 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1338 struct ieee80211_hdr *hdr; 1266 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1339 int final_ts_idx = 0, tx_status = 0; 1267 __le16 fc = hdr->frame_control;
1340 int long_retry = 0;
1341 __le16 fc;
1342 int i;
1343
1344 hdr = (struct ieee80211_hdr *)skb->data;
1345 fc = hdr->frame_control;
1346 for (i = 0; i < sc->hw->max_rates; i++) {
1347 struct ieee80211_tx_rate *rate = &tx_info->status.rates[i];
1348 if (rate->idx < 0 || !rate->count)
1349 break;
1350
1351 final_ts_idx = i;
1352 long_retry = rate->count - 1;
1353 }
1354 1268
1355 if (!priv_sta || !ieee80211_is_data(fc)) 1269 if (!priv_sta || !ieee80211_is_data(fc))
1356 return; 1270 return;
@@ -1363,11 +1277,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1363 if (tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) 1277 if (tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED)
1364 return; 1278 return;
1365 1279
1366 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) 1280 ath_rc_tx_status(sc, ath_rc_priv, skb);
1367 tx_status = 1;
1368
1369 ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
1370 long_retry);
1371 1281
1372 /* Check if aggregation has to be enabled for this tid */ 1282 /* Check if aggregation has to be enabled for this tid */
1373 if (conf_is_ht(&sc->hw->conf) && 1283 if (conf_is_ht(&sc->hw->conf) &&
@@ -1383,19 +1293,14 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1383 ieee80211_start_tx_ba_session(sta, tid, 0); 1293 ieee80211_start_tx_ba_session(sta, tid, 0);
1384 } 1294 }
1385 } 1295 }
1386
1387 ath_debug_stat_rc(ath_rc_priv,
1388 ath_rc_get_rateindex(ath_rc_priv->rate_table,
1389 &tx_info->status.rates[final_ts_idx]));
1390} 1296}
1391 1297
1392static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband, 1298static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
1393 struct ieee80211_sta *sta, void *priv_sta) 1299 struct ieee80211_sta *sta, void *priv_sta)
1394{ 1300{
1395 struct ath_softc *sc = priv; 1301 struct ath_softc *sc = priv;
1302 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1396 struct ath_rate_priv *ath_rc_priv = priv_sta; 1303 struct ath_rate_priv *ath_rc_priv = priv_sta;
1397 const struct ath_rate_table *rate_table;
1398 bool is_cw40, is_sgi = false;
1399 int i, j = 0; 1304 int i, j = 0;
1400 1305
1401 for (i = 0; i < sband->n_bitrates; i++) { 1306 for (i = 0; i < sband->n_bitrates; i++) {
@@ -1417,20 +1322,15 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
1417 ath_rc_priv->neg_ht_rates.rs_nrates = j; 1322 ath_rc_priv->neg_ht_rates.rs_nrates = j;
1418 } 1323 }
1419 1324
1420 is_cw40 = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40); 1325 ath_rc_priv->rate_table = ath_choose_rate_table(sc, sband->band,
1421 1326 sta->ht_cap.ht_supported);
1422 if (is_cw40) 1327 if (!ath_rc_priv->rate_table) {
1423 is_sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1328 ath_err(common, "No rate table chosen\n");
1424 else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 1329 return;
1425 is_sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1330 }
1426
1427 /* Choose rate table first */
1428
1429 rate_table = ath_choose_rate_table(sc, sband->band,
1430 sta->ht_cap.ht_supported);
1431 1331
1432 ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta, is_cw40, is_sgi); 1332 ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta);
1433 ath_rc_init(sc, priv_sta, sband, sta, rate_table); 1333 ath_rc_init(sc, priv_sta);
1434} 1334}
1435 1335
1436static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband, 1336static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
@@ -1439,40 +1339,14 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
1439{ 1339{
1440 struct ath_softc *sc = priv; 1340 struct ath_softc *sc = priv;
1441 struct ath_rate_priv *ath_rc_priv = priv_sta; 1341 struct ath_rate_priv *ath_rc_priv = priv_sta;
1442 const struct ath_rate_table *rate_table = NULL;
1443 bool oper_cw40 = false, oper_sgi;
1444 bool local_cw40 = !!(ath_rc_priv->ht_cap & WLAN_RC_40_FLAG);
1445 bool local_sgi = !!(ath_rc_priv->ht_cap & WLAN_RC_SGI_FLAG);
1446
1447 /* FIXME: Handle AP mode later when we support CWM */
1448 1342
1449 if (changed & IEEE80211_RC_BW_CHANGED) { 1343 if (changed & IEEE80211_RC_BW_CHANGED) {
1450 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1344 ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta);
1451 return; 1345 ath_rc_init(sc, priv_sta);
1452 1346
1453 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 1347 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG,
1454 oper_cw40 = true; 1348 "Operating HT Bandwidth changed to: %d\n",
1455 1349 sc->hw->conf.channel_type);
1456 if (oper_cw40)
1457 oper_sgi = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1458 true : false;
1459 else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
1460 oper_sgi = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1461 true : false;
1462 else
1463 oper_sgi = false;
1464
1465 if ((local_cw40 != oper_cw40) || (local_sgi != oper_sgi)) {
1466 rate_table = ath_choose_rate_table(sc, sband->band,
1467 sta->ht_cap.ht_supported);
1468 ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta,
1469 oper_cw40, oper_sgi);
1470 ath_rc_init(sc, priv_sta, sband, sta, rate_table);
1471
1472 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG,
1473 "Operating HT Bandwidth changed to: %d\n",
1474 sc->hw->conf.channel_type);
1475 }
1476 } 1350 }
1477} 1351}
1478 1352
@@ -1484,7 +1358,7 @@ static ssize_t read_file_rcstat(struct file *file, char __user *user_buf,
1484 struct ath_rate_priv *rc = file->private_data; 1358 struct ath_rate_priv *rc = file->private_data;
1485 char *buf; 1359 char *buf;
1486 unsigned int len = 0, max; 1360 unsigned int len = 0, max;
1487 int i = 0; 1361 int rix;
1488 ssize_t retval; 1362 ssize_t retval;
1489 1363
1490 if (rc->rate_table == NULL) 1364 if (rc->rate_table == NULL)
@@ -1500,7 +1374,8 @@ static ssize_t read_file_rcstat(struct file *file, char __user *user_buf,
1500 "HT", "MCS", "Rate", 1374 "HT", "MCS", "Rate",
1501 "Success", "Retries", "XRetries", "PER"); 1375 "Success", "Retries", "XRetries", "PER");
1502 1376
1503 for (i = 0; i < rc->rate_table_size; i++) { 1377 for (rix = 0; rix < rc->max_valid_rate; rix++) {
1378 u8 i = rc->valid_rate_index[rix];
1504 u32 ratekbps = rc->rate_table->info[i].ratekbps; 1379 u32 ratekbps = rc->rate_table->info[i].ratekbps;
1505 struct ath_rc_stats *stats = &rc->rcstats[i]; 1380 struct ath_rc_stats *stats = &rc->rcstats[i];
1506 char mcs[5]; 1381 char mcs[5];
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index 75f8e9b06b28..268e67dc5fb2 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -160,10 +160,6 @@ struct ath_rate_table {
160 u32 user_ratekbps; 160 u32 user_ratekbps;
161 u8 ratecode; 161 u8 ratecode;
162 u8 dot11rate; 162 u8 dot11rate;
163 u8 ctrl_rate;
164 u8 cw40index;
165 u8 sgi_index;
166 u8 ht_index;
167 } info[RATE_TABLE_SIZE]; 163 } info[RATE_TABLE_SIZE];
168 u32 probe_interval; 164 u32 probe_interval;
169 u8 initial_ratemax; 165 u8 initial_ratemax;
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index 4480c0cc655f..83d16e7ed272 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -424,8 +424,8 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
424 rfilt |= ATH9K_RX_FILTER_COMP_BAR; 424 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
425 425
426 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) { 426 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
427 /* The following may also be needed for other older chips */ 427 /* This is needed for older chips */
428 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) 428 if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160)
429 rfilt |= ATH9K_RX_FILTER_PROM; 429 rfilt |= ATH9K_RX_FILTER_PROM;
430 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; 430 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
431 } 431 }
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 87cac8eb7834..4e6760f8596d 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -801,6 +801,8 @@
801#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ 801#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
802#define AR_SREV_VERSION_9462 0x280 802#define AR_SREV_VERSION_9462 0x280
803#define AR_SREV_REVISION_9462_20 2 803#define AR_SREV_REVISION_9462_20 2
804#define AR_SREV_VERSION_9565 0x2C0
805#define AR_SREV_REVISION_9565_10 0
804#define AR_SREV_VERSION_9550 0x400 806#define AR_SREV_VERSION_9550 0x400
805 807
806#define AR_SREV_5416(_ah) \ 808#define AR_SREV_5416(_ah) \
@@ -909,6 +911,13 @@
909 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \ 911 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
910 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20)) 912 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20))
911 913
914#define AR_SREV_9565(_ah) \
915 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))
916
917#define AR_SREV_9565_10(_ah) \
918 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
919 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))
920
912#define AR_SREV_9550(_ah) \ 921#define AR_SREV_9550(_ah) \
913 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550)) 922 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
914 923
diff --git a/drivers/net/wireless/ath/ath9k/wow.c b/drivers/net/wireless/ath/ath9k/wow.c
index 44a08eb53c62..a483d518758c 100644
--- a/drivers/net/wireless/ath/ath9k/wow.c
+++ b/drivers/net/wireless/ath/ath9k/wow.c
@@ -497,7 +497,7 @@ void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
497 497
498 REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr); 498 REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
499 499
500 if (AR_SREV_9462(ah)) { 500 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
501 /* 501 /*
502 * this is needed to prevent the chip waking up 502 * this is needed to prevent the chip waking up
503 * the host within 3-4 seconds with certain 503 * the host within 3-4 seconds with certain
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 0d4155aec48d..36618e3a5e60 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -568,7 +568,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
568 if (!an->sleeping) { 568 if (!an->sleeping) {
569 ath_tx_queue_tid(txq, tid); 569 ath_tx_queue_tid(txq, tid);
570 570
571 if (ts->ts_status & ATH9K_TXERR_FILT) 571 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
572 tid->ac->clear_ps_filter = true; 572 tid->ac->clear_ps_filter = true;
573 } 573 }
574 } 574 }
@@ -1773,11 +1773,12 @@ static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1773 TX_STAT_INC(txq->axq_qnum, queued); 1773 TX_STAT_INC(txq->axq_qnum, queued);
1774} 1774}
1775 1775
1776static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb, 1776static void setup_frame_info(struct ieee80211_hw *hw,
1777 struct ieee80211_sta *sta,
1778 struct sk_buff *skb,
1777 int framelen) 1779 int framelen)
1778{ 1780{
1779 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1781 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1780 struct ieee80211_sta *sta = tx_info->control.sta;
1781 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 1782 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1782 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1783 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1783 const struct ieee80211_rate *rate; 1784 const struct ieee80211_rate *rate;
@@ -1819,10 +1820,14 @@ u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1819{ 1820{
1820 struct ath_hw *ah = sc->sc_ah; 1821 struct ath_hw *ah = sc->sc_ah;
1821 struct ath9k_channel *curchan = ah->curchan; 1822 struct ath9k_channel *curchan = ah->curchan;
1823
1822 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && 1824 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1823 (curchan->channelFlags & CHANNEL_5GHZ) && 1825 (curchan->channelFlags & CHANNEL_5GHZ) &&
1824 (chainmask == 0x7) && (rate < 0x90)) 1826 (chainmask == 0x7) && (rate < 0x90))
1825 return 0x3; 1827 return 0x3;
1828 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
1829 IS_CCK_RATE(rate))
1830 return 0x2;
1826 else 1831 else
1827 return chainmask; 1832 return chainmask;
1828} 1833}
@@ -1935,7 +1940,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1935{ 1940{
1936 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1941 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1937 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1942 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1938 struct ieee80211_sta *sta = info->control.sta; 1943 struct ieee80211_sta *sta = txctl->sta;
1939 struct ieee80211_vif *vif = info->control.vif; 1944 struct ieee80211_vif *vif = info->control.vif;
1940 struct ath_softc *sc = hw->priv; 1945 struct ath_softc *sc = hw->priv;
1941 struct ath_txq *txq = txctl->txq; 1946 struct ath_txq *txq = txctl->txq;
@@ -1979,7 +1984,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1979 !ieee80211_is_data(hdr->frame_control)) 1984 !ieee80211_is_data(hdr->frame_control))
1980 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1985 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1981 1986
1982 setup_frame_info(hw, skb, frmlen); 1987 setup_frame_info(hw, sta, skb, frmlen);
1983 1988
1984 /* 1989 /*
1985 * At this point, the vif, hw_key and sta pointers in the tx control 1990 * At this point, the vif, hw_key and sta pointers in the tx control
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 03:38:58 -0500