diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/init.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/init.c | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c index 6c6e88495394..f8d11efa7b0f 100644 --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c | |||
@@ -141,6 +141,16 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |||
141 | return val; | 141 | return val; |
142 | } | 142 | } |
143 | 143 | ||
144 | static void ath9k_multi_ioread32(void *hw_priv, u32 *addr, | ||
145 | u32 *val, u16 count) | ||
146 | { | ||
147 | int i; | ||
148 | |||
149 | for (i = 0; i < count; i++) | ||
150 | val[i] = ath9k_ioread32(hw_priv, addr[i]); | ||
151 | } | ||
152 | |||
153 | |||
144 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, | 154 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
145 | u32 set, u32 clr) | 155 | u32 set, u32 clr) |
146 | { | 156 | { |
@@ -437,8 +447,15 @@ static void ath9k_init_pcoem_platform(struct ath_softc *sc) | |||
437 | ath_info(common, "Enable WAR for ASPM D3/L1\n"); | 447 | ath_info(common, "Enable WAR for ASPM D3/L1\n"); |
438 | } | 448 | } |
439 | 449 | ||
450 | /* | ||
451 | * The default value of pll_pwrsave is 1. | ||
452 | * For certain AR9485 cards, it is set to 0. | ||
453 | * For AR9462, AR9565 it's set to 7. | ||
454 | */ | ||
455 | ah->config.pll_pwrsave = 1; | ||
456 | |||
440 | if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { | 457 | if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { |
441 | ah->config.no_pll_pwrsave = true; | 458 | ah->config.pll_pwrsave = 0; |
442 | ath_info(common, "Disable PLL PowerSave\n"); | 459 | ath_info(common, "Disable PLL PowerSave\n"); |
443 | } | 460 | } |
444 | 461 | ||
@@ -530,6 +547,7 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, | |||
530 | ah->hw = sc->hw; | 547 | ah->hw = sc->hw; |
531 | ah->hw_version.devid = devid; | 548 | ah->hw_version.devid = devid; |
532 | ah->reg_ops.read = ath9k_ioread32; | 549 | ah->reg_ops.read = ath9k_ioread32; |
550 | ah->reg_ops.multi_read = ath9k_multi_ioread32; | ||
533 | ah->reg_ops.write = ath9k_iowrite32; | 551 | ah->reg_ops.write = ath9k_iowrite32; |
534 | ah->reg_ops.rmw = ath9k_reg_rmw; | 552 | ah->reg_ops.rmw = ath9k_reg_rmw; |
535 | pCap = &ah->caps; | 553 | pCap = &ah->caps; |
@@ -763,7 +781,8 @@ static const struct ieee80211_iface_combination if_comb[] = { | |||
763 | .num_different_channels = 1, | 781 | .num_different_channels = 1, |
764 | .beacon_int_infra_match = true, | 782 | .beacon_int_infra_match = true, |
765 | .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | | 783 | .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | |
766 | BIT(NL80211_CHAN_WIDTH_20), | 784 | BIT(NL80211_CHAN_WIDTH_20) | |
785 | BIT(NL80211_CHAN_WIDTH_40), | ||
767 | } | 786 | } |
768 | #endif | 787 | #endif |
769 | }; | 788 | }; |