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path: root/drivers/net/wireless/ath/ath9k/hw.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c128
1 files changed, 64 insertions, 64 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index ecc6ec4a1edb..54b04155e43b 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -130,29 +130,29 @@ void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
130 130
131static void ath9k_hw_set_clockrate(struct ath_hw *ah) 131static void ath9k_hw_set_clockrate(struct ath_hw *ah)
132{ 132{
133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
134 struct ath_common *common = ath9k_hw_common(ah); 133 struct ath_common *common = ath9k_hw_common(ah);
134 struct ath9k_channel *chan = ah->curchan;
135 unsigned int clockrate; 135 unsigned int clockrate;
136 136
137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
139 clockrate = 117; 139 clockrate = 117;
140 else if (!ah->curchan) /* should really check for CCK instead */ 140 else if (!chan) /* should really check for CCK instead */
141 clockrate = ATH9K_CLOCK_RATE_CCK; 141 clockrate = ATH9K_CLOCK_RATE_CCK;
142 else if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ) 142 else if (IS_CHAN_2GHZ(chan))
143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
146 else 146 else
147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
148 148
149 if (conf_is_ht40(conf)) 149 if (IS_CHAN_HT40(chan))
150 clockrate *= 2; 150 clockrate *= 2;
151 151
152 if (ah->curchan) { 152 if (ah->curchan) {
153 if (IS_CHAN_HALF_RATE(ah->curchan)) 153 if (IS_CHAN_HALF_RATE(chan))
154 clockrate /= 2; 154 clockrate /= 2;
155 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 155 if (IS_CHAN_QUARTER_RATE(chan))
156 clockrate /= 4; 156 clockrate /= 4;
157 } 157 }
158 158
@@ -190,10 +190,7 @@ EXPORT_SYMBOL(ath9k_hw_wait);
190void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 190void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
191 int hw_delay) 191 int hw_delay)
192{ 192{
193 if (IS_CHAN_B(chan)) 193 hw_delay /= 10;
194 hw_delay = (4 * hw_delay) / 22;
195 else
196 hw_delay /= 10;
197 194
198 if (IS_CHAN_HALF_RATE(chan)) 195 if (IS_CHAN_HALF_RATE(chan))
199 hw_delay *= 2; 196 hw_delay *= 2;
@@ -294,8 +291,7 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah,
294 return; 291 return;
295 } 292 }
296 293
297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 294 if (IS_CHAN_HT40PLUS(chan)) {
298 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
299 centers->synth_center = 295 centers->synth_center =
300 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 296 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
301 extoff = 1; 297 extoff = 1;
@@ -549,6 +545,18 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
549 545
550 ath9k_hw_ani_init(ah); 546 ath9k_hw_ani_init(ah);
551 547
548 /*
549 * EEPROM needs to be initialized before we do this.
550 * This is required for regulatory compliance.
551 */
552 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
553 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
554 if ((regdmn & 0xF0) == CTL_FCC) {
555 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
556 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
557 }
558 }
559
552 return 0; 560 return 0;
553} 561}
554 562
@@ -1030,7 +1038,6 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1030void ath9k_hw_init_global_settings(struct ath_hw *ah) 1038void ath9k_hw_init_global_settings(struct ath_hw *ah)
1031{ 1039{
1032 struct ath_common *common = ath9k_hw_common(ah); 1040 struct ath_common *common = ath9k_hw_common(ah);
1033 struct ieee80211_conf *conf = &common->hw->conf;
1034 const struct ath9k_channel *chan = ah->curchan; 1041 const struct ath9k_channel *chan = ah->curchan;
1035 int acktimeout, ctstimeout, ack_offset = 0; 1042 int acktimeout, ctstimeout, ack_offset = 0;
1036 int slottime; 1043 int slottime;
@@ -1105,8 +1112,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
1105 * BA frames in some implementations, but it has been found to fix ACK 1112 * BA frames in some implementations, but it has been found to fix ACK
1106 * timeout issues in other cases as well. 1113 * timeout issues in other cases as well.
1107 */ 1114 */
1108 if (conf->chandef.chan && 1115 if (IS_CHAN_2GHZ(chan) &&
1109 conf->chandef.chan->band == IEEE80211_BAND_2GHZ &&
1110 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1116 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1111 acktimeout += 64 - sifstime - ah->slottime; 1117 acktimeout += 64 - sifstime - ah->slottime;
1112 ctstimeout += 48 - sifstime - ah->slottime; 1118 ctstimeout += 48 - sifstime - ah->slottime;
@@ -1148,9 +1154,7 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1148{ 1154{
1149 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1155 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1150 1156
1151 if (IS_CHAN_B(chan)) 1157 if (IS_CHAN_2GHZ(chan))
1152 ctl |= CTL_11B;
1153 else if (IS_CHAN_G(chan))
1154 ctl |= CTL_11G; 1158 ctl |= CTL_11G;
1155 else 1159 else
1156 ctl |= CTL_11A; 1160 ctl |= CTL_11A;
@@ -1498,10 +1502,8 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1498 int r; 1502 int r;
1499 1503
1500 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1504 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1501 u32 cur = ah->curchan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ); 1505 band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
1502 u32 new = chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ); 1506 mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
1503 band_switch = (cur != new);
1504 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1505 } 1507 }
1506 1508
1507 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1509 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
@@ -1540,9 +1542,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1540 ath9k_hw_set_clockrate(ah); 1542 ath9k_hw_set_clockrate(ah);
1541 ath9k_hw_apply_txpower(ah, chan, false); 1543 ath9k_hw_apply_txpower(ah, chan, false);
1542 1544
1543 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1545 ath9k_hw_set_delta_slope(ah, chan);
1544 ath9k_hw_set_delta_slope(ah, chan);
1545
1546 ath9k_hw_spur_mitigate_freq(ah, chan); 1546 ath9k_hw_spur_mitigate_freq(ah, chan);
1547 1547
1548 if (band_switch || ini_reloaded) 1548 if (band_switch || ini_reloaded)
@@ -1644,6 +1644,19 @@ hang_check_iter:
1644 return true; 1644 return true;
1645} 1645}
1646 1646
1647void ath9k_hw_check_nav(struct ath_hw *ah)
1648{
1649 struct ath_common *common = ath9k_hw_common(ah);
1650 u32 val;
1651
1652 val = REG_READ(ah, AR_NAV);
1653 if (val != 0xdeadbeef && val > 0x7fff) {
1654 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1655 REG_WRITE(ah, AR_NAV, 0);
1656 }
1657}
1658EXPORT_SYMBOL(ath9k_hw_check_nav);
1659
1647bool ath9k_hw_check_alive(struct ath_hw *ah) 1660bool ath9k_hw_check_alive(struct ath_hw *ah)
1648{ 1661{
1649 int count = 50; 1662 int count = 50;
@@ -1799,20 +1812,11 @@ static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1799 goto fail; 1812 goto fail;
1800 1813
1801 /* 1814 /*
1802 * If cross-band fcc is not supoprted, bail out if 1815 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1803 * either channelFlags or chanmode differ.
1804 *
1805 * chanmode will be different if the HT operating mode
1806 * changes because of CSA.
1807 */ 1816 */
1808 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH)) { 1817 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1809 if ((chan->channelFlags & CHANNEL_ALL) != 1818 chan->channelFlags != ah->curchan->channelFlags)
1810 (ah->curchan->channelFlags & CHANNEL_ALL)) 1819 goto fail;
1811 goto fail;
1812
1813 if (chan->chanmode != ah->curchan->chanmode)
1814 goto fail;
1815 }
1816 1820
1817 if (!ath9k_hw_check_alive(ah)) 1821 if (!ath9k_hw_check_alive(ah))
1818 goto fail; 1822 goto fail;
@@ -1822,9 +1826,9 @@ static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1822 * re-using are present. 1826 * re-using are present.
1823 */ 1827 */
1824 if (AR_SREV_9462(ah) && (ah->caldata && 1828 if (AR_SREV_9462(ah) && (ah->caldata &&
1825 (!ah->caldata->done_txiqcal_once || 1829 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1826 !ah->caldata->done_txclcal_once || 1830 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1827 !ah->caldata->rtt_done))) 1831 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1828 goto fail; 1832 goto fail;
1829 1833
1830 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1834 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
@@ -1874,15 +1878,14 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1874 1878
1875 ah->caldata = caldata; 1879 ah->caldata = caldata;
1876 if (caldata && (chan->channel != caldata->channel || 1880 if (caldata && (chan->channel != caldata->channel ||
1877 chan->channelFlags != caldata->channelFlags || 1881 chan->channelFlags != caldata->channelFlags)) {
1878 chan->chanmode != caldata->chanmode)) {
1879 /* Operating channel changed, reset channel calibration data */ 1882 /* Operating channel changed, reset channel calibration data */
1880 memset(caldata, 0, sizeof(*caldata)); 1883 memset(caldata, 0, sizeof(*caldata));
1881 ath9k_init_nfcal_hist_buffer(ah, chan); 1884 ath9k_init_nfcal_hist_buffer(ah, chan);
1882 } else if (caldata) { 1885 } else if (caldata) {
1883 caldata->paprd_packet_sent = false; 1886 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1884 } 1887 }
1885 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1888 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1886 1889
1887 if (fastcc) { 1890 if (fastcc) {
1888 r = ath9k_hw_do_fastcc(ah, chan); 1891 r = ath9k_hw_do_fastcc(ah, chan);
@@ -1964,9 +1967,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1964 1967
1965 ath9k_hw_init_mfp(ah); 1968 ath9k_hw_init_mfp(ah);
1966 1969
1967 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1970 ath9k_hw_set_delta_slope(ah, chan);
1968 ath9k_hw_set_delta_slope(ah, chan);
1969
1970 ath9k_hw_spur_mitigate_freq(ah, chan); 1971 ath9k_hw_spur_mitigate_freq(ah, chan);
1971 ah->eep_ops->set_board_values(ah, chan); 1972 ah->eep_ops->set_board_values(ah, chan);
1972 1973
@@ -2017,8 +2018,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2017 ath9k_hw_init_bb(ah, chan); 2018 ath9k_hw_init_bb(ah, chan);
2018 2019
2019 if (caldata) { 2020 if (caldata) {
2020 caldata->done_txiqcal_once = false; 2021 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2021 caldata->done_txclcal_once = false; 2022 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
2022 } 2023 }
2023 if (!ath9k_hw_init_cal(ah, chan)) 2024 if (!ath9k_hw_init_cal(ah, chan))
2024 return -EIO; 2025 return -EIO;
@@ -2943,12 +2944,11 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2943} 2944}
2944EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2945EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2945 2946
2946void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2947void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
2947{ 2948{
2948 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2949 u32 macmode; 2949 u32 macmode;
2950 2950
2951 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2951 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
2952 macmode = AR_2040_JOINED_RX_CLEAR; 2952 macmode = AR_2040_JOINED_RX_CLEAR;
2953 else 2953 else
2954 macmode = 0; 2954 macmode = 0;
@@ -3240,19 +3240,19 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3240 3240
3241 /* chipsets >= AR9280 are single-chip */ 3241 /* chipsets >= AR9280 are single-chip */
3242 if (AR_SREV_9280_20_OR_LATER(ah)) { 3242 if (AR_SREV_9280_20_OR_LATER(ah)) {
3243 used = snprintf(hw_name, len, 3243 used = scnprintf(hw_name, len,
3244 "Atheros AR%s Rev:%x", 3244 "Atheros AR%s Rev:%x",
3245 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3245 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3246 ah->hw_version.macRev); 3246 ah->hw_version.macRev);
3247 } 3247 }
3248 else { 3248 else {
3249 used = snprintf(hw_name, len, 3249 used = scnprintf(hw_name, len,
3250 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3250 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3251 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3251 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3252 ah->hw_version.macRev, 3252 ah->hw_version.macRev,
3253 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3253 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3254 AR_RADIO_SREV_MAJOR)), 3254 & AR_RADIO_SREV_MAJOR)),
3255 ah->hw_version.phyRev); 3255 ah->hw_version.phyRev);
3256 } 3256 }
3257 3257
3258 hw_name[used] = '\0'; 3258 hw_name[used] = '\0';