diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/eeprom.h')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom.h | 245 |
1 files changed, 145 insertions, 100 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h index db77e90ed9ab..4fe33f7eee9d 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom.h +++ b/drivers/net/wireless/ath/ath9k/eeprom.h | |||
@@ -385,106 +385,124 @@ struct calDataPerFreqOpLoop { | |||
385 | } __packed; | 385 | } __packed; |
386 | 386 | ||
387 | struct modal_eep_4k_header { | 387 | struct modal_eep_4k_header { |
388 | u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; | 388 | u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; |
389 | u32 antCtrlCommon; | 389 | u32 antCtrlCommon; |
390 | u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; | 390 | u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; |
391 | u8 switchSettling; | 391 | u8 switchSettling; |
392 | u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; | 392 | u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; |
393 | u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; | 393 | u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; |
394 | u8 adcDesiredSize; | 394 | u8 adcDesiredSize; |
395 | u8 pgaDesiredSize; | 395 | u8 pgaDesiredSize; |
396 | u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; | 396 | u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; |
397 | u8 txEndToXpaOff; | 397 | u8 txEndToXpaOff; |
398 | u8 txEndToRxOn; | 398 | u8 txEndToRxOn; |
399 | u8 txFrameToXpaOn; | 399 | u8 txFrameToXpaOn; |
400 | u8 thresh62; | 400 | u8 thresh62; |
401 | u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; | 401 | u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; |
402 | u8 xpdGain; | 402 | u8 xpdGain; |
403 | u8 xpd; | 403 | u8 xpd; |
404 | u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; | 404 | u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; |
405 | u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; | 405 | u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; |
406 | u8 pdGainOverlap; | 406 | u8 pdGainOverlap; |
407 | u8 ob_01; | 407 | #ifdef __BIG_ENDIAN_BITFIELD |
408 | u8 db1_01; | 408 | u8 ob_1:4, ob_0:4; |
409 | u8 xpaBiasLvl; | 409 | u8 db1_1:4, db1_0:4; |
410 | u8 txFrameToDataStart; | 410 | #else |
411 | u8 txFrameToPaOn; | 411 | u8 ob_0:4, ob_1:4; |
412 | u8 ht40PowerIncForPdadc; | 412 | u8 db1_0:4, db1_1:4; |
413 | u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; | 413 | #endif |
414 | u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; | 414 | u8 xpaBiasLvl; |
415 | u8 swSettleHt40; | 415 | u8 txFrameToDataStart; |
416 | u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; | 416 | u8 txFrameToPaOn; |
417 | u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; | 417 | u8 ht40PowerIncForPdadc; |
418 | u8 db2_01; | 418 | u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; |
419 | u8 version; | 419 | u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; |
420 | u16 ob_234; | 420 | u8 swSettleHt40; |
421 | u16 db1_234; | 421 | u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; |
422 | u16 db2_234; | 422 | u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; |
423 | u8 futureModal[4]; | 423 | #ifdef __BIG_ENDIAN_BITFIELD |
424 | 424 | u8 db2_1:4, db2_0:4; | |
425 | #else | ||
426 | u8 db2_0:4, db2_1:4; | ||
427 | #endif | ||
428 | u8 version; | ||
429 | #ifdef __BIG_ENDIAN_BITFIELD | ||
430 | u8 ob_3:4, ob_2:4; | ||
431 | u8 antdiv_ctl1:4, ob_4:4; | ||
432 | u8 db1_3:4, db1_2:4; | ||
433 | u8 antdiv_ctl2:4, db1_4:4; | ||
434 | u8 db2_2:4, db2_3:4; | ||
435 | u8 reserved:4, db2_4:4; | ||
436 | #else | ||
437 | u8 ob_2:4, ob_3:4; | ||
438 | u8 ob_4:4, antdiv_ctl1:4; | ||
439 | u8 db1_2:4, db1_3:4; | ||
440 | u8 db1_4:4, antdiv_ctl2:4; | ||
441 | u8 db2_2:4, db2_3:4; | ||
442 | u8 db2_4:4, reserved:4; | ||
443 | #endif | ||
444 | u8 futureModal[4]; | ||
425 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; | 445 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; |
426 | } __packed; | 446 | } __packed; |
427 | 447 | ||
428 | struct base_eep_ar9287_header { | 448 | struct base_eep_ar9287_header { |
429 | u16 length; | 449 | u16 length; |
430 | u16 checksum; | 450 | u16 checksum; |
431 | u16 version; | 451 | u16 version; |
432 | u8 opCapFlags; | 452 | u8 opCapFlags; |
433 | u8 eepMisc; | 453 | u8 eepMisc; |
434 | u16 regDmn[2]; | 454 | u16 regDmn[2]; |
435 | u8 macAddr[6]; | 455 | u8 macAddr[6]; |
436 | u8 rxMask; | 456 | u8 rxMask; |
437 | u8 txMask; | 457 | u8 txMask; |
438 | u16 rfSilent; | 458 | u16 rfSilent; |
439 | u16 blueToothOptions; | 459 | u16 blueToothOptions; |
440 | u16 deviceCap; | 460 | u16 deviceCap; |
441 | u32 binBuildNumber; | 461 | u32 binBuildNumber; |
442 | u8 deviceType; | 462 | u8 deviceType; |
443 | u8 openLoopPwrCntl; | 463 | u8 openLoopPwrCntl; |
444 | int8_t pwrTableOffset; | 464 | int8_t pwrTableOffset; |
445 | int8_t tempSensSlope; | 465 | int8_t tempSensSlope; |
446 | int8_t tempSensSlopePalOn; | 466 | int8_t tempSensSlopePalOn; |
447 | u8 futureBase[29]; | 467 | u8 futureBase[29]; |
448 | } __packed; | 468 | } __packed; |
449 | 469 | ||
450 | struct modal_eep_ar9287_header { | 470 | struct modal_eep_ar9287_header { |
451 | u32 antCtrlChain[AR9287_MAX_CHAINS]; | 471 | u32 antCtrlChain[AR9287_MAX_CHAINS]; |
452 | u32 antCtrlCommon; | 472 | u32 antCtrlCommon; |
453 | int8_t antennaGainCh[AR9287_MAX_CHAINS]; | 473 | int8_t antennaGainCh[AR9287_MAX_CHAINS]; |
454 | u8 switchSettling; | 474 | u8 switchSettling; |
455 | u8 txRxAttenCh[AR9287_MAX_CHAINS]; | 475 | u8 txRxAttenCh[AR9287_MAX_CHAINS]; |
456 | u8 rxTxMarginCh[AR9287_MAX_CHAINS]; | 476 | u8 rxTxMarginCh[AR9287_MAX_CHAINS]; |
457 | int8_t adcDesiredSize; | 477 | int8_t adcDesiredSize; |
458 | u8 txEndToXpaOff; | 478 | u8 txEndToXpaOff; |
459 | u8 txEndToRxOn; | 479 | u8 txEndToRxOn; |
460 | u8 txFrameToXpaOn; | 480 | u8 txFrameToXpaOn; |
461 | u8 thresh62; | 481 | u8 thresh62; |
462 | int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; | 482 | int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; |
463 | u8 xpdGain; | 483 | u8 xpdGain; |
464 | u8 xpd; | 484 | u8 xpd; |
465 | int8_t iqCalICh[AR9287_MAX_CHAINS]; | 485 | int8_t iqCalICh[AR9287_MAX_CHAINS]; |
466 | int8_t iqCalQCh[AR9287_MAX_CHAINS]; | 486 | int8_t iqCalQCh[AR9287_MAX_CHAINS]; |
467 | u8 pdGainOverlap; | 487 | u8 pdGainOverlap; |
468 | u8 xpaBiasLvl; | 488 | u8 xpaBiasLvl; |
469 | u8 txFrameToDataStart; | 489 | u8 txFrameToDataStart; |
470 | u8 txFrameToPaOn; | 490 | u8 txFrameToPaOn; |
471 | u8 ht40PowerIncForPdadc; | 491 | u8 ht40PowerIncForPdadc; |
472 | u8 bswAtten[AR9287_MAX_CHAINS]; | 492 | u8 bswAtten[AR9287_MAX_CHAINS]; |
473 | u8 bswMargin[AR9287_MAX_CHAINS]; | 493 | u8 bswMargin[AR9287_MAX_CHAINS]; |
474 | u8 swSettleHt40; | 494 | u8 swSettleHt40; |
475 | u8 version; | 495 | u8 version; |
476 | u8 db1; | 496 | u8 db1; |
477 | u8 db2; | 497 | u8 db2; |
478 | u8 ob_cck; | 498 | u8 ob_cck; |
479 | u8 ob_psk; | 499 | u8 ob_psk; |
480 | u8 ob_qam; | 500 | u8 ob_qam; |
481 | u8 ob_pal_off; | 501 | u8 ob_pal_off; |
482 | u8 futureModal[30]; | 502 | u8 futureModal[30]; |
483 | struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; | 503 | struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; |
484 | } __packed; | 504 | } __packed; |
485 | 505 | ||
486 | |||
487 | |||
488 | struct cal_data_per_freq { | 506 | struct cal_data_per_freq { |
489 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | 507 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
490 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | 508 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
@@ -525,7 +543,6 @@ struct cal_data_op_loop_ar9287 { | |||
525 | u8 empty[2][5]; | 543 | u8 empty[2][5]; |
526 | } __packed; | 544 | } __packed; |
527 | 545 | ||
528 | |||
529 | struct cal_data_per_freq_ar9287 { | 546 | struct cal_data_per_freq_ar9287 { |
530 | u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; | 547 | u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; |
531 | u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; | 548 | u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; |
@@ -601,26 +618,25 @@ struct ar5416_eeprom_4k { | |||
601 | } __packed; | 618 | } __packed; |
602 | 619 | ||
603 | struct ar9287_eeprom { | 620 | struct ar9287_eeprom { |
604 | struct base_eep_ar9287_header baseEepHeader; | 621 | struct base_eep_ar9287_header baseEepHeader; |
605 | u8 custData[AR9287_DATA_SZ]; | 622 | u8 custData[AR9287_DATA_SZ]; |
606 | struct modal_eep_ar9287_header modalHeader; | 623 | struct modal_eep_ar9287_header modalHeader; |
607 | u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; | 624 | u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; |
608 | union cal_data_per_freq_ar9287_u | 625 | union cal_data_per_freq_ar9287_u |
609 | calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; | 626 | calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; |
610 | struct cal_target_power_leg | 627 | struct cal_target_power_leg |
611 | calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; | 628 | calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; |
612 | struct cal_target_power_leg | 629 | struct cal_target_power_leg |
613 | calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; | 630 | calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; |
614 | struct cal_target_power_ht | 631 | struct cal_target_power_ht |
615 | calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; | 632 | calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; |
616 | struct cal_target_power_ht | 633 | struct cal_target_power_ht |
617 | calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; | 634 | calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; |
618 | u8 ctlIndex[AR9287_NUM_CTLS]; | 635 | u8 ctlIndex[AR9287_NUM_CTLS]; |
619 | struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; | 636 | struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; |
620 | u8 padding; | 637 | u8 padding; |
621 | } __packed; | 638 | } __packed; |
622 | 639 | ||
623 | |||
624 | enum reg_ext_bitmap { | 640 | enum reg_ext_bitmap { |
625 | REG_EXT_JAPAN_MIDBAND = 1, | 641 | REG_EXT_JAPAN_MIDBAND = 1, |
626 | REG_EXT_FCC_DFS_HT40 = 2, | 642 | REG_EXT_FCC_DFS_HT40 = 2, |
@@ -661,10 +677,39 @@ struct eeprom_ops { | |||
661 | u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); | 677 | u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); |
662 | }; | 678 | }; |
663 | 679 | ||
680 | void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, | ||
681 | u32 shift, u32 val); | ||
682 | int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, | ||
683 | int16_t targetLeft, | ||
684 | int16_t targetRight); | ||
685 | bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, | ||
686 | u16 *indexL, u16 *indexR); | ||
687 | bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); | ||
688 | void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, | ||
689 | u8 *pVpdList, u16 numIntercepts, | ||
690 | u8 *pRetVpdList); | ||
691 | void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, | ||
692 | struct ath9k_channel *chan, | ||
693 | struct cal_target_power_leg *powInfo, | ||
694 | u16 numChannels, | ||
695 | struct cal_target_power_leg *pNewPower, | ||
696 | u16 numRates, bool isExtTarget); | ||
697 | void ath9k_hw_get_target_powers(struct ath_hw *ah, | ||
698 | struct ath9k_channel *chan, | ||
699 | struct cal_target_power_ht *powInfo, | ||
700 | u16 numChannels, | ||
701 | struct cal_target_power_ht *pNewPower, | ||
702 | u16 numRates, bool isHt40Target); | ||
703 | u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, | ||
704 | bool is2GHz, int num_band_edges); | ||
705 | int ath9k_hw_eeprom_init(struct ath_hw *ah); | ||
706 | |||
664 | #define ar5416_get_ntxchains(_txchainmask) \ | 707 | #define ar5416_get_ntxchains(_txchainmask) \ |
665 | (((_txchainmask >> 2) & 1) + \ | 708 | (((_txchainmask >> 2) & 1) + \ |
666 | ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) | 709 | ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) |
667 | 710 | ||
668 | int ath9k_hw_eeprom_init(struct ath_hw *ah); | 711 | extern const struct eeprom_ops eep_def_ops; |
712 | extern const struct eeprom_ops eep_4k_ops; | ||
713 | extern const struct eeprom_ops eep_AR9287_ops; | ||
669 | 714 | ||
670 | #endif /* EEPROM_H */ | 715 | #endif /* EEPROM_H */ |