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path: root/drivers/net/wireless/ath/ath9k/ar9003_phy.h
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_phy.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h66
1 files changed, 33 insertions, 33 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index f08cc8bda005..676d3f1123f4 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -483,10 +483,10 @@
483#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c) 483#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
484#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450) 484#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450)
485 485
486#define AR_PHY_PANIC_WD_STATUS (AR_SM_BASE + 0x5c0) 486#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
487#define AR_PHY_PANIC_WD_CTL_1 (AR_SM_BASE + 0x5c4) 487#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
488#define AR_PHY_PANIC_WD_CTL_2 (AR_SM_BASE + 0x5c8) 488#define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8)
489#define AR_PHY_BT_CTL (AR_SM_BASE + 0x5cc) 489#define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc)
490#define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0) 490#define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
491#define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4) 491#define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
492#define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc) 492#define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
@@ -812,35 +812,35 @@
812#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) 812#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
813#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) 813#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
814 814
815#define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001 815#define AR_PHY_WATCHDOG_NON_IDLE_ENABLE 0x00000001
816#define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002 816#define AR_PHY_WATCHDOG_IDLE_ENABLE 0x00000002
817#define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000 817#define AR_PHY_WATCHDOG_IDLE_MASK 0xFFFF0000
818#define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC 818#define AR_PHY_WATCHDOG_NON_IDLE_MASK 0x0000FFFC
819 819
820#define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002 820#define AR_PHY_WATCHDOG_RST_ENABLE 0x00000002
821#define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004 821#define AR_PHY_WATCHDOG_IRQ_ENABLE 0x00000004
822#define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9 822#define AR_PHY_WATCHDOG_CNTL2_MASK 0xFFFFFFF9
823 823
824#define AR_PHY_BB_WD_STATUS 0x00000007 824#define AR_PHY_WATCHDOG_INFO 0x00000007
825#define AR_PHY_BB_WD_STATUS_S 0 825#define AR_PHY_WATCHDOG_INFO_S 0
826#define AR_PHY_BB_WD_DET_HANG 0x00000008 826#define AR_PHY_WATCHDOG_DET_HANG 0x00000008
827#define AR_PHY_BB_WD_DET_HANG_S 3 827#define AR_PHY_WATCHDOG_DET_HANG_S 3
828#define AR_PHY_BB_WD_RADAR_SM 0x000000F0 828#define AR_PHY_WATCHDOG_RADAR_SM 0x000000F0
829#define AR_PHY_BB_WD_RADAR_SM_S 4 829#define AR_PHY_WATCHDOG_RADAR_SM_S 4
830#define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00 830#define AR_PHY_WATCHDOG_RX_OFDM_SM 0x00000F00
831#define AR_PHY_BB_WD_RX_OFDM_SM_S 8 831#define AR_PHY_WATCHDOG_RX_OFDM_SM_S 8
832#define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000 832#define AR_PHY_WATCHDOG_RX_CCK_SM 0x0000F000
833#define AR_PHY_BB_WD_RX_CCK_SM_S 12 833#define AR_PHY_WATCHDOG_RX_CCK_SM_S 12
834#define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000 834#define AR_PHY_WATCHDOG_TX_OFDM_SM 0x000F0000
835#define AR_PHY_BB_WD_TX_OFDM_SM_S 16 835#define AR_PHY_WATCHDOG_TX_OFDM_SM_S 16
836#define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000 836#define AR_PHY_WATCHDOG_TX_CCK_SM 0x00F00000
837#define AR_PHY_BB_WD_TX_CCK_SM_S 20 837#define AR_PHY_WATCHDOG_TX_CCK_SM_S 20
838#define AR_PHY_BB_WD_AGC_SM 0x0F000000 838#define AR_PHY_WATCHDOG_AGC_SM 0x0F000000
839#define AR_PHY_BB_WD_AGC_SM_S 24 839#define AR_PHY_WATCHDOG_AGC_SM_S 24
840#define AR_PHY_BB_WD_SRCH_SM 0xF0000000 840#define AR_PHY_WATCHDOG_SRCH_SM 0xF0000000
841#define AR_PHY_BB_WD_SRCH_SM_S 28 841#define AR_PHY_WATCHDOG_SRCH_SM_S 28
842 842
843#define AR_PHY_BB_WD_STATUS_CLR 0x00000008 843#define AR_PHY_WATCHDOG_STATUS_CLR 0x00000008
844 844
845void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 845void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
846 846