1 files changed, 128 insertions, 62 deletions

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 1f694ab3cc78..e897648d3233 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -632,6 +632,22 @@ static void ar9003_hw_override_ini(struct ath_hw *ah)
 
         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
                     AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+
+        if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
+                REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
+                          AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
+
+                if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
+                                   AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
+                        ah->enabled_cals |= TX_IQ_CAL;
+                else
+                        ah->enabled_cals &= ~TX_IQ_CAL;
+
+                if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
+                        ah->enabled_cals |= TX_CL_CAL;
+                else
+                        ah->enabled_cals &= ~TX_CL_CAL;
+        }
 }
 
 static void ar9003_hw_prog_ini(struct ath_hw *ah,
@@ -814,29 +830,12 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
         if (chan->channel == 2484)
                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 
-        if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
-                REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
-                          AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
-
         ah->modes_index = modesIndex;
         ar9003_hw_override_ini(ah);
         ar9003_hw_set_channel_regs(ah, chan);
         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
         ath9k_hw_apply_txpower(ah, chan, false);
 
-        if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
-                if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
-                                   AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
-                        ah->enabled_cals |= TX_IQ_CAL;
-                else
-                        ah->enabled_cals &= ~TX_IQ_CAL;
-
-                if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
-                        ah->enabled_cals |= TX_CL_CAL;
-                else
-                        ah->enabled_cals &= ~TX_CL_CAL;
-        }
-
         return 0;
 }
 
@@ -1173,6 +1172,10 @@ skip_ws_det:
                  * is_on == 0 means MRC CCK is OFF (more noise imm)
                  */
                 bool is_on = param ? 1 : 0;
+
+                if (ah->caps.rx_chainmask == 1)
+                        break;
+
                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
                               AR_PHY_MRC_CCK_ENABLE, is_on);
                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
@@ -1190,8 +1193,6 @@ skip_ws_det:
                 }
         break;
         }
-        case ATH9K_ANI_PRESENT:
-                break;
         default:
                 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
                 return false;
@@ -1413,65 +1414,111 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 }
 
-static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
-                                                  bool enable)
+#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
+
+static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
 {
+        struct ath9k_hw_capabilities *pCap = &ah->caps;
         u8 ant_div_ctl1;
         u32 regval;
 
-        if (!AR_SREV_9565(ah))
+        if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
                 return;
 
-        ah->shared_chain_lnadiv = enable;
+        if (AR_SREV_9485(ah)) {
+                regval = ar9003_hw_ant_ctrl_common_2_get(ah,
+                                                 IS_CHAN_2GHZ(ah->curchan));
+                if (enable) {
+                        regval &= ~AR_SWITCH_TABLE_COM2_ALL;
+                        regval |= ah->config.ant_ctrl_comm2g_switch_enable;
+                }
+                REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
+                              AR_SWITCH_TABLE_COM2_ALL, regval);
+        }
+
         ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
 
+        /*
+         * Set MAIN/ALT LNA conf.
+         * Set MAIN/ALT gain_tb.
+         */
         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
         regval &= (~AR_ANT_DIV_CTRL_ALL);
         regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
-        regval &= ~AR_PHY_ANT_DIV_LNADIV;
-        regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
-
-        if (enable)
-                regval |= AR_ANT_DIV_ENABLE;
-
         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 
-        regval = REG_READ(ah, AR_PHY_CCK_DETECT);
-        regval &= ~AR_FAST_DIV_ENABLE;
-        regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
-
-        if (enable)
-                regval |= AR_FAST_DIV_ENABLE;
-
-        REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
-
-        if (enable) {
-                REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
-                            (1 << AR_PHY_ANT_SW_RX_PROT_S));
-                if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
-                        REG_SET_BIT(ah, AR_PHY_RESTART,
-                                    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
-                REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
-                            AR_BTCOEX_WL_LNADIV_FORCE_ON);
-        } else {
-                REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
-                REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
-                            (1 << AR_PHY_ANT_SW_RX_PROT_S));
-                REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
-                REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
-                            AR_BTCOEX_WL_LNADIV_FORCE_ON);
-
+        if (AR_SREV_9485_11_OR_LATER(ah)) {
+                /*
+                 * Enable LNA diversity.
+                 */
                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
-                regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
-                        AR_PHY_ANT_DIV_ALT_LNACONF |
-                        AR_PHY_ANT_DIV_MAIN_GAINTB |
-                        AR_PHY_ANT_DIV_ALT_GAINTB);
-                regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
-                regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
+                regval &= ~AR_PHY_ANT_DIV_LNADIV;
+                regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
+                if (enable)
+                        regval |= AR_ANT_DIV_ENABLE;
+
                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+
+                /*
+                 * Enable fast antenna diversity.
+                 */
+                regval = REG_READ(ah, AR_PHY_CCK_DETECT);
+                regval &= ~AR_FAST_DIV_ENABLE;
+                regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
+                if (enable)
+                        regval |= AR_FAST_DIV_ENABLE;
+
+                REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
+
+                if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
+                        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+                        regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
+                                     AR_PHY_ANT_DIV_ALT_LNACONF |
+                                     AR_PHY_ANT_DIV_ALT_GAINTB |
+                                     AR_PHY_ANT_DIV_MAIN_GAINTB));
+                        /*
+                         * Set MAIN to LNA1 and ALT to LNA2 at the
+                         * beginning.
+                         */
+                        regval |= (ATH_ANT_DIV_COMB_LNA1 <<
+                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
+                        regval |= (ATH_ANT_DIV_COMB_LNA2 <<
+                                   AR_PHY_ANT_DIV_ALT_LNACONF_S);
+                        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+                }
+        } else if (AR_SREV_9565(ah)) {
+                if (enable) {
+                        REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
+                                    (1 << AR_PHY_ANT_SW_RX_PROT_S));
+                        if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
+                                REG_SET_BIT(ah, AR_PHY_RESTART,
+                                            AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
+                        REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
+                                    AR_BTCOEX_WL_LNADIV_FORCE_ON);
+                } else {
+                        REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
+                        REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
+                                    (1 << AR_PHY_ANT_SW_RX_PROT_S));
+                        REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
+                        REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
+                                    AR_BTCOEX_WL_LNADIV_FORCE_ON);
+
+                        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+                        regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
+                                    AR_PHY_ANT_DIV_ALT_LNACONF |
+                                    AR_PHY_ANT_DIV_MAIN_GAINTB |
+                                    AR_PHY_ANT_DIV_ALT_GAINTB);
+                        regval |= (ATH_ANT_DIV_COMB_LNA1 <<
+                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
+                        regval |= (ATH_ANT_DIV_COMB_LNA2 <<
+                                   AR_PHY_ANT_DIV_ALT_LNACONF_S);
+                        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+                }
         }
 }
 
+#endif
+
 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
                                       struct ath9k_channel *chan,
                                       u8 *ini_reloaded)
@@ -1518,6 +1565,18 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
 
         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 
+        if (AR_SREV_9462_20_OR_LATER(ah)) {
+                /*
+                 * CUS217 mix LNA mode.
+                 */
+                if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
+                        REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
+                                        1, regWrites);
+                        REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
+                                        modesIndex, regWrites);
+                }
+        }
+
         /*
          * For 5GHz channels requiring Fast Clock, apply
          * different modal values.
@@ -1528,7 +1587,11 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
         if (AR_SREV_9565(ah))
                 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
 
-        REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
+        /*
+         * JAPAN regulatory.
+         */
+        if (chan->channel == 2484)
+                ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 
         ah->modes_index = modesIndex;
         *ini_reloaded = true;
@@ -1631,11 +1694,14 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
 
         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
-        ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
         ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
         ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
         ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
 
+#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
+        ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
+#endif
+
         ar9003_hw_set_nf_limits(ah);
         ar9003_hw_set_radar_conf(ah);
         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));