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path: root/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_eeprom.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c24
1 files changed, 20 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index 819b0a6cb83e..45fe5c2ec3b9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3034,6 +3034,8 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3034 return !!(pBase->featureEnable & BIT(5)); 3034 return !!(pBase->featureEnable & BIT(5));
3035 case EEP_CHAIN_MASK_REDUCE: 3035 case EEP_CHAIN_MASK_REDUCE:
3036 return (pBase->miscConfiguration >> 0x3) & 0x1; 3036 return (pBase->miscConfiguration >> 0x3) & 0x1;
3037 case EEP_ANT_DIV_CTL1:
3038 return le32_to_cpu(eep->base_ext1.ant_div_control);
3037 default: 3039 default:
3038 return 0; 3040 return 0;
3039 } 3041 }
@@ -3513,11 +3515,25 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3513 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz); 3515 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3514 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value); 3516 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3515 3517
3516 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz); 3518 if (!AR_SREV_9485(ah)) {
3517 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value); 3519 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3520 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL,
3521 value);
3518 3522
3519 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz); 3523 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3520 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value); 3524 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL,
3525 value);
3526 }
3527
3528 if (AR_SREV_9485(ah)) {
3529 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3530 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
3531 value);
3532 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
3533 value >> 6);
3534 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
3535 value >> 7);
3536 }
3521} 3537}
3522 3538
3523static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) 3539static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)