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path: root/drivers/net/wireless/ath/ath9k/ar9002_hw.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9002_hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c66
1 files changed, 0 insertions, 66 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 75b80d13ff91..303c63da5ea3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -85,21 +85,6 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
85 ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 85 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
86 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), 86 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
87 2); 87 2);
88 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
89 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
90 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
91 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
92 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
93
94 if (ah->config.pcie_clock_req)
95 INIT_INI_ARRAY(&ah->iniPcieSerdes,
96 ar9287PciePhy_clkreq_off_L1_9287_1_0,
97 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
98 else
99 INIT_INI_ARRAY(&ah->iniPcieSerdes,
100 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
101 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
102 2);
103 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 88 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
104 89
105 90
@@ -118,21 +103,6 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
118 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 103 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
119 2); 104 2);
120 } 105 }
121 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
122 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
123 ARRAY_SIZE(ar9285Modes_9285), 6);
124 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
125 ARRAY_SIZE(ar9285Common_9285), 2);
126
127 if (ah->config.pcie_clock_req) {
128 INIT_INI_ARRAY(&ah->iniPcieSerdes,
129 ar9285PciePhy_clkreq_off_L1_9285,
130 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
131 } else {
132 INIT_INI_ARRAY(&ah->iniPcieSerdes,
133 ar9285PciePhy_clkreq_always_on_L1_9285,
134 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
135 }
136 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 106 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
137 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, 107 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
138 ARRAY_SIZE(ar9280Modes_9280_2), 6); 108 ARRAY_SIZE(ar9280Modes_9280_2), 6);
@@ -151,11 +121,6 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
151 INIT_INI_ARRAY(&ah->iniModesAdditional, 121 INIT_INI_ARRAY(&ah->iniModesAdditional,
152 ar9280Modes_fast_clock_9280_2, 122 ar9280Modes_fast_clock_9280_2,
153 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 123 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
154 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
155 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
156 ARRAY_SIZE(ar9280Modes_9280), 6);
157 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
158 ARRAY_SIZE(ar9280Common_9280), 2);
159 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 124 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
160 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, 125 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
161 ARRAY_SIZE(ar5416Modes_9160), 6); 126 ARRAY_SIZE(ar5416Modes_9160), 6);
@@ -305,10 +270,6 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
305 INIT_INI_ARRAY(&ah->iniModesRxGain, 270 INIT_INI_ARRAY(&ah->iniModesRxGain,
306 ar9287Modes_rx_gain_9287_1_1, 271 ar9287Modes_rx_gain_9287_1_1,
307 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); 272 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
308 else if (AR_SREV_9287_10(ah))
309 INIT_INI_ARRAY(&ah->iniModesRxGain,
310 ar9287Modes_rx_gain_9287_1_0,
311 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
312 else if (AR_SREV_9280_20(ah)) 273 else if (AR_SREV_9280_20(ah))
313 ar9280_20_hw_init_rxgain_ini(ah); 274 ar9280_20_hw_init_rxgain_ini(ah);
314 275
@@ -316,10 +277,6 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
316 INIT_INI_ARRAY(&ah->iniModesTxGain, 277 INIT_INI_ARRAY(&ah->iniModesTxGain,
317 ar9287Modes_tx_gain_9287_1_1, 278 ar9287Modes_tx_gain_9287_1_1,
318 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); 279 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
319 } else if (AR_SREV_9287_10(ah)) {
320 INIT_INI_ARRAY(&ah->iniModesTxGain,
321 ar9287Modes_tx_gain_9287_1_0,
322 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
323 } else if (AR_SREV_9280_20(ah)) { 280 } else if (AR_SREV_9280_20(ah)) {
324 ar9280_20_hw_init_txgain_ini(ah); 281 ar9280_20_hw_init_txgain_ini(ah);
325 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 282 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
@@ -389,29 +346,6 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
389 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), 346 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
390 INI_RA(&ah->iniPcieSerdes, i, 1)); 347 INI_RA(&ah->iniPcieSerdes, i, 1));
391 } 348 }
392 } else if (AR_SREV_9280(ah) &&
393 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
394 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
395 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
396
397 /* RX shut off when elecidle is asserted */
398 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
399 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
400 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
401
402 /* Shut off CLKREQ active in L1 */
403 if (ah->config.pcie_clock_req)
404 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
405 else
406 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
407
408 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
409 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
410 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
411
412 /* Load the new settings */
413 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
414
415 } else { 349 } else {
416 ENABLE_REGWRITE_BUFFER(ah); 350 ENABLE_REGWRITE_BUFFER(ah);
417 351