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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar5008_phy.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c1374
1 files changed, 1374 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
new file mode 100644
index 000000000000..b2c17c98bb38
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -0,0 +1,1374 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
21
22/* All code below is for non single-chip solutions */
23
24/**
25 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
26 * @rfbuf:
27 * @reg32:
28 * @numBits:
29 * @firstBit:
30 * @column:
31 *
32 * Performs analog "swizzling" of parameters into their location.
33 * Used on external AR2133/AR5133 radios.
34 */
35static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
36 u32 numBits, u32 firstBit,
37 u32 column)
38{
39 u32 tmp32, mask, arrayEntry, lastBit;
40 int32_t bitPosition, bitsLeft;
41
42 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
43 arrayEntry = (firstBit - 1) / 8;
44 bitPosition = (firstBit - 1) % 8;
45 bitsLeft = numBits;
46 while (bitsLeft > 0) {
47 lastBit = (bitPosition + bitsLeft > 8) ?
48 8 : bitPosition + bitsLeft;
49 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
50 (column * 8);
51 rfBuf[arrayEntry] &= ~mask;
52 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
53 (column * 8)) & mask;
54 bitsLeft -= 8 - bitPosition;
55 tmp32 = tmp32 >> (8 - bitPosition);
56 bitPosition = 0;
57 arrayEntry++;
58 }
59}
60
61/*
62 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
63 * rf_pwd_icsyndiv.
64 *
65 * Theoretical Rules:
66 * if 2 GHz band
67 * if forceBiasAuto
68 * if synth_freq < 2412
69 * bias = 0
70 * else if 2412 <= synth_freq <= 2422
71 * bias = 1
72 * else // synth_freq > 2422
73 * bias = 2
74 * else if forceBias > 0
75 * bias = forceBias & 7
76 * else
77 * no change, use value from ini file
78 * else
79 * no change, invalid band
80 *
81 * 1st Mod:
82 * 2422 also uses value of 2
83 * <approved>
84 *
85 * 2nd Mod:
86 * Less than 2412 uses value of 0, 2412 and above uses value of 2
87 */
88static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
89{
90 struct ath_common *common = ath9k_hw_common(ah);
91 u32 tmp_reg;
92 int reg_writes = 0;
93 u32 new_bias = 0;
94
95 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
96 return;
97
98 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
99
100 if (synth_freq < 2412)
101 new_bias = 0;
102 else if (synth_freq < 2422)
103 new_bias = 1;
104 else
105 new_bias = 2;
106
107 /* pre-reverse this field */
108 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
109
110 ath_print(common, ATH_DBG_CONFIG,
111 "Force rf_pwd_icsyndiv to %1d on %4d\n",
112 new_bias, synth_freq);
113
114 /* swizzle rf_pwd_icsyndiv */
115 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
116
117 /* write Bank 6 with new params */
118 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
119}
120
121/**
122 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
123 * @ah: atheros hardware stucture
124 * @chan:
125 *
126 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
127 * the channel value. Assumes writes enabled to analog bus and bank6 register
128 * cache in ah->analogBank6Data.
129 */
130static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
131{
132 struct ath_common *common = ath9k_hw_common(ah);
133 u32 channelSel = 0;
134 u32 bModeSynth = 0;
135 u32 aModeRefSel = 0;
136 u32 reg32 = 0;
137 u16 freq;
138 struct chan_centers centers;
139
140 ath9k_hw_get_channel_centers(ah, chan, &centers);
141 freq = centers.synth_center;
142
143 if (freq < 4800) {
144 u32 txctl;
145
146 if (((freq - 2192) % 5) == 0) {
147 channelSel = ((freq - 672) * 2 - 3040) / 10;
148 bModeSynth = 0;
149 } else if (((freq - 2224) % 5) == 0) {
150 channelSel = ((freq - 704) * 2 - 3040) / 10;
151 bModeSynth = 1;
152 } else {
153 ath_print(common, ATH_DBG_FATAL,
154 "Invalid channel %u MHz\n", freq);
155 return -EINVAL;
156 }
157
158 channelSel = (channelSel << 2) & 0xff;
159 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
160
161 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
162 if (freq == 2484) {
163
164 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
165 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
166 } else {
167 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
168 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
169 }
170
171 } else if ((freq % 20) == 0 && freq >= 5120) {
172 channelSel =
173 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
174 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
175 } else if ((freq % 10) == 0) {
176 channelSel =
177 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
178 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
179 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
180 else
181 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
182 } else if ((freq % 5) == 0) {
183 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
184 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
185 } else {
186 ath_print(common, ATH_DBG_FATAL,
187 "Invalid channel %u MHz\n", freq);
188 return -EINVAL;
189 }
190
191 ar5008_hw_force_bias(ah, freq);
192
193 reg32 =
194 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
195 (1 << 5) | 0x1;
196
197 REG_WRITE(ah, AR_PHY(0x37), reg32);
198
199 ah->curchan = chan;
200 ah->curchan_rad_index = -1;
201
202 return 0;
203}
204
205/**
206 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
207 * @ah: atheros hardware structure
208 * @chan:
209 *
210 * For non single-chip solutions. Converts to baseband spur frequency given the
211 * input channel frequency and compute register settings below.
212 */
213static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
214 struct ath9k_channel *chan)
215{
216 int bb_spur = AR_NO_SPUR;
217 int bin, cur_bin;
218 int spur_freq_sd;
219 int spur_delta_phase;
220 int denominator;
221 int upper, lower, cur_vit_mask;
222 int tmp, new;
223 int i;
224 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
225 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
226 };
227 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
228 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
229 };
230 int inc[4] = { 0, 100, 0, 0 };
231
232 int8_t mask_m[123];
233 int8_t mask_p[123];
234 int8_t mask_amt;
235 int tmp_mask;
236 int cur_bb_spur;
237 bool is2GHz = IS_CHAN_2GHZ(chan);
238
239 memset(&mask_m, 0, sizeof(int8_t) * 123);
240 memset(&mask_p, 0, sizeof(int8_t) * 123);
241
242 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
243 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
244 if (AR_NO_SPUR == cur_bb_spur)
245 break;
246 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
247 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
248 bb_spur = cur_bb_spur;
249 break;
250 }
251 }
252
253 if (AR_NO_SPUR == bb_spur)
254 return;
255
256 bin = bb_spur * 32;
257
258 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
259 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
260 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
261 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
262 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
263
264 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
265
266 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
267 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
268 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
269 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
270 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
271 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
272
273 spur_delta_phase = ((bb_spur * 524288) / 100) &
274 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
275
276 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
277 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
278
279 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
280 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
281 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
282 REG_WRITE(ah, AR_PHY_TIMING11, new);
283
284 cur_bin = -6000;
285 upper = bin + 100;
286 lower = bin - 100;
287
288 for (i = 0; i < 4; i++) {
289 int pilot_mask = 0;
290 int chan_mask = 0;
291 int bp = 0;
292 for (bp = 0; bp < 30; bp++) {
293 if ((cur_bin > lower) && (cur_bin < upper)) {
294 pilot_mask = pilot_mask | 0x1 << bp;
295 chan_mask = chan_mask | 0x1 << bp;
296 }
297 cur_bin += 100;
298 }
299 cur_bin += inc[i];
300 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
301 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
302 }
303
304 cur_vit_mask = 6100;
305 upper = bin + 120;
306 lower = bin - 120;
307
308 for (i = 0; i < 123; i++) {
309 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
310
311 /* workaround for gcc bug #37014 */
312 volatile int tmp_v = abs(cur_vit_mask - bin);
313
314 if (tmp_v < 75)
315 mask_amt = 1;
316 else
317 mask_amt = 0;
318 if (cur_vit_mask < 0)
319 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
320 else
321 mask_p[cur_vit_mask / 100] = mask_amt;
322 }
323 cur_vit_mask -= 100;
324 }
325
326 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
327 | (mask_m[48] << 26) | (mask_m[49] << 24)
328 | (mask_m[50] << 22) | (mask_m[51] << 20)
329 | (mask_m[52] << 18) | (mask_m[53] << 16)
330 | (mask_m[54] << 14) | (mask_m[55] << 12)
331 | (mask_m[56] << 10) | (mask_m[57] << 8)
332 | (mask_m[58] << 6) | (mask_m[59] << 4)
333 | (mask_m[60] << 2) | (mask_m[61] << 0);
334 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
335 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
336
337 tmp_mask = (mask_m[31] << 28)
338 | (mask_m[32] << 26) | (mask_m[33] << 24)
339 | (mask_m[34] << 22) | (mask_m[35] << 20)
340 | (mask_m[36] << 18) | (mask_m[37] << 16)
341 | (mask_m[48] << 14) | (mask_m[39] << 12)
342 | (mask_m[40] << 10) | (mask_m[41] << 8)
343 | (mask_m[42] << 6) | (mask_m[43] << 4)
344 | (mask_m[44] << 2) | (mask_m[45] << 0);
345 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
346 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
347
348 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
349 | (mask_m[18] << 26) | (mask_m[18] << 24)
350 | (mask_m[20] << 22) | (mask_m[20] << 20)
351 | (mask_m[22] << 18) | (mask_m[22] << 16)
352 | (mask_m[24] << 14) | (mask_m[24] << 12)
353 | (mask_m[25] << 10) | (mask_m[26] << 8)
354 | (mask_m[27] << 6) | (mask_m[28] << 4)
355 | (mask_m[29] << 2) | (mask_m[30] << 0);
356 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
357 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
358
359 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
360 | (mask_m[2] << 26) | (mask_m[3] << 24)
361 | (mask_m[4] << 22) | (mask_m[5] << 20)
362 | (mask_m[6] << 18) | (mask_m[7] << 16)
363 | (mask_m[8] << 14) | (mask_m[9] << 12)
364 | (mask_m[10] << 10) | (mask_m[11] << 8)
365 | (mask_m[12] << 6) | (mask_m[13] << 4)
366 | (mask_m[14] << 2) | (mask_m[15] << 0);
367 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
368 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
369
370 tmp_mask = (mask_p[15] << 28)
371 | (mask_p[14] << 26) | (mask_p[13] << 24)
372 | (mask_p[12] << 22) | (mask_p[11] << 20)
373 | (mask_p[10] << 18) | (mask_p[9] << 16)
374 | (mask_p[8] << 14) | (mask_p[7] << 12)
375 | (mask_p[6] << 10) | (mask_p[5] << 8)
376 | (mask_p[4] << 6) | (mask_p[3] << 4)
377 | (mask_p[2] << 2) | (mask_p[1] << 0);
378 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
379 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
380
381 tmp_mask = (mask_p[30] << 28)
382 | (mask_p[29] << 26) | (mask_p[28] << 24)
383 | (mask_p[27] << 22) | (mask_p[26] << 20)
384 | (mask_p[25] << 18) | (mask_p[24] << 16)
385 | (mask_p[23] << 14) | (mask_p[22] << 12)
386 | (mask_p[21] << 10) | (mask_p[20] << 8)
387 | (mask_p[19] << 6) | (mask_p[18] << 4)
388 | (mask_p[17] << 2) | (mask_p[16] << 0);
389 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
390 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
391
392 tmp_mask = (mask_p[45] << 28)
393 | (mask_p[44] << 26) | (mask_p[43] << 24)
394 | (mask_p[42] << 22) | (mask_p[41] << 20)
395 | (mask_p[40] << 18) | (mask_p[39] << 16)
396 | (mask_p[38] << 14) | (mask_p[37] << 12)
397 | (mask_p[36] << 10) | (mask_p[35] << 8)
398 | (mask_p[34] << 6) | (mask_p[33] << 4)
399 | (mask_p[32] << 2) | (mask_p[31] << 0);
400 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
401 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
402
403 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
404 | (mask_p[59] << 26) | (mask_p[58] << 24)
405 | (mask_p[57] << 22) | (mask_p[56] << 20)
406 | (mask_p[55] << 18) | (mask_p[54] << 16)
407 | (mask_p[53] << 14) | (mask_p[52] << 12)
408 | (mask_p[51] << 10) | (mask_p[50] << 8)
409 | (mask_p[49] << 6) | (mask_p[48] << 4)
410 | (mask_p[47] << 2) | (mask_p[46] << 0);
411 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
412 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
413}
414
415/**
416 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
417 * @ah: atheros hardware structure
418 *
419 * Only required for older devices with external AR2133/AR5133 radios.
420 */
421static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
422{
423#define ATH_ALLOC_BANK(bank, size) do { \
424 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
425 if (!bank) { \
426 ath_print(common, ATH_DBG_FATAL, \
427 "Cannot allocate RF banks\n"); \
428 return -ENOMEM; \
429 } \
430 } while (0);
431
432 struct ath_common *common = ath9k_hw_common(ah);
433
434 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
435
436 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
437 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
438 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
439 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
440 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
441 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
442 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
443 ATH_ALLOC_BANK(ah->addac5416_21,
444 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
445 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
446
447 return 0;
448#undef ATH_ALLOC_BANK
449}
450
451
452/**
453 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
454 * @ah: atheros hardware struture
455 * For the external AR2133/AR5133 radios banks.
456 */
457static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
458{
459#define ATH_FREE_BANK(bank) do { \
460 kfree(bank); \
461 bank = NULL; \
462 } while (0);
463
464 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
465
466 ATH_FREE_BANK(ah->analogBank0Data);
467 ATH_FREE_BANK(ah->analogBank1Data);
468 ATH_FREE_BANK(ah->analogBank2Data);
469 ATH_FREE_BANK(ah->analogBank3Data);
470 ATH_FREE_BANK(ah->analogBank6Data);
471 ATH_FREE_BANK(ah->analogBank6TPCData);
472 ATH_FREE_BANK(ah->analogBank7Data);
473 ATH_FREE_BANK(ah->addac5416_21);
474 ATH_FREE_BANK(ah->bank6Temp);
475
476#undef ATH_FREE_BANK
477}
478
479/* *
480 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
481 * @ah: atheros hardware structure
482 * @chan:
483 * @modesIndex:
484 *
485 * Used for the external AR2133/AR5133 radios.
486 *
487 * Reads the EEPROM header info from the device structure and programs
488 * all rf registers. This routine requires access to the analog
489 * rf device. This is not required for single-chip devices.
490 */
491static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
492 struct ath9k_channel *chan,
493 u16 modesIndex)
494{
495 u32 eepMinorRev;
496 u32 ob5GHz = 0, db5GHz = 0;
497 u32 ob2GHz = 0, db2GHz = 0;
498 int regWrites = 0;
499
500 /*
501 * Software does not need to program bank data
502 * for single chip devices, that is AR9280 or anything
503 * after that.
504 */
505 if (AR_SREV_9280_10_OR_LATER(ah))
506 return true;
507
508 /* Setup rf parameters */
509 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
510
511 /* Setup Bank 0 Write */
512 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
513
514 /* Setup Bank 1 Write */
515 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
516
517 /* Setup Bank 2 Write */
518 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
519
520 /* Setup Bank 6 Write */
521 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
522 modesIndex);
523 {
524 int i;
525 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
526 ah->analogBank6Data[i] =
527 INI_RA(&ah->iniBank6TPC, i, modesIndex);
528 }
529 }
530
531 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
532 if (eepMinorRev >= 2) {
533 if (IS_CHAN_2GHZ(chan)) {
534 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
535 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
536 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
537 ob2GHz, 3, 197, 0);
538 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
539 db2GHz, 3, 194, 0);
540 } else {
541 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
542 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
543 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
544 ob5GHz, 3, 203, 0);
545 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
546 db5GHz, 3, 200, 0);
547 }
548 }
549
550 /* Setup Bank 7 Setup */
551 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
552
553 /* Write Analog registers */
554 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
555 regWrites);
556 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
557 regWrites);
558 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
559 regWrites);
560 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
561 regWrites);
562 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
563 regWrites);
564 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
565 regWrites);
566
567 return true;
568}
569
570static void ar5008_hw_init_bb(struct ath_hw *ah,
571 struct ath9k_channel *chan)
572{
573 u32 synthDelay;
574
575 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
576 if (IS_CHAN_B(chan))
577 synthDelay = (4 * synthDelay) / 22;
578 else
579 synthDelay /= 10;
580
581 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
582
583 udelay(synthDelay + BASE_ACTIVATE_DELAY);
584}
585
586static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
587{
588 int rx_chainmask, tx_chainmask;
589
590 rx_chainmask = ah->rxchainmask;
591 tx_chainmask = ah->txchainmask;
592
593 ENABLE_REGWRITE_BUFFER(ah);
594
595 switch (rx_chainmask) {
596 case 0x5:
597 DISABLE_REGWRITE_BUFFER(ah);
598 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
599 AR_PHY_SWAP_ALT_CHAIN);
600 ENABLE_REGWRITE_BUFFER(ah);
601 case 0x3:
602 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
603 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
604 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
605 break;
606 }
607 case 0x1:
608 case 0x2:
609 case 0x7:
610 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
611 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
612 break;
613 default:
614 break;
615 }
616
617 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
618
619 REGWRITE_BUFFER_FLUSH(ah);
620 DISABLE_REGWRITE_BUFFER(ah);
621
622 if (tx_chainmask == 0x5) {
623 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
624 AR_PHY_SWAP_ALT_CHAIN);
625 }
626 if (AR_SREV_9100(ah))
627 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
628 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
629}
630
631static void ar5008_hw_override_ini(struct ath_hw *ah,
632 struct ath9k_channel *chan)
633{
634 u32 val;
635
636 /*
637 * Set the RX_ABORT and RX_DIS and clear if off only after
638 * RXE is set for MAC. This prevents frames with corrupted
639 * descriptor status.
640 */
641 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
642
643 if (AR_SREV_9280_10_OR_LATER(ah)) {
644 val = REG_READ(ah, AR_PCU_MISC_MODE2);
645
646 if (!AR_SREV_9271(ah))
647 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
648
649 if (AR_SREV_9287_10_OR_LATER(ah))
650 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
651
652 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
653 }
654
655 if (!AR_SREV_5416_20_OR_LATER(ah) ||
656 AR_SREV_9280_10_OR_LATER(ah))
657 return;
658 /*
659 * Disable BB clock gating
660 * Necessary to avoid issues on AR5416 2.0
661 */
662 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
663
664 /*
665 * Disable RIFS search on some chips to avoid baseband
666 * hang issues.
667 */
668 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
669 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
670 val &= ~AR_PHY_RIFS_INIT_DELAY;
671 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
672 }
673}
674
675static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
676 struct ath9k_channel *chan)
677{
678 u32 phymode;
679 u32 enableDacFifo = 0;
680
681 if (AR_SREV_9285_10_OR_LATER(ah))
682 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
683 AR_PHY_FC_ENABLE_DAC_FIFO);
684
685 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
686 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
687
688 if (IS_CHAN_HT40(chan)) {
689 phymode |= AR_PHY_FC_DYN2040_EN;
690
691 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
692 (chan->chanmode == CHANNEL_G_HT40PLUS))
693 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
694
695 }
696 REG_WRITE(ah, AR_PHY_TURBO, phymode);
697
698 ath9k_hw_set11nmac2040(ah);
699
700 ENABLE_REGWRITE_BUFFER(ah);
701
702 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
703 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
704
705 REGWRITE_BUFFER_FLUSH(ah);
706 DISABLE_REGWRITE_BUFFER(ah);
707}
708
709
710static int ar5008_hw_process_ini(struct ath_hw *ah,
711 struct ath9k_channel *chan)
712{
713 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
714 int i, regWrites = 0;
715 struct ieee80211_channel *channel = chan->chan;
716 u32 modesIndex, freqIndex;
717
718 switch (chan->chanmode) {
719 case CHANNEL_A:
720 case CHANNEL_A_HT20:
721 modesIndex = 1;
722 freqIndex = 1;
723 break;
724 case CHANNEL_A_HT40PLUS:
725 case CHANNEL_A_HT40MINUS:
726 modesIndex = 2;
727 freqIndex = 1;
728 break;
729 case CHANNEL_G:
730 case CHANNEL_G_HT20:
731 case CHANNEL_B:
732 modesIndex = 4;
733 freqIndex = 2;
734 break;
735 case CHANNEL_G_HT40PLUS:
736 case CHANNEL_G_HT40MINUS:
737 modesIndex = 3;
738 freqIndex = 2;
739 break;
740
741 default:
742 return -EINVAL;
743 }
744
745 if (AR_SREV_9287_12_OR_LATER(ah)) {
746 /* Enable ASYNC FIFO */
747 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
748 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
749 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
750 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
751 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
752 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
753 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
754 }
755
756 /*
757 * Set correct baseband to analog shift setting to
758 * access analog chips.
759 */
760 REG_WRITE(ah, AR_PHY(0), 0x00000007);
761
762 /* Write ADDAC shifts */
763 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
764 ah->eep_ops->set_addac(ah, chan);
765
766 if (AR_SREV_5416_22_OR_LATER(ah)) {
767 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
768 } else {
769 struct ar5416IniArray temp;
770 u32 addacSize =
771 sizeof(u32) * ah->iniAddac.ia_rows *
772 ah->iniAddac.ia_columns;
773
774 /* For AR5416 2.0/2.1 */
775 memcpy(ah->addac5416_21,
776 ah->iniAddac.ia_array, addacSize);
777
778 /* override CLKDRV value at [row, column] = [31, 1] */
779 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
780
781 temp.ia_array = ah->addac5416_21;
782 temp.ia_columns = ah->iniAddac.ia_columns;
783 temp.ia_rows = ah->iniAddac.ia_rows;
784 REG_WRITE_ARRAY(&temp, 1, regWrites);
785 }
786
787 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
788
789 ENABLE_REGWRITE_BUFFER(ah);
790
791 for (i = 0; i < ah->iniModes.ia_rows; i++) {
792 u32 reg = INI_RA(&ah->iniModes, i, 0);
793 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
794
795 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
796 val &= ~AR_AN_TOP2_PWDCLKIND;
797
798 REG_WRITE(ah, reg, val);
799
800 if (reg >= 0x7800 && reg < 0x78a0
801 && ah->config.analog_shiftreg) {
802 udelay(100);
803 }
804
805 DO_DELAY(regWrites);
806 }
807
808 REGWRITE_BUFFER_FLUSH(ah);
809 DISABLE_REGWRITE_BUFFER(ah);
810
811 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
812 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
813
814 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
815 AR_SREV_9287_10_OR_LATER(ah))
816 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
817
818 if (AR_SREV_9271_10(ah))
819 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
820 modesIndex, regWrites);
821
822 ENABLE_REGWRITE_BUFFER(ah);
823
824 /* Write common array parameters */
825 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
826 u32 reg = INI_RA(&ah->iniCommon, i, 0);
827 u32 val = INI_RA(&ah->iniCommon, i, 1);
828
829 REG_WRITE(ah, reg, val);
830
831 if (reg >= 0x7800 && reg < 0x78a0
832 && ah->config.analog_shiftreg) {
833 udelay(100);
834 }
835
836 DO_DELAY(regWrites);
837 }
838
839 REGWRITE_BUFFER_FLUSH(ah);
840 DISABLE_REGWRITE_BUFFER(ah);
841
842 if (AR_SREV_9271(ah)) {
843 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
844 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
845 modesIndex, regWrites);
846 else
847 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
848 modesIndex, regWrites);
849 }
850
851 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
852
853 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
854 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
855 regWrites);
856 }
857
858 ar5008_hw_override_ini(ah, chan);
859 ar5008_hw_set_channel_regs(ah, chan);
860 ar5008_hw_init_chain_masks(ah);
861 ath9k_olc_init(ah);
862
863 /* Set TX power */
864 ah->eep_ops->set_txpower(ah, chan,
865 ath9k_regd_get_ctl(regulatory, chan),
866 channel->max_antenna_gain * 2,
867 channel->max_power * 2,
868 min((u32) MAX_RATE_POWER,
869 (u32) regulatory->power_limit));
870
871 /* Write analog registers */
872 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
873 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
874 "ar5416SetRfRegs failed\n");
875 return -EIO;
876 }
877
878 return 0;
879}
880
881static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
882{
883 u32 rfMode = 0;
884
885 if (chan == NULL)
886 return;
887
888 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
889 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
890
891 if (!AR_SREV_9280_10_OR_LATER(ah))
892 rfMode |= (IS_CHAN_5GHZ(chan)) ?
893 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
894
895 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
896 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
897
898 REG_WRITE(ah, AR_PHY_MODE, rfMode);
899}
900
901static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
902{
903 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
904}
905
906static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
907 struct ath9k_channel *chan)
908{
909 u32 coef_scaled, ds_coef_exp, ds_coef_man;
910 u32 clockMhzScaled = 0x64000000;
911 struct chan_centers centers;
912
913 if (IS_CHAN_HALF_RATE(chan))
914 clockMhzScaled = clockMhzScaled >> 1;
915 else if (IS_CHAN_QUARTER_RATE(chan))
916 clockMhzScaled = clockMhzScaled >> 2;
917
918 ath9k_hw_get_channel_centers(ah, chan, &centers);
919 coef_scaled = clockMhzScaled / centers.synth_center;
920
921 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
922 &ds_coef_exp);
923
924 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
925 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
926 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
927 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
928
929 coef_scaled = (9 * coef_scaled) / 10;
930
931 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
932 &ds_coef_exp);
933
934 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
935 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
936 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
937 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
938}
939
940static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
941{
942 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
943 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
944 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
945}
946
947static void ar5008_hw_rfbus_done(struct ath_hw *ah)
948{
949 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
950 if (IS_CHAN_B(ah->curchan))
951 synthDelay = (4 * synthDelay) / 22;
952 else
953 synthDelay /= 10;
954
955 udelay(synthDelay + BASE_ACTIVATE_DELAY);
956
957 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
958}
959
960static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
961{
962 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
963 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
964
965 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
966 AR_GPIO_INPUT_MUX2_RFSILENT);
967
968 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
969 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
970}
971
972static void ar5008_restore_chainmask(struct ath_hw *ah)
973{
974 int rx_chainmask = ah->rxchainmask;
975
976 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
977 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
978 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
979 }
980}
981
982static void ar5008_set_diversity(struct ath_hw *ah, bool value)
983{
984 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
985 if (value)
986 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
987 else
988 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
989 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
990}
991
992static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
993 struct ath9k_channel *chan)
994{
995 if (chan && IS_CHAN_5GHZ(chan))
996 return 0x1450;
997 return 0x1458;
998}
999
1000static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1001 struct ath9k_channel *chan)
1002{
1003 u32 pll;
1004
1005 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1006
1007 if (chan && IS_CHAN_HALF_RATE(chan))
1008 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1009 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1010 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1011
1012 if (chan && IS_CHAN_5GHZ(chan))
1013 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1014 else
1015 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1016
1017 return pll;
1018}
1019
1020static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1021 struct ath9k_channel *chan)
1022{
1023 u32 pll;
1024
1025 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1026
1027 if (chan && IS_CHAN_HALF_RATE(chan))
1028 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1029 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1030 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1031
1032 if (chan && IS_CHAN_5GHZ(chan))
1033 pll |= SM(0xa, AR_RTC_PLL_DIV);
1034 else
1035 pll |= SM(0xb, AR_RTC_PLL_DIV);
1036
1037 return pll;
1038}
1039
1040static bool ar5008_hw_ani_control(struct ath_hw *ah,
1041 enum ath9k_ani_cmd cmd, int param)
1042{
1043 struct ar5416AniState *aniState = ah->curani;
1044 struct ath_common *common = ath9k_hw_common(ah);
1045
1046 switch (cmd & ah->ani_function) {
1047 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1048 u32 level = param;
1049
1050 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1051 ath_print(common, ATH_DBG_ANI,
1052 "level out of range (%u > %u)\n",
1053 level,
1054 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
1055 return false;
1056 }
1057
1058 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1059 AR_PHY_DESIRED_SZ_TOT_DES,
1060 ah->totalSizeDesired[level]);
1061 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1062 AR_PHY_AGC_CTL1_COARSE_LOW,
1063 ah->coarse_low[level]);
1064 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1065 AR_PHY_AGC_CTL1_COARSE_HIGH,
1066 ah->coarse_high[level]);
1067 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1068 AR_PHY_FIND_SIG_FIRPWR,
1069 ah->firpwr[level]);
1070
1071 if (level > aniState->noiseImmunityLevel)
1072 ah->stats.ast_ani_niup++;
1073 else if (level < aniState->noiseImmunityLevel)
1074 ah->stats.ast_ani_nidown++;
1075 aniState->noiseImmunityLevel = level;
1076 break;
1077 }
1078 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1079 const int m1ThreshLow[] = { 127, 50 };
1080 const int m2ThreshLow[] = { 127, 40 };
1081 const int m1Thresh[] = { 127, 0x4d };
1082 const int m2Thresh[] = { 127, 0x40 };
1083 const int m2CountThr[] = { 31, 16 };
1084 const int m2CountThrLow[] = { 63, 48 };
1085 u32 on = param ? 1 : 0;
1086
1087 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1088 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1089 m1ThreshLow[on]);
1090 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1091 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1092 m2ThreshLow[on]);
1093 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1094 AR_PHY_SFCORR_M1_THRESH,
1095 m1Thresh[on]);
1096 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1097 AR_PHY_SFCORR_M2_THRESH,
1098 m2Thresh[on]);
1099 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1100 AR_PHY_SFCORR_M2COUNT_THR,
1101 m2CountThr[on]);
1102 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1103 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1104 m2CountThrLow[on]);
1105
1106 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1107 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1108 m1ThreshLow[on]);
1109 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1110 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1111 m2ThreshLow[on]);
1112 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1113 AR_PHY_SFCORR_EXT_M1_THRESH,
1114 m1Thresh[on]);
1115 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1116 AR_PHY_SFCORR_EXT_M2_THRESH,
1117 m2Thresh[on]);
1118
1119 if (on)
1120 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1121 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1122 else
1123 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1124 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1125
1126 if (!on != aniState->ofdmWeakSigDetectOff) {
1127 if (on)
1128 ah->stats.ast_ani_ofdmon++;
1129 else
1130 ah->stats.ast_ani_ofdmoff++;
1131 aniState->ofdmWeakSigDetectOff = !on;
1132 }
1133 break;
1134 }
1135 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1136 const int weakSigThrCck[] = { 8, 6 };
1137 u32 high = param ? 1 : 0;
1138
1139 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1140 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1141 weakSigThrCck[high]);
1142 if (high != aniState->cckWeakSigThreshold) {
1143 if (high)
1144 ah->stats.ast_ani_cckhigh++;
1145 else
1146 ah->stats.ast_ani_ccklow++;
1147 aniState->cckWeakSigThreshold = high;
1148 }
1149 break;
1150 }
1151 case ATH9K_ANI_FIRSTEP_LEVEL:{
1152 const int firstep[] = { 0, 4, 8 };
1153 u32 level = param;
1154
1155 if (level >= ARRAY_SIZE(firstep)) {
1156 ath_print(common, ATH_DBG_ANI,
1157 "level out of range (%u > %u)\n",
1158 level,
1159 (unsigned) ARRAY_SIZE(firstep));
1160 return false;
1161 }
1162 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1163 AR_PHY_FIND_SIG_FIRSTEP,
1164 firstep[level]);
1165 if (level > aniState->firstepLevel)
1166 ah->stats.ast_ani_stepup++;
1167 else if (level < aniState->firstepLevel)
1168 ah->stats.ast_ani_stepdown++;
1169 aniState->firstepLevel = level;
1170 break;
1171 }
1172 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1173 const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1174 u32 level = param;
1175
1176 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1177 ath_print(common, ATH_DBG_ANI,
1178 "level out of range (%u > %u)\n",
1179 level,
1180 (unsigned) ARRAY_SIZE(cycpwrThr1));
1181 return false;
1182 }
1183 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1184 AR_PHY_TIMING5_CYCPWR_THR1,
1185 cycpwrThr1[level]);
1186 if (level > aniState->spurImmunityLevel)
1187 ah->stats.ast_ani_spurup++;
1188 else if (level < aniState->spurImmunityLevel)
1189 ah->stats.ast_ani_spurdown++;
1190 aniState->spurImmunityLevel = level;
1191 break;
1192 }
1193 case ATH9K_ANI_PRESENT:
1194 break;
1195 default:
1196 ath_print(common, ATH_DBG_ANI,
1197 "invalid cmd %u\n", cmd);
1198 return false;
1199 }
1200
1201 ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
1202 ath_print(common, ATH_DBG_ANI,
1203 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
1204 "ofdmWeakSigDetectOff=%d\n",
1205 aniState->noiseImmunityLevel,
1206 aniState->spurImmunityLevel,
1207 !aniState->ofdmWeakSigDetectOff);
1208 ath_print(common, ATH_DBG_ANI,
1209 "cckWeakSigThreshold=%d, "
1210 "firstepLevel=%d, listenTime=%d\n",
1211 aniState->cckWeakSigThreshold,
1212 aniState->firstepLevel,
1213 aniState->listenTime);
1214 ath_print(common, ATH_DBG_ANI,
1215 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1216 aniState->cycleCount,
1217 aniState->ofdmPhyErrCount,
1218 aniState->cckPhyErrCount);
1219
1220 return true;
1221}
1222
1223static void ar5008_hw_do_getnf(struct ath_hw *ah,
1224 int16_t nfarray[NUM_NF_READINGS])
1225{
1226 struct ath_common *common = ath9k_hw_common(ah);
1227 int16_t nf;
1228
1229 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1230 if (nf & 0x100)
1231 nf = 0 - ((nf ^ 0x1ff) + 1);
1232 ath_print(common, ATH_DBG_CALIBRATE,
1233 "NF calibrated [ctl] [chain 0] is %d\n", nf);
1234 nfarray[0] = nf;
1235
1236 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1237 if (nf & 0x100)
1238 nf = 0 - ((nf ^ 0x1ff) + 1);
1239 ath_print(common, ATH_DBG_CALIBRATE,
1240 "NF calibrated [ctl] [chain 1] is %d\n", nf);
1241 nfarray[1] = nf;
1242
1243 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1244 if (nf & 0x100)
1245 nf = 0 - ((nf ^ 0x1ff) + 1);
1246 ath_print(common, ATH_DBG_CALIBRATE,
1247 "NF calibrated [ctl] [chain 2] is %d\n", nf);
1248 nfarray[2] = nf;
1249
1250 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1251 if (nf & 0x100)
1252 nf = 0 - ((nf ^ 0x1ff) + 1);
1253 ath_print(common, ATH_DBG_CALIBRATE,
1254 "NF calibrated [ext] [chain 0] is %d\n", nf);
1255 nfarray[3] = nf;
1256
1257 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1258 if (nf & 0x100)
1259 nf = 0 - ((nf ^ 0x1ff) + 1);
1260 ath_print(common, ATH_DBG_CALIBRATE,
1261 "NF calibrated [ext] [chain 1] is %d\n", nf);
1262 nfarray[4] = nf;
1263
1264 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1265 if (nf & 0x100)
1266 nf = 0 - ((nf ^ 0x1ff) + 1);
1267 ath_print(common, ATH_DBG_CALIBRATE,
1268 "NF calibrated [ext] [chain 2] is %d\n", nf);
1269 nfarray[5] = nf;
1270}
1271
1272static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
1273{
1274 struct ath9k_nfcal_hist *h;
1275 int i, j;
1276 int32_t val;
1277 const u32 ar5416_cca_regs[6] = {
1278 AR_PHY_CCA,
1279 AR_PHY_CH1_CCA,
1280 AR_PHY_CH2_CCA,
1281 AR_PHY_EXT_CCA,
1282 AR_PHY_CH1_EXT_CCA,
1283 AR_PHY_CH2_EXT_CCA
1284 };
1285 u8 chainmask, rx_chain_status;
1286
1287 rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
1288 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1289 chainmask = 0x9;
1290 else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
1291 if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
1292 chainmask = 0x1B;
1293 else
1294 chainmask = 0x09;
1295 } else {
1296 if (rx_chain_status & 0x4)
1297 chainmask = 0x3F;
1298 else if (rx_chain_status & 0x2)
1299 chainmask = 0x1B;
1300 else
1301 chainmask = 0x09;
1302 }
1303
1304 h = ah->nfCalHist;
1305
1306 for (i = 0; i < NUM_NF_READINGS; i++) {
1307 if (chainmask & (1 << i)) {
1308 val = REG_READ(ah, ar5416_cca_regs[i]);
1309 val &= 0xFFFFFE00;
1310 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1311 REG_WRITE(ah, ar5416_cca_regs[i], val);
1312 }
1313 }
1314
1315 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1316 AR_PHY_AGC_CONTROL_ENABLE_NF);
1317 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1318 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1319 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1320
1321 for (j = 0; j < 5; j++) {
1322 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1323 AR_PHY_AGC_CONTROL_NF) == 0)
1324 break;
1325 udelay(50);
1326 }
1327
1328 ENABLE_REGWRITE_BUFFER(ah);
1329
1330 for (i = 0; i < NUM_NF_READINGS; i++) {
1331 if (chainmask & (1 << i)) {
1332 val = REG_READ(ah, ar5416_cca_regs[i]);
1333 val &= 0xFFFFFE00;
1334 val |= (((u32) (-50) << 1) & 0x1ff);
1335 REG_WRITE(ah, ar5416_cca_regs[i], val);
1336 }
1337 }
1338
1339 REGWRITE_BUFFER_FLUSH(ah);
1340 DISABLE_REGWRITE_BUFFER(ah);
1341}
1342
1343void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1344{
1345 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1346
1347 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1348 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1349
1350 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1351 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1352 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1353 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1354 priv_ops->init_bb = ar5008_hw_init_bb;
1355 priv_ops->process_ini = ar5008_hw_process_ini;
1356 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1357 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1358 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1359 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1360 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1361 priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
1362 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1363 priv_ops->set_diversity = ar5008_set_diversity;
1364 priv_ops->ani_control = ar5008_hw_ani_control;
1365 priv_ops->do_getnf = ar5008_hw_do_getnf;
1366 priv_ops->loadnf = ar5008_hw_loadnf;
1367
1368 if (AR_SREV_9100(ah))
1369 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
1370 else if (AR_SREV_9160_10_OR_LATER(ah))
1371 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1372 else
1373 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1374}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 08:27:51 -0400