diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath10k/pci.h')
-rw-r--r-- | drivers/net/wireless/ath/ath10k/pci.h | 73 |
1 files changed, 30 insertions, 43 deletions
diff --git a/drivers/net/wireless/ath/ath10k/pci.h b/drivers/net/wireless/ath/ath10k/pci.h index 871bb339d56d..7c49f6f96f70 100644 --- a/drivers/net/wireless/ath/ath10k/pci.h +++ b/drivers/net/wireless/ath/ath10k/pci.h | |||
@@ -43,22 +43,23 @@ struct bmi_xfer { | |||
43 | u32 resp_len; | 43 | u32 resp_len; |
44 | }; | 44 | }; |
45 | 45 | ||
46 | enum ath10k_pci_compl_state { | ||
47 | ATH10K_PCI_COMPL_FREE = 0, | ||
48 | ATH10K_PCI_COMPL_SEND, | ||
49 | ATH10K_PCI_COMPL_RECV, | ||
50 | }; | ||
51 | |||
46 | struct ath10k_pci_compl { | 52 | struct ath10k_pci_compl { |
47 | struct list_head list; | 53 | struct list_head list; |
48 | int send_or_recv; | 54 | enum ath10k_pci_compl_state state; |
49 | struct ce_state *ce_state; | 55 | struct ath10k_ce_pipe *ce_state; |
50 | struct hif_ce_pipe_info *pipe_info; | 56 | struct ath10k_pci_pipe *pipe_info; |
51 | void *transfer_context; | 57 | struct sk_buff *skb; |
52 | unsigned int nbytes; | 58 | unsigned int nbytes; |
53 | unsigned int transfer_id; | 59 | unsigned int transfer_id; |
54 | unsigned int flags; | 60 | unsigned int flags; |
55 | }; | 61 | }; |
56 | 62 | ||
57 | /* compl_state.send_or_recv */ | ||
58 | #define HIF_CE_COMPLETE_FREE 0 | ||
59 | #define HIF_CE_COMPLETE_SEND 1 | ||
60 | #define HIF_CE_COMPLETE_RECV 2 | ||
61 | |||
62 | /* | 63 | /* |
63 | * PCI-specific Target state | 64 | * PCI-specific Target state |
64 | * | 65 | * |
@@ -152,17 +153,16 @@ struct service_to_pipe { | |||
152 | 153 | ||
153 | enum ath10k_pci_features { | 154 | enum ath10k_pci_features { |
154 | ATH10K_PCI_FEATURE_MSI_X = 0, | 155 | ATH10K_PCI_FEATURE_MSI_X = 0, |
155 | ATH10K_PCI_FEATURE_HW_1_0_WORKAROUND = 1, | 156 | ATH10K_PCI_FEATURE_SOC_POWER_SAVE = 1, |
156 | ATH10K_PCI_FEATURE_SOC_POWER_SAVE = 2, | ||
157 | 157 | ||
158 | /* keep last */ | 158 | /* keep last */ |
159 | ATH10K_PCI_FEATURE_COUNT | 159 | ATH10K_PCI_FEATURE_COUNT |
160 | }; | 160 | }; |
161 | 161 | ||
162 | /* Per-pipe state. */ | 162 | /* Per-pipe state. */ |
163 | struct hif_ce_pipe_info { | 163 | struct ath10k_pci_pipe { |
164 | /* Handle of underlying Copy Engine */ | 164 | /* Handle of underlying Copy Engine */ |
165 | struct ce_state *ce_hdl; | 165 | struct ath10k_ce_pipe *ce_hdl; |
166 | 166 | ||
167 | /* Our pipe number; facilitiates use of pipe_info ptrs. */ | 167 | /* Our pipe number; facilitiates use of pipe_info ptrs. */ |
168 | u8 pipe_num; | 168 | u8 pipe_num; |
@@ -190,7 +190,6 @@ struct ath10k_pci { | |||
190 | struct device *dev; | 190 | struct device *dev; |
191 | struct ath10k *ar; | 191 | struct ath10k *ar; |
192 | void __iomem *mem; | 192 | void __iomem *mem; |
193 | int cacheline_sz; | ||
194 | 193 | ||
195 | DECLARE_BITMAP(features, ATH10K_PCI_FEATURE_COUNT); | 194 | DECLARE_BITMAP(features, ATH10K_PCI_FEATURE_COUNT); |
196 | 195 | ||
@@ -219,7 +218,7 @@ struct ath10k_pci { | |||
219 | 218 | ||
220 | bool compl_processing; | 219 | bool compl_processing; |
221 | 220 | ||
222 | struct hif_ce_pipe_info pipe_info[CE_COUNT_MAX]; | 221 | struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX]; |
223 | 222 | ||
224 | struct ath10k_hif_cb msg_callbacks_current; | 223 | struct ath10k_hif_cb msg_callbacks_current; |
225 | 224 | ||
@@ -227,16 +226,13 @@ struct ath10k_pci { | |||
227 | u32 fw_indicator_address; | 226 | u32 fw_indicator_address; |
228 | 227 | ||
229 | /* Copy Engine used for Diagnostic Accesses */ | 228 | /* Copy Engine used for Diagnostic Accesses */ |
230 | struct ce_state *ce_diag; | 229 | struct ath10k_ce_pipe *ce_diag; |
231 | 230 | ||
232 | /* FIXME: document what this really protects */ | 231 | /* FIXME: document what this really protects */ |
233 | spinlock_t ce_lock; | 232 | spinlock_t ce_lock; |
234 | 233 | ||
235 | /* Map CE id to ce_state */ | 234 | /* Map CE id to ce_state */ |
236 | struct ce_state *ce_id_to_state[CE_COUNT_MAX]; | 235 | struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; |
237 | |||
238 | /* makes sure that dummy reads are atomic */ | ||
239 | spinlock_t hw_v1_workaround_lock; | ||
240 | }; | 236 | }; |
241 | 237 | ||
242 | static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar) | 238 | static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar) |
@@ -244,14 +240,18 @@ static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar) | |||
244 | return ar->hif.priv; | 240 | return ar->hif.priv; |
245 | } | 241 | } |
246 | 242 | ||
247 | static inline u32 ath10k_pci_reg_read32(void __iomem *mem, u32 addr) | 243 | static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) |
248 | { | 244 | { |
249 | return ioread32(mem + PCIE_LOCAL_BASE_ADDRESS + addr); | 245 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
246 | |||
247 | return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr); | ||
250 | } | 248 | } |
251 | 249 | ||
252 | static inline void ath10k_pci_reg_write32(void __iomem *mem, u32 addr, u32 val) | 250 | static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) |
253 | { | 251 | { |
254 | iowrite32(val, mem + PCIE_LOCAL_BASE_ADDRESS + addr); | 252 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
253 | |||
254 | iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr); | ||
255 | } | 255 | } |
256 | 256 | ||
257 | #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */ | 257 | #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */ |
@@ -310,23 +310,8 @@ static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, | |||
310 | u32 value) | 310 | u32 value) |
311 | { | 311 | { |
312 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | 312 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
313 | void __iomem *addr = ar_pci->mem; | ||
314 | |||
315 | if (test_bit(ATH10K_PCI_FEATURE_HW_1_0_WORKAROUND, ar_pci->features)) { | ||
316 | unsigned long irq_flags; | ||
317 | 313 | ||
318 | spin_lock_irqsave(&ar_pci->hw_v1_workaround_lock, irq_flags); | 314 | iowrite32(value, ar_pci->mem + offset); |
319 | |||
320 | ioread32(addr+offset+4); /* 3rd read prior to write */ | ||
321 | ioread32(addr+offset+4); /* 2nd read prior to write */ | ||
322 | ioread32(addr+offset+4); /* 1st read prior to write */ | ||
323 | iowrite32(value, addr+offset); | ||
324 | |||
325 | spin_unlock_irqrestore(&ar_pci->hw_v1_workaround_lock, | ||
326 | irq_flags); | ||
327 | } else { | ||
328 | iowrite32(value, addr+offset); | ||
329 | } | ||
330 | } | 315 | } |
331 | 316 | ||
332 | static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) | 317 | static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) |
@@ -336,15 +321,17 @@ static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) | |||
336 | return ioread32(ar_pci->mem + offset); | 321 | return ioread32(ar_pci->mem + offset); |
337 | } | 322 | } |
338 | 323 | ||
339 | void ath10k_do_pci_wake(struct ath10k *ar); | 324 | int ath10k_do_pci_wake(struct ath10k *ar); |
340 | void ath10k_do_pci_sleep(struct ath10k *ar); | 325 | void ath10k_do_pci_sleep(struct ath10k *ar); |
341 | 326 | ||
342 | static inline void ath10k_pci_wake(struct ath10k *ar) | 327 | static inline int ath10k_pci_wake(struct ath10k *ar) |
343 | { | 328 | { |
344 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | 329 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
345 | 330 | ||
346 | if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features)) | 331 | if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features)) |
347 | ath10k_do_pci_wake(ar); | 332 | return ath10k_do_pci_wake(ar); |
333 | |||
334 | return 0; | ||
348 | } | 335 | } |
349 | 336 | ||
350 | static inline void ath10k_pci_sleep(struct ath10k *ar) | 337 | static inline void ath10k_pci_sleep(struct ath10k *ar) |