diff options
Diffstat (limited to 'drivers/net/vxge/vxge-reg.h')
-rw-r--r-- | drivers/net/vxge/vxge-reg.h | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/drivers/net/vxge/vxge-reg.h b/drivers/net/vxge/vxge-reg.h index 3dd5c9615ef9..3e658b175947 100644 --- a/drivers/net/vxge/vxge-reg.h +++ b/drivers/net/vxge/vxge-reg.h | |||
@@ -49,6 +49,33 @@ | |||
49 | #define VXGE_HW_TITAN_VPMGMT_REG_SPACES 17 | 49 | #define VXGE_HW_TITAN_VPMGMT_REG_SPACES 17 |
50 | #define VXGE_HW_TITAN_VPATH_REG_SPACES 17 | 50 | #define VXGE_HW_TITAN_VPATH_REG_SPACES 17 |
51 | 51 | ||
52 | #define VXGE_HW_FW_API_GET_EPROM_REV 31 | ||
53 | |||
54 | #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) | ||
55 | #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) | ||
56 | #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) | ||
57 | #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) | ||
58 | |||
59 | #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) | ||
60 | #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) | ||
61 | #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) | ||
62 | #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16) | ||
63 | #define VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(val) vxge_vBIT(val, 16, 8) | ||
64 | |||
65 | #define VXGE_HW_FW_API_GET_FUNC_MODE 29 | ||
66 | #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) | ||
67 | |||
68 | #define VXGE_HW_FW_UPGRADE_MEMO 13 | ||
69 | #define VXGE_HW_FW_UPGRADE_ACTION 16 | ||
70 | #define VXGE_HW_FW_UPGRADE_OFFSET_START 2 | ||
71 | #define VXGE_HW_FW_UPGRADE_OFFSET_SEND 3 | ||
72 | #define VXGE_HW_FW_UPGRADE_OFFSET_COMMIT 4 | ||
73 | #define VXGE_HW_FW_UPGRADE_OFFSET_READ 5 | ||
74 | |||
75 | #define VXGE_HW_FW_UPGRADE_BLK_SIZE 16 | ||
76 | #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) | ||
77 | #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) | ||
78 | |||
52 | #define VXGE_HW_ASIC_MODE_RESERVED 0 | 79 | #define VXGE_HW_ASIC_MODE_RESERVED 0 |
53 | #define VXGE_HW_ASIC_MODE_NO_IOV 1 | 80 | #define VXGE_HW_ASIC_MODE_NO_IOV 1 |
54 | #define VXGE_HW_ASIC_MODE_SR_IOV 2 | 81 | #define VXGE_HW_ASIC_MODE_SR_IOV 2 |
@@ -165,13 +192,13 @@ | |||
165 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2 | 192 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2 |
166 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN 3 | 193 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN 3 |
167 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5 | 194 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5 |
168 | #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6 | 195 | #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6 |
169 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7 | 196 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7 |
170 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8 | 197 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8 |
171 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9 | 198 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9 |
172 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS 10 | 199 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS 10 |
173 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS 11 | 200 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS 11 |
174 | #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12 | 201 | #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12 |
175 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13 | 202 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13 |
176 | 203 | ||
177 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ | 204 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ |
@@ -437,6 +464,7 @@ | |||
437 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \ | 464 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \ |
438 | vxge_bVALn(bits, 48, 16) | 465 | vxge_bVALn(bits, 48, 16) |
439 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16) | 466 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16) |
467 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(bits) vxge_bVALn(bits, 0, 8) | ||
440 | 468 | ||
441 | #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\ | 469 | #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\ |
442 | vxge_bVALn(bits, 0, 18) | 470 | vxge_bVALn(bits, 0, 18) |
@@ -3998,6 +4026,7 @@ struct vxge_hw_vpath_reg { | |||
3998 | #define VXGE_HW_PRC_CFG6_L4_CPC_TRSFR_CODE_EN vxge_mBIT(9) | 4026 | #define VXGE_HW_PRC_CFG6_L4_CPC_TRSFR_CODE_EN vxge_mBIT(9) |
3999 | #define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9) | 4027 | #define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9) |
4000 | #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9) | 4028 | #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9) |
4029 | #define VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val) vxge_bVALn(val, 36, 9) | ||
4001 | /*0x00a78*/ u64 prc_cfg7; | 4030 | /*0x00a78*/ u64 prc_cfg7; |
4002 | #define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2) | 4031 | #define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2) |
4003 | #define VXGE_HW_PRC_CFG7_SMART_SCAT_EN vxge_mBIT(11) | 4032 | #define VXGE_HW_PRC_CFG7_SMART_SCAT_EN vxge_mBIT(11) |