diff options
Diffstat (limited to 'drivers/net/usb/sr9700.c')
-rw-r--r-- | drivers/net/usb/sr9700.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/net/usb/sr9700.c b/drivers/net/usb/sr9700.c index 99b69af14274..4a1e9c489f1f 100644 --- a/drivers/net/usb/sr9700.c +++ b/drivers/net/usb/sr9700.c | |||
@@ -77,7 +77,7 @@ static int wait_phy_eeprom_ready(struct usbnet *dev, int phy) | |||
77 | int ret; | 77 | int ret; |
78 | 78 | ||
79 | udelay(1); | 79 | udelay(1); |
80 | ret = sr_read_reg(dev, EPCR, &tmp); | 80 | ret = sr_read_reg(dev, SR_EPCR, &tmp); |
81 | if (ret < 0) | 81 | if (ret < 0) |
82 | return ret; | 82 | return ret; |
83 | 83 | ||
@@ -98,15 +98,15 @@ static int sr_share_read_word(struct usbnet *dev, int phy, u8 reg, | |||
98 | 98 | ||
99 | mutex_lock(&dev->phy_mutex); | 99 | mutex_lock(&dev->phy_mutex); |
100 | 100 | ||
101 | sr_write_reg(dev, EPAR, phy ? (reg | EPAR_PHY_ADR) : reg); | 101 | sr_write_reg(dev, SR_EPAR, phy ? (reg | EPAR_PHY_ADR) : reg); |
102 | sr_write_reg(dev, EPCR, phy ? (EPCR_EPOS | EPCR_ERPRR) : EPCR_ERPRR); | 102 | sr_write_reg(dev, SR_EPCR, phy ? (EPCR_EPOS | EPCR_ERPRR) : EPCR_ERPRR); |
103 | 103 | ||
104 | ret = wait_phy_eeprom_ready(dev, phy); | 104 | ret = wait_phy_eeprom_ready(dev, phy); |
105 | if (ret < 0) | 105 | if (ret < 0) |
106 | goto out_unlock; | 106 | goto out_unlock; |
107 | 107 | ||
108 | sr_write_reg(dev, EPCR, 0x0); | 108 | sr_write_reg(dev, SR_EPCR, 0x0); |
109 | ret = sr_read(dev, EPDR, 2, value); | 109 | ret = sr_read(dev, SR_EPDR, 2, value); |
110 | 110 | ||
111 | netdev_dbg(dev->net, "read shared %d 0x%02x returned 0x%04x, %d\n", | 111 | netdev_dbg(dev->net, "read shared %d 0x%02x returned 0x%04x, %d\n", |
112 | phy, reg, *value, ret); | 112 | phy, reg, *value, ret); |
@@ -123,19 +123,19 @@ static int sr_share_write_word(struct usbnet *dev, int phy, u8 reg, | |||
123 | 123 | ||
124 | mutex_lock(&dev->phy_mutex); | 124 | mutex_lock(&dev->phy_mutex); |
125 | 125 | ||
126 | ret = sr_write(dev, EPDR, 2, &value); | 126 | ret = sr_write(dev, SR_EPDR, 2, &value); |
127 | if (ret < 0) | 127 | if (ret < 0) |
128 | goto out_unlock; | 128 | goto out_unlock; |
129 | 129 | ||
130 | sr_write_reg(dev, EPAR, phy ? (reg | EPAR_PHY_ADR) : reg); | 130 | sr_write_reg(dev, SR_EPAR, phy ? (reg | EPAR_PHY_ADR) : reg); |
131 | sr_write_reg(dev, EPCR, phy ? (EPCR_WEP | EPCR_EPOS | EPCR_ERPRW) : | 131 | sr_write_reg(dev, SR_EPCR, phy ? (EPCR_WEP | EPCR_EPOS | EPCR_ERPRW) : |
132 | (EPCR_WEP | EPCR_ERPRW)); | 132 | (EPCR_WEP | EPCR_ERPRW)); |
133 | 133 | ||
134 | ret = wait_phy_eeprom_ready(dev, phy); | 134 | ret = wait_phy_eeprom_ready(dev, phy); |
135 | if (ret < 0) | 135 | if (ret < 0) |
136 | goto out_unlock; | 136 | goto out_unlock; |
137 | 137 | ||
138 | sr_write_reg(dev, EPCR, 0x0); | 138 | sr_write_reg(dev, SR_EPCR, 0x0); |
139 | 139 | ||
140 | out_unlock: | 140 | out_unlock: |
141 | mutex_unlock(&dev->phy_mutex); | 141 | mutex_unlock(&dev->phy_mutex); |
@@ -188,7 +188,7 @@ static int sr_mdio_read(struct net_device *netdev, int phy_id, int loc) | |||
188 | if (loc == MII_BMSR) { | 188 | if (loc == MII_BMSR) { |
189 | u8 value; | 189 | u8 value; |
190 | 190 | ||
191 | sr_read_reg(dev, NSR, &value); | 191 | sr_read_reg(dev, SR_NSR, &value); |
192 | if (value & NSR_LINKST) | 192 | if (value & NSR_LINKST) |
193 | rc = 1; | 193 | rc = 1; |
194 | } | 194 | } |
@@ -228,7 +228,7 @@ static u32 sr9700_get_link(struct net_device *netdev) | |||
228 | int rc = 0; | 228 | int rc = 0; |
229 | 229 | ||
230 | /* Get the Link Status directly */ | 230 | /* Get the Link Status directly */ |
231 | sr_read_reg(dev, NSR, &value); | 231 | sr_read_reg(dev, SR_NSR, &value); |
232 | if (value & NSR_LINKST) | 232 | if (value & NSR_LINKST) |
233 | rc = 1; | 233 | rc = 1; |
234 | 234 | ||
@@ -281,8 +281,8 @@ static void sr9700_set_multicast(struct net_device *netdev) | |||
281 | } | 281 | } |
282 | } | 282 | } |
283 | 283 | ||
284 | sr_write_async(dev, MAR, SR_MCAST_SIZE, hashes); | 284 | sr_write_async(dev, SR_MAR, SR_MCAST_SIZE, hashes); |
285 | sr_write_reg_async(dev, RCR, rx_ctl); | 285 | sr_write_reg_async(dev, SR_RCR, rx_ctl); |
286 | } | 286 | } |
287 | 287 | ||
288 | static int sr9700_set_mac_address(struct net_device *netdev, void *p) | 288 | static int sr9700_set_mac_address(struct net_device *netdev, void *p) |
@@ -297,7 +297,7 @@ static int sr9700_set_mac_address(struct net_device *netdev, void *p) | |||
297 | } | 297 | } |
298 | 298 | ||
299 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | 299 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
300 | sr_write_async(dev, PAR, 6, netdev->dev_addr); | 300 | sr_write_async(dev, SR_PAR, 6, netdev->dev_addr); |
301 | 301 | ||
302 | return 0; | 302 | return 0; |
303 | } | 303 | } |
@@ -340,7 +340,7 @@ static int sr9700_bind(struct usbnet *dev, struct usb_interface *intf) | |||
340 | mii->phy_id_mask = 0x1f; | 340 | mii->phy_id_mask = 0x1f; |
341 | mii->reg_num_mask = 0x1f; | 341 | mii->reg_num_mask = 0x1f; |
342 | 342 | ||
343 | sr_write_reg(dev, NCR, NCR_RST); | 343 | sr_write_reg(dev, SR_NCR, NCR_RST); |
344 | udelay(20); | 344 | udelay(20); |
345 | 345 | ||
346 | /* read MAC | 346 | /* read MAC |
@@ -348,17 +348,17 @@ static int sr9700_bind(struct usbnet *dev, struct usb_interface *intf) | |||
348 | * EEPROM automatically to PAR. In case there is no EEPROM externally, | 348 | * EEPROM automatically to PAR. In case there is no EEPROM externally, |
349 | * a default MAC address is stored in PAR for making chip work properly. | 349 | * a default MAC address is stored in PAR for making chip work properly. |
350 | */ | 350 | */ |
351 | if (sr_read(dev, PAR, ETH_ALEN, netdev->dev_addr) < 0) { | 351 | if (sr_read(dev, SR_PAR, ETH_ALEN, netdev->dev_addr) < 0) { |
352 | netdev_err(netdev, "Error reading MAC address\n"); | 352 | netdev_err(netdev, "Error reading MAC address\n"); |
353 | ret = -ENODEV; | 353 | ret = -ENODEV; |
354 | goto out; | 354 | goto out; |
355 | } | 355 | } |
356 | 356 | ||
357 | /* power up and reset phy */ | 357 | /* power up and reset phy */ |
358 | sr_write_reg(dev, PRR, PRR_PHY_RST); | 358 | sr_write_reg(dev, SR_PRR, PRR_PHY_RST); |
359 | /* at least 10ms, here 20ms for safe */ | 359 | /* at least 10ms, here 20ms for safe */ |
360 | mdelay(20); | 360 | mdelay(20); |
361 | sr_write_reg(dev, PRR, 0); | 361 | sr_write_reg(dev, SR_PRR, 0); |
362 | /* at least 1ms, here 2ms for reading right register */ | 362 | /* at least 1ms, here 2ms for reading right register */ |
363 | udelay(2 * 1000); | 363 | udelay(2 * 1000); |
364 | 364 | ||