1 files changed, 183 insertions, 98 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 5e96706ad108..5b3d2f34da7a 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -23,11 +23,13 @@
 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
 #define TG3_BDINFO_SIZE                 0x10UL
 
-#define TG3_RX_INTERNAL_RING_SZ_5906    32
-
-#define RX_STD_MAX_SIZE_5705            512
-#define RX_STD_MAX_SIZE_5717            2048
-#define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
+#define TG3_RX_STD_MAX_SIZE_5700        512
+#define TG3_RX_STD_MAX_SIZE_5717        2048
+#define TG3_RX_JMB_MAX_SIZE_5700        256
+#define TG3_RX_JMB_MAX_SIZE_5717        1024
+#define TG3_RX_RET_MAX_SIZE_5700        1024
+#define TG3_RX_RET_MAX_SIZE_5705        512
+#define TG3_RX_RET_MAX_SIZE_5717        4096
 
 /* First 256 bytes are a mirror of PCI config space. */
 #define TG3PCI_VENDOR                   0x00000000
@@ -54,6 +56,7 @@
 #define  TG3PCI_DEVICE_TIGON3_57791      0x16b2
 #define  TG3PCI_DEVICE_TIGON3_57795      0x16b6
 #define  TG3PCI_DEVICE_TIGON3_5719       0x1657
+#define  TG3PCI_DEVICE_TIGON3_5720       0x165f
 /* 0x04 --> 0x2c unused */
 #define TG3PCI_SUBVENDOR_ID_BROADCOM            PCI_VENDOR_ID_BROADCOM
 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6    0x1644
@@ -142,6 +145,7 @@
 #define  CHIPREV_ID_5717_A0              0x05717000
 #define  CHIPREV_ID_57765_A0             0x57785000
 #define  CHIPREV_ID_5719_A0              0x05719000
+#define  CHIPREV_ID_5720_A0              0x05720000
 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                  0x07
 #define   ASIC_REV_5701                  0x00
@@ -163,6 +167,7 @@
 #define   ASIC_REV_5717                  0x5717
 #define   ASIC_REV_57765                 0x57785
 #define   ASIC_REV_5719                  0x5719
+#define   ASIC_REV_5720                  0x5720
 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX                0x70
 #define   CHIPREV_5700_BX                0x71
@@ -175,6 +180,7 @@
 #define   CHIPREV_5750_BX                0x41
 #define   CHIPREV_5784_AX                0x57840
 #define   CHIPREV_5761_AX                0x57610
+#define   CHIPREV_57765_AX               0x577650
 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
 #define   METAL_REV_A0                   0x00
 #define   METAL_REV_A1                   0x01
@@ -183,6 +189,7 @@
 #define   METAL_REV_B2                   0x02
 #define TG3PCI_DMA_RW_CTRL              0x0000006c
 #define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
+#define  DMA_RWCTRL_TAGGED_STAT_WA       0x00000080
 #define  DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
@@ -473,6 +480,8 @@
 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
 #define  TX_MODE_MBUF_LOCKUP_FIX         0x00000100
+#define  TX_MODE_JMB_FRM_LEN             0x00400000
+#define  TX_MODE_CNT_DN_MODE             0x00800000
 #define MAC_TX_STATUS                   0x00000460
 #define  TX_STATUS_XOFFED                0x00000001
 #define  TX_STATUS_SENT_XOFF             0x00000002
@@ -487,6 +496,8 @@
 #define  TX_LENGTHS_IPG_SHIFT            8
 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
+#define  TX_LENGTHS_JMB_FRM_LEN_MSK      0x00ff0000
+#define  TX_LENGTHS_CNT_DWN_VAL_MSK      0xff000000
 #define MAC_RX_MODE                     0x00000468
 #define  RX_MODE_RESET                   0x00000001
 #define  RX_MODE_ENABLE                  0x00000002
@@ -1079,6 +1090,9 @@
 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
 /* 0x3620 --> 0x3630 unused */
 
+#define TG3_CPMU_CLCK_ORIDE             0x00003624
+#define  CPMU_CLCK_ORIDE_MAC_ORIDE_EN    0x80000000
+
 #define TG3_CPMU_CLCK_STAT              0x00003630
 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
@@ -1188,6 +1202,7 @@
 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
 #define HOSTCC_FLOW_ATTN                0x00003c48
+#define HOSTCC_FLOW_ATTN_MBUF_LWM        0x00000040
 /* 0x3c4c --> 0x3c50 unused */
 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
 #define HOSTCC_STD_CON_IDX              0x00003c54
@@ -1321,6 +1336,7 @@
 #define  RDMAC_MODE_MULT_DMA_RD_DIS      0x01000000
 #define  RDMAC_MODE_IPV4_LSO_EN          0x08000000
 #define  RDMAC_MODE_IPV6_LSO_EN          0x10000000
+#define  RDMAC_MODE_H2BNC_VLAN_DET       0x20000000
 #define RDMAC_STATUS                    0x00004804
 #define  RDMAC_STATUS_TGTABORT           0x00000004
 #define  RDMAC_STATUS_MSTABORT           0x00000008
@@ -1597,6 +1613,7 @@
 #define  MSGINT_MODE_ONE_SHOT_DISABLE    0x00000020
 #define  MSGINT_MODE_MULTIVEC_EN         0x00000080
 #define MSGINT_STATUS                   0x00006004
+#define  MSGINT_STATUS_MSI_REQ           0x00000001
 #define MSGINT_FIFO                     0x00006008
 /* 0x600c --> 0x6400 unused */
 
@@ -1613,6 +1630,8 @@
 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
 #define  GRC_MODE_BSWAP_DATA            0x00000010
 #define  GRC_MODE_WSWAP_DATA            0x00000020
+#define  GRC_MODE_BYTE_SWAP_B2HRX_DATA  0x00000040
+#define  GRC_MODE_WORD_SWAP_B2HRX_DATA  0x00000080
 #define  GRC_MODE_SPLITHDR              0x00000100
 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
 #define  GRC_MODE_INCL_CRC              0x00000400
@@ -1620,8 +1639,10 @@
 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
+#define  GRC_MODE_B2HRX_ENABLE          0x00008000
 #define  GRC_MODE_HOST_STACKUP          0x00010000
 #define  GRC_MODE_HOST_SENDBDS          0x00020000
+#define  GRC_MODE_HTX2B_ENABLE          0x00040000
 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
 #define  GRC_MODE_PCIE_TL_SEL           0x00000000
@@ -1818,6 +1839,38 @@
 #define  FLASH_5717VENDOR_ATMEL_45USPT   0x03400000
 #define  FLASH_5717VENDOR_ST_25USPT      0x03400002
 #define  FLASH_5717VENDOR_ST_45USPT      0x03400001
+#define  FLASH_5720_EEPROM_HD            0x00000001
+#define  FLASH_5720_EEPROM_LD            0x00000003
+#define  FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
+#define  FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
+#define  FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
+#define  FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
+#define  FLASH_5720VENDOR_M_ST_M25PE10   0x02000000
+#define  FLASH_5720VENDOR_M_ST_M25PE20   0x02000002
+#define  FLASH_5720VENDOR_M_ST_M25PE40   0x02000001
+#define  FLASH_5720VENDOR_M_ST_M25PE80   0x02000003
+#define  FLASH_5720VENDOR_M_ST_M45PE10   0x03000000
+#define  FLASH_5720VENDOR_M_ST_M45PE20   0x03000002
+#define  FLASH_5720VENDOR_M_ST_M45PE40   0x03000001
+#define  FLASH_5720VENDOR_M_ST_M45PE80   0x03000003
+#define  FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
+#define  FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
+#define  FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
+#define  FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
+#define  FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
+#define  FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
+#define  FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
+#define  FLASH_5720VENDOR_A_ST_M25PE10   0x02800000
+#define  FLASH_5720VENDOR_A_ST_M25PE20   0x02800002
+#define  FLASH_5720VENDOR_A_ST_M25PE40   0x02800001
+#define  FLASH_5720VENDOR_A_ST_M25PE80   0x02800003
+#define  FLASH_5720VENDOR_A_ST_M45PE10   0x02c00000
+#define  FLASH_5720VENDOR_A_ST_M45PE20   0x02c00002
+#define  FLASH_5720VENDOR_A_ST_M45PE40   0x02c00001
+#define  FLASH_5720VENDOR_A_ST_M45PE80   0x02c00003
+#define  FLASH_5720VENDOR_ATMEL_45USPT   0x03c00000
+#define  FLASH_5720VENDOR_ST_25USPT      0x03c00002
+#define  FLASH_5720VENDOR_ST_45USPT      0x03c00001
 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
 #define  FLASH_5752PAGE_SIZE_256         0x00000000
 #define  FLASH_5752PAGE_SIZE_512         0x10000000
@@ -1899,11 +1952,16 @@
 
 /* Alternate PCIE definitions */
 #define TG3_PCIE_TLDLPL_PORT            0x00007c00
+#define TG3_PCIE_DL_LO_FTSMAX           0x0000000c
+#define TG3_PCIE_DL_LO_FTSMAX_MSK       0x000000ff
+#define TG3_PCIE_DL_LO_FTSMAX_VAL       0x0000002c
 #define TG3_PCIE_PL_LO_PHYCTL1           0x00000004
 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN         0x00001000
 #define TG3_PCIE_PL_LO_PHYCTL5           0x00000014
 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ       0x80000000
 
+#define TG3_REG_BLK_SIZE                0x00008000
+
 /* OTP bit definitions */
 #define TG3_OTP_AGCTGT_MASK             0x000000e0
 #define TG3_OTP_AGCTGT_SHIFT            1
@@ -1955,7 +2013,9 @@
 #define TG3_NVM_DIR_END                 0x78
 #define TG3_NVM_DIRENT_SIZE             0xc
 #define TG3_NVM_DIRTYPE_SHIFT           24
+#define TG3_NVM_DIRTYPE_LENMSK          0x003fffff
 #define TG3_NVM_DIRTYPE_ASFINI          1
+#define TG3_NVM_DIRTYPE_EXTVPD          20
 #define TG3_NVM_PTREV_BCVER             0x94
 #define TG3_NVM_BCVER_MAJMSK            0x0000ff00
 #define TG3_NVM_BCVER_MAJSFT            8
@@ -2079,6 +2139,13 @@
 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
 
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700       128
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755       64
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906       32
+
+#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700       64
+#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717       16
+
 
 /* Currently this is fixed. */
 #define TG3_PHY_MII_ADDR                0x01
@@ -2119,7 +2186,7 @@
 #define  MII_TG3_DSP_TAP26_OPCSINPT     0x0004
 #define MII_TG3_DSP_AADJ1CH0            0x001f
 #define MII_TG3_DSP_CH34TP2             0x4022
-#define MII_TG3_DSP_CH34TP2_HIBW01      0x0010
+#define MII_TG3_DSP_CH34TP2_HIBW01      0x017b
 #define MII_TG3_DSP_AADJ1CH3            0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
 #define MII_TG3_DSP_EXP1_INT_STAT       0x0f01
@@ -2132,19 +2199,26 @@
 
 #define MII_TG3_AUX_CTRL                0x18 /* auxiliary control register */
 
+#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
+#define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
+#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
+#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN   0x4000
+
+#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
+#define MII_TG3_AUXCTL_PCTL_WOL_EN      0x0008
 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR  0x0010
 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
+#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
 #define MII_TG3_AUXCTL_PCTL_VREG_11V    0x0180
-#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
 
-#define MII_TG3_AUXCTL_MISC_WREN        0x8000
-#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
-#define MII_TG3_AUXCTL_MISC_RDSEL_MISC  0x7000
+#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
+
 #define MII_TG3_AUXCTL_SHDWSEL_MISC     0x0007
+#define MII_TG3_AUXCTL_MISC_WIRESPD_EN  0x0010
+#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
+#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
+#define MII_TG3_AUXCTL_MISC_WREN        0x8000
 
-#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
-#define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
-#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
 
 #define MII_TG3_AUX_STAT                0x19 /* auxiliary status register */
 #define MII_TG3_AUX_STAT_LPASS          0x0004
@@ -2564,7 +2638,12 @@ struct tg3_hw_stats {
         tg3_stat64_t                    nic_avoided_irqs;
         tg3_stat64_t                    nic_tx_threshold_hit;
 
-        u8                              __reserved4[0xb00-0x9c0];
+        /* NOT a part of the hardware statistics block format.
+         * These stats are here as storage for tg3_periodic_fetch_stats().
+         */
+        tg3_stat64_t                    mbuf_lwm_thresh_hit;
+
+        u8                              __reserved4[0xb00-0x9c8];
 };
 
 /* 'mapping' is superfluous as the chip does not write into
@@ -2696,6 +2775,8 @@ struct tg3_ethtool_stats {
         u64             nic_irqs;
         u64             nic_avoided_irqs;
         u64             nic_tx_threshold_hit;
+
+        u64             mbuf_lwm_thresh_hit;
 };
 
 struct tg3_rx_prodring_set {
@@ -2745,6 +2826,86 @@ struct tg3_napi {
         unsigned int                    irq_vec;
 };
 
+enum TG3_FLAGS {
+        TG3_FLAG_TAGGED_STATUS = 0,
+        TG3_FLAG_TXD_MBOX_HWBUG,
+        TG3_FLAG_USE_LINKCHG_REG,
+        TG3_FLAG_ERROR_PROCESSED,
+        TG3_FLAG_ENABLE_ASF,
+        TG3_FLAG_ASPM_WORKAROUND,
+        TG3_FLAG_POLL_SERDES,
+        TG3_FLAG_MBOX_WRITE_REORDER,
+        TG3_FLAG_PCIX_TARGET_HWBUG,
+        TG3_FLAG_WOL_SPEED_100MB,
+        TG3_FLAG_WOL_ENABLE,
+        TG3_FLAG_EEPROM_WRITE_PROT,
+        TG3_FLAG_NVRAM,
+        TG3_FLAG_NVRAM_BUFFERED,
+        TG3_FLAG_SUPPORT_MSI,
+        TG3_FLAG_SUPPORT_MSIX,
+        TG3_FLAG_PCIX_MODE,
+        TG3_FLAG_PCI_HIGH_SPEED,
+        TG3_FLAG_PCI_32BIT,
+        TG3_FLAG_SRAM_USE_CONFIG,
+        TG3_FLAG_TX_RECOVERY_PENDING,
+        TG3_FLAG_WOL_CAP,
+        TG3_FLAG_JUMBO_RING_ENABLE,
+        TG3_FLAG_PAUSE_AUTONEG,
+        TG3_FLAG_CPMU_PRESENT,
+        TG3_FLAG_40BIT_DMA_BUG,
+        TG3_FLAG_BROKEN_CHECKSUMS,
+        TG3_FLAG_JUMBO_CAPABLE,
+        TG3_FLAG_CHIP_RESETTING,
+        TG3_FLAG_INIT_COMPLETE,
+        TG3_FLAG_RESTART_TIMER,
+        TG3_FLAG_TSO_BUG,
+        TG3_FLAG_IS_5788,
+        TG3_FLAG_MAX_RXPEND_64,
+        TG3_FLAG_TSO_CAPABLE,
+        TG3_FLAG_PCI_EXPRESS,
+        TG3_FLAG_ASF_NEW_HANDSHAKE,
+        TG3_FLAG_HW_AUTONEG,
+        TG3_FLAG_IS_NIC,
+        TG3_FLAG_FLASH,
+        TG3_FLAG_HW_TSO_1,
+        TG3_FLAG_5705_PLUS,
+        TG3_FLAG_5750_PLUS,
+        TG3_FLAG_HW_TSO_3,
+        TG3_FLAG_USING_MSI,
+        TG3_FLAG_USING_MSIX,
+        TG3_FLAG_ICH_WORKAROUND,
+        TG3_FLAG_5780_CLASS,
+        TG3_FLAG_HW_TSO_2,
+        TG3_FLAG_1SHOT_MSI,
+        TG3_FLAG_NO_FWARE_REPORTED,
+        TG3_FLAG_NO_NVRAM_ADDR_TRANS,
+        TG3_FLAG_ENABLE_APE,
+        TG3_FLAG_PROTECTED_NVRAM,
+        TG3_FLAG_5701_DMA_BUG,
+        TG3_FLAG_USE_PHYLIB,
+        TG3_FLAG_MDIOBUS_INITED,
+        TG3_FLAG_LRG_PROD_RING_CAP,
+        TG3_FLAG_RGMII_INBAND_DISABLE,
+        TG3_FLAG_RGMII_EXT_IBND_RX_EN,
+        TG3_FLAG_RGMII_EXT_IBND_TX_EN,
+        TG3_FLAG_CLKREQ_BUG,
+        TG3_FLAG_5755_PLUS,
+        TG3_FLAG_NO_NVRAM,
+        TG3_FLAG_ENABLE_RSS,
+        TG3_FLAG_ENABLE_TSS,
+        TG3_FLAG_4G_DMA_BNDRY_BUG,
+        TG3_FLAG_40BIT_DMA_LIMIT_BUG,
+        TG3_FLAG_SHORT_DMA_BUG,
+        TG3_FLAG_USE_JUMBO_BDFLAG,
+        TG3_FLAG_L1PLLPD_EN,
+        TG3_FLAG_57765_PLUS,
+        TG3_FLAG_APE_HAS_NCSI,
+        TG3_FLAG_5717_PLUS,
+
+        /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
+        TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
+};
+
 struct tg3 {
         /* begin "general, frequently-used members" cacheline section */
 
@@ -2768,7 +2929,7 @@ struct tg3 {
         /* SMP locking strategy:
          *
          * lock: Held during reset, PHY access, timer, and when
-         *       updating tg3_flags and tg3_flags2.
+         *       updating tg3_flags.
          *
          * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
          *                netif_tx_lock when it needs to call
@@ -2825,94 +2986,13 @@ struct tg3 {
         struct tg3_ethtool_stats        estats;
         struct tg3_ethtool_stats        estats_prev;
 
+        DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
+
         union {
         unsigned long                   phy_crc_errors;
         unsigned long                   last_event_jiffies;
         };
 
-        u32                             tg3_flags;
-#define TG3_FLAG_TAGGED_STATUS          0x00000001
-#define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
-#define TG3_FLAG_RX_CHECKSUMS           0x00000004
-#define TG3_FLAG_USE_LINKCHG_REG        0x00000008
-#define TG3_FLAG_ENABLE_ASF             0x00000020
-#define TG3_FLAG_ASPM_WORKAROUND        0x00000040
-#define TG3_FLAG_POLL_SERDES            0x00000080
-#define TG3_FLAG_MBOX_WRITE_REORDER     0x00000100
-#define TG3_FLAG_PCIX_TARGET_HWBUG      0x00000200
-#define TG3_FLAG_WOL_SPEED_100MB        0x00000400
-#define TG3_FLAG_WOL_ENABLE             0x00000800
-#define TG3_FLAG_EEPROM_WRITE_PROT      0x00001000
-#define TG3_FLAG_NVRAM                  0x00002000
-#define TG3_FLAG_NVRAM_BUFFERED         0x00004000
-#define TG3_FLAG_SUPPORT_MSI            0x00008000
-#define TG3_FLAG_SUPPORT_MSIX           0x00010000
-#define TG3_FLAG_SUPPORT_MSI_OR_MSIX    (TG3_FLAG_SUPPORT_MSI | \
-                                         TG3_FLAG_SUPPORT_MSIX)
-#define TG3_FLAG_PCIX_MODE              0x00020000
-#define TG3_FLAG_PCI_HIGH_SPEED         0x00040000
-#define TG3_FLAG_PCI_32BIT              0x00080000
-#define TG3_FLAG_SRAM_USE_CONFIG        0x00100000
-#define TG3_FLAG_TX_RECOVERY_PENDING    0x00200000
-#define TG3_FLAG_WOL_CAP                0x00400000
-#define TG3_FLAG_JUMBO_RING_ENABLE      0x00800000
-#define TG3_FLAG_PAUSE_AUTONEG          0x02000000
-#define TG3_FLAG_CPMU_PRESENT           0x04000000
-#define TG3_FLAG_40BIT_DMA_BUG          0x08000000
-#define TG3_FLAG_BROKEN_CHECKSUMS       0x10000000
-#define TG3_FLAG_JUMBO_CAPABLE          0x20000000
-#define TG3_FLAG_CHIP_RESETTING         0x40000000
-#define TG3_FLAG_INIT_COMPLETE          0x80000000
-        u32                             tg3_flags2;
-#define TG3_FLG2_RESTART_TIMER          0x00000001
-#define TG3_FLG2_TSO_BUG                0x00000002
-#define TG3_FLG2_IS_5788                0x00000008
-#define TG3_FLG2_MAX_RXPEND_64          0x00000010
-#define TG3_FLG2_TSO_CAPABLE            0x00000020
-#define TG3_FLG2_PCI_EXPRESS            0x00000200
-#define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
-#define TG3_FLG2_HW_AUTONEG             0x00000800
-#define TG3_FLG2_IS_NIC                 0x00001000
-#define TG3_FLG2_FLASH                  0x00008000
-#define TG3_FLG2_HW_TSO_1               0x00010000
-#define TG3_FLG2_5705_PLUS              0x00040000
-#define TG3_FLG2_5750_PLUS              0x00080000
-#define TG3_FLG2_HW_TSO_3               0x00100000
-#define TG3_FLG2_USING_MSI              0x00200000
-#define TG3_FLG2_USING_MSIX             0x00400000
-#define TG3_FLG2_USING_MSI_OR_MSIX      (TG3_FLG2_USING_MSI | \
-                                        TG3_FLG2_USING_MSIX)
-#define TG3_FLG2_ICH_WORKAROUND         0x02000000
-#define TG3_FLG2_5780_CLASS             0x04000000
-#define TG3_FLG2_HW_TSO_2               0x08000000
-#define TG3_FLG2_HW_TSO                 (TG3_FLG2_HW_TSO_1 | \
-                                         TG3_FLG2_HW_TSO_2 | \
-                                         TG3_FLG2_HW_TSO_3)
-#define TG3_FLG2_1SHOT_MSI              0x10000000
-#define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
-        u32                             tg3_flags3;
-#define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
-#define TG3_FLG3_ENABLE_APE             0x00000002
-#define TG3_FLG3_PROTECTED_NVRAM        0x00000004
-#define TG3_FLG3_5701_DMA_BUG           0x00000008
-#define TG3_FLG3_USE_PHYLIB             0x00000010
-#define TG3_FLG3_MDIOBUS_INITED         0x00000020
-#define TG3_FLG3_RGMII_INBAND_DISABLE   0x00000100
-#define TG3_FLG3_RGMII_EXT_IBND_RX_EN   0x00000200
-#define TG3_FLG3_RGMII_EXT_IBND_TX_EN   0x00000400
-#define TG3_FLG3_CLKREQ_BUG             0x00000800
-#define TG3_FLG3_5755_PLUS              0x00002000
-#define TG3_FLG3_NO_NVRAM               0x00004000
-#define TG3_FLG3_ENABLE_RSS             0x00020000
-#define TG3_FLG3_ENABLE_TSS             0x00040000
-#define TG3_FLG3_4G_DMA_BNDRY_BUG       0x00080000
-#define TG3_FLG3_40BIT_DMA_LIMIT_BUG    0x00100000
-#define TG3_FLG3_SHORT_DMA_BUG          0x00200000
-#define TG3_FLG3_USE_JUMBO_BDFLAG       0x00400000
-#define TG3_FLG3_L1PLLPD_EN             0x00800000
-#define TG3_FLG3_5717_PLUS              0x01000000
-#define TG3_FLG3_APE_HAS_NCSI           0x02000000
-
         struct timer_list               timer;
         u16                             timer_counter;
         u16                             timer_multiplier;
@@ -2983,6 +3063,7 @@ struct tg3 {
 #define TG3_PHY_ID_BCM5718S             0xbc050ff0
 #define TG3_PHY_ID_BCM57765             0x5c0d8a40
 #define TG3_PHY_ID_BCM5719C             0x5c0d8a20
+#define TG3_PHY_ID_BCM5720C             0x5c0d8b60
 #define TG3_PHY_ID_BCM5906              0xdc00ac40
 #define TG3_PHY_ID_BCM8002              0x60010140
 #define TG3_PHY_ID_INVALID              0xffffffff
@@ -3049,6 +3130,7 @@ struct tg3 {
 
         int                             nvram_lock_cnt;
         u32                             nvram_size;
+#define TG3_NVRAM_SIZE_2KB              0x00000800
 #define TG3_NVRAM_SIZE_64KB             0x00010000
 #define TG3_NVRAM_SIZE_128KB            0x00020000
 #define TG3_NVRAM_SIZE_256KB            0x00040000
@@ -3064,6 +3146,9 @@ struct tg3 {
 #define JEDEC_SAIFUN                    0x4f
 #define JEDEC_SST                       0xbf
 
+#define ATMEL_AT24C02_CHIP_SIZE         TG3_NVRAM_SIZE_2KB
+#define ATMEL_AT24C02_PAGE_SIZE         (8)
+
 #define ATMEL_AT24C64_CHIP_SIZE         TG3_NVRAM_SIZE_64KB
 #define ATMEL_AT24C64_PAGE_SIZE         (32)